1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2018 SiFive, Inc 5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 7 * Copyright (c) 2008 Fabrice Bellard 8 * 9 * Based on i386/tcg-target.c and mips/tcg-target.c 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a copy 12 * of this software and associated documentation files (the "Software"), to deal 13 * in the Software without restriction, including without limitation the rights 14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 * copies of the Software, and to permit persons to whom the Software is 16 * furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 * THE SOFTWARE. 28 */ 29 30/* Used for function call generation. */ 31#define TCG_REG_CALL_STACK TCG_REG_SP 32#define TCG_TARGET_STACK_ALIGN 16 33#define TCG_TARGET_CALL_STACK_OFFSET 0 34#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 35#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 37#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 38 39#ifdef CONFIG_DEBUG_TCG 40static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 41 "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", 42 "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", 43 "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", 44 "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6", 45 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 46 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 47 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 48 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 49}; 50#endif 51 52static const int tcg_target_reg_alloc_order[] = { 53 /* Call saved registers */ 54 /* TCG_REG_S0 reserved for TCG_AREG0 */ 55 TCG_REG_S1, 56 TCG_REG_S2, 57 TCG_REG_S3, 58 TCG_REG_S4, 59 TCG_REG_S5, 60 TCG_REG_S6, 61 TCG_REG_S7, 62 TCG_REG_S8, 63 TCG_REG_S9, 64 TCG_REG_S10, 65 TCG_REG_S11, 66 67 /* Call clobbered registers */ 68 TCG_REG_T0, 69 TCG_REG_T1, 70 TCG_REG_T2, 71 TCG_REG_T3, 72 TCG_REG_T4, 73 TCG_REG_T5, 74 TCG_REG_T6, 75 76 /* Argument registers */ 77 TCG_REG_A0, 78 TCG_REG_A1, 79 TCG_REG_A2, 80 TCG_REG_A3, 81 TCG_REG_A4, 82 TCG_REG_A5, 83 TCG_REG_A6, 84 TCG_REG_A7, 85 86 /* Vector registers and TCG_REG_V0 reserved for mask. */ 87 TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, TCG_REG_V4, 88 TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, TCG_REG_V8, 89 TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, TCG_REG_V12, 90 TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, TCG_REG_V16, 91 TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, TCG_REG_V20, 92 TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, TCG_REG_V24, 93 TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, TCG_REG_V28, 94 TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, 95}; 96 97static const int tcg_target_call_iarg_regs[] = { 98 TCG_REG_A0, 99 TCG_REG_A1, 100 TCG_REG_A2, 101 TCG_REG_A3, 102 TCG_REG_A4, 103 TCG_REG_A5, 104 TCG_REG_A6, 105 TCG_REG_A7, 106}; 107 108static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 109{ 110 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 111 tcg_debug_assert(slot >= 0 && slot <= 1); 112 return TCG_REG_A0 + slot; 113} 114 115#define TCG_CT_CONST_S12 0x100 116#define TCG_CT_CONST_M12 0x200 117#define TCG_CT_CONST_S5 0x400 118#define TCG_CT_CONST_CMP_VI 0x800 119 120#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 121#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 122#define ALL_DVECTOR_REG_GROUPS 0x5555555500000000 123#define ALL_QVECTOR_REG_GROUPS 0x1111111100000000 124 125#define sextreg sextract64 126 127/* 128 * RISC-V Base ISA opcodes (IM) 129 */ 130 131#define V_OPIVV (0x0 << 12) 132#define V_OPFVV (0x1 << 12) 133#define V_OPMVV (0x2 << 12) 134#define V_OPIVI (0x3 << 12) 135#define V_OPIVX (0x4 << 12) 136#define V_OPFVF (0x5 << 12) 137#define V_OPMVX (0x6 << 12) 138#define V_OPCFG (0x7 << 12) 139 140/* NF <= 7 && NF >= 0 */ 141#define V_NF(x) (x << 29) 142#define V_UNIT_STRIDE (0x0 << 20) 143#define V_UNIT_STRIDE_WHOLE_REG (0x8 << 20) 144 145typedef enum { 146 VLMUL_M1 = 0, /* LMUL=1 */ 147 VLMUL_M2, /* LMUL=2 */ 148 VLMUL_M4, /* LMUL=4 */ 149 VLMUL_M8, /* LMUL=8 */ 150 VLMUL_RESERVED, 151 VLMUL_MF8, /* LMUL=1/8 */ 152 VLMUL_MF4, /* LMUL=1/4 */ 153 VLMUL_MF2, /* LMUL=1/2 */ 154} RISCVVlmul; 155 156typedef enum { 157 OPC_ADD = 0x33, 158 OPC_ADDI = 0x13, 159 OPC_AND = 0x7033, 160 OPC_ANDI = 0x7013, 161 OPC_AUIPC = 0x17, 162 OPC_BEQ = 0x63, 163 OPC_BEXTI = 0x48005013, 164 OPC_BGE = 0x5063, 165 OPC_BGEU = 0x7063, 166 OPC_BLT = 0x4063, 167 OPC_BLTU = 0x6063, 168 OPC_BNE = 0x1063, 169 OPC_DIV = 0x2004033, 170 OPC_DIVU = 0x2005033, 171 OPC_JAL = 0x6f, 172 OPC_JALR = 0x67, 173 OPC_LB = 0x3, 174 OPC_LBU = 0x4003, 175 OPC_LD = 0x3003, 176 OPC_LH = 0x1003, 177 OPC_LHU = 0x5003, 178 OPC_LUI = 0x37, 179 OPC_LW = 0x2003, 180 OPC_LWU = 0x6003, 181 OPC_MUL = 0x2000033, 182 OPC_MULH = 0x2001033, 183 OPC_MULHSU = 0x2002033, 184 OPC_MULHU = 0x2003033, 185 OPC_OR = 0x6033, 186 OPC_ORI = 0x6013, 187 OPC_REM = 0x2006033, 188 OPC_REMU = 0x2007033, 189 OPC_SB = 0x23, 190 OPC_SD = 0x3023, 191 OPC_SH = 0x1023, 192 OPC_SLL = 0x1033, 193 OPC_SLLI = 0x1013, 194 OPC_SLT = 0x2033, 195 OPC_SLTI = 0x2013, 196 OPC_SLTIU = 0x3013, 197 OPC_SLTU = 0x3033, 198 OPC_SRA = 0x40005033, 199 OPC_SRAI = 0x40005013, 200 OPC_SRL = 0x5033, 201 OPC_SRLI = 0x5013, 202 OPC_SUB = 0x40000033, 203 OPC_SW = 0x2023, 204 OPC_XOR = 0x4033, 205 OPC_XORI = 0x4013, 206 207 OPC_ADDIW = 0x1b, 208 OPC_ADDW = 0x3b, 209 OPC_DIVUW = 0x200503b, 210 OPC_DIVW = 0x200403b, 211 OPC_MULW = 0x200003b, 212 OPC_REMUW = 0x200703b, 213 OPC_REMW = 0x200603b, 214 OPC_SLLIW = 0x101b, 215 OPC_SLLW = 0x103b, 216 OPC_SRAIW = 0x4000501b, 217 OPC_SRAW = 0x4000503b, 218 OPC_SRLIW = 0x501b, 219 OPC_SRLW = 0x503b, 220 OPC_SUBW = 0x4000003b, 221 222 OPC_FENCE = 0x0000000f, 223 OPC_NOP = OPC_ADDI, /* nop = addi r0,r0,0 */ 224 225 /* Zba: Bit manipulation extension, address generation */ 226 OPC_ADD_UW = 0x0800003b, 227 228 /* Zbb: Bit manipulation extension, basic bit manipulation */ 229 OPC_ANDN = 0x40007033, 230 OPC_CLZ = 0x60001013, 231 OPC_CLZW = 0x6000101b, 232 OPC_CPOP = 0x60201013, 233 OPC_CPOPW = 0x6020101b, 234 OPC_CTZ = 0x60101013, 235 OPC_CTZW = 0x6010101b, 236 OPC_ORN = 0x40006033, 237 OPC_REV8 = 0x6b805013, 238 OPC_ROL = 0x60001033, 239 OPC_ROLW = 0x6000103b, 240 OPC_ROR = 0x60005033, 241 OPC_RORW = 0x6000503b, 242 OPC_RORI = 0x60005013, 243 OPC_RORIW = 0x6000501b, 244 OPC_SEXT_B = 0x60401013, 245 OPC_SEXT_H = 0x60501013, 246 OPC_XNOR = 0x40004033, 247 OPC_ZEXT_H = 0x0800403b, 248 249 /* Zicond: integer conditional operations */ 250 OPC_CZERO_EQZ = 0x0e005033, 251 OPC_CZERO_NEZ = 0x0e007033, 252 253 /* V: Vector extension 1.0 */ 254 OPC_VSETVLI = 0x57 | V_OPCFG, 255 OPC_VSETIVLI = 0xc0000057 | V_OPCFG, 256 OPC_VSETVL = 0x80000057 | V_OPCFG, 257 258 OPC_VLE8_V = 0x7 | V_UNIT_STRIDE, 259 OPC_VLE16_V = 0x5007 | V_UNIT_STRIDE, 260 OPC_VLE32_V = 0x6007 | V_UNIT_STRIDE, 261 OPC_VLE64_V = 0x7007 | V_UNIT_STRIDE, 262 OPC_VSE8_V = 0x27 | V_UNIT_STRIDE, 263 OPC_VSE16_V = 0x5027 | V_UNIT_STRIDE, 264 OPC_VSE32_V = 0x6027 | V_UNIT_STRIDE, 265 OPC_VSE64_V = 0x7027 | V_UNIT_STRIDE, 266 267 OPC_VL1RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(0), 268 OPC_VL2RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), 269 OPC_VL4RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), 270 OPC_VL8RE64_V = 0x2007007 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), 271 272 OPC_VS1R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(0), 273 OPC_VS2R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(1), 274 OPC_VS4R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(3), 275 OPC_VS8R_V = 0x2000027 | V_UNIT_STRIDE_WHOLE_REG | V_NF(7), 276 277 OPC_VMERGE_VIM = 0x5c000057 | V_OPIVI, 278 OPC_VMERGE_VVM = 0x5c000057 | V_OPIVV, 279 280 OPC_VADD_VV = 0x57 | V_OPIVV, 281 OPC_VADD_VI = 0x57 | V_OPIVI, 282 OPC_VSUB_VV = 0x8000057 | V_OPIVV, 283 OPC_VRSUB_VI = 0xc000057 | V_OPIVI, 284 OPC_VAND_VV = 0x24000057 | V_OPIVV, 285 OPC_VAND_VI = 0x24000057 | V_OPIVI, 286 OPC_VOR_VV = 0x28000057 | V_OPIVV, 287 OPC_VOR_VI = 0x28000057 | V_OPIVI, 288 OPC_VXOR_VV = 0x2c000057 | V_OPIVV, 289 OPC_VXOR_VI = 0x2c000057 | V_OPIVI, 290 291 OPC_VMUL_VV = 0x94000057 | V_OPMVV, 292 OPC_VSADD_VV = 0x84000057 | V_OPIVV, 293 OPC_VSADD_VI = 0x84000057 | V_OPIVI, 294 OPC_VSSUB_VV = 0x8c000057 | V_OPIVV, 295 OPC_VSSUB_VI = 0x8c000057 | V_OPIVI, 296 OPC_VSADDU_VV = 0x80000057 | V_OPIVV, 297 OPC_VSADDU_VI = 0x80000057 | V_OPIVI, 298 OPC_VSSUBU_VV = 0x88000057 | V_OPIVV, 299 OPC_VSSUBU_VI = 0x88000057 | V_OPIVI, 300 301 OPC_VMAX_VV = 0x1c000057 | V_OPIVV, 302 OPC_VMAX_VI = 0x1c000057 | V_OPIVI, 303 OPC_VMAXU_VV = 0x18000057 | V_OPIVV, 304 OPC_VMAXU_VI = 0x18000057 | V_OPIVI, 305 OPC_VMIN_VV = 0x14000057 | V_OPIVV, 306 OPC_VMIN_VI = 0x14000057 | V_OPIVI, 307 OPC_VMINU_VV = 0x10000057 | V_OPIVV, 308 OPC_VMINU_VI = 0x10000057 | V_OPIVI, 309 310 OPC_VMSEQ_VV = 0x60000057 | V_OPIVV, 311 OPC_VMSEQ_VI = 0x60000057 | V_OPIVI, 312 OPC_VMSEQ_VX = 0x60000057 | V_OPIVX, 313 OPC_VMSNE_VV = 0x64000057 | V_OPIVV, 314 OPC_VMSNE_VI = 0x64000057 | V_OPIVI, 315 OPC_VMSNE_VX = 0x64000057 | V_OPIVX, 316 317 OPC_VMSLTU_VV = 0x68000057 | V_OPIVV, 318 OPC_VMSLTU_VX = 0x68000057 | V_OPIVX, 319 OPC_VMSLT_VV = 0x6c000057 | V_OPIVV, 320 OPC_VMSLT_VX = 0x6c000057 | V_OPIVX, 321 OPC_VMSLEU_VV = 0x70000057 | V_OPIVV, 322 OPC_VMSLEU_VX = 0x70000057 | V_OPIVX, 323 OPC_VMSLE_VV = 0x74000057 | V_OPIVV, 324 OPC_VMSLE_VX = 0x74000057 | V_OPIVX, 325 326 OPC_VMSLEU_VI = 0x70000057 | V_OPIVI, 327 OPC_VMSLE_VI = 0x74000057 | V_OPIVI, 328 OPC_VMSGTU_VI = 0x78000057 | V_OPIVI, 329 OPC_VMSGTU_VX = 0x78000057 | V_OPIVX, 330 OPC_VMSGT_VI = 0x7c000057 | V_OPIVI, 331 OPC_VMSGT_VX = 0x7c000057 | V_OPIVX, 332 333 OPC_VSLL_VV = 0x94000057 | V_OPIVV, 334 OPC_VSLL_VI = 0x94000057 | V_OPIVI, 335 OPC_VSLL_VX = 0x94000057 | V_OPIVX, 336 OPC_VSRL_VV = 0xa0000057 | V_OPIVV, 337 OPC_VSRL_VI = 0xa0000057 | V_OPIVI, 338 OPC_VSRL_VX = 0xa0000057 | V_OPIVX, 339 OPC_VSRA_VV = 0xa4000057 | V_OPIVV, 340 OPC_VSRA_VI = 0xa4000057 | V_OPIVI, 341 OPC_VSRA_VX = 0xa4000057 | V_OPIVX, 342 343 OPC_VMV_V_V = 0x5e000057 | V_OPIVV, 344 OPC_VMV_V_I = 0x5e000057 | V_OPIVI, 345 OPC_VMV_V_X = 0x5e000057 | V_OPIVX, 346 347 OPC_VMVNR_V = 0x9e000057 | V_OPIVI, 348} RISCVInsn; 349 350static const struct { 351 RISCVInsn op; 352 bool swap; 353} tcg_cmpcond_to_rvv_vv[] = { 354 [TCG_COND_EQ] = { OPC_VMSEQ_VV, false }, 355 [TCG_COND_NE] = { OPC_VMSNE_VV, false }, 356 [TCG_COND_LT] = { OPC_VMSLT_VV, false }, 357 [TCG_COND_GE] = { OPC_VMSLE_VV, true }, 358 [TCG_COND_GT] = { OPC_VMSLT_VV, true }, 359 [TCG_COND_LE] = { OPC_VMSLE_VV, false }, 360 [TCG_COND_LTU] = { OPC_VMSLTU_VV, false }, 361 [TCG_COND_GEU] = { OPC_VMSLEU_VV, true }, 362 [TCG_COND_GTU] = { OPC_VMSLTU_VV, true }, 363 [TCG_COND_LEU] = { OPC_VMSLEU_VV, false } 364}; 365 366static const struct { 367 RISCVInsn op; 368 int min; 369 int max; 370 bool adjust; 371} tcg_cmpcond_to_rvv_vi[] = { 372 [TCG_COND_EQ] = { OPC_VMSEQ_VI, -16, 15, false }, 373 [TCG_COND_NE] = { OPC_VMSNE_VI, -16, 15, false }, 374 [TCG_COND_GT] = { OPC_VMSGT_VI, -16, 15, false }, 375 [TCG_COND_LE] = { OPC_VMSLE_VI, -16, 15, false }, 376 [TCG_COND_LT] = { OPC_VMSLE_VI, -15, 16, true }, 377 [TCG_COND_GE] = { OPC_VMSGT_VI, -15, 16, true }, 378 [TCG_COND_LEU] = { OPC_VMSLEU_VI, 0, 15, false }, 379 [TCG_COND_GTU] = { OPC_VMSGTU_VI, 0, 15, false }, 380 [TCG_COND_LTU] = { OPC_VMSLEU_VI, 1, 16, true }, 381 [TCG_COND_GEU] = { OPC_VMSGTU_VI, 1, 16, true }, 382}; 383 384/* test if a constant matches the constraint */ 385static bool tcg_target_const_match(int64_t val, int ct, 386 TCGType type, TCGCond cond, int vece) 387{ 388 if (ct & TCG_CT_CONST) { 389 return 1; 390 } 391 if (type >= TCG_TYPE_V64) { 392 /* Val is replicated by VECE; extract the highest element. */ 393 val >>= (-8 << vece) & 63; 394 } 395 /* 396 * Sign extended from 12 bits: [-0x800, 0x7ff]. 397 * Used for most arithmetic, as this is the isa field. 398 */ 399 if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { 400 return 1; 401 } 402 /* 403 * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. 404 * Used by movcond, which may need the negative value, 405 * and requires the modified constant to be representable. 406 */ 407 if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { 408 return 1; 409 } 410 /* 411 * Sign extended from 5 bits: [-0x10, 0x0f]. 412 * Used for vector-immediate. 413 */ 414 if ((ct & TCG_CT_CONST_S5) && val >= -0x10 && val <= 0x0f) { 415 return 1; 416 } 417 /* 418 * Used for vector compare OPIVI instructions. 419 */ 420 if ((ct & TCG_CT_CONST_CMP_VI) && 421 val >= tcg_cmpcond_to_rvv_vi[cond].min && 422 val <= tcg_cmpcond_to_rvv_vi[cond].max) { 423 return true; 424 } 425 return 0; 426} 427 428/* 429 * RISC-V immediate and instruction encoders (excludes 16-bit RVC) 430 */ 431 432/* Type-R */ 433 434static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) 435{ 436 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; 437} 438 439/* Type-I */ 440 441static int32_t encode_imm12(uint32_t imm) 442{ 443 return (imm & 0xfff) << 20; 444} 445 446static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) 447{ 448 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); 449} 450 451/* Type-S */ 452 453static int32_t encode_simm12(uint32_t imm) 454{ 455 int32_t ret = 0; 456 457 ret |= (imm & 0xFE0) << 20; 458 ret |= (imm & 0x1F) << 7; 459 460 return ret; 461} 462 463static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 464{ 465 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); 466} 467 468/* Type-SB */ 469 470static int32_t encode_sbimm12(uint32_t imm) 471{ 472 int32_t ret = 0; 473 474 ret |= (imm & 0x1000) << 19; 475 ret |= (imm & 0x7e0) << 20; 476 ret |= (imm & 0x1e) << 7; 477 ret |= (imm & 0x800) >> 4; 478 479 return ret; 480} 481 482static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 483{ 484 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); 485} 486 487/* Type-U */ 488 489static int32_t encode_uimm20(uint32_t imm) 490{ 491 return imm & 0xfffff000; 492} 493 494static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) 495{ 496 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); 497} 498 499/* Type-UJ */ 500 501static int32_t encode_ujimm20(uint32_t imm) 502{ 503 int32_t ret = 0; 504 505 ret |= (imm & 0x0007fe) << (21 - 1); 506 ret |= (imm & 0x000800) << (20 - 11); 507 ret |= (imm & 0x0ff000) << (12 - 12); 508 ret |= (imm & 0x100000) << (31 - 20); 509 510 return ret; 511} 512 513static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) 514{ 515 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); 516} 517 518 519/* Type-OPIVI */ 520 521static int32_t encode_vi(RISCVInsn opc, TCGReg rd, int32_t imm, 522 TCGReg vs2, bool vm) 523{ 524 return opc | (rd & 0x1f) << 7 | (imm & 0x1f) << 15 | 525 (vs2 & 0x1f) << 20 | (vm << 25); 526} 527 528/* Type-OPIVV/OPMVV/OPIVX/OPMVX, Vector load and store */ 529 530static int32_t encode_v(RISCVInsn opc, TCGReg d, TCGReg s1, 531 TCGReg s2, bool vm) 532{ 533 return opc | (d & 0x1f) << 7 | (s1 & 0x1f) << 15 | 534 (s2 & 0x1f) << 20 | (vm << 25); 535} 536 537/* Vector vtype */ 538 539static uint32_t encode_vtype(bool vta, bool vma, 540 MemOp vsew, RISCVVlmul vlmul) 541{ 542 return vma << 7 | vta << 6 | vsew << 3 | vlmul; 543} 544 545static int32_t encode_vset(RISCVInsn opc, TCGReg rd, 546 TCGArg rs1, uint32_t vtype) 547{ 548 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (vtype & 0x7ff) << 20; 549} 550 551static int32_t encode_vseti(RISCVInsn opc, TCGReg rd, 552 uint32_t uimm, uint32_t vtype) 553{ 554 return opc | (rd & 0x1f) << 7 | (uimm & 0x1f) << 15 | (vtype & 0x3ff) << 20; 555} 556 557/* 558 * RISC-V instruction emitters 559 */ 560 561static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc, 562 TCGReg rd, TCGReg rs1, TCGReg rs2) 563{ 564 tcg_out32(s, encode_r(opc, rd, rs1, rs2)); 565} 566 567static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc, 568 TCGReg rd, TCGReg rs1, TCGArg imm) 569{ 570 tcg_out32(s, encode_i(opc, rd, rs1, imm)); 571} 572 573static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc, 574 TCGReg rs1, TCGReg rs2, uint32_t imm) 575{ 576 tcg_out32(s, encode_s(opc, rs1, rs2, imm)); 577} 578 579static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc, 580 TCGReg rs1, TCGReg rs2, uint32_t imm) 581{ 582 tcg_out32(s, encode_sb(opc, rs1, rs2, imm)); 583} 584 585static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc, 586 TCGReg rd, uint32_t imm) 587{ 588 tcg_out32(s, encode_u(opc, rd, imm)); 589} 590 591static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, 592 TCGReg rd, uint32_t imm) 593{ 594 tcg_out32(s, encode_uj(opc, rd, imm)); 595} 596 597static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 598{ 599 int i; 600 for (i = 0; i < count; ++i) { 601 p[i] = OPC_NOP; 602 } 603} 604 605/* 606 * Relocations 607 */ 608 609static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 610{ 611 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 612 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 613 614 tcg_debug_assert((offset & 1) == 0); 615 if (offset == sextreg(offset, 0, 12)) { 616 *src_rw |= encode_sbimm12(offset); 617 return true; 618 } 619 620 return false; 621} 622 623static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 624{ 625 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 626 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 627 628 tcg_debug_assert((offset & 1) == 0); 629 if (offset == sextreg(offset, 0, 20)) { 630 *src_rw |= encode_ujimm20(offset); 631 return true; 632 } 633 634 return false; 635} 636 637static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 638{ 639 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 640 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 641 int32_t lo = sextreg(offset, 0, 12); 642 int32_t hi = offset - lo; 643 644 if (offset == hi + lo) { 645 src_rw[0] |= encode_uimm20(hi); 646 src_rw[1] |= encode_imm12(lo); 647 return true; 648 } 649 650 return false; 651} 652 653static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 654 intptr_t value, intptr_t addend) 655{ 656 tcg_debug_assert(addend == 0); 657 switch (type) { 658 case R_RISCV_BRANCH: 659 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); 660 case R_RISCV_JAL: 661 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); 662 case R_RISCV_CALL: 663 return reloc_call(code_ptr, (tcg_insn_unit *)value); 664 default: 665 g_assert_not_reached(); 666 } 667} 668 669/* 670 * RISC-V vector instruction emitters 671 */ 672 673/* 674 * Vector registers uses the same 5 lower bits as GPR registers, 675 * and vm=0 (vm = false) means vector masking ENABLED. 676 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the 677 * second operand. 678 */ 679static void tcg_out_opc_vv(TCGContext *s, RISCVInsn opc, 680 TCGReg vd, TCGReg vs2, TCGReg vs1) 681{ 682 tcg_out32(s, encode_v(opc, vd, vs1, vs2, true)); 683} 684 685static void tcg_out_opc_vx(TCGContext *s, RISCVInsn opc, 686 TCGReg vd, TCGReg vs2, TCGReg rs1) 687{ 688 tcg_out32(s, encode_v(opc, vd, rs1, vs2, true)); 689} 690 691static void tcg_out_opc_vi(TCGContext *s, RISCVInsn opc, 692 TCGReg vd, TCGReg vs2, int32_t imm) 693{ 694 tcg_out32(s, encode_vi(opc, vd, imm, vs2, true)); 695} 696 697static void tcg_out_opc_vv_vi(TCGContext *s, RISCVInsn o_vv, RISCVInsn o_vi, 698 TCGReg vd, TCGReg vs2, TCGArg vi1, int c_vi1) 699{ 700 if (c_vi1) { 701 tcg_out_opc_vi(s, o_vi, vd, vs2, vi1); 702 } else { 703 tcg_out_opc_vv(s, o_vv, vd, vs2, vi1); 704 } 705} 706 707static void tcg_out_opc_vim_mask(TCGContext *s, RISCVInsn opc, TCGReg vd, 708 TCGReg vs2, int32_t imm) 709{ 710 tcg_out32(s, encode_vi(opc, vd, imm, vs2, false)); 711} 712 713static void tcg_out_opc_vvm_mask(TCGContext *s, RISCVInsn opc, TCGReg vd, 714 TCGReg vs2, TCGReg vs1) 715{ 716 tcg_out32(s, encode_v(opc, vd, vs1, vs2, false)); 717} 718 719typedef struct VsetCache { 720 uint32_t movi_insn; 721 uint32_t vset_insn; 722} VsetCache; 723 724static VsetCache riscv_vset_cache[3][4]; 725 726static void set_vtype(TCGContext *s, TCGType type, MemOp vsew) 727{ 728 const VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew]; 729 730 s->riscv_cur_type = type; 731 s->riscv_cur_vsew = vsew; 732 733 if (p->movi_insn) { 734 tcg_out32(s, p->movi_insn); 735 } 736 tcg_out32(s, p->vset_insn); 737} 738 739static MemOp set_vtype_len(TCGContext *s, TCGType type) 740{ 741 if (type != s->riscv_cur_type) { 742 set_vtype(s, type, MO_64); 743 } 744 return s->riscv_cur_vsew; 745} 746 747static void set_vtype_len_sew(TCGContext *s, TCGType type, MemOp vsew) 748{ 749 if (type != s->riscv_cur_type || vsew != s->riscv_cur_vsew) { 750 set_vtype(s, type, vsew); 751 } 752} 753 754/* 755 * TCG intrinsics 756 */ 757 758static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 759{ 760 if (ret == arg) { 761 return true; 762 } 763 switch (type) { 764 case TCG_TYPE_I32: 765 case TCG_TYPE_I64: 766 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); 767 break; 768 case TCG_TYPE_V64: 769 case TCG_TYPE_V128: 770 case TCG_TYPE_V256: 771 { 772 int lmul = type - riscv_lg2_vlenb; 773 int nf = 1 << MAX(lmul, 0); 774 tcg_out_opc_vi(s, OPC_VMVNR_V, ret, arg, nf - 1); 775 } 776 break; 777 default: 778 g_assert_not_reached(); 779 } 780 return true; 781} 782 783static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 784 tcg_target_long val) 785{ 786 tcg_target_long lo, hi, tmp; 787 int shift, ret; 788 789 if (type == TCG_TYPE_I32) { 790 val = (int32_t)val; 791 } 792 793 lo = sextreg(val, 0, 12); 794 if (val == lo) { 795 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo); 796 return; 797 } 798 799 hi = val - lo; 800 if (val == (int32_t)val) { 801 tcg_out_opc_upper(s, OPC_LUI, rd, hi); 802 if (lo != 0) { 803 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); 804 } 805 return; 806 } 807 808 tmp = tcg_pcrel_diff(s, (void *)val); 809 if (tmp == (int32_t)tmp) { 810 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 811 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); 812 ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val); 813 tcg_debug_assert(ret == true); 814 return; 815 } 816 817 /* Look for a single 20-bit section. */ 818 shift = ctz64(val); 819 tmp = val >> shift; 820 if (tmp == sextreg(tmp, 0, 20)) { 821 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12); 822 if (shift > 12) { 823 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12); 824 } else { 825 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift); 826 } 827 return; 828 } 829 830 /* Look for a few high zero bits, with lots of bits set in the middle. */ 831 shift = clz64(val); 832 tmp = val << shift; 833 if (tmp == sextreg(tmp, 12, 20) << 12) { 834 tcg_out_opc_upper(s, OPC_LUI, rd, tmp); 835 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 836 return; 837 } else if (tmp == sextreg(tmp, 0, 12)) { 838 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp); 839 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 840 return; 841 } 842 843 /* Drop into the constant pool. */ 844 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0); 845 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 846 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); 847} 848 849static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 850{ 851 return false; 852} 853 854static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 855 tcg_target_long imm) 856{ 857 /* This function is only used for passing structs by reference. */ 858 g_assert_not_reached(); 859} 860 861static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 862{ 863 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); 864} 865 866static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 867{ 868 if (cpuinfo & CPUINFO_ZBB) { 869 tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO); 870 } else { 871 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 872 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16); 873 } 874} 875 876static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 877{ 878 if (cpuinfo & CPUINFO_ZBA) { 879 tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO); 880 } else { 881 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); 882 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); 883 } 884} 885 886static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 887{ 888 if (cpuinfo & CPUINFO_ZBB) { 889 tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0); 890 } else { 891 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); 892 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); 893 } 894} 895 896static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 897{ 898 if (cpuinfo & CPUINFO_ZBB) { 899 tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0); 900 } else { 901 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 902 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); 903 } 904} 905 906static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 907{ 908 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); 909} 910 911static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 912{ 913 if (ret != arg) { 914 tcg_out_ext32s(s, ret, arg); 915 } 916} 917 918static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 919{ 920 tcg_out_ext32u(s, ret, arg); 921} 922 923static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 924{ 925 tcg_out_ext32s(s, ret, arg); 926} 927 928static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, 929 TCGReg addr, intptr_t offset) 930{ 931 intptr_t imm12 = sextreg(offset, 0, 12); 932 933 if (offset != imm12) { 934 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 935 936 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 937 imm12 = sextreg(diff, 0, 12); 938 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12); 939 } else { 940 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 941 if (addr != TCG_REG_ZERO) { 942 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr); 943 } 944 } 945 addr = TCG_REG_TMP2; 946 } 947 948 switch (opc) { 949 case OPC_SB: 950 case OPC_SH: 951 case OPC_SW: 952 case OPC_SD: 953 tcg_out_opc_store(s, opc, addr, data, imm12); 954 break; 955 case OPC_LB: 956 case OPC_LBU: 957 case OPC_LH: 958 case OPC_LHU: 959 case OPC_LW: 960 case OPC_LWU: 961 case OPC_LD: 962 tcg_out_opc_imm(s, opc, data, addr, imm12); 963 break; 964 default: 965 g_assert_not_reached(); 966 } 967} 968 969static void tcg_out_vec_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, 970 TCGReg addr, intptr_t offset) 971{ 972 tcg_debug_assert(data >= TCG_REG_V0); 973 tcg_debug_assert(addr < TCG_REG_V0); 974 975 if (offset) { 976 tcg_debug_assert(addr != TCG_REG_ZERO); 977 if (offset == sextreg(offset, 0, 12)) { 978 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP0, addr, offset); 979 } else { 980 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 981 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP0, addr); 982 } 983 addr = TCG_REG_TMP0; 984 } 985 tcg_out32(s, encode_v(opc, data, addr, 0, true)); 986} 987 988static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 989 TCGReg arg1, intptr_t arg2) 990{ 991 RISCVInsn insn; 992 993 switch (type) { 994 case TCG_TYPE_I32: 995 tcg_out_ldst(s, OPC_LW, arg, arg1, arg2); 996 break; 997 case TCG_TYPE_I64: 998 tcg_out_ldst(s, OPC_LD, arg, arg1, arg2); 999 break; 1000 case TCG_TYPE_V64: 1001 case TCG_TYPE_V128: 1002 case TCG_TYPE_V256: 1003 if (type >= riscv_lg2_vlenb) { 1004 static const RISCVInsn whole_reg_ld[] = { 1005 OPC_VL1RE64_V, OPC_VL2RE64_V, OPC_VL4RE64_V, OPC_VL8RE64_V 1006 }; 1007 unsigned idx = type - riscv_lg2_vlenb; 1008 1009 tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_ld)); 1010 insn = whole_reg_ld[idx]; 1011 } else { 1012 static const RISCVInsn unit_stride_ld[] = { 1013 OPC_VLE8_V, OPC_VLE16_V, OPC_VLE32_V, OPC_VLE64_V 1014 }; 1015 MemOp prev_vsew = set_vtype_len(s, type); 1016 1017 tcg_debug_assert(prev_vsew < ARRAY_SIZE(unit_stride_ld)); 1018 insn = unit_stride_ld[prev_vsew]; 1019 } 1020 tcg_out_vec_ldst(s, insn, arg, arg1, arg2); 1021 break; 1022 default: 1023 g_assert_not_reached(); 1024 } 1025} 1026 1027static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1028 TCGReg arg1, intptr_t arg2) 1029{ 1030 RISCVInsn insn; 1031 1032 switch (type) { 1033 case TCG_TYPE_I32: 1034 tcg_out_ldst(s, OPC_SW, arg, arg1, arg2); 1035 break; 1036 case TCG_TYPE_I64: 1037 tcg_out_ldst(s, OPC_SD, arg, arg1, arg2); 1038 break; 1039 case TCG_TYPE_V64: 1040 case TCG_TYPE_V128: 1041 case TCG_TYPE_V256: 1042 if (type >= riscv_lg2_vlenb) { 1043 static const RISCVInsn whole_reg_st[] = { 1044 OPC_VS1R_V, OPC_VS2R_V, OPC_VS4R_V, OPC_VS8R_V 1045 }; 1046 unsigned idx = type - riscv_lg2_vlenb; 1047 1048 tcg_debug_assert(idx < ARRAY_SIZE(whole_reg_st)); 1049 insn = whole_reg_st[idx]; 1050 } else { 1051 static const RISCVInsn unit_stride_st[] = { 1052 OPC_VSE8_V, OPC_VSE16_V, OPC_VSE32_V, OPC_VSE64_V 1053 }; 1054 MemOp prev_vsew = set_vtype_len(s, type); 1055 1056 tcg_debug_assert(prev_vsew < ARRAY_SIZE(unit_stride_st)); 1057 insn = unit_stride_st[prev_vsew]; 1058 } 1059 tcg_out_vec_ldst(s, insn, arg, arg1, arg2); 1060 break; 1061 default: 1062 g_assert_not_reached(); 1063 } 1064} 1065 1066static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1067 TCGReg base, intptr_t ofs) 1068{ 1069 if (val == 0) { 1070 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 1071 return true; 1072 } 1073 return false; 1074} 1075 1076static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1077 TCGReg dst, TCGReg src) 1078{ 1079 set_vtype_len_sew(s, type, vece); 1080 tcg_out_opc_vx(s, OPC_VMV_V_X, dst, 0, src); 1081 return true; 1082} 1083 1084static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1085 TCGReg dst, TCGReg base, intptr_t offset) 1086{ 1087 tcg_out_ld(s, TCG_TYPE_REG, TCG_REG_TMP0, base, offset); 1088 return tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); 1089} 1090 1091static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1092 TCGReg dst, int64_t arg) 1093{ 1094 /* Arg is replicated by VECE; extract the highest element. */ 1095 arg >>= (-8 << vece) & 63; 1096 1097 if (arg >= -16 && arg < 16) { 1098 if (arg == 0 || arg == -1) { 1099 set_vtype_len(s, type); 1100 } else { 1101 set_vtype_len_sew(s, type, vece); 1102 } 1103 tcg_out_opc_vi(s, OPC_VMV_V_I, dst, 0, arg); 1104 return; 1105 } 1106 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, arg); 1107 tcg_out_dup_vec(s, type, vece, dst, TCG_REG_TMP0); 1108} 1109 1110static const struct { 1111 RISCVInsn op; 1112 bool swap; 1113} tcg_brcond_to_riscv[] = { 1114 [TCG_COND_EQ] = { OPC_BEQ, false }, 1115 [TCG_COND_NE] = { OPC_BNE, false }, 1116 [TCG_COND_LT] = { OPC_BLT, false }, 1117 [TCG_COND_GE] = { OPC_BGE, false }, 1118 [TCG_COND_LE] = { OPC_BGE, true }, 1119 [TCG_COND_GT] = { OPC_BLT, true }, 1120 [TCG_COND_LTU] = { OPC_BLTU, false }, 1121 [TCG_COND_GEU] = { OPC_BGEU, false }, 1122 [TCG_COND_LEU] = { OPC_BGEU, true }, 1123 [TCG_COND_GTU] = { OPC_BLTU, true } 1124}; 1125 1126static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 1127 TCGReg arg1, TCGReg arg2, TCGLabel *l) 1128{ 1129 RISCVInsn op = tcg_brcond_to_riscv[cond].op; 1130 1131 tcg_debug_assert(op != 0); 1132 1133 if (tcg_brcond_to_riscv[cond].swap) { 1134 TCGReg t = arg1; 1135 arg1 = arg2; 1136 arg2 = t; 1137 } 1138 1139 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); 1140 tcg_out_opc_branch(s, op, arg1, arg2, 0); 1141} 1142 1143static const TCGOutOpBrcond outop_brcond = { 1144 .base.static_constraint = C_O0_I2(r, rz), 1145 .out_rr = tgen_brcond, 1146}; 1147 1148#define SETCOND_INV TCG_TARGET_NB_REGS 1149#define SETCOND_NEZ (SETCOND_INV << 1) 1150#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 1151 1152static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 1153 TCGReg arg1, tcg_target_long arg2, bool c2) 1154{ 1155 int flags = 0; 1156 1157 switch (cond) { 1158 case TCG_COND_EQ: /* -> NE */ 1159 case TCG_COND_GE: /* -> LT */ 1160 case TCG_COND_GEU: /* -> LTU */ 1161 case TCG_COND_GT: /* -> LE */ 1162 case TCG_COND_GTU: /* -> LEU */ 1163 cond = tcg_invert_cond(cond); 1164 flags ^= SETCOND_INV; 1165 break; 1166 default: 1167 break; 1168 } 1169 1170 switch (cond) { 1171 case TCG_COND_LE: 1172 case TCG_COND_LEU: 1173 /* 1174 * If we have a constant input, the most efficient way to implement 1175 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 1176 * We don't need to care for this for LE because the constant input 1177 * is constrained to signed 12-bit, and 0x800 is representable in the 1178 * temporary register. 1179 */ 1180 if (c2) { 1181 if (cond == TCG_COND_LEU) { 1182 /* unsigned <= -1 is true */ 1183 if (arg2 == -1) { 1184 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 1185 return ret; 1186 } 1187 cond = TCG_COND_LTU; 1188 } else { 1189 cond = TCG_COND_LT; 1190 } 1191 tcg_debug_assert(arg2 <= 0x7ff); 1192 if (++arg2 == 0x800) { 1193 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 1194 arg2 = TCG_REG_TMP0; 1195 c2 = false; 1196 } 1197 } else { 1198 TCGReg tmp = arg2; 1199 arg2 = arg1; 1200 arg1 = tmp; 1201 cond = tcg_swap_cond(cond); /* LE -> GE */ 1202 cond = tcg_invert_cond(cond); /* GE -> LT */ 1203 flags ^= SETCOND_INV; 1204 } 1205 break; 1206 default: 1207 break; 1208 } 1209 1210 switch (cond) { 1211 case TCG_COND_NE: 1212 flags |= SETCOND_NEZ; 1213 if (!c2) { 1214 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 1215 } else if (arg2 == 0) { 1216 ret = arg1; 1217 } else { 1218 tcg_out_opc_imm(s, OPC_XORI, ret, arg1, arg2); 1219 } 1220 break; 1221 1222 case TCG_COND_LT: 1223 if (c2) { 1224 tcg_out_opc_imm(s, OPC_SLTI, ret, arg1, arg2); 1225 } else { 1226 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 1227 } 1228 break; 1229 1230 case TCG_COND_LTU: 1231 if (c2) { 1232 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, arg2); 1233 } else { 1234 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 1235 } 1236 break; 1237 1238 default: 1239 g_assert_not_reached(); 1240 } 1241 1242 return ret | flags; 1243} 1244 1245static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 1246 TCGReg arg1, tcg_target_long arg2, bool c2) 1247{ 1248 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 1249 1250 if (tmpflags != ret) { 1251 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1252 1253 switch (tmpflags & SETCOND_FLAGS) { 1254 case SETCOND_INV: 1255 /* Intermediate result is boolean: simply invert. */ 1256 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 1257 break; 1258 case SETCOND_NEZ: 1259 /* Intermediate result is zero/non-zero: test != 0. */ 1260 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 1261 break; 1262 case SETCOND_NEZ | SETCOND_INV: 1263 /* Intermediate result is zero/non-zero: test == 0. */ 1264 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 1265 break; 1266 default: 1267 g_assert_not_reached(); 1268 } 1269 } 1270} 1271 1272static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 1273 TCGReg dest, TCGReg arg1, TCGReg arg2) 1274{ 1275 tcg_out_setcond(s, cond, dest, arg1, arg2, false); 1276} 1277 1278static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 1279 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 1280{ 1281 tcg_out_setcond(s, cond, dest, arg1, arg2, true); 1282} 1283 1284static const TCGOutOpSetcond outop_setcond = { 1285 .base.static_constraint = C_O1_I2(r, r, rI), 1286 .out_rrr = tgen_setcond, 1287 .out_rri = tgen_setcondi, 1288}; 1289 1290static void tcg_out_negsetcond(TCGContext *s, TCGCond cond, TCGReg ret, 1291 TCGReg arg1, tcg_target_long arg2, bool c2) 1292{ 1293 int tmpflags; 1294 TCGReg tmp; 1295 1296 /* For LT/GE comparison against 0, replicate the sign bit. */ 1297 if (c2 && arg2 == 0) { 1298 switch (cond) { 1299 case TCG_COND_GE: 1300 tcg_out_opc_imm(s, OPC_XORI, ret, arg1, -1); 1301 arg1 = ret; 1302 /* fall through */ 1303 case TCG_COND_LT: 1304 tcg_out_opc_imm(s, OPC_SRAI, ret, arg1, TCG_TARGET_REG_BITS - 1); 1305 return; 1306 default: 1307 break; 1308 } 1309 } 1310 1311 tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 1312 tmp = tmpflags & ~SETCOND_FLAGS; 1313 1314 /* If intermediate result is zero/non-zero: test != 0. */ 1315 if (tmpflags & SETCOND_NEZ) { 1316 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 1317 tmp = ret; 1318 } 1319 1320 /* Produce the 0/-1 result. */ 1321 if (tmpflags & SETCOND_INV) { 1322 tcg_out_opc_imm(s, OPC_ADDI, ret, tmp, -1); 1323 } else { 1324 tcg_out_opc_reg(s, OPC_SUB, ret, TCG_REG_ZERO, tmp); 1325 } 1326} 1327 1328static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 1329 TCGReg dest, TCGReg arg1, TCGReg arg2) 1330{ 1331 tcg_out_negsetcond(s, cond, dest, arg1, arg2, false); 1332} 1333 1334static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 1335 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 1336{ 1337 tcg_out_negsetcond(s, cond, dest, arg1, arg2, true); 1338} 1339 1340static const TCGOutOpSetcond outop_negsetcond = { 1341 .base.static_constraint = C_O1_I2(r, r, rI), 1342 .out_rrr = tgen_negsetcond, 1343 .out_rri = tgen_negsetcondi, 1344}; 1345 1346static void tcg_out_movcond_zicond(TCGContext *s, TCGReg ret, TCGReg test_ne, 1347 int val1, bool c_val1, 1348 int val2, bool c_val2) 1349{ 1350 if (val1 == 0) { 1351 if (c_val2) { 1352 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val2); 1353 val2 = TCG_REG_TMP1; 1354 } 1355 tcg_out_opc_reg(s, OPC_CZERO_NEZ, ret, val2, test_ne); 1356 return; 1357 } 1358 1359 if (val2 == 0) { 1360 if (c_val1) { 1361 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1); 1362 val1 = TCG_REG_TMP1; 1363 } 1364 tcg_out_opc_reg(s, OPC_CZERO_EQZ, ret, val1, test_ne); 1365 return; 1366 } 1367 1368 if (c_val2) { 1369 if (c_val1) { 1370 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1 - val2); 1371 } else { 1372 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val1, -val2); 1373 } 1374 tcg_out_opc_reg(s, OPC_CZERO_EQZ, ret, TCG_REG_TMP1, test_ne); 1375 tcg_out_opc_imm(s, OPC_ADDI, ret, ret, val2); 1376 return; 1377 } 1378 1379 if (c_val1) { 1380 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val2, -val1); 1381 tcg_out_opc_reg(s, OPC_CZERO_NEZ, ret, TCG_REG_TMP1, test_ne); 1382 tcg_out_opc_imm(s, OPC_ADDI, ret, ret, val1); 1383 return; 1384 } 1385 1386 tcg_out_opc_reg(s, OPC_CZERO_NEZ, TCG_REG_TMP1, val2, test_ne); 1387 tcg_out_opc_reg(s, OPC_CZERO_EQZ, TCG_REG_TMP0, val1, test_ne); 1388 tcg_out_opc_reg(s, OPC_OR, ret, TCG_REG_TMP0, TCG_REG_TMP1); 1389} 1390 1391static void tcg_out_movcond_br1(TCGContext *s, TCGCond cond, TCGReg ret, 1392 TCGReg cmp1, TCGReg cmp2, 1393 int val, bool c_val) 1394{ 1395 RISCVInsn op; 1396 int disp = 8; 1397 1398 tcg_debug_assert((unsigned)cond < ARRAY_SIZE(tcg_brcond_to_riscv)); 1399 op = tcg_brcond_to_riscv[cond].op; 1400 tcg_debug_assert(op != 0); 1401 1402 if (tcg_brcond_to_riscv[cond].swap) { 1403 tcg_out_opc_branch(s, op, cmp2, cmp1, disp); 1404 } else { 1405 tcg_out_opc_branch(s, op, cmp1, cmp2, disp); 1406 } 1407 if (c_val) { 1408 tcg_out_opc_imm(s, OPC_ADDI, ret, TCG_REG_ZERO, val); 1409 } else { 1410 tcg_out_opc_imm(s, OPC_ADDI, ret, val, 0); 1411 } 1412} 1413 1414static void tcg_out_movcond_br2(TCGContext *s, TCGCond cond, TCGReg ret, 1415 TCGReg cmp1, TCGReg cmp2, 1416 int val1, bool c_val1, 1417 int val2, bool c_val2) 1418{ 1419 TCGReg tmp; 1420 1421 /* TCG optimizer reorders to prefer ret matching val2. */ 1422 if (!c_val2 && ret == val2) { 1423 cond = tcg_invert_cond(cond); 1424 tcg_out_movcond_br1(s, cond, ret, cmp1, cmp2, val1, c_val1); 1425 return; 1426 } 1427 1428 if (!c_val1 && ret == val1) { 1429 tcg_out_movcond_br1(s, cond, ret, cmp1, cmp2, val2, c_val2); 1430 return; 1431 } 1432 1433 tmp = (ret == cmp1 || ret == cmp2 ? TCG_REG_TMP1 : ret); 1434 if (c_val1) { 1435 tcg_out_movi(s, TCG_TYPE_REG, tmp, val1); 1436 } else { 1437 tcg_out_mov(s, TCG_TYPE_REG, tmp, val1); 1438 } 1439 tcg_out_movcond_br1(s, cond, tmp, cmp1, cmp2, val2, c_val2); 1440 tcg_out_mov(s, TCG_TYPE_REG, ret, tmp); 1441} 1442 1443static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, 1444 TCGReg ret, TCGReg cmp1, TCGArg cmp2, bool c_cmp2, 1445 TCGArg val1, bool c_val1, 1446 TCGArg val2, bool c_val2) 1447{ 1448 int tmpflags; 1449 TCGReg t; 1450 1451 if (!(cpuinfo & CPUINFO_ZICOND) && (!c_cmp2 || cmp2 == 0)) { 1452 tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2, 1453 val1, c_val1, val2, c_val2); 1454 return; 1455 } 1456 1457 tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2); 1458 t = tmpflags & ~SETCOND_FLAGS; 1459 1460 if (cpuinfo & CPUINFO_ZICOND) { 1461 if (tmpflags & SETCOND_INV) { 1462 tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1); 1463 } else { 1464 tcg_out_movcond_zicond(s, ret, t, val1, c_val1, val2, c_val2); 1465 } 1466 } else { 1467 cond = tmpflags & SETCOND_INV ? TCG_COND_EQ : TCG_COND_NE; 1468 tcg_out_movcond_br2(s, cond, ret, t, TCG_REG_ZERO, 1469 val1, c_val1, val2, c_val2); 1470 } 1471} 1472 1473static const TCGOutOpMovcond outop_movcond = { 1474 .base.static_constraint = C_O1_I4(r, r, rI, rM, rM), 1475 .out = tcg_out_movcond, 1476}; 1477 1478static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn, 1479 TCGReg ret, TCGReg src1, int src2, bool c_src2) 1480{ 1481 tcg_out_opc_imm(s, insn, ret, src1, 0); 1482 1483 if (!c_src2 || src2 != (type == TCG_TYPE_I32 ? 32 : 64)) { 1484 /* 1485 * The requested zero result does not match the insn, so adjust. 1486 * Note that constraints put 'ret' in a new register, so the 1487 * computation above did not clobber either 'src1' or 'src2'. 1488 */ 1489 tcg_out_movcond(s, type, TCG_COND_EQ, ret, src1, 0, true, 1490 src2, c_src2, ret, false); 1491 } 1492} 1493 1494static void tcg_out_cmpsel(TCGContext *s, TCGType type, unsigned vece, 1495 TCGCond cond, TCGReg ret, 1496 TCGReg cmp1, TCGReg cmp2, bool c_cmp2, 1497 TCGReg val1, bool c_val1, 1498 TCGReg val2, bool c_val2) 1499{ 1500 set_vtype_len_sew(s, type, vece); 1501 1502 /* Use only vmerge_vim if possible, by inverting the test. */ 1503 if (c_val2 && !c_val1) { 1504 TCGArg temp = val1; 1505 cond = tcg_invert_cond(cond); 1506 val1 = val2; 1507 val2 = temp; 1508 c_val1 = true; 1509 c_val2 = false; 1510 } 1511 1512 /* Perform the comparison into V0 mask. */ 1513 if (c_cmp2) { 1514 tcg_out_opc_vi(s, tcg_cmpcond_to_rvv_vi[cond].op, TCG_REG_V0, cmp1, 1515 cmp2 - tcg_cmpcond_to_rvv_vi[cond].adjust); 1516 } else if (tcg_cmpcond_to_rvv_vv[cond].swap) { 1517 tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, 1518 TCG_REG_V0, cmp2, cmp1); 1519 } else { 1520 tcg_out_opc_vv(s, tcg_cmpcond_to_rvv_vv[cond].op, 1521 TCG_REG_V0, cmp1, cmp2); 1522 } 1523 if (c_val1) { 1524 if (c_val2) { 1525 tcg_out_opc_vi(s, OPC_VMV_V_I, ret, 0, val2); 1526 val2 = ret; 1527 } 1528 /* vd[i] == v0.mask[i] ? imm : vs2[i] */ 1529 tcg_out_opc_vim_mask(s, OPC_VMERGE_VIM, ret, val2, val1); 1530 } else { 1531 /* vd[i] == v0.mask[i] ? vs1[i] : vs2[i] */ 1532 tcg_out_opc_vvm_mask(s, OPC_VMERGE_VVM, ret, val2, val1); 1533 } 1534} 1535 1536static void tcg_out_vshifti(TCGContext *s, RISCVInsn opc_vi, RISCVInsn opc_vx, 1537 TCGReg dst, TCGReg src, unsigned imm) 1538{ 1539 if (imm < 32) { 1540 tcg_out_opc_vi(s, opc_vi, dst, src, imm); 1541 } else { 1542 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_TMP0, imm); 1543 tcg_out_opc_vx(s, opc_vx, dst, src, TCG_REG_TMP0); 1544 } 1545} 1546 1547static void init_setting_vtype(TCGContext *s) 1548{ 1549 s->riscv_cur_type = TCG_TYPE_COUNT; 1550} 1551 1552static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1553{ 1554 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 1555 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 1556 int ret; 1557 1558 init_setting_vtype(s); 1559 1560 tcg_debug_assert((offset & 1) == 0); 1561 if (offset == sextreg(offset, 0, 20)) { 1562 /* short jump: -2097150 to 2097152 */ 1563 tcg_out_opc_jump(s, OPC_JAL, link, offset); 1564 } else if (offset == (int32_t)offset) { 1565 /* long jump: -2147483646 to 2147483648 */ 1566 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); 1567 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); 1568 ret = reloc_call(s->code_ptr - 2, arg); 1569 tcg_debug_assert(ret == true); 1570 } else { 1571 /* far jump: 64-bit */ 1572 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); 1573 tcg_target_long base = (tcg_target_long)arg - imm; 1574 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); 1575 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); 1576 } 1577} 1578 1579static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1580 const TCGHelperInfo *info) 1581{ 1582 tcg_out_call_int(s, arg, false); 1583} 1584 1585static void tcg_out_mb(TCGContext *s, TCGArg a0) 1586{ 1587 tcg_insn_unit insn = OPC_FENCE; 1588 1589 if (a0 & TCG_MO_LD_LD) { 1590 insn |= 0x02200000; 1591 } 1592 if (a0 & TCG_MO_ST_LD) { 1593 insn |= 0x01200000; 1594 } 1595 if (a0 & TCG_MO_LD_ST) { 1596 insn |= 0x02100000; 1597 } 1598 if (a0 & TCG_MO_ST_ST) { 1599 insn |= 0x01100000; 1600 } 1601 tcg_out32(s, insn); 1602} 1603 1604/* 1605 * Load/store and TLB 1606 */ 1607 1608static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 1609{ 1610 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 1611 bool ok = reloc_jimm20(s->code_ptr - 1, target); 1612 tcg_debug_assert(ok); 1613} 1614 1615bool tcg_target_has_memory_bswap(MemOp memop) 1616{ 1617 return false; 1618} 1619 1620/* We have three temps, we might as well expose them. */ 1621static const TCGLdstHelperParam ldst_helper_param = { 1622 .ntmp = 3, .tmp = { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 } 1623}; 1624 1625static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1626{ 1627 MemOp opc = get_memop(l->oi); 1628 1629 /* resolve label address */ 1630 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1631 return false; 1632 } 1633 1634 /* call load helper */ 1635 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1636 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1637 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1638 1639 tcg_out_goto(s, l->raddr); 1640 return true; 1641} 1642 1643static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1644{ 1645 MemOp opc = get_memop(l->oi); 1646 1647 /* resolve label address */ 1648 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1649 return false; 1650 } 1651 1652 /* call store helper */ 1653 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1654 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1655 1656 tcg_out_goto(s, l->raddr); 1657 return true; 1658} 1659 1660/* We expect to use a 12-bit negative offset from ENV. */ 1661#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 1662 1663/* 1664 * For system-mode, perform the TLB load and compare. 1665 * For user-mode, perform any required alignment tests. 1666 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1667 * is required and fill in @h with the host address for the fast path. 1668 */ 1669static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, 1670 TCGReg addr_reg, MemOpIdx oi, 1671 bool is_ld) 1672{ 1673 TCGType addr_type = s->addr_type; 1674 TCGLabelQemuLdst *ldst = NULL; 1675 MemOp opc = get_memop(oi); 1676 TCGAtomAlign aa; 1677 unsigned a_mask; 1678 1679 aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1680 a_mask = (1u << aa.align) - 1; 1681 1682 if (tcg_use_softmmu) { 1683 unsigned s_bits = opc & MO_SIZE; 1684 unsigned s_mask = (1u << s_bits) - 1; 1685 int mem_index = get_mmuidx(oi); 1686 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 1687 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 1688 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 1689 int compare_mask; 1690 TCGReg addr_adj; 1691 1692 ldst = new_ldst_label(s); 1693 ldst->is_ld = is_ld; 1694 ldst->oi = oi; 1695 ldst->addr_reg = addr_reg; 1696 1697 init_setting_vtype(s); 1698 1699 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 1700 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 1701 1702 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, 1703 s->page_bits - CPU_TLB_ENTRY_BITS); 1704 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 1705 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 1706 1707 /* 1708 * For aligned accesses, we check the first byte and include the 1709 * alignment bits within the address. For unaligned access, we 1710 * check that we don't cross pages using the address of the last 1711 * byte of the access. 1712 */ 1713 addr_adj = addr_reg; 1714 if (a_mask < s_mask) { 1715 addr_adj = TCG_REG_TMP0; 1716 tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI, 1717 addr_adj, addr_reg, s_mask - a_mask); 1718 } 1719 compare_mask = s->page_mask | a_mask; 1720 if (compare_mask == sextreg(compare_mask, 0, 12)) { 1721 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask); 1722 } else { 1723 tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask); 1724 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj); 1725 } 1726 1727 /* Load the tlb comparator and the addend. */ 1728 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 1729 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 1730 is_ld ? offsetof(CPUTLBEntry, addr_read) 1731 : offsetof(CPUTLBEntry, addr_write)); 1732 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 1733 offsetof(CPUTLBEntry, addend)); 1734 1735 /* Compare masked address with the TLB entry. */ 1736 ldst->label_ptr[0] = s->code_ptr; 1737 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1738 1739 /* TLB Hit - translate address using addend. */ 1740 if (addr_type != TCG_TYPE_I32) { 1741 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); 1742 } else if (cpuinfo & CPUINFO_ZBA) { 1743 tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, 1744 addr_reg, TCG_REG_TMP2); 1745 } else { 1746 tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); 1747 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, 1748 TCG_REG_TMP0, TCG_REG_TMP2); 1749 } 1750 *pbase = TCG_REG_TMP0; 1751 } else { 1752 TCGReg base; 1753 1754 if (a_mask) { 1755 ldst = new_ldst_label(s); 1756 ldst->is_ld = is_ld; 1757 ldst->oi = oi; 1758 ldst->addr_reg = addr_reg; 1759 1760 init_setting_vtype(s); 1761 1762 /* We are expecting alignment max 7, so we can always use andi. */ 1763 tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12)); 1764 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); 1765 1766 ldst->label_ptr[0] = s->code_ptr; 1767 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1768 } 1769 1770 if (guest_base != 0) { 1771 base = TCG_REG_TMP0; 1772 if (addr_type != TCG_TYPE_I32) { 1773 tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, 1774 TCG_GUEST_BASE_REG); 1775 } else if (cpuinfo & CPUINFO_ZBA) { 1776 tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, 1777 TCG_GUEST_BASE_REG); 1778 } else { 1779 tcg_out_ext32u(s, base, addr_reg); 1780 tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG); 1781 } 1782 } else if (addr_type != TCG_TYPE_I32) { 1783 base = addr_reg; 1784 } else { 1785 base = TCG_REG_TMP0; 1786 tcg_out_ext32u(s, base, addr_reg); 1787 } 1788 *pbase = base; 1789 } 1790 1791 return ldst; 1792} 1793 1794static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, 1795 TCGReg base, MemOp opc, TCGType type) 1796{ 1797 /* Byte swapping is left to middle-end expansion. */ 1798 tcg_debug_assert((opc & MO_BSWAP) == 0); 1799 1800 switch (opc & (MO_SSIZE)) { 1801 case MO_UB: 1802 tcg_out_opc_imm(s, OPC_LBU, val, base, 0); 1803 break; 1804 case MO_SB: 1805 tcg_out_opc_imm(s, OPC_LB, val, base, 0); 1806 break; 1807 case MO_UW: 1808 tcg_out_opc_imm(s, OPC_LHU, val, base, 0); 1809 break; 1810 case MO_SW: 1811 tcg_out_opc_imm(s, OPC_LH, val, base, 0); 1812 break; 1813 case MO_UL: 1814 if (type == TCG_TYPE_I64) { 1815 tcg_out_opc_imm(s, OPC_LWU, val, base, 0); 1816 break; 1817 } 1818 /* FALLTHRU */ 1819 case MO_SL: 1820 tcg_out_opc_imm(s, OPC_LW, val, base, 0); 1821 break; 1822 case MO_UQ: 1823 tcg_out_opc_imm(s, OPC_LD, val, base, 0); 1824 break; 1825 default: 1826 g_assert_not_reached(); 1827 } 1828} 1829 1830static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1831 MemOpIdx oi, TCGType data_type) 1832{ 1833 TCGLabelQemuLdst *ldst; 1834 TCGReg base; 1835 1836 ldst = prepare_host_addr(s, &base, addr_reg, oi, true); 1837 tcg_out_qemu_ld_direct(s, data_reg, base, get_memop(oi), data_type); 1838 1839 if (ldst) { 1840 ldst->type = data_type; 1841 ldst->datalo_reg = data_reg; 1842 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1843 } 1844} 1845 1846static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, 1847 TCGReg base, MemOp opc) 1848{ 1849 /* Byte swapping is left to middle-end expansion. */ 1850 tcg_debug_assert((opc & MO_BSWAP) == 0); 1851 1852 switch (opc & (MO_SSIZE)) { 1853 case MO_8: 1854 tcg_out_opc_store(s, OPC_SB, base, val, 0); 1855 break; 1856 case MO_16: 1857 tcg_out_opc_store(s, OPC_SH, base, val, 0); 1858 break; 1859 case MO_32: 1860 tcg_out_opc_store(s, OPC_SW, base, val, 0); 1861 break; 1862 case MO_64: 1863 tcg_out_opc_store(s, OPC_SD, base, val, 0); 1864 break; 1865 default: 1866 g_assert_not_reached(); 1867 } 1868} 1869 1870static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1871 MemOpIdx oi, TCGType data_type) 1872{ 1873 TCGLabelQemuLdst *ldst; 1874 TCGReg base; 1875 1876 ldst = prepare_host_addr(s, &base, addr_reg, oi, false); 1877 tcg_out_qemu_st_direct(s, data_reg, base, get_memop(oi)); 1878 1879 if (ldst) { 1880 ldst->type = data_type; 1881 ldst->datalo_reg = data_reg; 1882 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1883 } 1884} 1885 1886static const tcg_insn_unit *tb_ret_addr; 1887 1888static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1889{ 1890 /* Reuse the zeroing that exists for goto_ptr. */ 1891 if (a0 == 0) { 1892 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1893 } else { 1894 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1895 tcg_out_call_int(s, tb_ret_addr, true); 1896 } 1897} 1898 1899static void tcg_out_goto_tb(TCGContext *s, int which) 1900{ 1901 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1902 set_jmp_insn_offset(s, which); 1903 tcg_out32(s, OPC_JAL); 1904 1905 /* When branch is out of range, fall through to indirect. */ 1906 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, 1907 get_jmp_target_addr(s, which)); 1908 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1909 set_jmp_reset_offset(s, which); 1910} 1911 1912void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1913 uintptr_t jmp_rx, uintptr_t jmp_rw) 1914{ 1915 uintptr_t addr = tb->jmp_target_addr[n]; 1916 ptrdiff_t offset = addr - jmp_rx; 1917 tcg_insn_unit insn; 1918 1919 /* Either directly branch, or fall through to indirect branch. */ 1920 if (offset == sextreg(offset, 0, 20)) { 1921 insn = encode_uj(OPC_JAL, TCG_REG_ZERO, offset); 1922 } else { 1923 insn = OPC_NOP; 1924 } 1925 qatomic_set((uint32_t *)jmp_rw, insn); 1926 flush_idcache_range(jmp_rx, jmp_rw, 4); 1927} 1928 1929 1930static void tgen_add(TCGContext *s, TCGType type, 1931 TCGReg a0, TCGReg a1, TCGReg a2) 1932{ 1933 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_ADDW : OPC_ADD; 1934 tcg_out_opc_reg(s, insn, a0, a1, a2); 1935} 1936 1937static void tgen_addi(TCGContext *s, TCGType type, 1938 TCGReg a0, TCGReg a1, tcg_target_long a2) 1939{ 1940 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI; 1941 tcg_out_opc_imm(s, insn, a0, a1, a2); 1942} 1943 1944static const TCGOutOpBinary outop_add = { 1945 .base.static_constraint = C_O1_I2(r, r, rI), 1946 .out_rrr = tgen_add, 1947 .out_rri = tgen_addi, 1948}; 1949 1950static void tgen_and(TCGContext *s, TCGType type, 1951 TCGReg a0, TCGReg a1, TCGReg a2) 1952{ 1953 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1954} 1955 1956static void tgen_andi(TCGContext *s, TCGType type, 1957 TCGReg a0, TCGReg a1, tcg_target_long a2) 1958{ 1959 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1960} 1961 1962static const TCGOutOpBinary outop_and = { 1963 .base.static_constraint = C_O1_I2(r, r, rI), 1964 .out_rrr = tgen_and, 1965 .out_rri = tgen_andi, 1966}; 1967 1968static void tgen_andc(TCGContext *s, TCGType type, 1969 TCGReg a0, TCGReg a1, TCGReg a2) 1970{ 1971 tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2); 1972} 1973 1974static TCGConstraintSetIndex cset_zbb_rrr(TCGType type, unsigned flags) 1975{ 1976 return cpuinfo & CPUINFO_ZBB ? C_O1_I2(r, r, r) : C_NotImplemented; 1977} 1978 1979static const TCGOutOpBinary outop_andc = { 1980 .base.static_constraint = C_Dynamic, 1981 .base.dynamic_constraint = cset_zbb_rrr, 1982 .out_rrr = tgen_andc, 1983}; 1984 1985static void tgen_clz(TCGContext *s, TCGType type, 1986 TCGReg a0, TCGReg a1, TCGReg a2) 1987{ 1988 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_CLZW : OPC_CLZ; 1989 tcg_out_cltz(s, type, insn, a0, a1, a2, false); 1990} 1991 1992static void tgen_clzi(TCGContext *s, TCGType type, 1993 TCGReg a0, TCGReg a1, tcg_target_long a2) 1994{ 1995 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_CLZW : OPC_CLZ; 1996 tcg_out_cltz(s, type, insn, a0, a1, a2, true); 1997} 1998 1999static TCGConstraintSetIndex cset_clzctz(TCGType type, unsigned flags) 2000{ 2001 return cpuinfo & CPUINFO_ZBB ? C_N1_I2(r, r, rM) : C_NotImplemented; 2002} 2003 2004static const TCGOutOpBinary outop_clz = { 2005 .base.static_constraint = C_Dynamic, 2006 .base.dynamic_constraint = cset_clzctz, 2007 .out_rrr = tgen_clz, 2008 .out_rri = tgen_clzi, 2009}; 2010 2011static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2012{ 2013 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_CPOPW : OPC_CPOP; 2014 tcg_out_opc_imm(s, insn, a0, a1, 0); 2015} 2016 2017static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags) 2018{ 2019 return cpuinfo & CPUINFO_ZBB ? C_O1_I1(r, r) : C_NotImplemented; 2020} 2021 2022static const TCGOutOpUnary outop_ctpop = { 2023 .base.static_constraint = C_Dynamic, 2024 .base.dynamic_constraint = cset_ctpop, 2025 .out_rr = tgen_ctpop, 2026}; 2027 2028static void tgen_ctz(TCGContext *s, TCGType type, 2029 TCGReg a0, TCGReg a1, TCGReg a2) 2030{ 2031 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_CTZW : OPC_CTZ; 2032 tcg_out_cltz(s, type, insn, a0, a1, a2, false); 2033} 2034 2035static void tgen_ctzi(TCGContext *s, TCGType type, 2036 TCGReg a0, TCGReg a1, tcg_target_long a2) 2037{ 2038 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_CTZW : OPC_CTZ; 2039 tcg_out_cltz(s, type, insn, a0, a1, a2, true); 2040} 2041 2042static const TCGOutOpBinary outop_ctz = { 2043 .base.static_constraint = C_Dynamic, 2044 .base.dynamic_constraint = cset_clzctz, 2045 .out_rrr = tgen_ctz, 2046 .out_rri = tgen_ctzi, 2047}; 2048 2049static void tgen_divs(TCGContext *s, TCGType type, 2050 TCGReg a0, TCGReg a1, TCGReg a2) 2051{ 2052 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_DIVW : OPC_DIV; 2053 tcg_out_opc_reg(s, insn, a0, a1, a2); 2054} 2055 2056static const TCGOutOpBinary outop_divs = { 2057 .base.static_constraint = C_O1_I2(r, r, r), 2058 .out_rrr = tgen_divs, 2059}; 2060 2061static const TCGOutOpDivRem outop_divs2 = { 2062 .base.static_constraint = C_NotImplemented, 2063}; 2064 2065static void tgen_divu(TCGContext *s, TCGType type, 2066 TCGReg a0, TCGReg a1, TCGReg a2) 2067{ 2068 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_DIVUW : OPC_DIVU; 2069 tcg_out_opc_reg(s, insn, a0, a1, a2); 2070} 2071 2072static const TCGOutOpBinary outop_divu = { 2073 .base.static_constraint = C_O1_I2(r, r, r), 2074 .out_rrr = tgen_divu, 2075}; 2076 2077static const TCGOutOpDivRem outop_divu2 = { 2078 .base.static_constraint = C_NotImplemented, 2079}; 2080 2081static void tgen_eqv(TCGContext *s, TCGType type, 2082 TCGReg a0, TCGReg a1, TCGReg a2) 2083{ 2084 tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2); 2085} 2086 2087static const TCGOutOpBinary outop_eqv = { 2088 .base.static_constraint = C_Dynamic, 2089 .base.dynamic_constraint = cset_zbb_rrr, 2090 .out_rrr = tgen_eqv, 2091}; 2092 2093static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 2094{ 2095 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); 2096} 2097 2098static const TCGOutOpUnary outop_extrh_i64_i32 = { 2099 .base.static_constraint = C_O1_I1(r, r), 2100 .out_rr = tgen_extrh_i64_i32, 2101}; 2102 2103static void tgen_mul(TCGContext *s, TCGType type, 2104 TCGReg a0, TCGReg a1, TCGReg a2) 2105{ 2106 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_MULW : OPC_MUL; 2107 tcg_out_opc_reg(s, insn, a0, a1, a2); 2108} 2109 2110static const TCGOutOpBinary outop_mul = { 2111 .base.static_constraint = C_O1_I2(r, r, r), 2112 .out_rrr = tgen_mul, 2113}; 2114 2115static const TCGOutOpMul2 outop_muls2 = { 2116 .base.static_constraint = C_NotImplemented, 2117}; 2118 2119static TCGConstraintSetIndex cset_mulh(TCGType type, unsigned flags) 2120{ 2121 return type == TCG_TYPE_I32 ? C_NotImplemented : C_O1_I2(r, r, r); 2122} 2123 2124static void tgen_mulsh(TCGContext *s, TCGType type, 2125 TCGReg a0, TCGReg a1, TCGReg a2) 2126{ 2127 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); 2128} 2129 2130static const TCGOutOpBinary outop_mulsh = { 2131 .base.static_constraint = C_Dynamic, 2132 .base.dynamic_constraint = cset_mulh, 2133 .out_rrr = tgen_mulsh, 2134}; 2135 2136static const TCGOutOpMul2 outop_mulu2 = { 2137 .base.static_constraint = C_NotImplemented, 2138}; 2139 2140static void tgen_muluh(TCGContext *s, TCGType type, 2141 TCGReg a0, TCGReg a1, TCGReg a2) 2142{ 2143 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); 2144} 2145 2146static const TCGOutOpBinary outop_muluh = { 2147 .base.static_constraint = C_Dynamic, 2148 .base.dynamic_constraint = cset_mulh, 2149 .out_rrr = tgen_muluh, 2150}; 2151 2152static const TCGOutOpBinary outop_nand = { 2153 .base.static_constraint = C_NotImplemented, 2154}; 2155 2156static const TCGOutOpBinary outop_nor = { 2157 .base.static_constraint = C_NotImplemented, 2158}; 2159 2160static void tgen_or(TCGContext *s, TCGType type, 2161 TCGReg a0, TCGReg a1, TCGReg a2) 2162{ 2163 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 2164} 2165 2166static void tgen_ori(TCGContext *s, TCGType type, 2167 TCGReg a0, TCGReg a1, tcg_target_long a2) 2168{ 2169 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 2170} 2171 2172static const TCGOutOpBinary outop_or = { 2173 .base.static_constraint = C_O1_I2(r, r, rI), 2174 .out_rrr = tgen_or, 2175 .out_rri = tgen_ori, 2176}; 2177 2178static void tgen_orc(TCGContext *s, TCGType type, 2179 TCGReg a0, TCGReg a1, TCGReg a2) 2180{ 2181 tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2); 2182} 2183 2184static const TCGOutOpBinary outop_orc = { 2185 .base.static_constraint = C_Dynamic, 2186 .base.dynamic_constraint = cset_zbb_rrr, 2187 .out_rrr = tgen_orc, 2188}; 2189 2190static void tgen_rems(TCGContext *s, TCGType type, 2191 TCGReg a0, TCGReg a1, TCGReg a2) 2192{ 2193 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_REMW : OPC_REM; 2194 tcg_out_opc_reg(s, insn, a0, a1, a2); 2195} 2196 2197static const TCGOutOpBinary outop_rems = { 2198 .base.static_constraint = C_O1_I2(r, r, r), 2199 .out_rrr = tgen_rems, 2200}; 2201 2202static void tgen_remu(TCGContext *s, TCGType type, 2203 TCGReg a0, TCGReg a1, TCGReg a2) 2204{ 2205 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_REMUW : OPC_REMU; 2206 tcg_out_opc_reg(s, insn, a0, a1, a2); 2207} 2208 2209static const TCGOutOpBinary outop_remu = { 2210 .base.static_constraint = C_O1_I2(r, r, r), 2211 .out_rrr = tgen_remu, 2212}; 2213 2214static TCGConstraintSetIndex cset_rot(TCGType type, unsigned flags) 2215{ 2216 return cpuinfo & CPUINFO_ZBB ? C_O1_I2(r, r, ri) : C_NotImplemented; 2217} 2218 2219static void tgen_rotr(TCGContext *s, TCGType type, 2220 TCGReg a0, TCGReg a1, TCGReg a2) 2221{ 2222 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_RORW : OPC_ROR; 2223 tcg_out_opc_reg(s, insn, a0, a1, a2); 2224} 2225 2226static void tgen_rotri(TCGContext *s, TCGType type, 2227 TCGReg a0, TCGReg a1, tcg_target_long a2) 2228{ 2229 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_RORIW : OPC_RORI; 2230 unsigned mask = type == TCG_TYPE_I32 ? 31 : 63; 2231 tcg_out_opc_imm(s, insn, a0, a1, a2 & mask); 2232} 2233 2234static const TCGOutOpBinary outop_rotr = { 2235 .base.static_constraint = C_Dynamic, 2236 .base.dynamic_constraint = cset_rot, 2237 .out_rrr = tgen_rotr, 2238 .out_rri = tgen_rotri, 2239}; 2240 2241static void tgen_rotl(TCGContext *s, TCGType type, 2242 TCGReg a0, TCGReg a1, TCGReg a2) 2243{ 2244 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_ROLW : OPC_ROL; 2245 tcg_out_opc_reg(s, insn, a0, a1, a2); 2246} 2247 2248static void tgen_rotli(TCGContext *s, TCGType type, 2249 TCGReg a0, TCGReg a1, tcg_target_long a2) 2250{ 2251 tgen_rotri(s, type, a0, a1, -a2); 2252} 2253 2254static const TCGOutOpBinary outop_rotl = { 2255 .base.static_constraint = C_Dynamic, 2256 .base.dynamic_constraint = cset_rot, 2257 .out_rrr = tgen_rotl, 2258 .out_rri = tgen_rotli, 2259}; 2260 2261static void tgen_sar(TCGContext *s, TCGType type, 2262 TCGReg a0, TCGReg a1, TCGReg a2) 2263{ 2264 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SRAW : OPC_SRA; 2265 tcg_out_opc_reg(s, insn, a0, a1, a2); 2266} 2267 2268static void tgen_sari(TCGContext *s, TCGType type, 2269 TCGReg a0, TCGReg a1, tcg_target_long a2) 2270{ 2271 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SRAIW : OPC_SRAI; 2272 unsigned mask = type == TCG_TYPE_I32 ? 31 : 63; 2273 tcg_out_opc_imm(s, insn, a0, a1, a2 & mask); 2274} 2275 2276static const TCGOutOpBinary outop_sar = { 2277 .base.static_constraint = C_O1_I2(r, r, ri), 2278 .out_rrr = tgen_sar, 2279 .out_rri = tgen_sari, 2280}; 2281 2282static void tgen_shl(TCGContext *s, TCGType type, 2283 TCGReg a0, TCGReg a1, TCGReg a2) 2284{ 2285 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SLLW : OPC_SLL; 2286 tcg_out_opc_reg(s, insn, a0, a1, a2); 2287} 2288 2289static void tgen_shli(TCGContext *s, TCGType type, 2290 TCGReg a0, TCGReg a1, tcg_target_long a2) 2291{ 2292 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SLLIW : OPC_SLLI; 2293 unsigned mask = type == TCG_TYPE_I32 ? 31 : 63; 2294 tcg_out_opc_imm(s, insn, a0, a1, a2 & mask); 2295} 2296 2297static const TCGOutOpBinary outop_shl = { 2298 .base.static_constraint = C_O1_I2(r, r, ri), 2299 .out_rrr = tgen_shl, 2300 .out_rri = tgen_shli, 2301}; 2302 2303static void tgen_shr(TCGContext *s, TCGType type, 2304 TCGReg a0, TCGReg a1, TCGReg a2) 2305{ 2306 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SRLW : OPC_SRL; 2307 tcg_out_opc_reg(s, insn, a0, a1, a2); 2308} 2309 2310static void tgen_shri(TCGContext *s, TCGType type, 2311 TCGReg a0, TCGReg a1, tcg_target_long a2) 2312{ 2313 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SRLIW : OPC_SRLI; 2314 unsigned mask = type == TCG_TYPE_I32 ? 31 : 63; 2315 tcg_out_opc_imm(s, insn, a0, a1, a2 & mask); 2316} 2317 2318static const TCGOutOpBinary outop_shr = { 2319 .base.static_constraint = C_O1_I2(r, r, ri), 2320 .out_rrr = tgen_shr, 2321 .out_rri = tgen_shri, 2322}; 2323 2324static void tgen_sub(TCGContext *s, TCGType type, 2325 TCGReg a0, TCGReg a1, TCGReg a2) 2326{ 2327 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SUBW : OPC_SUB; 2328 tcg_out_opc_reg(s, insn, a0, a1, a2); 2329} 2330 2331static const TCGOutOpSubtract outop_sub = { 2332 .base.static_constraint = C_O1_I2(r, r, r), 2333 .out_rrr = tgen_sub, 2334}; 2335 2336static void tgen_xor(TCGContext *s, TCGType type, 2337 TCGReg a0, TCGReg a1, TCGReg a2) 2338{ 2339 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2340} 2341 2342static void tgen_xori(TCGContext *s, TCGType type, 2343 TCGReg a0, TCGReg a1, tcg_target_long a2) 2344{ 2345 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2346} 2347 2348static const TCGOutOpBinary outop_xor = { 2349 .base.static_constraint = C_O1_I2(r, r, rI), 2350 .out_rrr = tgen_xor, 2351 .out_rri = tgen_xori, 2352}; 2353 2354static TCGConstraintSetIndex cset_bswap(TCGType type, unsigned flags) 2355{ 2356 return cpuinfo & CPUINFO_ZBB ? C_O1_I1(r, r) : C_NotImplemented; 2357} 2358 2359static void tgen_bswap16(TCGContext *s, TCGType type, 2360 TCGReg a0, TCGReg a1, unsigned flags) 2361{ 2362 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 2363 if (flags & TCG_BSWAP_OZ) { 2364 tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48); 2365 } else { 2366 tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48); 2367 } 2368} 2369 2370static const TCGOutOpBswap outop_bswap16 = { 2371 .base.static_constraint = C_Dynamic, 2372 .base.dynamic_constraint = cset_bswap, 2373 .out_rr = tgen_bswap16, 2374}; 2375 2376static void tgen_bswap32(TCGContext *s, TCGType type, 2377 TCGReg a0, TCGReg a1, unsigned flags) 2378{ 2379 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 2380 if (flags & TCG_BSWAP_OZ) { 2381 tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32); 2382 } else { 2383 tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32); 2384 } 2385} 2386 2387static const TCGOutOpBswap outop_bswap32 = { 2388 .base.static_constraint = C_Dynamic, 2389 .base.dynamic_constraint = cset_bswap, 2390 .out_rr = tgen_bswap32, 2391}; 2392 2393static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2394{ 2395 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 2396} 2397 2398static const TCGOutOpUnary outop_bswap64 = { 2399 .base.static_constraint = C_Dynamic, 2400 .base.dynamic_constraint = cset_bswap, 2401 .out_rr = tgen_bswap64, 2402}; 2403 2404static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2405{ 2406 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2407} 2408 2409static const TCGOutOpUnary outop_neg = { 2410 .base.static_constraint = C_O1_I1(r, r), 2411 .out_rr = tgen_neg, 2412}; 2413 2414static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2415{ 2416 tgen_xori(s, type, a0, a1, -1); 2417} 2418 2419static const TCGOutOpUnary outop_not = { 2420 .base.static_constraint = C_O1_I1(r, r), 2421 .out_rr = tgen_not, 2422}; 2423 2424static const TCGOutOpDeposit outop_deposit = { 2425 .base.static_constraint = C_NotImplemented, 2426}; 2427 2428static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2429 unsigned ofs, unsigned len) 2430{ 2431 if (ofs == 0) { 2432 switch (len) { 2433 case 16: 2434 tcg_out_ext16u(s, a0, a1); 2435 return; 2436 case 32: 2437 tcg_out_ext32u(s, a0, a1); 2438 return; 2439 } 2440 } 2441 if (ofs + len == 32) { 2442 tgen_shli(s, TCG_TYPE_I32, a0, a1, ofs); 2443 return; 2444 } 2445 if (len == 1) { 2446 tcg_out_opc_imm(s, OPC_BEXTI, a0, a1, ofs); 2447 return; 2448 } 2449 g_assert_not_reached(); 2450} 2451 2452static const TCGOutOpExtract outop_extract = { 2453 .base.static_constraint = C_O1_I1(r, r), 2454 .out_rr = tgen_extract, 2455}; 2456 2457static void tgen_sextract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2458 unsigned ofs, unsigned len) 2459{ 2460 if (ofs == 0) { 2461 switch (len) { 2462 case 8: 2463 tcg_out_ext8s(s, type, a0, a1); 2464 return; 2465 case 16: 2466 tcg_out_ext16s(s, type, a0, a1); 2467 return; 2468 case 32: 2469 tcg_out_ext32s(s, a0, a1); 2470 return; 2471 } 2472 } else if (ofs + len == 32) { 2473 tgen_sari(s, TCG_TYPE_I32, a0, a1, ofs); 2474 return; 2475 } 2476 g_assert_not_reached(); 2477} 2478 2479static const TCGOutOpExtract outop_sextract = { 2480 .base.static_constraint = C_O1_I1(r, r), 2481 .out_rr = tgen_sextract, 2482}; 2483 2484static const TCGOutOpExtract2 outop_extract2 = { 2485 .base.static_constraint = C_NotImplemented, 2486}; 2487 2488 2489static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2490 const TCGArg args[TCG_MAX_OP_ARGS], 2491 const int const_args[TCG_MAX_OP_ARGS]) 2492{ 2493 TCGArg a0 = args[0]; 2494 TCGArg a1 = args[1]; 2495 TCGArg a2 = args[2]; 2496 2497 switch (opc) { 2498 case INDEX_op_goto_ptr: 2499 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); 2500 break; 2501 2502 case INDEX_op_br: 2503 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0); 2504 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 2505 break; 2506 2507 case INDEX_op_ld8u_i32: 2508 case INDEX_op_ld8u_i64: 2509 tcg_out_ldst(s, OPC_LBU, a0, a1, a2); 2510 break; 2511 case INDEX_op_ld8s_i32: 2512 case INDEX_op_ld8s_i64: 2513 tcg_out_ldst(s, OPC_LB, a0, a1, a2); 2514 break; 2515 case INDEX_op_ld16u_i32: 2516 case INDEX_op_ld16u_i64: 2517 tcg_out_ldst(s, OPC_LHU, a0, a1, a2); 2518 break; 2519 case INDEX_op_ld16s_i32: 2520 case INDEX_op_ld16s_i64: 2521 tcg_out_ldst(s, OPC_LH, a0, a1, a2); 2522 break; 2523 case INDEX_op_ld32u_i64: 2524 tcg_out_ldst(s, OPC_LWU, a0, a1, a2); 2525 break; 2526 case INDEX_op_ld_i32: 2527 case INDEX_op_ld32s_i64: 2528 tcg_out_ldst(s, OPC_LW, a0, a1, a2); 2529 break; 2530 case INDEX_op_ld_i64: 2531 tcg_out_ldst(s, OPC_LD, a0, a1, a2); 2532 break; 2533 2534 case INDEX_op_st8_i32: 2535 case INDEX_op_st8_i64: 2536 tcg_out_ldst(s, OPC_SB, a0, a1, a2); 2537 break; 2538 case INDEX_op_st16_i32: 2539 case INDEX_op_st16_i64: 2540 tcg_out_ldst(s, OPC_SH, a0, a1, a2); 2541 break; 2542 case INDEX_op_st_i32: 2543 case INDEX_op_st32_i64: 2544 tcg_out_ldst(s, OPC_SW, a0, a1, a2); 2545 break; 2546 case INDEX_op_st_i64: 2547 tcg_out_ldst(s, OPC_SD, a0, a1, a2); 2548 break; 2549 2550 case INDEX_op_qemu_ld_i32: 2551 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 2552 break; 2553 case INDEX_op_qemu_ld_i64: 2554 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 2555 break; 2556 case INDEX_op_qemu_st_i32: 2557 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 2558 break; 2559 case INDEX_op_qemu_st_i64: 2560 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 2561 break; 2562 2563 case INDEX_op_mb: 2564 tcg_out_mb(s, a0); 2565 break; 2566 2567 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2568 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2569 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2570 default: 2571 g_assert_not_reached(); 2572 } 2573} 2574 2575static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2576 unsigned vecl, unsigned vece, 2577 const TCGArg args[TCG_MAX_OP_ARGS], 2578 const int const_args[TCG_MAX_OP_ARGS]) 2579{ 2580 TCGType type = vecl + TCG_TYPE_V64; 2581 TCGArg a0, a1, a2; 2582 int c2; 2583 2584 a0 = args[0]; 2585 a1 = args[1]; 2586 a2 = args[2]; 2587 c2 = const_args[2]; 2588 2589 switch (opc) { 2590 case INDEX_op_dupm_vec: 2591 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2592 break; 2593 case INDEX_op_ld_vec: 2594 tcg_out_ld(s, type, a0, a1, a2); 2595 break; 2596 case INDEX_op_st_vec: 2597 tcg_out_st(s, type, a0, a1, a2); 2598 break; 2599 case INDEX_op_add_vec: 2600 set_vtype_len_sew(s, type, vece); 2601 tcg_out_opc_vv_vi(s, OPC_VADD_VV, OPC_VADD_VI, a0, a1, a2, c2); 2602 break; 2603 case INDEX_op_sub_vec: 2604 set_vtype_len_sew(s, type, vece); 2605 if (const_args[1]) { 2606 tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a2, a1); 2607 } else { 2608 tcg_out_opc_vv(s, OPC_VSUB_VV, a0, a1, a2); 2609 } 2610 break; 2611 case INDEX_op_and_vec: 2612 set_vtype_len(s, type); 2613 tcg_out_opc_vv_vi(s, OPC_VAND_VV, OPC_VAND_VI, a0, a1, a2, c2); 2614 break; 2615 case INDEX_op_or_vec: 2616 set_vtype_len(s, type); 2617 tcg_out_opc_vv_vi(s, OPC_VOR_VV, OPC_VOR_VI, a0, a1, a2, c2); 2618 break; 2619 case INDEX_op_xor_vec: 2620 set_vtype_len(s, type); 2621 tcg_out_opc_vv_vi(s, OPC_VXOR_VV, OPC_VXOR_VI, a0, a1, a2, c2); 2622 break; 2623 case INDEX_op_not_vec: 2624 set_vtype_len(s, type); 2625 tcg_out_opc_vi(s, OPC_VXOR_VI, a0, a1, -1); 2626 break; 2627 case INDEX_op_neg_vec: 2628 set_vtype_len_sew(s, type, vece); 2629 tcg_out_opc_vi(s, OPC_VRSUB_VI, a0, a1, 0); 2630 break; 2631 case INDEX_op_mul_vec: 2632 set_vtype_len_sew(s, type, vece); 2633 tcg_out_opc_vv(s, OPC_VMUL_VV, a0, a1, a2); 2634 break; 2635 case INDEX_op_ssadd_vec: 2636 set_vtype_len_sew(s, type, vece); 2637 tcg_out_opc_vv_vi(s, OPC_VSADD_VV, OPC_VSADD_VI, a0, a1, a2, c2); 2638 break; 2639 case INDEX_op_sssub_vec: 2640 set_vtype_len_sew(s, type, vece); 2641 tcg_out_opc_vv_vi(s, OPC_VSSUB_VV, OPC_VSSUB_VI, a0, a1, a2, c2); 2642 break; 2643 case INDEX_op_usadd_vec: 2644 set_vtype_len_sew(s, type, vece); 2645 tcg_out_opc_vv_vi(s, OPC_VSADDU_VV, OPC_VSADDU_VI, a0, a1, a2, c2); 2646 break; 2647 case INDEX_op_ussub_vec: 2648 set_vtype_len_sew(s, type, vece); 2649 tcg_out_opc_vv_vi(s, OPC_VSSUBU_VV, OPC_VSSUBU_VI, a0, a1, a2, c2); 2650 break; 2651 case INDEX_op_smax_vec: 2652 set_vtype_len_sew(s, type, vece); 2653 tcg_out_opc_vv_vi(s, OPC_VMAX_VV, OPC_VMAX_VI, a0, a1, a2, c2); 2654 break; 2655 case INDEX_op_smin_vec: 2656 set_vtype_len_sew(s, type, vece); 2657 tcg_out_opc_vv_vi(s, OPC_VMIN_VV, OPC_VMIN_VI, a0, a1, a2, c2); 2658 break; 2659 case INDEX_op_umax_vec: 2660 set_vtype_len_sew(s, type, vece); 2661 tcg_out_opc_vv_vi(s, OPC_VMAXU_VV, OPC_VMAXU_VI, a0, a1, a2, c2); 2662 break; 2663 case INDEX_op_umin_vec: 2664 set_vtype_len_sew(s, type, vece); 2665 tcg_out_opc_vv_vi(s, OPC_VMINU_VV, OPC_VMINU_VI, a0, a1, a2, c2); 2666 break; 2667 case INDEX_op_shls_vec: 2668 set_vtype_len_sew(s, type, vece); 2669 tcg_out_opc_vx(s, OPC_VSLL_VX, a0, a1, a2); 2670 break; 2671 case INDEX_op_shrs_vec: 2672 set_vtype_len_sew(s, type, vece); 2673 tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, a2); 2674 break; 2675 case INDEX_op_sars_vec: 2676 set_vtype_len_sew(s, type, vece); 2677 tcg_out_opc_vx(s, OPC_VSRA_VX, a0, a1, a2); 2678 break; 2679 case INDEX_op_shlv_vec: 2680 set_vtype_len_sew(s, type, vece); 2681 tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2); 2682 break; 2683 case INDEX_op_shrv_vec: 2684 set_vtype_len_sew(s, type, vece); 2685 tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2); 2686 break; 2687 case INDEX_op_sarv_vec: 2688 set_vtype_len_sew(s, type, vece); 2689 tcg_out_opc_vv(s, OPC_VSRA_VV, a0, a1, a2); 2690 break; 2691 case INDEX_op_shli_vec: 2692 set_vtype_len_sew(s, type, vece); 2693 tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, a0, a1, a2); 2694 break; 2695 case INDEX_op_shri_vec: 2696 set_vtype_len_sew(s, type, vece); 2697 tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, a2); 2698 break; 2699 case INDEX_op_sari_vec: 2700 set_vtype_len_sew(s, type, vece); 2701 tcg_out_vshifti(s, OPC_VSRA_VI, OPC_VSRA_VX, a0, a1, a2); 2702 break; 2703 case INDEX_op_rotli_vec: 2704 set_vtype_len_sew(s, type, vece); 2705 tcg_out_vshifti(s, OPC_VSLL_VI, OPC_VSLL_VX, TCG_REG_V0, a1, a2); 2706 tcg_out_vshifti(s, OPC_VSRL_VI, OPC_VSRL_VX, a0, a1, 2707 -a2 & ((8 << vece) - 1)); 2708 tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); 2709 break; 2710 case INDEX_op_rotls_vec: 2711 set_vtype_len_sew(s, type, vece); 2712 tcg_out_opc_vx(s, OPC_VSLL_VX, TCG_REG_V0, a1, a2); 2713 tcg_out_opc_reg(s, OPC_SUBW, TCG_REG_TMP0, TCG_REG_ZERO, a2); 2714 tcg_out_opc_vx(s, OPC_VSRL_VX, a0, a1, TCG_REG_TMP0); 2715 tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); 2716 break; 2717 case INDEX_op_rotlv_vec: 2718 set_vtype_len_sew(s, type, vece); 2719 tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0); 2720 tcg_out_opc_vv(s, OPC_VSRL_VV, TCG_REG_V0, a1, TCG_REG_V0); 2721 tcg_out_opc_vv(s, OPC_VSLL_VV, a0, a1, a2); 2722 tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); 2723 break; 2724 case INDEX_op_rotrv_vec: 2725 set_vtype_len_sew(s, type, vece); 2726 tcg_out_opc_vi(s, OPC_VRSUB_VI, TCG_REG_V0, a2, 0); 2727 tcg_out_opc_vv(s, OPC_VSLL_VV, TCG_REG_V0, a1, TCG_REG_V0); 2728 tcg_out_opc_vv(s, OPC_VSRL_VV, a0, a1, a2); 2729 tcg_out_opc_vv(s, OPC_VOR_VV, a0, a0, TCG_REG_V0); 2730 break; 2731 case INDEX_op_cmp_vec: 2732 tcg_out_cmpsel(s, type, vece, args[3], a0, a1, a2, c2, 2733 -1, true, 0, true); 2734 break; 2735 case INDEX_op_cmpsel_vec: 2736 tcg_out_cmpsel(s, type, vece, args[5], a0, a1, a2, c2, 2737 args[3], const_args[3], args[4], const_args[4]); 2738 break; 2739 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 2740 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 2741 default: 2742 g_assert_not_reached(); 2743 } 2744} 2745 2746void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2747 TCGArg a0, ...) 2748{ 2749 g_assert_not_reached(); 2750} 2751 2752int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2753{ 2754 switch (opc) { 2755 case INDEX_op_add_vec: 2756 case INDEX_op_sub_vec: 2757 case INDEX_op_and_vec: 2758 case INDEX_op_or_vec: 2759 case INDEX_op_xor_vec: 2760 case INDEX_op_not_vec: 2761 case INDEX_op_neg_vec: 2762 case INDEX_op_mul_vec: 2763 case INDEX_op_ssadd_vec: 2764 case INDEX_op_sssub_vec: 2765 case INDEX_op_usadd_vec: 2766 case INDEX_op_ussub_vec: 2767 case INDEX_op_smax_vec: 2768 case INDEX_op_smin_vec: 2769 case INDEX_op_umax_vec: 2770 case INDEX_op_umin_vec: 2771 case INDEX_op_shls_vec: 2772 case INDEX_op_shrs_vec: 2773 case INDEX_op_sars_vec: 2774 case INDEX_op_shlv_vec: 2775 case INDEX_op_shrv_vec: 2776 case INDEX_op_sarv_vec: 2777 case INDEX_op_shri_vec: 2778 case INDEX_op_shli_vec: 2779 case INDEX_op_sari_vec: 2780 case INDEX_op_rotls_vec: 2781 case INDEX_op_rotlv_vec: 2782 case INDEX_op_rotrv_vec: 2783 case INDEX_op_rotli_vec: 2784 case INDEX_op_cmp_vec: 2785 case INDEX_op_cmpsel_vec: 2786 return 1; 2787 default: 2788 return 0; 2789 } 2790} 2791 2792static TCGConstraintSetIndex 2793tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2794{ 2795 switch (op) { 2796 case INDEX_op_goto_ptr: 2797 return C_O0_I1(r); 2798 2799 case INDEX_op_ld8u_i32: 2800 case INDEX_op_ld8s_i32: 2801 case INDEX_op_ld16u_i32: 2802 case INDEX_op_ld16s_i32: 2803 case INDEX_op_ld_i32: 2804 case INDEX_op_ld8u_i64: 2805 case INDEX_op_ld8s_i64: 2806 case INDEX_op_ld16u_i64: 2807 case INDEX_op_ld16s_i64: 2808 case INDEX_op_ld32s_i64: 2809 case INDEX_op_ld32u_i64: 2810 case INDEX_op_ld_i64: 2811 return C_O1_I1(r, r); 2812 2813 case INDEX_op_st8_i32: 2814 case INDEX_op_st16_i32: 2815 case INDEX_op_st_i32: 2816 case INDEX_op_st8_i64: 2817 case INDEX_op_st16_i64: 2818 case INDEX_op_st32_i64: 2819 case INDEX_op_st_i64: 2820 return C_O0_I2(rz, r); 2821 2822 case INDEX_op_qemu_ld_i32: 2823 case INDEX_op_qemu_ld_i64: 2824 return C_O1_I1(r, r); 2825 case INDEX_op_qemu_st_i32: 2826 case INDEX_op_qemu_st_i64: 2827 return C_O0_I2(rz, r); 2828 2829 case INDEX_op_st_vec: 2830 return C_O0_I2(v, r); 2831 case INDEX_op_dup_vec: 2832 case INDEX_op_dupm_vec: 2833 case INDEX_op_ld_vec: 2834 return C_O1_I1(v, r); 2835 case INDEX_op_neg_vec: 2836 case INDEX_op_not_vec: 2837 case INDEX_op_shli_vec: 2838 case INDEX_op_shri_vec: 2839 case INDEX_op_sari_vec: 2840 case INDEX_op_rotli_vec: 2841 return C_O1_I1(v, v); 2842 case INDEX_op_add_vec: 2843 case INDEX_op_and_vec: 2844 case INDEX_op_or_vec: 2845 case INDEX_op_xor_vec: 2846 case INDEX_op_ssadd_vec: 2847 case INDEX_op_sssub_vec: 2848 case INDEX_op_usadd_vec: 2849 case INDEX_op_ussub_vec: 2850 case INDEX_op_smax_vec: 2851 case INDEX_op_smin_vec: 2852 case INDEX_op_umax_vec: 2853 case INDEX_op_umin_vec: 2854 return C_O1_I2(v, v, vK); 2855 case INDEX_op_sub_vec: 2856 return C_O1_I2(v, vK, v); 2857 case INDEX_op_mul_vec: 2858 case INDEX_op_shlv_vec: 2859 case INDEX_op_shrv_vec: 2860 case INDEX_op_sarv_vec: 2861 case INDEX_op_rotlv_vec: 2862 case INDEX_op_rotrv_vec: 2863 return C_O1_I2(v, v, v); 2864 case INDEX_op_shls_vec: 2865 case INDEX_op_shrs_vec: 2866 case INDEX_op_sars_vec: 2867 case INDEX_op_rotls_vec: 2868 return C_O1_I2(v, v, r); 2869 case INDEX_op_cmp_vec: 2870 return C_O1_I2(v, v, vL); 2871 case INDEX_op_cmpsel_vec: 2872 return C_O1_I4(v, v, vL, vK, vK); 2873 default: 2874 return C_NotImplemented; 2875 } 2876} 2877 2878static const int tcg_target_callee_save_regs[] = { 2879 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2880 TCG_REG_S1, 2881 TCG_REG_S2, 2882 TCG_REG_S3, 2883 TCG_REG_S4, 2884 TCG_REG_S5, 2885 TCG_REG_S6, 2886 TCG_REG_S7, 2887 TCG_REG_S8, 2888 TCG_REG_S9, 2889 TCG_REG_S10, 2890 TCG_REG_S11, 2891 TCG_REG_RA, /* should be last for ABI compliance */ 2892}; 2893 2894/* Stack frame parameters. */ 2895#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2896#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2897#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2898#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2899 + TCG_TARGET_STACK_ALIGN - 1) \ 2900 & -TCG_TARGET_STACK_ALIGN) 2901#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2902 2903/* We're expecting to be able to use an immediate for frame allocation. */ 2904QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2905 2906/* Generate global QEMU prologue and epilogue code */ 2907static void tcg_target_qemu_prologue(TCGContext *s) 2908{ 2909 int i; 2910 2911 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2912 2913 /* TB prologue */ 2914 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2915 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2916 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2917 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2918 } 2919 2920 if (!tcg_use_softmmu && guest_base) { 2921 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2922 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2923 } 2924 2925 /* Call generated code */ 2926 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2927 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2928 2929 /* Return path for goto_ptr. Set return value to 0 */ 2930 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2931 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2932 2933 /* TB epilogue */ 2934 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2935 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2936 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2937 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2938 } 2939 2940 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2941 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); 2942} 2943 2944static void tcg_out_tb_start(TCGContext *s) 2945{ 2946 init_setting_vtype(s); 2947} 2948 2949static bool vtype_check(unsigned vtype) 2950{ 2951 unsigned long tmp; 2952 2953 /* vsetvl tmp, zero, vtype */ 2954 asm(".insn r 0x57, 7, 0x40, %0, zero, %1" : "=r"(tmp) : "r"(vtype)); 2955 return tmp != 0; 2956} 2957 2958static void probe_frac_lmul_1(TCGType type, MemOp vsew) 2959{ 2960 VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew]; 2961 unsigned avl = tcg_type_size(type) >> vsew; 2962 int lmul = type - riscv_lg2_vlenb; 2963 unsigned vtype = encode_vtype(true, true, vsew, lmul & 7); 2964 bool lmul_eq_avl = true; 2965 2966 /* Guaranteed by Zve64x. */ 2967 assert(lmul < 3); 2968 2969 /* 2970 * For LMUL < -3, the host vector size is so large that TYPE 2971 * is smaller than the minimum 1/8 fraction. 2972 * 2973 * For other fractional LMUL settings, implementations must 2974 * support SEW settings between SEW_MIN and LMUL * ELEN, inclusive. 2975 * So if ELEN = 64, LMUL = 1/2, then SEW will support e8, e16, e32, 2976 * but e64 may not be supported. In other words, the hardware only 2977 * guarantees SEW_MIN <= SEW <= LMUL * ELEN. Check. 2978 */ 2979 if (lmul < 0 && (lmul < -3 || !vtype_check(vtype))) { 2980 vtype = encode_vtype(true, true, vsew, VLMUL_M1); 2981 lmul_eq_avl = false; 2982 } 2983 2984 if (avl < 32) { 2985 p->vset_insn = encode_vseti(OPC_VSETIVLI, TCG_REG_ZERO, avl, vtype); 2986 } else if (lmul_eq_avl) { 2987 /* rd != 0 and rs1 == 0 uses vlmax */ 2988 p->vset_insn = encode_vset(OPC_VSETVLI, TCG_REG_TMP0, TCG_REG_ZERO, vtype); 2989 } else { 2990 p->movi_insn = encode_i(OPC_ADDI, TCG_REG_TMP0, TCG_REG_ZERO, avl); 2991 p->vset_insn = encode_vset(OPC_VSETVLI, TCG_REG_ZERO, TCG_REG_TMP0, vtype); 2992 } 2993} 2994 2995static void probe_frac_lmul(void) 2996{ 2997 /* Match riscv_lg2_vlenb to TCG_TYPE_V64. */ 2998 QEMU_BUILD_BUG_ON(TCG_TYPE_V64 != 3); 2999 3000 for (TCGType t = TCG_TYPE_V64; t <= TCG_TYPE_V256; t++) { 3001 for (MemOp e = MO_8; e <= MO_64; e++) { 3002 probe_frac_lmul_1(t, e); 3003 } 3004 } 3005} 3006 3007static void tcg_target_init(TCGContext *s) 3008{ 3009 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 3010 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 3011 3012 tcg_target_call_clobber_regs = -1; 3013 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 3014 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 3015 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 3016 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 3017 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 3018 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 3019 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 3020 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 3021 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 3022 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 3023 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10); 3024 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11); 3025 3026 s->reserved_regs = 0; 3027 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 3028 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 3029 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 3030 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 3031 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 3032 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); 3033 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 3034 3035 if (cpuinfo & CPUINFO_ZVE64X) { 3036 switch (riscv_lg2_vlenb) { 3037 case TCG_TYPE_V64: 3038 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 3039 tcg_target_available_regs[TCG_TYPE_V128] = ALL_DVECTOR_REG_GROUPS; 3040 tcg_target_available_regs[TCG_TYPE_V256] = ALL_QVECTOR_REG_GROUPS; 3041 s->reserved_regs |= (~ALL_QVECTOR_REG_GROUPS & ALL_VECTOR_REGS); 3042 break; 3043 case TCG_TYPE_V128: 3044 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 3045 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 3046 tcg_target_available_regs[TCG_TYPE_V256] = ALL_DVECTOR_REG_GROUPS; 3047 s->reserved_regs |= (~ALL_DVECTOR_REG_GROUPS & ALL_VECTOR_REGS); 3048 break; 3049 default: 3050 /* Guaranteed by Zve64x. */ 3051 tcg_debug_assert(riscv_lg2_vlenb >= TCG_TYPE_V256); 3052 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 3053 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 3054 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 3055 break; 3056 } 3057 tcg_regset_set_reg(s->reserved_regs, TCG_REG_V0); 3058 probe_frac_lmul(); 3059 } 3060} 3061 3062typedef struct { 3063 DebugFrameHeader h; 3064 uint8_t fde_def_cfa[4]; 3065 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 3066} DebugFrame; 3067 3068#define ELF_HOST_MACHINE EM_RISCV 3069 3070static const DebugFrame debug_frame = { 3071 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 3072 .h.cie.id = -1, 3073 .h.cie.version = 1, 3074 .h.cie.code_align = 1, 3075 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 3076 .h.cie.return_column = TCG_REG_RA, 3077 3078 /* Total FDE size does not include the "len" member. */ 3079 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 3080 3081 .fde_def_cfa = { 3082 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 3083 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3084 (FRAME_SIZE >> 7) 3085 }, 3086 .fde_reg_ofs = { 3087 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ 3088 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ 3089 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ 3090 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ 3091 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ 3092 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ 3093 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ 3094 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ 3095 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ 3096 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ 3097 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ 3098 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 3099 } 3100}; 3101 3102void tcg_register_jit(const void *buf, size_t buf_size) 3103{ 3104 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 3105} 3106