1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2018 SiFive, Inc 5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 7 * Copyright (c) 2008 Fabrice Bellard 8 * 9 * Based on i386/tcg-target.c and mips/tcg-target.c 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a copy 12 * of this software and associated documentation files (the "Software"), to deal 13 * in the Software without restriction, including without limitation the rights 14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 * copies of the Software, and to permit persons to whom the Software is 16 * furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 * THE SOFTWARE. 28 */ 29 30#include "../tcg-pool.c.inc" 31 32#ifdef CONFIG_DEBUG_TCG 33static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 34 "zero", 35 "ra", 36 "sp", 37 "gp", 38 "tp", 39 "t0", 40 "t1", 41 "t2", 42 "s0", 43 "s1", 44 "a0", 45 "a1", 46 "a2", 47 "a3", 48 "a4", 49 "a5", 50 "a6", 51 "a7", 52 "s2", 53 "s3", 54 "s4", 55 "s5", 56 "s6", 57 "s7", 58 "s8", 59 "s9", 60 "s10", 61 "s11", 62 "t3", 63 "t4", 64 "t5", 65 "t6" 66}; 67#endif 68 69static const int tcg_target_reg_alloc_order[] = { 70 /* Call saved registers */ 71 /* TCG_REG_S0 reservered for TCG_AREG0 */ 72 TCG_REG_S1, 73 TCG_REG_S2, 74 TCG_REG_S3, 75 TCG_REG_S4, 76 TCG_REG_S5, 77 TCG_REG_S6, 78 TCG_REG_S7, 79 TCG_REG_S8, 80 TCG_REG_S9, 81 TCG_REG_S10, 82 TCG_REG_S11, 83 84 /* Call clobbered registers */ 85 TCG_REG_T0, 86 TCG_REG_T1, 87 TCG_REG_T2, 88 TCG_REG_T3, 89 TCG_REG_T4, 90 TCG_REG_T5, 91 TCG_REG_T6, 92 93 /* Argument registers */ 94 TCG_REG_A0, 95 TCG_REG_A1, 96 TCG_REG_A2, 97 TCG_REG_A3, 98 TCG_REG_A4, 99 TCG_REG_A5, 100 TCG_REG_A6, 101 TCG_REG_A7, 102}; 103 104static const int tcg_target_call_iarg_regs[] = { 105 TCG_REG_A0, 106 TCG_REG_A1, 107 TCG_REG_A2, 108 TCG_REG_A3, 109 TCG_REG_A4, 110 TCG_REG_A5, 111 TCG_REG_A6, 112 TCG_REG_A7, 113}; 114 115static const int tcg_target_call_oarg_regs[] = { 116 TCG_REG_A0, 117 TCG_REG_A1, 118}; 119 120#define TCG_CT_CONST_ZERO 0x100 121#define TCG_CT_CONST_S12 0x200 122#define TCG_CT_CONST_N12 0x400 123#define TCG_CT_CONST_M12 0x800 124 125static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 126{ 127 if (TCG_TARGET_REG_BITS == 32) { 128 return sextract32(val, pos, len); 129 } else { 130 return sextract64(val, pos, len); 131 } 132} 133 134/* parse target specific constraints */ 135static const char *target_parse_constraint(TCGArgConstraint *ct, 136 const char *ct_str, TCGType type) 137{ 138 switch (*ct_str++) { 139 case 'r': 140 ct->regs = 0xffffffff; 141 break; 142 case 'L': 143 /* qemu_ld/qemu_st constraint */ 144 ct->regs = 0xffffffff; 145 /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ 146#if defined(CONFIG_SOFTMMU) 147 tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]); 148 tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]); 149 tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]); 150 tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]); 151 tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]); 152#endif 153 break; 154 case 'I': 155 ct->ct |= TCG_CT_CONST_S12; 156 break; 157 case 'N': 158 ct->ct |= TCG_CT_CONST_N12; 159 break; 160 case 'M': 161 ct->ct |= TCG_CT_CONST_M12; 162 break; 163 case 'Z': 164 /* we can use a zero immediate as a zero register argument. */ 165 ct->ct |= TCG_CT_CONST_ZERO; 166 break; 167 default: 168 return NULL; 169 } 170 return ct_str; 171} 172 173/* test if a constant matches the constraint */ 174static int tcg_target_const_match(tcg_target_long val, TCGType type, 175 const TCGArgConstraint *arg_ct) 176{ 177 int ct = arg_ct->ct; 178 if (ct & TCG_CT_CONST) { 179 return 1; 180 } 181 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 182 return 1; 183 } 184 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 185 return 1; 186 } 187 if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { 188 return 1; 189 } 190 if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) { 191 return 1; 192 } 193 return 0; 194} 195 196/* 197 * RISC-V Base ISA opcodes (IM) 198 */ 199 200typedef enum { 201 OPC_ADD = 0x33, 202 OPC_ADDI = 0x13, 203 OPC_AND = 0x7033, 204 OPC_ANDI = 0x7013, 205 OPC_AUIPC = 0x17, 206 OPC_BEQ = 0x63, 207 OPC_BGE = 0x5063, 208 OPC_BGEU = 0x7063, 209 OPC_BLT = 0x4063, 210 OPC_BLTU = 0x6063, 211 OPC_BNE = 0x1063, 212 OPC_DIV = 0x2004033, 213 OPC_DIVU = 0x2005033, 214 OPC_JAL = 0x6f, 215 OPC_JALR = 0x67, 216 OPC_LB = 0x3, 217 OPC_LBU = 0x4003, 218 OPC_LD = 0x3003, 219 OPC_LH = 0x1003, 220 OPC_LHU = 0x5003, 221 OPC_LUI = 0x37, 222 OPC_LW = 0x2003, 223 OPC_LWU = 0x6003, 224 OPC_MUL = 0x2000033, 225 OPC_MULH = 0x2001033, 226 OPC_MULHSU = 0x2002033, 227 OPC_MULHU = 0x2003033, 228 OPC_OR = 0x6033, 229 OPC_ORI = 0x6013, 230 OPC_REM = 0x2006033, 231 OPC_REMU = 0x2007033, 232 OPC_SB = 0x23, 233 OPC_SD = 0x3023, 234 OPC_SH = 0x1023, 235 OPC_SLL = 0x1033, 236 OPC_SLLI = 0x1013, 237 OPC_SLT = 0x2033, 238 OPC_SLTI = 0x2013, 239 OPC_SLTIU = 0x3013, 240 OPC_SLTU = 0x3033, 241 OPC_SRA = 0x40005033, 242 OPC_SRAI = 0x40005013, 243 OPC_SRL = 0x5033, 244 OPC_SRLI = 0x5013, 245 OPC_SUB = 0x40000033, 246 OPC_SW = 0x2023, 247 OPC_XOR = 0x4033, 248 OPC_XORI = 0x4013, 249 250#if TCG_TARGET_REG_BITS == 64 251 OPC_ADDIW = 0x1b, 252 OPC_ADDW = 0x3b, 253 OPC_DIVUW = 0x200503b, 254 OPC_DIVW = 0x200403b, 255 OPC_MULW = 0x200003b, 256 OPC_REMUW = 0x200703b, 257 OPC_REMW = 0x200603b, 258 OPC_SLLIW = 0x101b, 259 OPC_SLLW = 0x103b, 260 OPC_SRAIW = 0x4000501b, 261 OPC_SRAW = 0x4000503b, 262 OPC_SRLIW = 0x501b, 263 OPC_SRLW = 0x503b, 264 OPC_SUBW = 0x4000003b, 265#else 266 /* Simplify code throughout by defining aliases for RV32. */ 267 OPC_ADDIW = OPC_ADDI, 268 OPC_ADDW = OPC_ADD, 269 OPC_DIVUW = OPC_DIVU, 270 OPC_DIVW = OPC_DIV, 271 OPC_MULW = OPC_MUL, 272 OPC_REMUW = OPC_REMU, 273 OPC_REMW = OPC_REM, 274 OPC_SLLIW = OPC_SLLI, 275 OPC_SLLW = OPC_SLL, 276 OPC_SRAIW = OPC_SRAI, 277 OPC_SRAW = OPC_SRA, 278 OPC_SRLIW = OPC_SRLI, 279 OPC_SRLW = OPC_SRL, 280 OPC_SUBW = OPC_SUB, 281#endif 282 283 OPC_FENCE = 0x0000000f, 284} RISCVInsn; 285 286/* 287 * RISC-V immediate and instruction encoders (excludes 16-bit RVC) 288 */ 289 290/* Type-R */ 291 292static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) 293{ 294 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; 295} 296 297/* Type-I */ 298 299static int32_t encode_imm12(uint32_t imm) 300{ 301 return (imm & 0xfff) << 20; 302} 303 304static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) 305{ 306 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); 307} 308 309/* Type-S */ 310 311static int32_t encode_simm12(uint32_t imm) 312{ 313 int32_t ret = 0; 314 315 ret |= (imm & 0xFE0) << 20; 316 ret |= (imm & 0x1F) << 7; 317 318 return ret; 319} 320 321static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 322{ 323 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); 324} 325 326/* Type-SB */ 327 328static int32_t encode_sbimm12(uint32_t imm) 329{ 330 int32_t ret = 0; 331 332 ret |= (imm & 0x1000) << 19; 333 ret |= (imm & 0x7e0) << 20; 334 ret |= (imm & 0x1e) << 7; 335 ret |= (imm & 0x800) >> 4; 336 337 return ret; 338} 339 340static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 341{ 342 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); 343} 344 345/* Type-U */ 346 347static int32_t encode_uimm20(uint32_t imm) 348{ 349 return imm & 0xfffff000; 350} 351 352static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) 353{ 354 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); 355} 356 357/* Type-UJ */ 358 359static int32_t encode_ujimm20(uint32_t imm) 360{ 361 int32_t ret = 0; 362 363 ret |= (imm & 0x0007fe) << (21 - 1); 364 ret |= (imm & 0x000800) << (20 - 11); 365 ret |= (imm & 0x0ff000) << (12 - 12); 366 ret |= (imm & 0x100000) << (31 - 20); 367 368 return ret; 369} 370 371static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) 372{ 373 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); 374} 375 376/* 377 * RISC-V instruction emitters 378 */ 379 380static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc, 381 TCGReg rd, TCGReg rs1, TCGReg rs2) 382{ 383 tcg_out32(s, encode_r(opc, rd, rs1, rs2)); 384} 385 386static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc, 387 TCGReg rd, TCGReg rs1, TCGArg imm) 388{ 389 tcg_out32(s, encode_i(opc, rd, rs1, imm)); 390} 391 392static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc, 393 TCGReg rs1, TCGReg rs2, uint32_t imm) 394{ 395 tcg_out32(s, encode_s(opc, rs1, rs2, imm)); 396} 397 398static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc, 399 TCGReg rs1, TCGReg rs2, uint32_t imm) 400{ 401 tcg_out32(s, encode_sb(opc, rs1, rs2, imm)); 402} 403 404static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc, 405 TCGReg rd, uint32_t imm) 406{ 407 tcg_out32(s, encode_u(opc, rd, imm)); 408} 409 410static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, 411 TCGReg rd, uint32_t imm) 412{ 413 tcg_out32(s, encode_uj(opc, rd, imm)); 414} 415 416static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 417{ 418 int i; 419 for (i = 0; i < count; ++i) { 420 p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); 421 } 422} 423 424/* 425 * Relocations 426 */ 427 428static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) 429{ 430 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; 431 432 if (offset == sextreg(offset, 1, 12) << 1) { 433 code_ptr[0] |= encode_sbimm12(offset); 434 return true; 435 } 436 437 return false; 438} 439 440static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) 441{ 442 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; 443 444 if (offset == sextreg(offset, 1, 20) << 1) { 445 code_ptr[0] |= encode_ujimm20(offset); 446 return true; 447 } 448 449 return false; 450} 451 452static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target) 453{ 454 intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; 455 int32_t lo = sextreg(offset, 0, 12); 456 int32_t hi = offset - lo; 457 458 if (offset == hi + lo) { 459 code_ptr[0] |= encode_uimm20(hi); 460 code_ptr[1] |= encode_imm12(lo); 461 return true; 462 } 463 464 return false; 465} 466 467static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 468 intptr_t value, intptr_t addend) 469{ 470 uint32_t insn = *code_ptr; 471 intptr_t diff; 472 bool short_jmp; 473 474 tcg_debug_assert(addend == 0); 475 476 switch (type) { 477 case R_RISCV_BRANCH: 478 diff = value - (uintptr_t)code_ptr; 479 short_jmp = diff == sextreg(diff, 0, 12); 480 if (short_jmp) { 481 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); 482 } else { 483 /* Invert the condition */ 484 insn = insn ^ (1 << 12); 485 /* Clear the offset */ 486 insn &= 0x01fff07f; 487 /* Set the offset to the PC + 8 */ 488 insn |= encode_sbimm12(8); 489 490 /* Move forward */ 491 code_ptr[0] = insn; 492 493 /* Overwrite the NOP with jal x0,value */ 494 diff = value - (uintptr_t)(code_ptr + 1); 495 insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff); 496 code_ptr[1] = insn; 497 498 return true; 499 } 500 break; 501 case R_RISCV_JAL: 502 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); 503 case R_RISCV_CALL: 504 return reloc_call(code_ptr, (tcg_insn_unit *)value); 505 default: 506 tcg_abort(); 507 } 508} 509 510/* 511 * TCG intrinsics 512 */ 513 514static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 515{ 516 if (ret == arg) { 517 return true; 518 } 519 switch (type) { 520 case TCG_TYPE_I32: 521 case TCG_TYPE_I64: 522 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); 523 break; 524 default: 525 g_assert_not_reached(); 526 } 527 return true; 528} 529 530static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 531 tcg_target_long val) 532{ 533 tcg_target_long lo, hi, tmp; 534 int shift, ret; 535 536 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 537 val = (int32_t)val; 538 } 539 540 lo = sextreg(val, 0, 12); 541 if (val == lo) { 542 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo); 543 return; 544 } 545 546 hi = val - lo; 547 if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) { 548 tcg_out_opc_upper(s, OPC_LUI, rd, hi); 549 if (lo != 0) { 550 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); 551 } 552 return; 553 } 554 555 /* We can only be here if TCG_TARGET_REG_BITS != 32 */ 556 tmp = tcg_pcrel_diff(s, (void *)val); 557 if (tmp == (int32_t)tmp) { 558 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 559 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); 560 ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); 561 tcg_debug_assert(ret == true); 562 return; 563 } 564 565 /* Look for a single 20-bit section. */ 566 shift = ctz64(val); 567 tmp = val >> shift; 568 if (tmp == sextreg(tmp, 0, 20)) { 569 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12); 570 if (shift > 12) { 571 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12); 572 } else { 573 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift); 574 } 575 return; 576 } 577 578 /* Look for a few high zero bits, with lots of bits set in the middle. */ 579 shift = clz64(val); 580 tmp = val << shift; 581 if (tmp == sextreg(tmp, 12, 20) << 12) { 582 tcg_out_opc_upper(s, OPC_LUI, rd, tmp); 583 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 584 return; 585 } else if (tmp == sextreg(tmp, 0, 12)) { 586 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp); 587 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 588 return; 589 } 590 591 /* Drop into the constant pool. */ 592 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0); 593 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 594 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); 595} 596 597static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 598{ 599 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); 600} 601 602static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 603{ 604 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 605 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16); 606} 607 608static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 609{ 610 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); 611 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); 612} 613 614static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) 615{ 616 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); 617 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); 618} 619 620static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) 621{ 622 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 623 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); 624} 625 626static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 627{ 628 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); 629} 630 631static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, 632 TCGReg addr, intptr_t offset) 633{ 634 intptr_t imm12 = sextreg(offset, 0, 12); 635 636 if (offset != imm12) { 637 intptr_t diff = offset - (uintptr_t)s->code_ptr; 638 639 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 640 imm12 = sextreg(diff, 0, 12); 641 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12); 642 } else { 643 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 644 if (addr != TCG_REG_ZERO) { 645 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr); 646 } 647 } 648 addr = TCG_REG_TMP2; 649 } 650 651 switch (opc) { 652 case OPC_SB: 653 case OPC_SH: 654 case OPC_SW: 655 case OPC_SD: 656 tcg_out_opc_store(s, opc, addr, data, imm12); 657 break; 658 case OPC_LB: 659 case OPC_LBU: 660 case OPC_LH: 661 case OPC_LHU: 662 case OPC_LW: 663 case OPC_LWU: 664 case OPC_LD: 665 tcg_out_opc_imm(s, opc, data, addr, imm12); 666 break; 667 default: 668 g_assert_not_reached(); 669 } 670} 671 672static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 673 TCGReg arg1, intptr_t arg2) 674{ 675 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); 676 tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2); 677} 678 679static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 680 TCGReg arg1, intptr_t arg2) 681{ 682 bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); 683 tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2); 684} 685 686static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 687 TCGReg base, intptr_t ofs) 688{ 689 if (val == 0) { 690 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 691 return true; 692 } 693 return false; 694} 695 696static void tcg_out_addsub2(TCGContext *s, 697 TCGReg rl, TCGReg rh, 698 TCGReg al, TCGReg ah, 699 TCGArg bl, TCGArg bh, 700 bool cbl, bool cbh, bool is_sub, bool is32bit) 701{ 702 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD; 703 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI; 704 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB; 705 TCGReg th = TCG_REG_TMP1; 706 707 /* If we have a negative constant such that negating it would 708 make the high part zero, we can (usually) eliminate one insn. */ 709 if (cbl && cbh && bh == -1 && bl != 0) { 710 bl = -bl; 711 bh = 0; 712 is_sub = !is_sub; 713 } 714 715 /* By operating on the high part first, we get to use the final 716 carry operation to move back from the temporary. */ 717 if (!cbh) { 718 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh); 719 } else if (bh != 0 || ah == rl) { 720 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh)); 721 } else { 722 th = ah; 723 } 724 725 /* Note that tcg optimization should eliminate the bl == 0 case. */ 726 if (is_sub) { 727 if (cbl) { 728 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl); 729 tcg_out_opc_imm(s, opc_addi, rl, al, -bl); 730 } else { 731 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl); 732 tcg_out_opc_reg(s, opc_sub, rl, al, bl); 733 } 734 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0); 735 } else { 736 if (cbl) { 737 tcg_out_opc_imm(s, opc_addi, rl, al, bl); 738 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); 739 } else if (rl == al && rl == bl) { 740 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); 741 tcg_out_opc_reg(s, opc_addi, rl, al, bl); 742 } else { 743 tcg_out_opc_reg(s, opc_add, rl, al, bl); 744 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, 745 rl, (rl == bl ? al : bl)); 746 } 747 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0); 748 } 749} 750 751static const struct { 752 RISCVInsn op; 753 bool swap; 754} tcg_brcond_to_riscv[] = { 755 [TCG_COND_EQ] = { OPC_BEQ, false }, 756 [TCG_COND_NE] = { OPC_BNE, false }, 757 [TCG_COND_LT] = { OPC_BLT, false }, 758 [TCG_COND_GE] = { OPC_BGE, false }, 759 [TCG_COND_LE] = { OPC_BGE, true }, 760 [TCG_COND_GT] = { OPC_BLT, true }, 761 [TCG_COND_LTU] = { OPC_BLTU, false }, 762 [TCG_COND_GEU] = { OPC_BGEU, false }, 763 [TCG_COND_LEU] = { OPC_BGEU, true }, 764 [TCG_COND_GTU] = { OPC_BLTU, true } 765}; 766 767static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 768 TCGReg arg2, TCGLabel *l) 769{ 770 RISCVInsn op = tcg_brcond_to_riscv[cond].op; 771 772 tcg_debug_assert(op != 0); 773 774 if (tcg_brcond_to_riscv[cond].swap) { 775 TCGReg t = arg1; 776 arg1 = arg2; 777 arg2 = t; 778 } 779 780 if (l->has_value) { 781 intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr); 782 if (diff == sextreg(diff, 0, 12)) { 783 tcg_out_opc_branch(s, op, arg1, arg2, diff); 784 } else { 785 /* Invert the conditional branch. */ 786 tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8); 787 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4); 788 } 789 } else { 790 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); 791 tcg_out_opc_branch(s, op, arg1, arg2, 0); 792 /* NOP to allow patching later */ 793 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); 794 } 795} 796 797static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 798 TCGReg arg1, TCGReg arg2) 799{ 800 switch (cond) { 801 case TCG_COND_EQ: 802 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); 803 tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1); 804 break; 805 case TCG_COND_NE: 806 tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); 807 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret); 808 break; 809 case TCG_COND_LT: 810 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 811 break; 812 case TCG_COND_GE: 813 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 814 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 815 break; 816 case TCG_COND_LE: 817 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 818 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 819 break; 820 case TCG_COND_GT: 821 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 822 break; 823 case TCG_COND_LTU: 824 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 825 break; 826 case TCG_COND_GEU: 827 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 828 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 829 break; 830 case TCG_COND_LEU: 831 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 832 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 833 break; 834 case TCG_COND_GTU: 835 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 836 break; 837 default: 838 g_assert_not_reached(); 839 break; 840 } 841} 842 843static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 844 TCGReg bl, TCGReg bh, TCGLabel *l) 845{ 846 /* todo */ 847 g_assert_not_reached(); 848} 849 850static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 851 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 852{ 853 /* todo */ 854 g_assert_not_reached(); 855} 856 857static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) 858{ 859 ptrdiff_t offset = tcg_pcrel_diff(s, target); 860 tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1); 861 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); 862} 863 864static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) 865{ 866 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 867 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 868 int ret; 869 870 if (offset == sextreg(offset, 1, 20) << 1) { 871 /* short jump: -2097150 to 2097152 */ 872 tcg_out_opc_jump(s, OPC_JAL, link, offset); 873 } else if (TCG_TARGET_REG_BITS == 32 || 874 offset == sextreg(offset, 1, 31) << 1) { 875 /* long jump: -2147483646 to 2147483648 */ 876 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); 877 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); 878 ret = reloc_call(s->code_ptr - 2, arg);\ 879 tcg_debug_assert(ret == true); 880 } else if (TCG_TARGET_REG_BITS == 64) { 881 /* far jump: 64-bit */ 882 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); 883 tcg_target_long base = (tcg_target_long)arg - imm; 884 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); 885 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); 886 } else { 887 g_assert_not_reached(); 888 } 889} 890 891static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) 892{ 893 tcg_out_call_int(s, arg, false); 894} 895 896static void tcg_out_mb(TCGContext *s, TCGArg a0) 897{ 898 tcg_insn_unit insn = OPC_FENCE; 899 900 if (a0 & TCG_MO_LD_LD) { 901 insn |= 0x02200000; 902 } 903 if (a0 & TCG_MO_ST_LD) { 904 insn |= 0x01200000; 905 } 906 if (a0 & TCG_MO_LD_ST) { 907 insn |= 0x02100000; 908 } 909 if (a0 & TCG_MO_ST_ST) { 910 insn |= 0x02200000; 911 } 912 tcg_out32(s, insn); 913} 914 915/* 916 * Load/store and TLB 917 */ 918 919#if defined(CONFIG_SOFTMMU) 920#include "../tcg-ldst.c.inc" 921 922/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, 923 * TCGMemOpIdx oi, uintptr_t ra) 924 */ 925static void * const qemu_ld_helpers[16] = { 926 [MO_UB] = helper_ret_ldub_mmu, 927 [MO_SB] = helper_ret_ldsb_mmu, 928 [MO_LEUW] = helper_le_lduw_mmu, 929 [MO_LESW] = helper_le_ldsw_mmu, 930 [MO_LEUL] = helper_le_ldul_mmu, 931#if TCG_TARGET_REG_BITS == 64 932 [MO_LESL] = helper_le_ldsl_mmu, 933#endif 934 [MO_LEQ] = helper_le_ldq_mmu, 935 [MO_BEUW] = helper_be_lduw_mmu, 936 [MO_BESW] = helper_be_ldsw_mmu, 937 [MO_BEUL] = helper_be_ldul_mmu, 938#if TCG_TARGET_REG_BITS == 64 939 [MO_BESL] = helper_be_ldsl_mmu, 940#endif 941 [MO_BEQ] = helper_be_ldq_mmu, 942}; 943 944/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, 945 * uintxx_t val, TCGMemOpIdx oi, 946 * uintptr_t ra) 947 */ 948static void * const qemu_st_helpers[16] = { 949 [MO_UB] = helper_ret_stb_mmu, 950 [MO_LEUW] = helper_le_stw_mmu, 951 [MO_LEUL] = helper_le_stl_mmu, 952 [MO_LEQ] = helper_le_stq_mmu, 953 [MO_BEUW] = helper_be_stw_mmu, 954 [MO_BEUL] = helper_be_stl_mmu, 955 [MO_BEQ] = helper_be_stq_mmu, 956}; 957 958/* We don't support oversize guests */ 959QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS < TARGET_LONG_BITS); 960 961/* We expect to use a 12-bit negative offset from ENV. */ 962QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 963QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); 964 965static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, 966 TCGReg addrh, TCGMemOpIdx oi, 967 tcg_insn_unit **label_ptr, bool is_load) 968{ 969 MemOp opc = get_memop(oi); 970 unsigned s_bits = opc & MO_SIZE; 971 unsigned a_bits = get_alignment_bits(opc); 972 tcg_target_long compare_mask; 973 int mem_index = get_mmuidx(oi); 974 int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); 975 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 976 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 977 TCGReg mask_base = TCG_AREG0, table_base = TCG_AREG0; 978 979 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, mask_base, mask_ofs); 980 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, table_base, table_ofs); 981 982 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addrl, 983 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 984 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 985 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 986 987 /* Load the tlb comparator and the addend. */ 988 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, 989 is_load ? offsetof(CPUTLBEntry, addr_read) 990 : offsetof(CPUTLBEntry, addr_write)); 991 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 992 offsetof(CPUTLBEntry, addend)); 993 994 /* We don't support unaligned accesses. */ 995 if (a_bits < s_bits) { 996 a_bits = s_bits; 997 } 998 /* Clear the non-page, non-alignment bits from the address. */ 999 compare_mask = (tcg_target_long)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 1000 if (compare_mask == sextreg(compare_mask, 0, 12)) { 1001 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, compare_mask); 1002 } else { 1003 tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); 1004 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl); 1005 } 1006 1007 /* Compare masked address with the TLB entry. */ 1008 label_ptr[0] = s->code_ptr; 1009 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1010 /* NOP to allow patching later */ 1011 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); 1012 1013 /* TLB Hit - translate address using addend. */ 1014 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1015 tcg_out_ext32u(s, TCG_REG_TMP0, addrl); 1016 addrl = TCG_REG_TMP0; 1017 } 1018 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); 1019} 1020 1021static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, 1022 TCGType ext, 1023 TCGReg datalo, TCGReg datahi, 1024 TCGReg addrlo, TCGReg addrhi, 1025 void *raddr, tcg_insn_unit **label_ptr) 1026{ 1027 TCGLabelQemuLdst *label = new_ldst_label(s); 1028 1029 label->is_ld = is_ld; 1030 label->oi = oi; 1031 label->type = ext; 1032 label->datalo_reg = datalo; 1033 label->datahi_reg = datahi; 1034 label->addrlo_reg = addrlo; 1035 label->addrhi_reg = addrhi; 1036 label->raddr = raddr; 1037 label->label_ptr[0] = label_ptr[0]; 1038} 1039 1040static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1041{ 1042 TCGMemOpIdx oi = l->oi; 1043 MemOp opc = get_memop(oi); 1044 TCGReg a0 = tcg_target_call_iarg_regs[0]; 1045 TCGReg a1 = tcg_target_call_iarg_regs[1]; 1046 TCGReg a2 = tcg_target_call_iarg_regs[2]; 1047 TCGReg a3 = tcg_target_call_iarg_regs[3]; 1048 1049 /* We don't support oversize guests */ 1050 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1051 g_assert_not_reached(); 1052 } 1053 1054 /* resolve label address */ 1055 if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, 1056 (intptr_t) s->code_ptr, 0)) { 1057 return false; 1058 } 1059 1060 /* call load helper */ 1061 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); 1062 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); 1063 tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); 1064 tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); 1065 1066 tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); 1067 tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0); 1068 1069 tcg_out_goto(s, l->raddr); 1070 return true; 1071} 1072 1073static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1074{ 1075 TCGMemOpIdx oi = l->oi; 1076 MemOp opc = get_memop(oi); 1077 MemOp s_bits = opc & MO_SIZE; 1078 TCGReg a0 = tcg_target_call_iarg_regs[0]; 1079 TCGReg a1 = tcg_target_call_iarg_regs[1]; 1080 TCGReg a2 = tcg_target_call_iarg_regs[2]; 1081 TCGReg a3 = tcg_target_call_iarg_regs[3]; 1082 TCGReg a4 = tcg_target_call_iarg_regs[4]; 1083 1084 /* We don't support oversize guests */ 1085 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1086 g_assert_not_reached(); 1087 } 1088 1089 /* resolve label address */ 1090 if (!patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, 1091 (intptr_t) s->code_ptr, 0)) { 1092 return false; 1093 } 1094 1095 /* call store helper */ 1096 tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); 1097 tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); 1098 tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg); 1099 switch (s_bits) { 1100 case MO_8: 1101 tcg_out_ext8u(s, a2, a2); 1102 break; 1103 case MO_16: 1104 tcg_out_ext16u(s, a2, a2); 1105 break; 1106 default: 1107 break; 1108 } 1109 tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); 1110 tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); 1111 1112 tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]); 1113 1114 tcg_out_goto(s, l->raddr); 1115 return true; 1116} 1117#endif /* CONFIG_SOFTMMU */ 1118 1119static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1120 TCGReg base, MemOp opc, bool is_64) 1121{ 1122 const MemOp bswap = opc & MO_BSWAP; 1123 1124 /* We don't yet handle byteswapping, assert */ 1125 g_assert(!bswap); 1126 1127 switch (opc & (MO_SSIZE)) { 1128 case MO_UB: 1129 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1130 break; 1131 case MO_SB: 1132 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1133 break; 1134 case MO_UW: 1135 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1136 break; 1137 case MO_SW: 1138 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1139 break; 1140 case MO_UL: 1141 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1142 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1143 break; 1144 } 1145 /* FALLTHRU */ 1146 case MO_SL: 1147 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1148 break; 1149 case MO_Q: 1150 /* Prefer to load from offset 0 first, but allow for overlap. */ 1151 if (TCG_TARGET_REG_BITS == 64) { 1152 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1153 } else if (lo != base) { 1154 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1155 tcg_out_opc_imm(s, OPC_LW, hi, base, 4); 1156 } else { 1157 tcg_out_opc_imm(s, OPC_LW, hi, base, 4); 1158 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1159 } 1160 break; 1161 default: 1162 g_assert_not_reached(); 1163 } 1164} 1165 1166static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1167{ 1168 TCGReg addr_regl, addr_regh __attribute__((unused)); 1169 TCGReg data_regl, data_regh; 1170 TCGMemOpIdx oi; 1171 MemOp opc; 1172#if defined(CONFIG_SOFTMMU) 1173 tcg_insn_unit *label_ptr[1]; 1174#endif 1175 TCGReg base = TCG_REG_TMP0; 1176 1177 data_regl = *args++; 1178 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1179 addr_regl = *args++; 1180 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1181 oi = *args++; 1182 opc = get_memop(oi); 1183 1184#if defined(CONFIG_SOFTMMU) 1185 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); 1186 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1187 add_qemu_ldst_label(s, 1, oi, 1188 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1189 data_regl, data_regh, addr_regl, addr_regh, 1190 s->code_ptr, label_ptr); 1191#else 1192 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1193 tcg_out_ext32u(s, base, addr_regl); 1194 addr_regl = base; 1195 } 1196 1197 if (guest_base == 0) { 1198 tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); 1199 } else { 1200 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); 1201 } 1202 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1203#endif 1204} 1205 1206static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1207 TCGReg base, MemOp opc) 1208{ 1209 const MemOp bswap = opc & MO_BSWAP; 1210 1211 /* We don't yet handle byteswapping, assert */ 1212 g_assert(!bswap); 1213 1214 switch (opc & (MO_SSIZE)) { 1215 case MO_8: 1216 tcg_out_opc_store(s, OPC_SB, base, lo, 0); 1217 break; 1218 case MO_16: 1219 tcg_out_opc_store(s, OPC_SH, base, lo, 0); 1220 break; 1221 case MO_32: 1222 tcg_out_opc_store(s, OPC_SW, base, lo, 0); 1223 break; 1224 case MO_64: 1225 if (TCG_TARGET_REG_BITS == 64) { 1226 tcg_out_opc_store(s, OPC_SD, base, lo, 0); 1227 } else { 1228 tcg_out_opc_store(s, OPC_SW, base, lo, 0); 1229 tcg_out_opc_store(s, OPC_SW, base, hi, 4); 1230 } 1231 break; 1232 default: 1233 g_assert_not_reached(); 1234 } 1235} 1236 1237static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1238{ 1239 TCGReg addr_regl, addr_regh __attribute__((unused)); 1240 TCGReg data_regl, data_regh; 1241 TCGMemOpIdx oi; 1242 MemOp opc; 1243#if defined(CONFIG_SOFTMMU) 1244 tcg_insn_unit *label_ptr[1]; 1245#endif 1246 TCGReg base = TCG_REG_TMP0; 1247 1248 data_regl = *args++; 1249 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1250 addr_regl = *args++; 1251 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1252 oi = *args++; 1253 opc = get_memop(oi); 1254 1255#if defined(CONFIG_SOFTMMU) 1256 tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); 1257 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1258 add_qemu_ldst_label(s, 0, oi, 1259 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1260 data_regl, data_regh, addr_regl, addr_regh, 1261 s->code_ptr, label_ptr); 1262#else 1263 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1264 tcg_out_ext32u(s, base, addr_regl); 1265 addr_regl = base; 1266 } 1267 1268 if (guest_base == 0) { 1269 tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); 1270 } else { 1271 tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); 1272 } 1273 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1274#endif 1275} 1276 1277static tcg_insn_unit *tb_ret_addr; 1278 1279static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1280 const TCGArg *args, const int *const_args) 1281{ 1282 TCGArg a0 = args[0]; 1283 TCGArg a1 = args[1]; 1284 TCGArg a2 = args[2]; 1285 int c2 = const_args[2]; 1286 1287 switch (opc) { 1288 case INDEX_op_exit_tb: 1289 /* Reuse the zeroing that exists for goto_ptr. */ 1290 if (a0 == 0) { 1291 tcg_out_call_int(s, s->code_gen_epilogue, true); 1292 } else { 1293 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1294 tcg_out_call_int(s, tb_ret_addr, true); 1295 } 1296 break; 1297 1298 case INDEX_op_goto_tb: 1299 assert(s->tb_jmp_insn_offset == 0); 1300 /* indirect jump method */ 1301 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, 1302 (uintptr_t)(s->tb_jmp_target_addr + a0)); 1303 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1304 set_jmp_reset_offset(s, a0); 1305 break; 1306 1307 case INDEX_op_goto_ptr: 1308 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); 1309 break; 1310 1311 case INDEX_op_br: 1312 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0); 1313 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 1314 break; 1315 1316 case INDEX_op_ld8u_i32: 1317 case INDEX_op_ld8u_i64: 1318 tcg_out_ldst(s, OPC_LBU, a0, a1, a2); 1319 break; 1320 case INDEX_op_ld8s_i32: 1321 case INDEX_op_ld8s_i64: 1322 tcg_out_ldst(s, OPC_LB, a0, a1, a2); 1323 break; 1324 case INDEX_op_ld16u_i32: 1325 case INDEX_op_ld16u_i64: 1326 tcg_out_ldst(s, OPC_LHU, a0, a1, a2); 1327 break; 1328 case INDEX_op_ld16s_i32: 1329 case INDEX_op_ld16s_i64: 1330 tcg_out_ldst(s, OPC_LH, a0, a1, a2); 1331 break; 1332 case INDEX_op_ld32u_i64: 1333 tcg_out_ldst(s, OPC_LWU, a0, a1, a2); 1334 break; 1335 case INDEX_op_ld_i32: 1336 case INDEX_op_ld32s_i64: 1337 tcg_out_ldst(s, OPC_LW, a0, a1, a2); 1338 break; 1339 case INDEX_op_ld_i64: 1340 tcg_out_ldst(s, OPC_LD, a0, a1, a2); 1341 break; 1342 1343 case INDEX_op_st8_i32: 1344 case INDEX_op_st8_i64: 1345 tcg_out_ldst(s, OPC_SB, a0, a1, a2); 1346 break; 1347 case INDEX_op_st16_i32: 1348 case INDEX_op_st16_i64: 1349 tcg_out_ldst(s, OPC_SH, a0, a1, a2); 1350 break; 1351 case INDEX_op_st_i32: 1352 case INDEX_op_st32_i64: 1353 tcg_out_ldst(s, OPC_SW, a0, a1, a2); 1354 break; 1355 case INDEX_op_st_i64: 1356 tcg_out_ldst(s, OPC_SD, a0, a1, a2); 1357 break; 1358 1359 case INDEX_op_add_i32: 1360 if (c2) { 1361 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2); 1362 } else { 1363 tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2); 1364 } 1365 break; 1366 case INDEX_op_add_i64: 1367 if (c2) { 1368 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2); 1369 } else { 1370 tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2); 1371 } 1372 break; 1373 1374 case INDEX_op_sub_i32: 1375 if (c2) { 1376 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2); 1377 } else { 1378 tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); 1379 } 1380 break; 1381 case INDEX_op_sub_i64: 1382 if (c2) { 1383 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2); 1384 } else { 1385 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); 1386 } 1387 break; 1388 1389 case INDEX_op_and_i32: 1390 case INDEX_op_and_i64: 1391 if (c2) { 1392 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1393 } else { 1394 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1395 } 1396 break; 1397 1398 case INDEX_op_or_i32: 1399 case INDEX_op_or_i64: 1400 if (c2) { 1401 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1402 } else { 1403 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1404 } 1405 break; 1406 1407 case INDEX_op_xor_i32: 1408 case INDEX_op_xor_i64: 1409 if (c2) { 1410 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 1411 } else { 1412 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 1413 } 1414 break; 1415 1416 case INDEX_op_not_i32: 1417 case INDEX_op_not_i64: 1418 tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1); 1419 break; 1420 1421 case INDEX_op_neg_i32: 1422 tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1); 1423 break; 1424 case INDEX_op_neg_i64: 1425 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1); 1426 break; 1427 1428 case INDEX_op_mul_i32: 1429 tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2); 1430 break; 1431 case INDEX_op_mul_i64: 1432 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1433 break; 1434 1435 case INDEX_op_div_i32: 1436 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2); 1437 break; 1438 case INDEX_op_div_i64: 1439 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2); 1440 break; 1441 1442 case INDEX_op_divu_i32: 1443 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2); 1444 break; 1445 case INDEX_op_divu_i64: 1446 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2); 1447 break; 1448 1449 case INDEX_op_rem_i32: 1450 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2); 1451 break; 1452 case INDEX_op_rem_i64: 1453 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2); 1454 break; 1455 1456 case INDEX_op_remu_i32: 1457 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2); 1458 break; 1459 case INDEX_op_remu_i64: 1460 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2); 1461 break; 1462 1463 case INDEX_op_shl_i32: 1464 if (c2) { 1465 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2); 1466 } else { 1467 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2); 1468 } 1469 break; 1470 case INDEX_op_shl_i64: 1471 if (c2) { 1472 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2); 1473 } else { 1474 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2); 1475 } 1476 break; 1477 1478 case INDEX_op_shr_i32: 1479 if (c2) { 1480 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); 1481 } else { 1482 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2); 1483 } 1484 break; 1485 case INDEX_op_shr_i64: 1486 if (c2) { 1487 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2); 1488 } else { 1489 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2); 1490 } 1491 break; 1492 1493 case INDEX_op_sar_i32: 1494 if (c2) { 1495 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2); 1496 } else { 1497 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2); 1498 } 1499 break; 1500 case INDEX_op_sar_i64: 1501 if (c2) { 1502 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2); 1503 } else { 1504 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2); 1505 } 1506 break; 1507 1508 case INDEX_op_add2_i32: 1509 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1510 const_args[4], const_args[5], false, true); 1511 break; 1512 case INDEX_op_add2_i64: 1513 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1514 const_args[4], const_args[5], false, false); 1515 break; 1516 case INDEX_op_sub2_i32: 1517 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1518 const_args[4], const_args[5], true, true); 1519 break; 1520 case INDEX_op_sub2_i64: 1521 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1522 const_args[4], const_args[5], true, false); 1523 break; 1524 1525 case INDEX_op_brcond_i32: 1526 case INDEX_op_brcond_i64: 1527 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1528 break; 1529 case INDEX_op_brcond2_i32: 1530 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 1531 break; 1532 1533 case INDEX_op_setcond_i32: 1534 case INDEX_op_setcond_i64: 1535 tcg_out_setcond(s, args[3], a0, a1, a2); 1536 break; 1537 case INDEX_op_setcond2_i32: 1538 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 1539 break; 1540 1541 case INDEX_op_qemu_ld_i32: 1542 tcg_out_qemu_ld(s, args, false); 1543 break; 1544 case INDEX_op_qemu_ld_i64: 1545 tcg_out_qemu_ld(s, args, true); 1546 break; 1547 case INDEX_op_qemu_st_i32: 1548 tcg_out_qemu_st(s, args, false); 1549 break; 1550 case INDEX_op_qemu_st_i64: 1551 tcg_out_qemu_st(s, args, true); 1552 break; 1553 1554 case INDEX_op_ext8u_i32: 1555 case INDEX_op_ext8u_i64: 1556 tcg_out_ext8u(s, a0, a1); 1557 break; 1558 1559 case INDEX_op_ext16u_i32: 1560 case INDEX_op_ext16u_i64: 1561 tcg_out_ext16u(s, a0, a1); 1562 break; 1563 1564 case INDEX_op_ext32u_i64: 1565 case INDEX_op_extu_i32_i64: 1566 tcg_out_ext32u(s, a0, a1); 1567 break; 1568 1569 case INDEX_op_ext8s_i32: 1570 case INDEX_op_ext8s_i64: 1571 tcg_out_ext8s(s, a0, a1); 1572 break; 1573 1574 case INDEX_op_ext16s_i32: 1575 case INDEX_op_ext16s_i64: 1576 tcg_out_ext16s(s, a0, a1); 1577 break; 1578 1579 case INDEX_op_ext32s_i64: 1580 case INDEX_op_extrl_i64_i32: 1581 case INDEX_op_ext_i32_i64: 1582 tcg_out_ext32s(s, a0, a1); 1583 break; 1584 1585 case INDEX_op_extrh_i64_i32: 1586 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); 1587 break; 1588 1589 case INDEX_op_mulsh_i32: 1590 case INDEX_op_mulsh_i64: 1591 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); 1592 break; 1593 1594 case INDEX_op_muluh_i32: 1595 case INDEX_op_muluh_i64: 1596 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); 1597 break; 1598 1599 case INDEX_op_mb: 1600 tcg_out_mb(s, a0); 1601 break; 1602 1603 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1604 case INDEX_op_mov_i64: 1605 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ 1606 case INDEX_op_movi_i64: 1607 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1608 default: 1609 g_assert_not_reached(); 1610 } 1611} 1612 1613static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) 1614{ 1615 static const TCGTargetOpDef r 1616 = { .args_ct_str = { "r" } }; 1617 static const TCGTargetOpDef r_r 1618 = { .args_ct_str = { "r", "r" } }; 1619 static const TCGTargetOpDef rZ_r 1620 = { .args_ct_str = { "rZ", "r" } }; 1621 static const TCGTargetOpDef rZ_rZ 1622 = { .args_ct_str = { "rZ", "rZ" } }; 1623 static const TCGTargetOpDef rZ_rZ_rZ_rZ 1624 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; 1625 static const TCGTargetOpDef r_r_ri 1626 = { .args_ct_str = { "r", "r", "ri" } }; 1627 static const TCGTargetOpDef r_r_rI 1628 = { .args_ct_str = { "r", "r", "rI" } }; 1629 static const TCGTargetOpDef r_rZ_rN 1630 = { .args_ct_str = { "r", "rZ", "rN" } }; 1631 static const TCGTargetOpDef r_rZ_rZ 1632 = { .args_ct_str = { "r", "rZ", "rZ" } }; 1633 static const TCGTargetOpDef r_rZ_rZ_rZ_rZ 1634 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; 1635 static const TCGTargetOpDef r_L 1636 = { .args_ct_str = { "r", "L" } }; 1637 static const TCGTargetOpDef r_r_L 1638 = { .args_ct_str = { "r", "r", "L" } }; 1639 static const TCGTargetOpDef r_L_L 1640 = { .args_ct_str = { "r", "L", "L" } }; 1641 static const TCGTargetOpDef r_r_L_L 1642 = { .args_ct_str = { "r", "r", "L", "L" } }; 1643 static const TCGTargetOpDef LZ_L 1644 = { .args_ct_str = { "LZ", "L" } }; 1645 static const TCGTargetOpDef LZ_L_L 1646 = { .args_ct_str = { "LZ", "L", "L" } }; 1647 static const TCGTargetOpDef LZ_LZ_L 1648 = { .args_ct_str = { "LZ", "LZ", "L" } }; 1649 static const TCGTargetOpDef LZ_LZ_L_L 1650 = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; 1651 static const TCGTargetOpDef r_r_rZ_rZ_rM_rM 1652 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; 1653 1654 switch (op) { 1655 case INDEX_op_goto_ptr: 1656 return &r; 1657 1658 case INDEX_op_ld8u_i32: 1659 case INDEX_op_ld8s_i32: 1660 case INDEX_op_ld16u_i32: 1661 case INDEX_op_ld16s_i32: 1662 case INDEX_op_ld_i32: 1663 case INDEX_op_not_i32: 1664 case INDEX_op_neg_i32: 1665 case INDEX_op_ld8u_i64: 1666 case INDEX_op_ld8s_i64: 1667 case INDEX_op_ld16u_i64: 1668 case INDEX_op_ld16s_i64: 1669 case INDEX_op_ld32s_i64: 1670 case INDEX_op_ld32u_i64: 1671 case INDEX_op_ld_i64: 1672 case INDEX_op_not_i64: 1673 case INDEX_op_neg_i64: 1674 case INDEX_op_ext8u_i32: 1675 case INDEX_op_ext8u_i64: 1676 case INDEX_op_ext16u_i32: 1677 case INDEX_op_ext16u_i64: 1678 case INDEX_op_ext32u_i64: 1679 case INDEX_op_extu_i32_i64: 1680 case INDEX_op_ext8s_i32: 1681 case INDEX_op_ext8s_i64: 1682 case INDEX_op_ext16s_i32: 1683 case INDEX_op_ext16s_i64: 1684 case INDEX_op_ext32s_i64: 1685 case INDEX_op_extrl_i64_i32: 1686 case INDEX_op_extrh_i64_i32: 1687 case INDEX_op_ext_i32_i64: 1688 return &r_r; 1689 1690 case INDEX_op_st8_i32: 1691 case INDEX_op_st16_i32: 1692 case INDEX_op_st_i32: 1693 case INDEX_op_st8_i64: 1694 case INDEX_op_st16_i64: 1695 case INDEX_op_st32_i64: 1696 case INDEX_op_st_i64: 1697 return &rZ_r; 1698 1699 case INDEX_op_add_i32: 1700 case INDEX_op_and_i32: 1701 case INDEX_op_or_i32: 1702 case INDEX_op_xor_i32: 1703 case INDEX_op_add_i64: 1704 case INDEX_op_and_i64: 1705 case INDEX_op_or_i64: 1706 case INDEX_op_xor_i64: 1707 return &r_r_rI; 1708 1709 case INDEX_op_sub_i32: 1710 case INDEX_op_sub_i64: 1711 return &r_rZ_rN; 1712 1713 case INDEX_op_mul_i32: 1714 case INDEX_op_mulsh_i32: 1715 case INDEX_op_muluh_i32: 1716 case INDEX_op_div_i32: 1717 case INDEX_op_divu_i32: 1718 case INDEX_op_rem_i32: 1719 case INDEX_op_remu_i32: 1720 case INDEX_op_setcond_i32: 1721 case INDEX_op_mul_i64: 1722 case INDEX_op_mulsh_i64: 1723 case INDEX_op_muluh_i64: 1724 case INDEX_op_div_i64: 1725 case INDEX_op_divu_i64: 1726 case INDEX_op_rem_i64: 1727 case INDEX_op_remu_i64: 1728 case INDEX_op_setcond_i64: 1729 return &r_rZ_rZ; 1730 1731 case INDEX_op_shl_i32: 1732 case INDEX_op_shr_i32: 1733 case INDEX_op_sar_i32: 1734 case INDEX_op_shl_i64: 1735 case INDEX_op_shr_i64: 1736 case INDEX_op_sar_i64: 1737 return &r_r_ri; 1738 1739 case INDEX_op_brcond_i32: 1740 case INDEX_op_brcond_i64: 1741 return &rZ_rZ; 1742 1743 case INDEX_op_add2_i32: 1744 case INDEX_op_add2_i64: 1745 case INDEX_op_sub2_i32: 1746 case INDEX_op_sub2_i64: 1747 return &r_r_rZ_rZ_rM_rM; 1748 1749 case INDEX_op_brcond2_i32: 1750 return &rZ_rZ_rZ_rZ; 1751 1752 case INDEX_op_setcond2_i32: 1753 return &r_rZ_rZ_rZ_rZ; 1754 1755 case INDEX_op_qemu_ld_i32: 1756 return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; 1757 case INDEX_op_qemu_st_i32: 1758 return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; 1759 case INDEX_op_qemu_ld_i64: 1760 return TCG_TARGET_REG_BITS == 64 ? &r_L 1761 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L 1762 : &r_r_L_L; 1763 case INDEX_op_qemu_st_i64: 1764 return TCG_TARGET_REG_BITS == 64 ? &LZ_L 1765 : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L 1766 : &LZ_LZ_L_L; 1767 1768 default: 1769 return NULL; 1770 } 1771} 1772 1773static const int tcg_target_callee_save_regs[] = { 1774 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 1775 TCG_REG_S1, 1776 TCG_REG_S2, 1777 TCG_REG_S3, 1778 TCG_REG_S4, 1779 TCG_REG_S5, 1780 TCG_REG_S6, 1781 TCG_REG_S7, 1782 TCG_REG_S8, 1783 TCG_REG_S9, 1784 TCG_REG_S10, 1785 TCG_REG_S11, 1786 TCG_REG_RA, /* should be last for ABI compliance */ 1787}; 1788 1789/* Stack frame parameters. */ 1790#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 1791#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 1792#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 1793#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 1794 + TCG_TARGET_STACK_ALIGN - 1) \ 1795 & -TCG_TARGET_STACK_ALIGN) 1796#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 1797 1798/* We're expecting to be able to use an immediate for frame allocation. */ 1799QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 1800 1801/* Generate global QEMU prologue and epilogue code */ 1802static void tcg_target_qemu_prologue(TCGContext *s) 1803{ 1804 int i; 1805 1806 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 1807 1808 /* TB prologue */ 1809 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 1810 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 1811 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 1812 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 1813 } 1814 1815#if !defined(CONFIG_SOFTMMU) 1816 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 1817 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 1818#endif 1819 1820 /* Call generated code */ 1821 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 1822 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 1823 1824 /* Return path for goto_ptr. Set return value to 0 */ 1825 s->code_gen_epilogue = s->code_ptr; 1826 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 1827 1828 /* TB epilogue */ 1829 tb_ret_addr = s->code_ptr; 1830 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 1831 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 1832 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 1833 } 1834 1835 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 1836 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); 1837} 1838 1839static void tcg_target_init(TCGContext *s) 1840{ 1841 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 1842 if (TCG_TARGET_REG_BITS == 64) { 1843 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 1844 } 1845 1846 tcg_target_call_clobber_regs = -1u; 1847 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 1848 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 1849 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 1850 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 1851 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 1852 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 1853 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 1854 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 1855 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 1856 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 1857 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10); 1858 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11); 1859 1860 s->reserved_regs = 0; 1861 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 1862 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 1863 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 1864 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 1865 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 1866 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); 1867 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 1868} 1869 1870typedef struct { 1871 DebugFrameHeader h; 1872 uint8_t fde_def_cfa[4]; 1873 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 1874} DebugFrame; 1875 1876#define ELF_HOST_MACHINE EM_RISCV 1877 1878static const DebugFrame debug_frame = { 1879 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 1880 .h.cie.id = -1, 1881 .h.cie.version = 1, 1882 .h.cie.code_align = 1, 1883 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 1884 .h.cie.return_column = TCG_REG_RA, 1885 1886 /* Total FDE size does not include the "len" member. */ 1887 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 1888 1889 .fde_def_cfa = { 1890 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 1891 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 1892 (FRAME_SIZE >> 7) 1893 }, 1894 .fde_reg_ofs = { 1895 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ 1896 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ 1897 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ 1898 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ 1899 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ 1900 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ 1901 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ 1902 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ 1903 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ 1904 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ 1905 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ 1906 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 1907 } 1908}; 1909 1910void tcg_register_jit(void *buf, size_t buf_size) 1911{ 1912 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 1913} 1914