1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2018 SiFive, Inc 5 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 6 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 7 * Copyright (c) 2008 Fabrice Bellard 8 * 9 * Based on i386/tcg-target.c and mips/tcg-target.c 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a copy 12 * of this software and associated documentation files (the "Software"), to deal 13 * in the Software without restriction, including without limitation the rights 14 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 15 * copies of the Software, and to permit persons to whom the Software is 16 * furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice shall be included in 19 * all copies or substantial portions of the Software. 20 * 21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 26 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 27 * THE SOFTWARE. 28 */ 29 30#include "../tcg-ldst.c.inc" 31#include "../tcg-pool.c.inc" 32 33#ifdef CONFIG_DEBUG_TCG 34static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 35 "zero", 36 "ra", 37 "sp", 38 "gp", 39 "tp", 40 "t0", 41 "t1", 42 "t2", 43 "s0", 44 "s1", 45 "a0", 46 "a1", 47 "a2", 48 "a3", 49 "a4", 50 "a5", 51 "a6", 52 "a7", 53 "s2", 54 "s3", 55 "s4", 56 "s5", 57 "s6", 58 "s7", 59 "s8", 60 "s9", 61 "s10", 62 "s11", 63 "t3", 64 "t4", 65 "t5", 66 "t6" 67}; 68#endif 69 70static const int tcg_target_reg_alloc_order[] = { 71 /* Call saved registers */ 72 /* TCG_REG_S0 reserved for TCG_AREG0 */ 73 TCG_REG_S1, 74 TCG_REG_S2, 75 TCG_REG_S3, 76 TCG_REG_S4, 77 TCG_REG_S5, 78 TCG_REG_S6, 79 TCG_REG_S7, 80 TCG_REG_S8, 81 TCG_REG_S9, 82 TCG_REG_S10, 83 TCG_REG_S11, 84 85 /* Call clobbered registers */ 86 TCG_REG_T0, 87 TCG_REG_T1, 88 TCG_REG_T2, 89 TCG_REG_T3, 90 TCG_REG_T4, 91 TCG_REG_T5, 92 TCG_REG_T6, 93 94 /* Argument registers */ 95 TCG_REG_A0, 96 TCG_REG_A1, 97 TCG_REG_A2, 98 TCG_REG_A3, 99 TCG_REG_A4, 100 TCG_REG_A5, 101 TCG_REG_A6, 102 TCG_REG_A7, 103}; 104 105static const int tcg_target_call_iarg_regs[] = { 106 TCG_REG_A0, 107 TCG_REG_A1, 108 TCG_REG_A2, 109 TCG_REG_A3, 110 TCG_REG_A4, 111 TCG_REG_A5, 112 TCG_REG_A6, 113 TCG_REG_A7, 114}; 115 116#ifndef have_zbb 117bool have_zbb; 118#endif 119#if defined(__riscv_arch_test) && defined(__riscv_zba) 120# define have_zba true 121#else 122static bool have_zba; 123#endif 124#if defined(__riscv_arch_test) && defined(__riscv_zicond) 125# define have_zicond true 126#else 127static bool have_zicond; 128#endif 129 130static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 131{ 132 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 133 tcg_debug_assert(slot >= 0 && slot <= 1); 134 return TCG_REG_A0 + slot; 135} 136 137#define TCG_CT_CONST_ZERO 0x100 138#define TCG_CT_CONST_S12 0x200 139#define TCG_CT_CONST_N12 0x400 140#define TCG_CT_CONST_M12 0x800 141#define TCG_CT_CONST_J12 0x1000 142 143#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 144 145#define sextreg sextract64 146 147/* test if a constant matches the constraint */ 148static bool tcg_target_const_match(int64_t val, int ct, 149 TCGType type, TCGCond cond, int vece) 150{ 151 if (ct & TCG_CT_CONST) { 152 return 1; 153 } 154 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 155 return 1; 156 } 157 /* 158 * Sign extended from 12 bits: [-0x800, 0x7ff]. 159 * Used for most arithmetic, as this is the isa field. 160 */ 161 if ((ct & TCG_CT_CONST_S12) && val >= -0x800 && val <= 0x7ff) { 162 return 1; 163 } 164 /* 165 * Sign extended from 12 bits, negated: [-0x7ff, 0x800]. 166 * Used for subtraction, where a constant must be handled by ADDI. 167 */ 168 if ((ct & TCG_CT_CONST_N12) && val >= -0x7ff && val <= 0x800) { 169 return 1; 170 } 171 /* 172 * Sign extended from 12 bits, +/- matching: [-0x7ff, 0x7ff]. 173 * Used by addsub2 and movcond, which may need the negative value, 174 * and requires the modified constant to be representable. 175 */ 176 if ((ct & TCG_CT_CONST_M12) && val >= -0x7ff && val <= 0x7ff) { 177 return 1; 178 } 179 /* 180 * Inverse of sign extended from 12 bits: ~[-0x800, 0x7ff]. 181 * Used to map ANDN back to ANDI, etc. 182 */ 183 if ((ct & TCG_CT_CONST_J12) && ~val >= -0x800 && ~val <= 0x7ff) { 184 return 1; 185 } 186 return 0; 187} 188 189/* 190 * RISC-V Base ISA opcodes (IM) 191 */ 192 193typedef enum { 194 OPC_ADD = 0x33, 195 OPC_ADDI = 0x13, 196 OPC_AND = 0x7033, 197 OPC_ANDI = 0x7013, 198 OPC_AUIPC = 0x17, 199 OPC_BEQ = 0x63, 200 OPC_BGE = 0x5063, 201 OPC_BGEU = 0x7063, 202 OPC_BLT = 0x4063, 203 OPC_BLTU = 0x6063, 204 OPC_BNE = 0x1063, 205 OPC_DIV = 0x2004033, 206 OPC_DIVU = 0x2005033, 207 OPC_JAL = 0x6f, 208 OPC_JALR = 0x67, 209 OPC_LB = 0x3, 210 OPC_LBU = 0x4003, 211 OPC_LD = 0x3003, 212 OPC_LH = 0x1003, 213 OPC_LHU = 0x5003, 214 OPC_LUI = 0x37, 215 OPC_LW = 0x2003, 216 OPC_LWU = 0x6003, 217 OPC_MUL = 0x2000033, 218 OPC_MULH = 0x2001033, 219 OPC_MULHSU = 0x2002033, 220 OPC_MULHU = 0x2003033, 221 OPC_OR = 0x6033, 222 OPC_ORI = 0x6013, 223 OPC_REM = 0x2006033, 224 OPC_REMU = 0x2007033, 225 OPC_SB = 0x23, 226 OPC_SD = 0x3023, 227 OPC_SH = 0x1023, 228 OPC_SLL = 0x1033, 229 OPC_SLLI = 0x1013, 230 OPC_SLT = 0x2033, 231 OPC_SLTI = 0x2013, 232 OPC_SLTIU = 0x3013, 233 OPC_SLTU = 0x3033, 234 OPC_SRA = 0x40005033, 235 OPC_SRAI = 0x40005013, 236 OPC_SRL = 0x5033, 237 OPC_SRLI = 0x5013, 238 OPC_SUB = 0x40000033, 239 OPC_SW = 0x2023, 240 OPC_XOR = 0x4033, 241 OPC_XORI = 0x4013, 242 243 OPC_ADDIW = 0x1b, 244 OPC_ADDW = 0x3b, 245 OPC_DIVUW = 0x200503b, 246 OPC_DIVW = 0x200403b, 247 OPC_MULW = 0x200003b, 248 OPC_REMUW = 0x200703b, 249 OPC_REMW = 0x200603b, 250 OPC_SLLIW = 0x101b, 251 OPC_SLLW = 0x103b, 252 OPC_SRAIW = 0x4000501b, 253 OPC_SRAW = 0x4000503b, 254 OPC_SRLIW = 0x501b, 255 OPC_SRLW = 0x503b, 256 OPC_SUBW = 0x4000003b, 257 258 OPC_FENCE = 0x0000000f, 259 OPC_NOP = OPC_ADDI, /* nop = addi r0,r0,0 */ 260 261 /* Zba: Bit manipulation extension, address generation */ 262 OPC_ADD_UW = 0x0800003b, 263 264 /* Zbb: Bit manipulation extension, basic bit manipulation */ 265 OPC_ANDN = 0x40007033, 266 OPC_CLZ = 0x60001013, 267 OPC_CLZW = 0x6000101b, 268 OPC_CPOP = 0x60201013, 269 OPC_CPOPW = 0x6020101b, 270 OPC_CTZ = 0x60101013, 271 OPC_CTZW = 0x6010101b, 272 OPC_ORN = 0x40006033, 273 OPC_REV8 = 0x6b805013, 274 OPC_ROL = 0x60001033, 275 OPC_ROLW = 0x6000103b, 276 OPC_ROR = 0x60005033, 277 OPC_RORW = 0x6000503b, 278 OPC_RORI = 0x60005013, 279 OPC_RORIW = 0x6000501b, 280 OPC_SEXT_B = 0x60401013, 281 OPC_SEXT_H = 0x60501013, 282 OPC_XNOR = 0x40004033, 283 OPC_ZEXT_H = 0x0800403b, 284 285 /* Zicond: integer conditional operations */ 286 OPC_CZERO_EQZ = 0x0e005033, 287 OPC_CZERO_NEZ = 0x0e007033, 288} RISCVInsn; 289 290/* 291 * RISC-V immediate and instruction encoders (excludes 16-bit RVC) 292 */ 293 294/* Type-R */ 295 296static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) 297{ 298 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; 299} 300 301/* Type-I */ 302 303static int32_t encode_imm12(uint32_t imm) 304{ 305 return (imm & 0xfff) << 20; 306} 307 308static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) 309{ 310 return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); 311} 312 313/* Type-S */ 314 315static int32_t encode_simm12(uint32_t imm) 316{ 317 int32_t ret = 0; 318 319 ret |= (imm & 0xFE0) << 20; 320 ret |= (imm & 0x1F) << 7; 321 322 return ret; 323} 324 325static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 326{ 327 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); 328} 329 330/* Type-SB */ 331 332static int32_t encode_sbimm12(uint32_t imm) 333{ 334 int32_t ret = 0; 335 336 ret |= (imm & 0x1000) << 19; 337 ret |= (imm & 0x7e0) << 20; 338 ret |= (imm & 0x1e) << 7; 339 ret |= (imm & 0x800) >> 4; 340 341 return ret; 342} 343 344static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) 345{ 346 return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); 347} 348 349/* Type-U */ 350 351static int32_t encode_uimm20(uint32_t imm) 352{ 353 return imm & 0xfffff000; 354} 355 356static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) 357{ 358 return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); 359} 360 361/* Type-UJ */ 362 363static int32_t encode_ujimm20(uint32_t imm) 364{ 365 int32_t ret = 0; 366 367 ret |= (imm & 0x0007fe) << (21 - 1); 368 ret |= (imm & 0x000800) << (20 - 11); 369 ret |= (imm & 0x0ff000) << (12 - 12); 370 ret |= (imm & 0x100000) << (31 - 20); 371 372 return ret; 373} 374 375static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) 376{ 377 return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); 378} 379 380/* 381 * RISC-V instruction emitters 382 */ 383 384static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc, 385 TCGReg rd, TCGReg rs1, TCGReg rs2) 386{ 387 tcg_out32(s, encode_r(opc, rd, rs1, rs2)); 388} 389 390static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc, 391 TCGReg rd, TCGReg rs1, TCGArg imm) 392{ 393 tcg_out32(s, encode_i(opc, rd, rs1, imm)); 394} 395 396static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc, 397 TCGReg rs1, TCGReg rs2, uint32_t imm) 398{ 399 tcg_out32(s, encode_s(opc, rs1, rs2, imm)); 400} 401 402static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc, 403 TCGReg rs1, TCGReg rs2, uint32_t imm) 404{ 405 tcg_out32(s, encode_sb(opc, rs1, rs2, imm)); 406} 407 408static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc, 409 TCGReg rd, uint32_t imm) 410{ 411 tcg_out32(s, encode_u(opc, rd, imm)); 412} 413 414static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, 415 TCGReg rd, uint32_t imm) 416{ 417 tcg_out32(s, encode_uj(opc, rd, imm)); 418} 419 420static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 421{ 422 int i; 423 for (i = 0; i < count; ++i) { 424 p[i] = OPC_NOP; 425 } 426} 427 428/* 429 * Relocations 430 */ 431 432static bool reloc_sbimm12(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 433{ 434 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 435 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 436 437 tcg_debug_assert((offset & 1) == 0); 438 if (offset == sextreg(offset, 0, 12)) { 439 *src_rw |= encode_sbimm12(offset); 440 return true; 441 } 442 443 return false; 444} 445 446static bool reloc_jimm20(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 447{ 448 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 449 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 450 451 tcg_debug_assert((offset & 1) == 0); 452 if (offset == sextreg(offset, 0, 20)) { 453 *src_rw |= encode_ujimm20(offset); 454 return true; 455 } 456 457 return false; 458} 459 460static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 461{ 462 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 463 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 464 int32_t lo = sextreg(offset, 0, 12); 465 int32_t hi = offset - lo; 466 467 if (offset == hi + lo) { 468 src_rw[0] |= encode_uimm20(hi); 469 src_rw[1] |= encode_imm12(lo); 470 return true; 471 } 472 473 return false; 474} 475 476static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 477 intptr_t value, intptr_t addend) 478{ 479 tcg_debug_assert(addend == 0); 480 switch (type) { 481 case R_RISCV_BRANCH: 482 return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); 483 case R_RISCV_JAL: 484 return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); 485 case R_RISCV_CALL: 486 return reloc_call(code_ptr, (tcg_insn_unit *)value); 487 default: 488 g_assert_not_reached(); 489 } 490} 491 492/* 493 * TCG intrinsics 494 */ 495 496static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 497{ 498 if (ret == arg) { 499 return true; 500 } 501 switch (type) { 502 case TCG_TYPE_I32: 503 case TCG_TYPE_I64: 504 tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); 505 break; 506 default: 507 g_assert_not_reached(); 508 } 509 return true; 510} 511 512static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 513 tcg_target_long val) 514{ 515 tcg_target_long lo, hi, tmp; 516 int shift, ret; 517 518 if (type == TCG_TYPE_I32) { 519 val = (int32_t)val; 520 } 521 522 lo = sextreg(val, 0, 12); 523 if (val == lo) { 524 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo); 525 return; 526 } 527 528 hi = val - lo; 529 if (val == (int32_t)val) { 530 tcg_out_opc_upper(s, OPC_LUI, rd, hi); 531 if (lo != 0) { 532 tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); 533 } 534 return; 535 } 536 537 tmp = tcg_pcrel_diff(s, (void *)val); 538 if (tmp == (int32_t)tmp) { 539 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 540 tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); 541 ret = reloc_call(s->code_ptr - 2, (const tcg_insn_unit *)val); 542 tcg_debug_assert(ret == true); 543 return; 544 } 545 546 /* Look for a single 20-bit section. */ 547 shift = ctz64(val); 548 tmp = val >> shift; 549 if (tmp == sextreg(tmp, 0, 20)) { 550 tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12); 551 if (shift > 12) { 552 tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12); 553 } else { 554 tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift); 555 } 556 return; 557 } 558 559 /* Look for a few high zero bits, with lots of bits set in the middle. */ 560 shift = clz64(val); 561 tmp = val << shift; 562 if (tmp == sextreg(tmp, 12, 20) << 12) { 563 tcg_out_opc_upper(s, OPC_LUI, rd, tmp); 564 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 565 return; 566 } else if (tmp == sextreg(tmp, 0, 12)) { 567 tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp); 568 tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); 569 return; 570 } 571 572 /* Drop into the constant pool. */ 573 new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0); 574 tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); 575 tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); 576} 577 578static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 579{ 580 return false; 581} 582 583static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 584 tcg_target_long imm) 585{ 586 /* This function is only used for passing structs by reference. */ 587 g_assert_not_reached(); 588} 589 590static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 591{ 592 tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); 593} 594 595static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 596{ 597 if (have_zbb) { 598 tcg_out_opc_reg(s, OPC_ZEXT_H, ret, arg, TCG_REG_ZERO); 599 } else { 600 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 601 tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16); 602 } 603} 604 605static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 606{ 607 if (have_zba) { 608 tcg_out_opc_reg(s, OPC_ADD_UW, ret, arg, TCG_REG_ZERO); 609 } else { 610 tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); 611 tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); 612 } 613} 614 615static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 616{ 617 if (have_zbb) { 618 tcg_out_opc_imm(s, OPC_SEXT_B, ret, arg, 0); 619 } else { 620 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); 621 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); 622 } 623} 624 625static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 626{ 627 if (have_zbb) { 628 tcg_out_opc_imm(s, OPC_SEXT_H, ret, arg, 0); 629 } else { 630 tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); 631 tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); 632 } 633} 634 635static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 636{ 637 tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); 638} 639 640static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 641{ 642 if (ret != arg) { 643 tcg_out_ext32s(s, ret, arg); 644 } 645} 646 647static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 648{ 649 tcg_out_ext32u(s, ret, arg); 650} 651 652static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 653{ 654 tcg_out_ext32s(s, ret, arg); 655} 656 657static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, 658 TCGReg addr, intptr_t offset) 659{ 660 intptr_t imm12 = sextreg(offset, 0, 12); 661 662 if (offset != imm12) { 663 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 664 665 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 666 imm12 = sextreg(diff, 0, 12); 667 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12); 668 } else { 669 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 670 if (addr != TCG_REG_ZERO) { 671 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr); 672 } 673 } 674 addr = TCG_REG_TMP2; 675 } 676 677 switch (opc) { 678 case OPC_SB: 679 case OPC_SH: 680 case OPC_SW: 681 case OPC_SD: 682 tcg_out_opc_store(s, opc, addr, data, imm12); 683 break; 684 case OPC_LB: 685 case OPC_LBU: 686 case OPC_LH: 687 case OPC_LHU: 688 case OPC_LW: 689 case OPC_LWU: 690 case OPC_LD: 691 tcg_out_opc_imm(s, opc, data, addr, imm12); 692 break; 693 default: 694 g_assert_not_reached(); 695 } 696} 697 698static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 699 TCGReg arg1, intptr_t arg2) 700{ 701 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_LW : OPC_LD; 702 tcg_out_ldst(s, insn, arg, arg1, arg2); 703} 704 705static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 706 TCGReg arg1, intptr_t arg2) 707{ 708 RISCVInsn insn = type == TCG_TYPE_I32 ? OPC_SW : OPC_SD; 709 tcg_out_ldst(s, insn, arg, arg1, arg2); 710} 711 712static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 713 TCGReg base, intptr_t ofs) 714{ 715 if (val == 0) { 716 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 717 return true; 718 } 719 return false; 720} 721 722static void tcg_out_addsub2(TCGContext *s, 723 TCGReg rl, TCGReg rh, 724 TCGReg al, TCGReg ah, 725 TCGArg bl, TCGArg bh, 726 bool cbl, bool cbh, bool is_sub, bool is32bit) 727{ 728 const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD; 729 const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI; 730 const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB; 731 TCGReg th = TCG_REG_TMP1; 732 733 /* If we have a negative constant such that negating it would 734 make the high part zero, we can (usually) eliminate one insn. */ 735 if (cbl && cbh && bh == -1 && bl != 0) { 736 bl = -bl; 737 bh = 0; 738 is_sub = !is_sub; 739 } 740 741 /* By operating on the high part first, we get to use the final 742 carry operation to move back from the temporary. */ 743 if (!cbh) { 744 tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh); 745 } else if (bh != 0 || ah == rl) { 746 tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh)); 747 } else { 748 th = ah; 749 } 750 751 /* Note that tcg optimization should eliminate the bl == 0 case. */ 752 if (is_sub) { 753 if (cbl) { 754 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl); 755 tcg_out_opc_imm(s, opc_addi, rl, al, -bl); 756 } else { 757 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl); 758 tcg_out_opc_reg(s, opc_sub, rl, al, bl); 759 } 760 tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0); 761 } else { 762 if (cbl) { 763 tcg_out_opc_imm(s, opc_addi, rl, al, bl); 764 tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); 765 } else if (al == bl) { 766 /* 767 * If the input regs overlap, this is a simple doubling 768 * and carry-out is the input msb. This special case is 769 * required when the output reg overlaps the input, 770 * but we might as well use it always. 771 */ 772 tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); 773 tcg_out_opc_reg(s, opc_add, rl, al, al); 774 } else { 775 tcg_out_opc_reg(s, opc_add, rl, al, bl); 776 tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, 777 rl, (rl == bl ? al : bl)); 778 } 779 tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0); 780 } 781} 782 783static const struct { 784 RISCVInsn op; 785 bool swap; 786} tcg_brcond_to_riscv[] = { 787 [TCG_COND_EQ] = { OPC_BEQ, false }, 788 [TCG_COND_NE] = { OPC_BNE, false }, 789 [TCG_COND_LT] = { OPC_BLT, false }, 790 [TCG_COND_GE] = { OPC_BGE, false }, 791 [TCG_COND_LE] = { OPC_BGE, true }, 792 [TCG_COND_GT] = { OPC_BLT, true }, 793 [TCG_COND_LTU] = { OPC_BLTU, false }, 794 [TCG_COND_GEU] = { OPC_BGEU, false }, 795 [TCG_COND_LEU] = { OPC_BGEU, true }, 796 [TCG_COND_GTU] = { OPC_BLTU, true } 797}; 798 799static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 800 TCGReg arg2, TCGLabel *l) 801{ 802 RISCVInsn op = tcg_brcond_to_riscv[cond].op; 803 804 tcg_debug_assert(op != 0); 805 806 if (tcg_brcond_to_riscv[cond].swap) { 807 TCGReg t = arg1; 808 arg1 = arg2; 809 arg2 = t; 810 } 811 812 tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); 813 tcg_out_opc_branch(s, op, arg1, arg2, 0); 814} 815 816#define SETCOND_INV TCG_TARGET_NB_REGS 817#define SETCOND_NEZ (SETCOND_INV << 1) 818#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 819 820static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 821 TCGReg arg1, tcg_target_long arg2, bool c2) 822{ 823 int flags = 0; 824 825 switch (cond) { 826 case TCG_COND_EQ: /* -> NE */ 827 case TCG_COND_GE: /* -> LT */ 828 case TCG_COND_GEU: /* -> LTU */ 829 case TCG_COND_GT: /* -> LE */ 830 case TCG_COND_GTU: /* -> LEU */ 831 cond = tcg_invert_cond(cond); 832 flags ^= SETCOND_INV; 833 break; 834 default: 835 break; 836 } 837 838 switch (cond) { 839 case TCG_COND_LE: 840 case TCG_COND_LEU: 841 /* 842 * If we have a constant input, the most efficient way to implement 843 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 844 * We don't need to care for this for LE because the constant input 845 * is constrained to signed 12-bit, and 0x800 is representable in the 846 * temporary register. 847 */ 848 if (c2) { 849 if (cond == TCG_COND_LEU) { 850 /* unsigned <= -1 is true */ 851 if (arg2 == -1) { 852 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 853 return ret; 854 } 855 cond = TCG_COND_LTU; 856 } else { 857 cond = TCG_COND_LT; 858 } 859 tcg_debug_assert(arg2 <= 0x7ff); 860 if (++arg2 == 0x800) { 861 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 862 arg2 = TCG_REG_TMP0; 863 c2 = false; 864 } 865 } else { 866 TCGReg tmp = arg2; 867 arg2 = arg1; 868 arg1 = tmp; 869 cond = tcg_swap_cond(cond); /* LE -> GE */ 870 cond = tcg_invert_cond(cond); /* GE -> LT */ 871 flags ^= SETCOND_INV; 872 } 873 break; 874 default: 875 break; 876 } 877 878 switch (cond) { 879 case TCG_COND_NE: 880 flags |= SETCOND_NEZ; 881 if (!c2) { 882 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 883 } else if (arg2 == 0) { 884 ret = arg1; 885 } else { 886 tcg_out_opc_imm(s, OPC_XORI, ret, arg1, arg2); 887 } 888 break; 889 890 case TCG_COND_LT: 891 if (c2) { 892 tcg_out_opc_imm(s, OPC_SLTI, ret, arg1, arg2); 893 } else { 894 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 895 } 896 break; 897 898 case TCG_COND_LTU: 899 if (c2) { 900 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, arg2); 901 } else { 902 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 903 } 904 break; 905 906 default: 907 g_assert_not_reached(); 908 } 909 910 return ret | flags; 911} 912 913static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 914 TCGReg arg1, tcg_target_long arg2, bool c2) 915{ 916 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 917 918 if (tmpflags != ret) { 919 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 920 921 switch (tmpflags & SETCOND_FLAGS) { 922 case SETCOND_INV: 923 /* Intermediate result is boolean: simply invert. */ 924 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 925 break; 926 case SETCOND_NEZ: 927 /* Intermediate result is zero/non-zero: test != 0. */ 928 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 929 break; 930 case SETCOND_NEZ | SETCOND_INV: 931 /* Intermediate result is zero/non-zero: test == 0. */ 932 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 933 break; 934 default: 935 g_assert_not_reached(); 936 } 937 } 938} 939 940static void tcg_out_negsetcond(TCGContext *s, TCGCond cond, TCGReg ret, 941 TCGReg arg1, tcg_target_long arg2, bool c2) 942{ 943 int tmpflags; 944 TCGReg tmp; 945 946 /* For LT/GE comparison against 0, replicate the sign bit. */ 947 if (c2 && arg2 == 0) { 948 switch (cond) { 949 case TCG_COND_GE: 950 tcg_out_opc_imm(s, OPC_XORI, ret, arg1, -1); 951 arg1 = ret; 952 /* fall through */ 953 case TCG_COND_LT: 954 tcg_out_opc_imm(s, OPC_SRAI, ret, arg1, TCG_TARGET_REG_BITS - 1); 955 return; 956 default: 957 break; 958 } 959 } 960 961 tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 962 tmp = tmpflags & ~SETCOND_FLAGS; 963 964 /* If intermediate result is zero/non-zero: test != 0. */ 965 if (tmpflags & SETCOND_NEZ) { 966 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 967 tmp = ret; 968 } 969 970 /* Produce the 0/-1 result. */ 971 if (tmpflags & SETCOND_INV) { 972 tcg_out_opc_imm(s, OPC_ADDI, ret, tmp, -1); 973 } else { 974 tcg_out_opc_reg(s, OPC_SUB, ret, TCG_REG_ZERO, tmp); 975 } 976} 977 978static void tcg_out_movcond_zicond(TCGContext *s, TCGReg ret, TCGReg test_ne, 979 int val1, bool c_val1, 980 int val2, bool c_val2) 981{ 982 if (val1 == 0) { 983 if (c_val2) { 984 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val2); 985 val2 = TCG_REG_TMP1; 986 } 987 tcg_out_opc_reg(s, OPC_CZERO_NEZ, ret, val2, test_ne); 988 return; 989 } 990 991 if (val2 == 0) { 992 if (c_val1) { 993 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1); 994 val1 = TCG_REG_TMP1; 995 } 996 tcg_out_opc_reg(s, OPC_CZERO_EQZ, ret, val1, test_ne); 997 return; 998 } 999 1000 if (c_val2) { 1001 if (c_val1) { 1002 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, val1 - val2); 1003 } else { 1004 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val1, -val2); 1005 } 1006 tcg_out_opc_reg(s, OPC_CZERO_EQZ, ret, TCG_REG_TMP1, test_ne); 1007 tcg_out_opc_imm(s, OPC_ADDI, ret, ret, val2); 1008 return; 1009 } 1010 1011 if (c_val1) { 1012 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_TMP1, val2, -val1); 1013 tcg_out_opc_reg(s, OPC_CZERO_NEZ, ret, TCG_REG_TMP1, test_ne); 1014 tcg_out_opc_imm(s, OPC_ADDI, ret, ret, val1); 1015 return; 1016 } 1017 1018 tcg_out_opc_reg(s, OPC_CZERO_NEZ, TCG_REG_TMP1, val2, test_ne); 1019 tcg_out_opc_reg(s, OPC_CZERO_EQZ, TCG_REG_TMP0, val1, test_ne); 1020 tcg_out_opc_reg(s, OPC_OR, ret, TCG_REG_TMP0, TCG_REG_TMP1); 1021} 1022 1023static void tcg_out_movcond_br1(TCGContext *s, TCGCond cond, TCGReg ret, 1024 TCGReg cmp1, TCGReg cmp2, 1025 int val, bool c_val) 1026{ 1027 RISCVInsn op; 1028 int disp = 8; 1029 1030 tcg_debug_assert((unsigned)cond < ARRAY_SIZE(tcg_brcond_to_riscv)); 1031 op = tcg_brcond_to_riscv[cond].op; 1032 tcg_debug_assert(op != 0); 1033 1034 if (tcg_brcond_to_riscv[cond].swap) { 1035 tcg_out_opc_branch(s, op, cmp2, cmp1, disp); 1036 } else { 1037 tcg_out_opc_branch(s, op, cmp1, cmp2, disp); 1038 } 1039 if (c_val) { 1040 tcg_out_opc_imm(s, OPC_ADDI, ret, TCG_REG_ZERO, val); 1041 } else { 1042 tcg_out_opc_imm(s, OPC_ADDI, ret, val, 0); 1043 } 1044} 1045 1046static void tcg_out_movcond_br2(TCGContext *s, TCGCond cond, TCGReg ret, 1047 TCGReg cmp1, TCGReg cmp2, 1048 int val1, bool c_val1, 1049 int val2, bool c_val2) 1050{ 1051 TCGReg tmp; 1052 1053 /* TCG optimizer reorders to prefer ret matching val2. */ 1054 if (!c_val2 && ret == val2) { 1055 cond = tcg_invert_cond(cond); 1056 tcg_out_movcond_br1(s, cond, ret, cmp1, cmp2, val1, c_val1); 1057 return; 1058 } 1059 1060 if (!c_val1 && ret == val1) { 1061 tcg_out_movcond_br1(s, cond, ret, cmp1, cmp2, val2, c_val2); 1062 return; 1063 } 1064 1065 tmp = (ret == cmp1 || ret == cmp2 ? TCG_REG_TMP1 : ret); 1066 if (c_val1) { 1067 tcg_out_movi(s, TCG_TYPE_REG, tmp, val1); 1068 } else { 1069 tcg_out_mov(s, TCG_TYPE_REG, tmp, val1); 1070 } 1071 tcg_out_movcond_br1(s, cond, tmp, cmp1, cmp2, val2, c_val2); 1072 tcg_out_mov(s, TCG_TYPE_REG, ret, tmp); 1073} 1074 1075static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1076 TCGReg cmp1, int cmp2, bool c_cmp2, 1077 TCGReg val1, bool c_val1, 1078 TCGReg val2, bool c_val2) 1079{ 1080 int tmpflags; 1081 TCGReg t; 1082 1083 if (!have_zicond && (!c_cmp2 || cmp2 == 0)) { 1084 tcg_out_movcond_br2(s, cond, ret, cmp1, cmp2, 1085 val1, c_val1, val2, c_val2); 1086 return; 1087 } 1088 1089 tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, cmp1, cmp2, c_cmp2); 1090 t = tmpflags & ~SETCOND_FLAGS; 1091 1092 if (have_zicond) { 1093 if (tmpflags & SETCOND_INV) { 1094 tcg_out_movcond_zicond(s, ret, t, val2, c_val2, val1, c_val1); 1095 } else { 1096 tcg_out_movcond_zicond(s, ret, t, val1, c_val1, val2, c_val2); 1097 } 1098 } else { 1099 cond = tmpflags & SETCOND_INV ? TCG_COND_EQ : TCG_COND_NE; 1100 tcg_out_movcond_br2(s, cond, ret, t, TCG_REG_ZERO, 1101 val1, c_val1, val2, c_val2); 1102 } 1103} 1104 1105static void tcg_out_cltz(TCGContext *s, TCGType type, RISCVInsn insn, 1106 TCGReg ret, TCGReg src1, int src2, bool c_src2) 1107{ 1108 tcg_out_opc_imm(s, insn, ret, src1, 0); 1109 1110 if (!c_src2 || src2 != (type == TCG_TYPE_I32 ? 32 : 64)) { 1111 /* 1112 * The requested zero result does not match the insn, so adjust. 1113 * Note that constraints put 'ret' in a new register, so the 1114 * computation above did not clobber either 'src1' or 'src2'. 1115 */ 1116 tcg_out_movcond(s, TCG_COND_EQ, ret, src1, 0, true, 1117 src2, c_src2, ret, false); 1118 } 1119} 1120 1121static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1122{ 1123 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 1124 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 1125 int ret; 1126 1127 tcg_debug_assert((offset & 1) == 0); 1128 if (offset == sextreg(offset, 0, 20)) { 1129 /* short jump: -2097150 to 2097152 */ 1130 tcg_out_opc_jump(s, OPC_JAL, link, offset); 1131 } else if (offset == (int32_t)offset) { 1132 /* long jump: -2147483646 to 2147483648 */ 1133 tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); 1134 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); 1135 ret = reloc_call(s->code_ptr - 2, arg); 1136 tcg_debug_assert(ret == true); 1137 } else { 1138 /* far jump: 64-bit */ 1139 tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); 1140 tcg_target_long base = (tcg_target_long)arg - imm; 1141 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); 1142 tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); 1143 } 1144} 1145 1146static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1147 const TCGHelperInfo *info) 1148{ 1149 tcg_out_call_int(s, arg, false); 1150} 1151 1152static void tcg_out_mb(TCGContext *s, TCGArg a0) 1153{ 1154 tcg_insn_unit insn = OPC_FENCE; 1155 1156 if (a0 & TCG_MO_LD_LD) { 1157 insn |= 0x02200000; 1158 } 1159 if (a0 & TCG_MO_ST_LD) { 1160 insn |= 0x01200000; 1161 } 1162 if (a0 & TCG_MO_LD_ST) { 1163 insn |= 0x02100000; 1164 } 1165 if (a0 & TCG_MO_ST_ST) { 1166 insn |= 0x02200000; 1167 } 1168 tcg_out32(s, insn); 1169} 1170 1171/* 1172 * Load/store and TLB 1173 */ 1174 1175static void tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 1176{ 1177 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 1178 bool ok = reloc_jimm20(s->code_ptr - 1, target); 1179 tcg_debug_assert(ok); 1180} 1181 1182bool tcg_target_has_memory_bswap(MemOp memop) 1183{ 1184 return false; 1185} 1186 1187/* We have three temps, we might as well expose them. */ 1188static const TCGLdstHelperParam ldst_helper_param = { 1189 .ntmp = 3, .tmp = { TCG_REG_TMP0, TCG_REG_TMP1, TCG_REG_TMP2 } 1190}; 1191 1192static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1193{ 1194 MemOp opc = get_memop(l->oi); 1195 1196 /* resolve label address */ 1197 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1198 return false; 1199 } 1200 1201 /* call load helper */ 1202 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1203 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1204 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1205 1206 tcg_out_goto(s, l->raddr); 1207 return true; 1208} 1209 1210static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1211{ 1212 MemOp opc = get_memop(l->oi); 1213 1214 /* resolve label address */ 1215 if (!reloc_sbimm12(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1216 return false; 1217 } 1218 1219 /* call store helper */ 1220 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1221 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1222 1223 tcg_out_goto(s, l->raddr); 1224 return true; 1225} 1226 1227/* We expect to use a 12-bit negative offset from ENV. */ 1228#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 1229 1230/* 1231 * For system-mode, perform the TLB load and compare. 1232 * For user-mode, perform any required alignment tests. 1233 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1234 * is required and fill in @h with the host address for the fast path. 1235 */ 1236static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, 1237 TCGReg addr_reg, MemOpIdx oi, 1238 bool is_ld) 1239{ 1240 TCGType addr_type = s->addr_type; 1241 TCGLabelQemuLdst *ldst = NULL; 1242 MemOp opc = get_memop(oi); 1243 TCGAtomAlign aa; 1244 unsigned a_mask; 1245 1246 aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1247 a_mask = (1u << aa.align) - 1; 1248 1249 if (tcg_use_softmmu) { 1250 unsigned s_bits = opc & MO_SIZE; 1251 unsigned s_mask = (1u << s_bits) - 1; 1252 int mem_index = get_mmuidx(oi); 1253 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 1254 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 1255 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 1256 int compare_mask; 1257 TCGReg addr_adj; 1258 1259 ldst = new_ldst_label(s); 1260 ldst->is_ld = is_ld; 1261 ldst->oi = oi; 1262 ldst->addrlo_reg = addr_reg; 1263 1264 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 1265 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 1266 1267 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg, 1268 s->page_bits - CPU_TLB_ENTRY_BITS); 1269 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 1270 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 1271 1272 /* 1273 * For aligned accesses, we check the first byte and include the 1274 * alignment bits within the address. For unaligned access, we 1275 * check that we don't cross pages using the address of the last 1276 * byte of the access. 1277 */ 1278 addr_adj = addr_reg; 1279 if (a_mask < s_mask) { 1280 addr_adj = TCG_REG_TMP0; 1281 tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI, 1282 addr_adj, addr_reg, s_mask - a_mask); 1283 } 1284 compare_mask = s->page_mask | a_mask; 1285 if (compare_mask == sextreg(compare_mask, 0, 12)) { 1286 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask); 1287 } else { 1288 tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask); 1289 tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj); 1290 } 1291 1292 /* Load the tlb comparator and the addend. */ 1293 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 1294 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 1295 is_ld ? offsetof(CPUTLBEntry, addr_read) 1296 : offsetof(CPUTLBEntry, addr_write)); 1297 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 1298 offsetof(CPUTLBEntry, addend)); 1299 1300 /* Compare masked address with the TLB entry. */ 1301 ldst->label_ptr[0] = s->code_ptr; 1302 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1303 1304 /* TLB Hit - translate address using addend. */ 1305 if (addr_type != TCG_TYPE_I32) { 1306 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); 1307 } else if (have_zba) { 1308 tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, 1309 addr_reg, TCG_REG_TMP2); 1310 } else { 1311 tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg); 1312 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, 1313 TCG_REG_TMP0, TCG_REG_TMP2); 1314 } 1315 *pbase = TCG_REG_TMP0; 1316 } else { 1317 TCGReg base; 1318 1319 if (a_mask) { 1320 ldst = new_ldst_label(s); 1321 ldst->is_ld = is_ld; 1322 ldst->oi = oi; 1323 ldst->addrlo_reg = addr_reg; 1324 1325 /* We are expecting alignment max 7, so we can always use andi. */ 1326 tcg_debug_assert(a_mask == sextreg(a_mask, 0, 12)); 1327 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask); 1328 1329 ldst->label_ptr[0] = s->code_ptr; 1330 tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1331 } 1332 1333 if (guest_base != 0) { 1334 base = TCG_REG_TMP0; 1335 if (addr_type != TCG_TYPE_I32) { 1336 tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, 1337 TCG_GUEST_BASE_REG); 1338 } else if (have_zba) { 1339 tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, 1340 TCG_GUEST_BASE_REG); 1341 } else { 1342 tcg_out_ext32u(s, base, addr_reg); 1343 tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG); 1344 } 1345 } else if (addr_type != TCG_TYPE_I32) { 1346 base = addr_reg; 1347 } else { 1348 base = TCG_REG_TMP0; 1349 tcg_out_ext32u(s, base, addr_reg); 1350 } 1351 *pbase = base; 1352 } 1353 1354 return ldst; 1355} 1356 1357static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg val, 1358 TCGReg base, MemOp opc, TCGType type) 1359{ 1360 /* Byte swapping is left to middle-end expansion. */ 1361 tcg_debug_assert((opc & MO_BSWAP) == 0); 1362 1363 switch (opc & (MO_SSIZE)) { 1364 case MO_UB: 1365 tcg_out_opc_imm(s, OPC_LBU, val, base, 0); 1366 break; 1367 case MO_SB: 1368 tcg_out_opc_imm(s, OPC_LB, val, base, 0); 1369 break; 1370 case MO_UW: 1371 tcg_out_opc_imm(s, OPC_LHU, val, base, 0); 1372 break; 1373 case MO_SW: 1374 tcg_out_opc_imm(s, OPC_LH, val, base, 0); 1375 break; 1376 case MO_UL: 1377 if (type == TCG_TYPE_I64) { 1378 tcg_out_opc_imm(s, OPC_LWU, val, base, 0); 1379 break; 1380 } 1381 /* FALLTHRU */ 1382 case MO_SL: 1383 tcg_out_opc_imm(s, OPC_LW, val, base, 0); 1384 break; 1385 case MO_UQ: 1386 tcg_out_opc_imm(s, OPC_LD, val, base, 0); 1387 break; 1388 default: 1389 g_assert_not_reached(); 1390 } 1391} 1392 1393static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1394 MemOpIdx oi, TCGType data_type) 1395{ 1396 TCGLabelQemuLdst *ldst; 1397 TCGReg base; 1398 1399 ldst = prepare_host_addr(s, &base, addr_reg, oi, true); 1400 tcg_out_qemu_ld_direct(s, data_reg, base, get_memop(oi), data_type); 1401 1402 if (ldst) { 1403 ldst->type = data_type; 1404 ldst->datalo_reg = data_reg; 1405 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1406 } 1407} 1408 1409static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg val, 1410 TCGReg base, MemOp opc) 1411{ 1412 /* Byte swapping is left to middle-end expansion. */ 1413 tcg_debug_assert((opc & MO_BSWAP) == 0); 1414 1415 switch (opc & (MO_SSIZE)) { 1416 case MO_8: 1417 tcg_out_opc_store(s, OPC_SB, base, val, 0); 1418 break; 1419 case MO_16: 1420 tcg_out_opc_store(s, OPC_SH, base, val, 0); 1421 break; 1422 case MO_32: 1423 tcg_out_opc_store(s, OPC_SW, base, val, 0); 1424 break; 1425 case MO_64: 1426 tcg_out_opc_store(s, OPC_SD, base, val, 0); 1427 break; 1428 default: 1429 g_assert_not_reached(); 1430 } 1431} 1432 1433static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1434 MemOpIdx oi, TCGType data_type) 1435{ 1436 TCGLabelQemuLdst *ldst; 1437 TCGReg base; 1438 1439 ldst = prepare_host_addr(s, &base, addr_reg, oi, false); 1440 tcg_out_qemu_st_direct(s, data_reg, base, get_memop(oi)); 1441 1442 if (ldst) { 1443 ldst->type = data_type; 1444 ldst->datalo_reg = data_reg; 1445 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1446 } 1447} 1448 1449static const tcg_insn_unit *tb_ret_addr; 1450 1451static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1452{ 1453 /* Reuse the zeroing that exists for goto_ptr. */ 1454 if (a0 == 0) { 1455 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1456 } else { 1457 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1458 tcg_out_call_int(s, tb_ret_addr, true); 1459 } 1460} 1461 1462static void tcg_out_goto_tb(TCGContext *s, int which) 1463{ 1464 /* Direct branch will be patched by tb_target_set_jmp_target. */ 1465 set_jmp_insn_offset(s, which); 1466 tcg_out32(s, OPC_JAL); 1467 1468 /* When branch is out of range, fall through to indirect. */ 1469 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, 1470 get_jmp_target_addr(s, which)); 1471 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1472 set_jmp_reset_offset(s, which); 1473} 1474 1475void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1476 uintptr_t jmp_rx, uintptr_t jmp_rw) 1477{ 1478 uintptr_t addr = tb->jmp_target_addr[n]; 1479 ptrdiff_t offset = addr - jmp_rx; 1480 tcg_insn_unit insn; 1481 1482 /* Either directly branch, or fall through to indirect branch. */ 1483 if (offset == sextreg(offset, 0, 20)) { 1484 insn = encode_uj(OPC_JAL, TCG_REG_ZERO, offset); 1485 } else { 1486 insn = OPC_NOP; 1487 } 1488 qatomic_set((uint32_t *)jmp_rw, insn); 1489 flush_idcache_range(jmp_rx, jmp_rw, 4); 1490} 1491 1492static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1493 const TCGArg args[TCG_MAX_OP_ARGS], 1494 const int const_args[TCG_MAX_OP_ARGS]) 1495{ 1496 TCGArg a0 = args[0]; 1497 TCGArg a1 = args[1]; 1498 TCGArg a2 = args[2]; 1499 int c2 = const_args[2]; 1500 1501 switch (opc) { 1502 case INDEX_op_goto_ptr: 1503 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); 1504 break; 1505 1506 case INDEX_op_br: 1507 tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0); 1508 tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); 1509 break; 1510 1511 case INDEX_op_ld8u_i32: 1512 case INDEX_op_ld8u_i64: 1513 tcg_out_ldst(s, OPC_LBU, a0, a1, a2); 1514 break; 1515 case INDEX_op_ld8s_i32: 1516 case INDEX_op_ld8s_i64: 1517 tcg_out_ldst(s, OPC_LB, a0, a1, a2); 1518 break; 1519 case INDEX_op_ld16u_i32: 1520 case INDEX_op_ld16u_i64: 1521 tcg_out_ldst(s, OPC_LHU, a0, a1, a2); 1522 break; 1523 case INDEX_op_ld16s_i32: 1524 case INDEX_op_ld16s_i64: 1525 tcg_out_ldst(s, OPC_LH, a0, a1, a2); 1526 break; 1527 case INDEX_op_ld32u_i64: 1528 tcg_out_ldst(s, OPC_LWU, a0, a1, a2); 1529 break; 1530 case INDEX_op_ld_i32: 1531 case INDEX_op_ld32s_i64: 1532 tcg_out_ldst(s, OPC_LW, a0, a1, a2); 1533 break; 1534 case INDEX_op_ld_i64: 1535 tcg_out_ldst(s, OPC_LD, a0, a1, a2); 1536 break; 1537 1538 case INDEX_op_st8_i32: 1539 case INDEX_op_st8_i64: 1540 tcg_out_ldst(s, OPC_SB, a0, a1, a2); 1541 break; 1542 case INDEX_op_st16_i32: 1543 case INDEX_op_st16_i64: 1544 tcg_out_ldst(s, OPC_SH, a0, a1, a2); 1545 break; 1546 case INDEX_op_st_i32: 1547 case INDEX_op_st32_i64: 1548 tcg_out_ldst(s, OPC_SW, a0, a1, a2); 1549 break; 1550 case INDEX_op_st_i64: 1551 tcg_out_ldst(s, OPC_SD, a0, a1, a2); 1552 break; 1553 1554 case INDEX_op_add_i32: 1555 if (c2) { 1556 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2); 1557 } else { 1558 tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2); 1559 } 1560 break; 1561 case INDEX_op_add_i64: 1562 if (c2) { 1563 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2); 1564 } else { 1565 tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2); 1566 } 1567 break; 1568 1569 case INDEX_op_sub_i32: 1570 if (c2) { 1571 tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2); 1572 } else { 1573 tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); 1574 } 1575 break; 1576 case INDEX_op_sub_i64: 1577 if (c2) { 1578 tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2); 1579 } else { 1580 tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); 1581 } 1582 break; 1583 1584 case INDEX_op_and_i32: 1585 case INDEX_op_and_i64: 1586 if (c2) { 1587 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1588 } else { 1589 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1590 } 1591 break; 1592 1593 case INDEX_op_or_i32: 1594 case INDEX_op_or_i64: 1595 if (c2) { 1596 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1597 } else { 1598 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1599 } 1600 break; 1601 1602 case INDEX_op_xor_i32: 1603 case INDEX_op_xor_i64: 1604 if (c2) { 1605 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 1606 } else { 1607 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 1608 } 1609 break; 1610 1611 case INDEX_op_andc_i32: 1612 case INDEX_op_andc_i64: 1613 if (c2) { 1614 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, ~a2); 1615 } else { 1616 tcg_out_opc_reg(s, OPC_ANDN, a0, a1, a2); 1617 } 1618 break; 1619 case INDEX_op_orc_i32: 1620 case INDEX_op_orc_i64: 1621 if (c2) { 1622 tcg_out_opc_imm(s, OPC_ORI, a0, a1, ~a2); 1623 } else { 1624 tcg_out_opc_reg(s, OPC_ORN, a0, a1, a2); 1625 } 1626 break; 1627 case INDEX_op_eqv_i32: 1628 case INDEX_op_eqv_i64: 1629 if (c2) { 1630 tcg_out_opc_imm(s, OPC_XORI, a0, a1, ~a2); 1631 } else { 1632 tcg_out_opc_reg(s, OPC_XNOR, a0, a1, a2); 1633 } 1634 break; 1635 1636 case INDEX_op_not_i32: 1637 case INDEX_op_not_i64: 1638 tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1); 1639 break; 1640 1641 case INDEX_op_neg_i32: 1642 tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1); 1643 break; 1644 case INDEX_op_neg_i64: 1645 tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1); 1646 break; 1647 1648 case INDEX_op_mul_i32: 1649 tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2); 1650 break; 1651 case INDEX_op_mul_i64: 1652 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1653 break; 1654 1655 case INDEX_op_div_i32: 1656 tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2); 1657 break; 1658 case INDEX_op_div_i64: 1659 tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2); 1660 break; 1661 1662 case INDEX_op_divu_i32: 1663 tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2); 1664 break; 1665 case INDEX_op_divu_i64: 1666 tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2); 1667 break; 1668 1669 case INDEX_op_rem_i32: 1670 tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2); 1671 break; 1672 case INDEX_op_rem_i64: 1673 tcg_out_opc_reg(s, OPC_REM, a0, a1, a2); 1674 break; 1675 1676 case INDEX_op_remu_i32: 1677 tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2); 1678 break; 1679 case INDEX_op_remu_i64: 1680 tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2); 1681 break; 1682 1683 case INDEX_op_shl_i32: 1684 if (c2) { 1685 tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2 & 0x1f); 1686 } else { 1687 tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2); 1688 } 1689 break; 1690 case INDEX_op_shl_i64: 1691 if (c2) { 1692 tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2 & 0x3f); 1693 } else { 1694 tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2); 1695 } 1696 break; 1697 1698 case INDEX_op_shr_i32: 1699 if (c2) { 1700 tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2 & 0x1f); 1701 } else { 1702 tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2); 1703 } 1704 break; 1705 case INDEX_op_shr_i64: 1706 if (c2) { 1707 tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2 & 0x3f); 1708 } else { 1709 tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2); 1710 } 1711 break; 1712 1713 case INDEX_op_sar_i32: 1714 if (c2) { 1715 tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2 & 0x1f); 1716 } else { 1717 tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2); 1718 } 1719 break; 1720 case INDEX_op_sar_i64: 1721 if (c2) { 1722 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2 & 0x3f); 1723 } else { 1724 tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2); 1725 } 1726 break; 1727 1728 case INDEX_op_rotl_i32: 1729 if (c2) { 1730 tcg_out_opc_imm(s, OPC_RORIW, a0, a1, -a2 & 0x1f); 1731 } else { 1732 tcg_out_opc_reg(s, OPC_ROLW, a0, a1, a2); 1733 } 1734 break; 1735 case INDEX_op_rotl_i64: 1736 if (c2) { 1737 tcg_out_opc_imm(s, OPC_RORI, a0, a1, -a2 & 0x3f); 1738 } else { 1739 tcg_out_opc_reg(s, OPC_ROL, a0, a1, a2); 1740 } 1741 break; 1742 1743 case INDEX_op_rotr_i32: 1744 if (c2) { 1745 tcg_out_opc_imm(s, OPC_RORIW, a0, a1, a2 & 0x1f); 1746 } else { 1747 tcg_out_opc_reg(s, OPC_RORW, a0, a1, a2); 1748 } 1749 break; 1750 case INDEX_op_rotr_i64: 1751 if (c2) { 1752 tcg_out_opc_imm(s, OPC_RORI, a0, a1, a2 & 0x3f); 1753 } else { 1754 tcg_out_opc_reg(s, OPC_ROR, a0, a1, a2); 1755 } 1756 break; 1757 1758 case INDEX_op_bswap64_i64: 1759 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 1760 break; 1761 case INDEX_op_bswap32_i32: 1762 a2 = 0; 1763 /* fall through */ 1764 case INDEX_op_bswap32_i64: 1765 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 1766 if (a2 & TCG_BSWAP_OZ) { 1767 tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 32); 1768 } else { 1769 tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 32); 1770 } 1771 break; 1772 case INDEX_op_bswap16_i64: 1773 case INDEX_op_bswap16_i32: 1774 tcg_out_opc_imm(s, OPC_REV8, a0, a1, 0); 1775 if (a2 & TCG_BSWAP_OZ) { 1776 tcg_out_opc_imm(s, OPC_SRLI, a0, a0, 48); 1777 } else { 1778 tcg_out_opc_imm(s, OPC_SRAI, a0, a0, 48); 1779 } 1780 break; 1781 1782 case INDEX_op_ctpop_i32: 1783 tcg_out_opc_imm(s, OPC_CPOPW, a0, a1, 0); 1784 break; 1785 case INDEX_op_ctpop_i64: 1786 tcg_out_opc_imm(s, OPC_CPOP, a0, a1, 0); 1787 break; 1788 1789 case INDEX_op_clz_i32: 1790 tcg_out_cltz(s, TCG_TYPE_I32, OPC_CLZW, a0, a1, a2, c2); 1791 break; 1792 case INDEX_op_clz_i64: 1793 tcg_out_cltz(s, TCG_TYPE_I64, OPC_CLZ, a0, a1, a2, c2); 1794 break; 1795 case INDEX_op_ctz_i32: 1796 tcg_out_cltz(s, TCG_TYPE_I32, OPC_CTZW, a0, a1, a2, c2); 1797 break; 1798 case INDEX_op_ctz_i64: 1799 tcg_out_cltz(s, TCG_TYPE_I64, OPC_CTZ, a0, a1, a2, c2); 1800 break; 1801 1802 case INDEX_op_add2_i32: 1803 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1804 const_args[4], const_args[5], false, true); 1805 break; 1806 case INDEX_op_add2_i64: 1807 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1808 const_args[4], const_args[5], false, false); 1809 break; 1810 case INDEX_op_sub2_i32: 1811 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1812 const_args[4], const_args[5], true, true); 1813 break; 1814 case INDEX_op_sub2_i64: 1815 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1816 const_args[4], const_args[5], true, false); 1817 break; 1818 1819 case INDEX_op_brcond_i32: 1820 case INDEX_op_brcond_i64: 1821 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1822 break; 1823 1824 case INDEX_op_setcond_i32: 1825 case INDEX_op_setcond_i64: 1826 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 1827 break; 1828 1829 case INDEX_op_negsetcond_i32: 1830 case INDEX_op_negsetcond_i64: 1831 tcg_out_negsetcond(s, args[3], a0, a1, a2, c2); 1832 break; 1833 1834 case INDEX_op_movcond_i32: 1835 case INDEX_op_movcond_i64: 1836 tcg_out_movcond(s, args[5], a0, a1, a2, c2, 1837 args[3], const_args[3], args[4], const_args[4]); 1838 break; 1839 1840 case INDEX_op_qemu_ld_a32_i32: 1841 case INDEX_op_qemu_ld_a64_i32: 1842 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1843 break; 1844 case INDEX_op_qemu_ld_a32_i64: 1845 case INDEX_op_qemu_ld_a64_i64: 1846 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1847 break; 1848 case INDEX_op_qemu_st_a32_i32: 1849 case INDEX_op_qemu_st_a64_i32: 1850 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1851 break; 1852 case INDEX_op_qemu_st_a32_i64: 1853 case INDEX_op_qemu_st_a64_i64: 1854 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1855 break; 1856 1857 case INDEX_op_extrh_i64_i32: 1858 tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); 1859 break; 1860 1861 case INDEX_op_mulsh_i32: 1862 case INDEX_op_mulsh_i64: 1863 tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); 1864 break; 1865 1866 case INDEX_op_muluh_i32: 1867 case INDEX_op_muluh_i64: 1868 tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); 1869 break; 1870 1871 case INDEX_op_mb: 1872 tcg_out_mb(s, a0); 1873 break; 1874 1875 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1876 case INDEX_op_mov_i64: 1877 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1878 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1879 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1880 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1881 case INDEX_op_ext8s_i64: 1882 case INDEX_op_ext8u_i32: 1883 case INDEX_op_ext8u_i64: 1884 case INDEX_op_ext16s_i32: 1885 case INDEX_op_ext16s_i64: 1886 case INDEX_op_ext16u_i32: 1887 case INDEX_op_ext16u_i64: 1888 case INDEX_op_ext32s_i64: 1889 case INDEX_op_ext32u_i64: 1890 case INDEX_op_ext_i32_i64: 1891 case INDEX_op_extu_i32_i64: 1892 case INDEX_op_extrl_i64_i32: 1893 default: 1894 g_assert_not_reached(); 1895 } 1896} 1897 1898static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 1899{ 1900 switch (op) { 1901 case INDEX_op_goto_ptr: 1902 return C_O0_I1(r); 1903 1904 case INDEX_op_ld8u_i32: 1905 case INDEX_op_ld8s_i32: 1906 case INDEX_op_ld16u_i32: 1907 case INDEX_op_ld16s_i32: 1908 case INDEX_op_ld_i32: 1909 case INDEX_op_not_i32: 1910 case INDEX_op_neg_i32: 1911 case INDEX_op_ld8u_i64: 1912 case INDEX_op_ld8s_i64: 1913 case INDEX_op_ld16u_i64: 1914 case INDEX_op_ld16s_i64: 1915 case INDEX_op_ld32s_i64: 1916 case INDEX_op_ld32u_i64: 1917 case INDEX_op_ld_i64: 1918 case INDEX_op_not_i64: 1919 case INDEX_op_neg_i64: 1920 case INDEX_op_ext8u_i32: 1921 case INDEX_op_ext8u_i64: 1922 case INDEX_op_ext16u_i32: 1923 case INDEX_op_ext16u_i64: 1924 case INDEX_op_ext32u_i64: 1925 case INDEX_op_extu_i32_i64: 1926 case INDEX_op_ext8s_i32: 1927 case INDEX_op_ext8s_i64: 1928 case INDEX_op_ext16s_i32: 1929 case INDEX_op_ext16s_i64: 1930 case INDEX_op_ext32s_i64: 1931 case INDEX_op_extrl_i64_i32: 1932 case INDEX_op_extrh_i64_i32: 1933 case INDEX_op_ext_i32_i64: 1934 case INDEX_op_bswap16_i32: 1935 case INDEX_op_bswap32_i32: 1936 case INDEX_op_bswap16_i64: 1937 case INDEX_op_bswap32_i64: 1938 case INDEX_op_bswap64_i64: 1939 case INDEX_op_ctpop_i32: 1940 case INDEX_op_ctpop_i64: 1941 return C_O1_I1(r, r); 1942 1943 case INDEX_op_st8_i32: 1944 case INDEX_op_st16_i32: 1945 case INDEX_op_st_i32: 1946 case INDEX_op_st8_i64: 1947 case INDEX_op_st16_i64: 1948 case INDEX_op_st32_i64: 1949 case INDEX_op_st_i64: 1950 return C_O0_I2(rZ, r); 1951 1952 case INDEX_op_add_i32: 1953 case INDEX_op_and_i32: 1954 case INDEX_op_or_i32: 1955 case INDEX_op_xor_i32: 1956 case INDEX_op_add_i64: 1957 case INDEX_op_and_i64: 1958 case INDEX_op_or_i64: 1959 case INDEX_op_xor_i64: 1960 case INDEX_op_setcond_i32: 1961 case INDEX_op_setcond_i64: 1962 case INDEX_op_negsetcond_i32: 1963 case INDEX_op_negsetcond_i64: 1964 return C_O1_I2(r, r, rI); 1965 1966 case INDEX_op_andc_i32: 1967 case INDEX_op_andc_i64: 1968 case INDEX_op_orc_i32: 1969 case INDEX_op_orc_i64: 1970 case INDEX_op_eqv_i32: 1971 case INDEX_op_eqv_i64: 1972 return C_O1_I2(r, r, rJ); 1973 1974 case INDEX_op_sub_i32: 1975 case INDEX_op_sub_i64: 1976 return C_O1_I2(r, rZ, rN); 1977 1978 case INDEX_op_mul_i32: 1979 case INDEX_op_mulsh_i32: 1980 case INDEX_op_muluh_i32: 1981 case INDEX_op_div_i32: 1982 case INDEX_op_divu_i32: 1983 case INDEX_op_rem_i32: 1984 case INDEX_op_remu_i32: 1985 case INDEX_op_mul_i64: 1986 case INDEX_op_mulsh_i64: 1987 case INDEX_op_muluh_i64: 1988 case INDEX_op_div_i64: 1989 case INDEX_op_divu_i64: 1990 case INDEX_op_rem_i64: 1991 case INDEX_op_remu_i64: 1992 return C_O1_I2(r, rZ, rZ); 1993 1994 case INDEX_op_shl_i32: 1995 case INDEX_op_shr_i32: 1996 case INDEX_op_sar_i32: 1997 case INDEX_op_rotl_i32: 1998 case INDEX_op_rotr_i32: 1999 case INDEX_op_shl_i64: 2000 case INDEX_op_shr_i64: 2001 case INDEX_op_sar_i64: 2002 case INDEX_op_rotl_i64: 2003 case INDEX_op_rotr_i64: 2004 return C_O1_I2(r, r, ri); 2005 2006 case INDEX_op_clz_i32: 2007 case INDEX_op_clz_i64: 2008 case INDEX_op_ctz_i32: 2009 case INDEX_op_ctz_i64: 2010 return C_N1_I2(r, r, rM); 2011 2012 case INDEX_op_brcond_i32: 2013 case INDEX_op_brcond_i64: 2014 return C_O0_I2(rZ, rZ); 2015 2016 case INDEX_op_movcond_i32: 2017 case INDEX_op_movcond_i64: 2018 return C_O1_I4(r, r, rI, rM, rM); 2019 2020 case INDEX_op_add2_i32: 2021 case INDEX_op_add2_i64: 2022 case INDEX_op_sub2_i32: 2023 case INDEX_op_sub2_i64: 2024 return C_O2_I4(r, r, rZ, rZ, rM, rM); 2025 2026 case INDEX_op_qemu_ld_a32_i32: 2027 case INDEX_op_qemu_ld_a64_i32: 2028 case INDEX_op_qemu_ld_a32_i64: 2029 case INDEX_op_qemu_ld_a64_i64: 2030 return C_O1_I1(r, r); 2031 case INDEX_op_qemu_st_a32_i32: 2032 case INDEX_op_qemu_st_a64_i32: 2033 case INDEX_op_qemu_st_a32_i64: 2034 case INDEX_op_qemu_st_a64_i64: 2035 return C_O0_I2(rZ, r); 2036 2037 default: 2038 g_assert_not_reached(); 2039 } 2040} 2041 2042static const int tcg_target_callee_save_regs[] = { 2043 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2044 TCG_REG_S1, 2045 TCG_REG_S2, 2046 TCG_REG_S3, 2047 TCG_REG_S4, 2048 TCG_REG_S5, 2049 TCG_REG_S6, 2050 TCG_REG_S7, 2051 TCG_REG_S8, 2052 TCG_REG_S9, 2053 TCG_REG_S10, 2054 TCG_REG_S11, 2055 TCG_REG_RA, /* should be last for ABI compliance */ 2056}; 2057 2058/* Stack frame parameters. */ 2059#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2060#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2061#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2062#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2063 + TCG_TARGET_STACK_ALIGN - 1) \ 2064 & -TCG_TARGET_STACK_ALIGN) 2065#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2066 2067/* We're expecting to be able to use an immediate for frame allocation. */ 2068QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2069 2070/* Generate global QEMU prologue and epilogue code */ 2071static void tcg_target_qemu_prologue(TCGContext *s) 2072{ 2073 int i; 2074 2075 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2076 2077 /* TB prologue */ 2078 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2079 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2080 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2081 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2082 } 2083 2084 if (!tcg_use_softmmu && guest_base) { 2085 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2086 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2087 } 2088 2089 /* Call generated code */ 2090 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2091 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2092 2093 /* Return path for goto_ptr. Set return value to 0 */ 2094 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2095 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2096 2097 /* TB epilogue */ 2098 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2099 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2100 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2101 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2102 } 2103 2104 tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2105 tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); 2106} 2107 2108static void tcg_out_tb_start(TCGContext *s) 2109{ 2110 /* nothing to do */ 2111} 2112 2113static volatile sig_atomic_t got_sigill; 2114 2115static void sigill_handler(int signo, siginfo_t *si, void *data) 2116{ 2117 /* Skip the faulty instruction */ 2118 ucontext_t *uc = (ucontext_t *)data; 2119 uc->uc_mcontext.__gregs[REG_PC] += 4; 2120 2121 got_sigill = 1; 2122} 2123 2124static void tcg_target_detect_isa(void) 2125{ 2126#if !defined(have_zba) || !defined(have_zbb) || !defined(have_zicond) 2127 /* 2128 * TODO: It is expected that this will be determinable via 2129 * linux riscv_hwprobe syscall, not yet merged. 2130 * In the meantime, test via sigill. 2131 */ 2132 2133 struct sigaction sa_old, sa_new; 2134 2135 memset(&sa_new, 0, sizeof(sa_new)); 2136 sa_new.sa_flags = SA_SIGINFO; 2137 sa_new.sa_sigaction = sigill_handler; 2138 sigaction(SIGILL, &sa_new, &sa_old); 2139 2140#ifndef have_zba 2141 /* Probe for Zba: add.uw zero,zero,zero. */ 2142 got_sigill = 0; 2143 asm volatile(".insn r 0x3b, 0, 0x04, zero, zero, zero" : : : "memory"); 2144 have_zba = !got_sigill; 2145#endif 2146 2147#ifndef have_zbb 2148 /* Probe for Zba: andn zero,zero,zero. */ 2149 got_sigill = 0; 2150 asm volatile(".insn r 0x33, 7, 0x20, zero, zero, zero" : : : "memory"); 2151 have_zbb = !got_sigill; 2152#endif 2153 2154#ifndef have_zicond 2155 /* Probe for Zicond: czero.eqz zero,zero,zero. */ 2156 got_sigill = 0; 2157 asm volatile(".insn r 0x33, 5, 0x07, zero, zero, zero" : : : "memory"); 2158 have_zicond = !got_sigill; 2159#endif 2160 2161 sigaction(SIGILL, &sa_old, NULL); 2162#endif 2163} 2164 2165static void tcg_target_init(TCGContext *s) 2166{ 2167 tcg_target_detect_isa(); 2168 2169 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2170 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2171 2172 tcg_target_call_clobber_regs = -1u; 2173 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2174 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2175 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2176 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2177 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2178 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2179 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2180 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2181 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2182 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2183 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10); 2184 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11); 2185 2186 s->reserved_regs = 0; 2187 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2188 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2189 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2190 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2191 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2192 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); 2193 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2194} 2195 2196typedef struct { 2197 DebugFrameHeader h; 2198 uint8_t fde_def_cfa[4]; 2199 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2200} DebugFrame; 2201 2202#define ELF_HOST_MACHINE EM_RISCV 2203 2204static const DebugFrame debug_frame = { 2205 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2206 .h.cie.id = -1, 2207 .h.cie.version = 1, 2208 .h.cie.code_align = 1, 2209 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2210 .h.cie.return_column = TCG_REG_RA, 2211 2212 /* Total FDE size does not include the "len" member. */ 2213 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2214 2215 .fde_def_cfa = { 2216 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2217 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2218 (FRAME_SIZE >> 7) 2219 }, 2220 .fde_reg_ofs = { 2221 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ 2222 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ 2223 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ 2224 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ 2225 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ 2226 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ 2227 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ 2228 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ 2229 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ 2230 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ 2231 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ 2232 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 2233 } 2234}; 2235 2236void tcg_register_jit(const void *buf, size_t buf_size) 2237{ 2238 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2239} 2240