1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2018 SiFive, Inc 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_negsetcond_i32 1 14 #define TCG_TARGET_HAS_extract2_i32 0 15 #define TCG_TARGET_HAS_add2_i32 1 16 #define TCG_TARGET_HAS_sub2_i32 1 17 #define TCG_TARGET_HAS_mulu2_i32 0 18 #define TCG_TARGET_HAS_muls2_i32 0 19 #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) 20 #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) 21 #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) 22 #define TCG_TARGET_HAS_qemu_st8_i32 0 23 24 #define TCG_TARGET_HAS_negsetcond_i64 1 25 #define TCG_TARGET_HAS_extract2_i64 0 26 #define TCG_TARGET_HAS_extr_i64_i32 1 27 #define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) 28 #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) 29 #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) 30 #define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) 31 #define TCG_TARGET_HAS_add2_i64 1 32 #define TCG_TARGET_HAS_sub2_i64 1 33 #define TCG_TARGET_HAS_mulu2_i64 0 34 #define TCG_TARGET_HAS_muls2_i64 0 35 36 #define TCG_TARGET_HAS_qemu_ldst_i128 0 37 38 #define TCG_TARGET_HAS_tst 0 39 40 /* vector instructions */ 41 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X) 42 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X) 43 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X) 44 #define TCG_TARGET_HAS_andc_vec 0 45 #define TCG_TARGET_HAS_orc_vec 0 46 #define TCG_TARGET_HAS_nand_vec 0 47 #define TCG_TARGET_HAS_nor_vec 0 48 #define TCG_TARGET_HAS_eqv_vec 0 49 #define TCG_TARGET_HAS_not_vec 1 50 #define TCG_TARGET_HAS_neg_vec 1 51 #define TCG_TARGET_HAS_abs_vec 0 52 #define TCG_TARGET_HAS_roti_vec 1 53 #define TCG_TARGET_HAS_rots_vec 1 54 #define TCG_TARGET_HAS_rotv_vec 1 55 #define TCG_TARGET_HAS_shi_vec 1 56 #define TCG_TARGET_HAS_shs_vec 1 57 #define TCG_TARGET_HAS_shv_vec 1 58 #define TCG_TARGET_HAS_mul_vec 1 59 #define TCG_TARGET_HAS_sat_vec 1 60 #define TCG_TARGET_HAS_minmax_vec 1 61 #define TCG_TARGET_HAS_bitsel_vec 0 62 #define TCG_TARGET_HAS_cmpsel_vec 1 63 64 #define TCG_TARGET_HAS_tst_vec 0 65 66 static inline bool 67 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 68 { 69 if (type == TCG_TYPE_I64 && ofs + len == 32) { 70 /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ 71 return ofs || (cpuinfo & CPUINFO_ZBA); 72 } 73 switch (len) { 74 case 1: 75 return (cpuinfo & CPUINFO_ZBS) && ofs != 0; 76 case 16: 77 return (cpuinfo & CPUINFO_ZBB) && ofs == 0; 78 } 79 return false; 80 } 81 #define TCG_TARGET_extract_valid tcg_target_extract_valid 82 83 static inline bool 84 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 85 { 86 if (type == TCG_TYPE_I64 && ofs + len == 32) { 87 return true; 88 } 89 return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16); 90 } 91 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 92 93 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 94 95 #endif 96