1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2018 SiFive, Inc 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_extract2_i32 0 14 #define TCG_TARGET_HAS_add2_i32 1 15 #define TCG_TARGET_HAS_sub2_i32 1 16 #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) 17 #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) 18 #define TCG_TARGET_HAS_qemu_st8_i32 0 19 20 #define TCG_TARGET_HAS_extract2_i64 0 21 #define TCG_TARGET_HAS_extr_i64_i32 1 22 #define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) 23 #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) 24 #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) 25 #define TCG_TARGET_HAS_add2_i64 1 26 #define TCG_TARGET_HAS_sub2_i64 1 27 28 #define TCG_TARGET_HAS_qemu_ldst_i128 0 29 30 #define TCG_TARGET_HAS_tst 0 31 32 /* vector instructions */ 33 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X) 34 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X) 35 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X) 36 #define TCG_TARGET_HAS_andc_vec 0 37 #define TCG_TARGET_HAS_orc_vec 0 38 #define TCG_TARGET_HAS_nand_vec 0 39 #define TCG_TARGET_HAS_nor_vec 0 40 #define TCG_TARGET_HAS_eqv_vec 0 41 #define TCG_TARGET_HAS_not_vec 1 42 #define TCG_TARGET_HAS_neg_vec 1 43 #define TCG_TARGET_HAS_abs_vec 0 44 #define TCG_TARGET_HAS_roti_vec 1 45 #define TCG_TARGET_HAS_rots_vec 1 46 #define TCG_TARGET_HAS_rotv_vec 1 47 #define TCG_TARGET_HAS_shi_vec 1 48 #define TCG_TARGET_HAS_shs_vec 1 49 #define TCG_TARGET_HAS_shv_vec 1 50 #define TCG_TARGET_HAS_mul_vec 1 51 #define TCG_TARGET_HAS_sat_vec 1 52 #define TCG_TARGET_HAS_minmax_vec 1 53 #define TCG_TARGET_HAS_bitsel_vec 0 54 #define TCG_TARGET_HAS_cmpsel_vec 1 55 56 #define TCG_TARGET_HAS_tst_vec 0 57 58 static inline bool 59 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 60 { 61 if (type == TCG_TYPE_I64 && ofs + len == 32) { 62 /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ 63 return ofs || (cpuinfo & CPUINFO_ZBA); 64 } 65 switch (len) { 66 case 1: 67 return (cpuinfo & CPUINFO_ZBS) && ofs != 0; 68 case 16: 69 return (cpuinfo & CPUINFO_ZBB) && ofs == 0; 70 } 71 return false; 72 } 73 #define TCG_TARGET_extract_valid tcg_target_extract_valid 74 75 static inline bool 76 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 77 { 78 if (type == TCG_TYPE_I64 && ofs + len == 32) { 79 return true; 80 } 81 return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16); 82 } 83 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 84 85 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 86 87 #endif 88