1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2018 SiFive, Inc 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_negsetcond_i32 1 14 #define TCG_TARGET_HAS_div_i32 1 15 #define TCG_TARGET_HAS_rem_i32 1 16 #define TCG_TARGET_HAS_div2_i32 0 17 #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) 18 #define TCG_TARGET_HAS_extract2_i32 0 19 #define TCG_TARGET_HAS_add2_i32 1 20 #define TCG_TARGET_HAS_sub2_i32 1 21 #define TCG_TARGET_HAS_mulu2_i32 0 22 #define TCG_TARGET_HAS_muls2_i32 0 23 #define TCG_TARGET_HAS_muluh_i32 0 24 #define TCG_TARGET_HAS_mulsh_i32 0 25 #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) 26 #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) 27 #define TCG_TARGET_HAS_not_i32 1 28 #define TCG_TARGET_HAS_andc_i32 (cpuinfo & CPUINFO_ZBB) 29 #define TCG_TARGET_HAS_orc_i32 (cpuinfo & CPUINFO_ZBB) 30 #define TCG_TARGET_HAS_eqv_i32 (cpuinfo & CPUINFO_ZBB) 31 #define TCG_TARGET_HAS_nand_i32 0 32 #define TCG_TARGET_HAS_nor_i32 0 33 #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) 34 #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) 35 #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) 36 #define TCG_TARGET_HAS_qemu_st8_i32 0 37 38 #define TCG_TARGET_HAS_negsetcond_i64 1 39 #define TCG_TARGET_HAS_div_i64 1 40 #define TCG_TARGET_HAS_rem_i64 1 41 #define TCG_TARGET_HAS_div2_i64 0 42 #define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) 43 #define TCG_TARGET_HAS_extract2_i64 0 44 #define TCG_TARGET_HAS_extr_i64_i32 1 45 #define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) 46 #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) 47 #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) 48 #define TCG_TARGET_HAS_not_i64 1 49 #define TCG_TARGET_HAS_andc_i64 (cpuinfo & CPUINFO_ZBB) 50 #define TCG_TARGET_HAS_orc_i64 (cpuinfo & CPUINFO_ZBB) 51 #define TCG_TARGET_HAS_eqv_i64 (cpuinfo & CPUINFO_ZBB) 52 #define TCG_TARGET_HAS_nand_i64 0 53 #define TCG_TARGET_HAS_nor_i64 0 54 #define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB) 55 #define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB) 56 #define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) 57 #define TCG_TARGET_HAS_add2_i64 1 58 #define TCG_TARGET_HAS_sub2_i64 1 59 #define TCG_TARGET_HAS_mulu2_i64 0 60 #define TCG_TARGET_HAS_muls2_i64 0 61 #define TCG_TARGET_HAS_muluh_i64 1 62 #define TCG_TARGET_HAS_mulsh_i64 1 63 64 #define TCG_TARGET_HAS_qemu_ldst_i128 0 65 66 #define TCG_TARGET_HAS_tst 0 67 68 /* vector instructions */ 69 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X) 70 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X) 71 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X) 72 #define TCG_TARGET_HAS_andc_vec 0 73 #define TCG_TARGET_HAS_orc_vec 0 74 #define TCG_TARGET_HAS_nand_vec 0 75 #define TCG_TARGET_HAS_nor_vec 0 76 #define TCG_TARGET_HAS_eqv_vec 0 77 #define TCG_TARGET_HAS_not_vec 1 78 #define TCG_TARGET_HAS_neg_vec 1 79 #define TCG_TARGET_HAS_abs_vec 0 80 #define TCG_TARGET_HAS_roti_vec 1 81 #define TCG_TARGET_HAS_rots_vec 1 82 #define TCG_TARGET_HAS_rotv_vec 1 83 #define TCG_TARGET_HAS_shi_vec 1 84 #define TCG_TARGET_HAS_shs_vec 1 85 #define TCG_TARGET_HAS_shv_vec 1 86 #define TCG_TARGET_HAS_mul_vec 1 87 #define TCG_TARGET_HAS_sat_vec 1 88 #define TCG_TARGET_HAS_minmax_vec 1 89 #define TCG_TARGET_HAS_bitsel_vec 0 90 #define TCG_TARGET_HAS_cmpsel_vec 1 91 92 #define TCG_TARGET_HAS_tst_vec 0 93 94 static inline bool 95 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 96 { 97 if (type == TCG_TYPE_I64 && ofs + len == 32) { 98 /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ 99 return ofs || (cpuinfo & CPUINFO_ZBA); 100 } 101 switch (len) { 102 case 1: 103 return (cpuinfo & CPUINFO_ZBS) && ofs != 0; 104 case 16: 105 return (cpuinfo & CPUINFO_ZBB) && ofs == 0; 106 } 107 return false; 108 } 109 #define TCG_TARGET_extract_valid tcg_target_extract_valid 110 111 static inline bool 112 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 113 { 114 if (type == TCG_TYPE_I64 && ofs + len == 32) { 115 return true; 116 } 117 return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16); 118 } 119 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 120 121 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 122 123 #endif 124