xref: /openbmc/qemu/tcg/riscv/tcg-target-has.h (revision 3ad5d4ccb4bdebdff4e90957bb2b8a93e5e418e2)
1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Define target-specific opcode support
4  * Copyright (c) 2018 SiFive, Inc
5  */
6 
7 #ifndef TCG_TARGET_HAS_H
8 #define TCG_TARGET_HAS_H
9 
10 #include "host/cpuinfo.h"
11 
12 /* optional instructions */
13 #define TCG_TARGET_HAS_extract2_i32     0
14 #define TCG_TARGET_HAS_add2_i32         1
15 #define TCG_TARGET_HAS_sub2_i32         1
16 #define TCG_TARGET_HAS_qemu_st8_i32     0
17 
18 #define TCG_TARGET_HAS_extract2_i64     0
19 #define TCG_TARGET_HAS_extr_i64_i32     1
20 #define TCG_TARGET_HAS_add2_i64         1
21 #define TCG_TARGET_HAS_sub2_i64         1
22 
23 #define TCG_TARGET_HAS_qemu_ldst_i128   0
24 
25 #define TCG_TARGET_HAS_tst              0
26 
27 /* vector instructions */
28 #define TCG_TARGET_HAS_v64              (cpuinfo & CPUINFO_ZVE64X)
29 #define TCG_TARGET_HAS_v128             (cpuinfo & CPUINFO_ZVE64X)
30 #define TCG_TARGET_HAS_v256             (cpuinfo & CPUINFO_ZVE64X)
31 #define TCG_TARGET_HAS_andc_vec         0
32 #define TCG_TARGET_HAS_orc_vec          0
33 #define TCG_TARGET_HAS_nand_vec         0
34 #define TCG_TARGET_HAS_nor_vec          0
35 #define TCG_TARGET_HAS_eqv_vec          0
36 #define TCG_TARGET_HAS_not_vec          1
37 #define TCG_TARGET_HAS_neg_vec          1
38 #define TCG_TARGET_HAS_abs_vec          0
39 #define TCG_TARGET_HAS_roti_vec         1
40 #define TCG_TARGET_HAS_rots_vec         1
41 #define TCG_TARGET_HAS_rotv_vec         1
42 #define TCG_TARGET_HAS_shi_vec          1
43 #define TCG_TARGET_HAS_shs_vec          1
44 #define TCG_TARGET_HAS_shv_vec          1
45 #define TCG_TARGET_HAS_mul_vec          1
46 #define TCG_TARGET_HAS_sat_vec          1
47 #define TCG_TARGET_HAS_minmax_vec       1
48 #define TCG_TARGET_HAS_bitsel_vec       0
49 #define TCG_TARGET_HAS_cmpsel_vec       1
50 
51 #define TCG_TARGET_HAS_tst_vec          0
52 
53 static inline bool
54 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len)
55 {
56     if (type == TCG_TYPE_I64 && ofs + len == 32) {
57         /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */
58         return ofs || (cpuinfo & CPUINFO_ZBA);
59     }
60     switch (len) {
61     case 1:
62         return (cpuinfo & CPUINFO_ZBS) && ofs != 0;
63     case 16:
64         return (cpuinfo & CPUINFO_ZBB) && ofs == 0;
65     }
66     return false;
67 }
68 #define TCG_TARGET_extract_valid  tcg_target_extract_valid
69 
70 static inline bool
71 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len)
72 {
73     if (type == TCG_TYPE_I64 && ofs + len == 32) {
74         return true;
75     }
76     return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16);
77 }
78 #define TCG_TARGET_sextract_valid  tcg_target_sextract_valid
79 
80 #define TCG_TARGET_deposit_valid(type, ofs, len)  0
81 
82 #endif
83