1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2018 SiFive, Inc 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_negsetcond_i32 1 14 #define TCG_TARGET_HAS_div_i32 1 15 #define TCG_TARGET_HAS_rem_i32 1 16 #define TCG_TARGET_HAS_div2_i32 0 17 #define TCG_TARGET_HAS_rot_i32 (cpuinfo & CPUINFO_ZBB) 18 #define TCG_TARGET_HAS_extract2_i32 0 19 #define TCG_TARGET_HAS_add2_i32 1 20 #define TCG_TARGET_HAS_sub2_i32 1 21 #define TCG_TARGET_HAS_mulu2_i32 0 22 #define TCG_TARGET_HAS_muls2_i32 0 23 #define TCG_TARGET_HAS_muluh_i32 0 24 #define TCG_TARGET_HAS_mulsh_i32 0 25 #define TCG_TARGET_HAS_bswap16_i32 (cpuinfo & CPUINFO_ZBB) 26 #define TCG_TARGET_HAS_bswap32_i32 (cpuinfo & CPUINFO_ZBB) 27 #define TCG_TARGET_HAS_not_i32 1 28 #define TCG_TARGET_HAS_clz_i32 (cpuinfo & CPUINFO_ZBB) 29 #define TCG_TARGET_HAS_ctz_i32 (cpuinfo & CPUINFO_ZBB) 30 #define TCG_TARGET_HAS_ctpop_i32 (cpuinfo & CPUINFO_ZBB) 31 #define TCG_TARGET_HAS_qemu_st8_i32 0 32 33 #define TCG_TARGET_HAS_negsetcond_i64 1 34 #define TCG_TARGET_HAS_div_i64 1 35 #define TCG_TARGET_HAS_rem_i64 1 36 #define TCG_TARGET_HAS_div2_i64 0 37 #define TCG_TARGET_HAS_rot_i64 (cpuinfo & CPUINFO_ZBB) 38 #define TCG_TARGET_HAS_extract2_i64 0 39 #define TCG_TARGET_HAS_extr_i64_i32 1 40 #define TCG_TARGET_HAS_bswap16_i64 (cpuinfo & CPUINFO_ZBB) 41 #define TCG_TARGET_HAS_bswap32_i64 (cpuinfo & CPUINFO_ZBB) 42 #define TCG_TARGET_HAS_bswap64_i64 (cpuinfo & CPUINFO_ZBB) 43 #define TCG_TARGET_HAS_not_i64 1 44 #define TCG_TARGET_HAS_clz_i64 (cpuinfo & CPUINFO_ZBB) 45 #define TCG_TARGET_HAS_ctz_i64 (cpuinfo & CPUINFO_ZBB) 46 #define TCG_TARGET_HAS_ctpop_i64 (cpuinfo & CPUINFO_ZBB) 47 #define TCG_TARGET_HAS_add2_i64 1 48 #define TCG_TARGET_HAS_sub2_i64 1 49 #define TCG_TARGET_HAS_mulu2_i64 0 50 #define TCG_TARGET_HAS_muls2_i64 0 51 #define TCG_TARGET_HAS_muluh_i64 1 52 #define TCG_TARGET_HAS_mulsh_i64 1 53 54 #define TCG_TARGET_HAS_qemu_ldst_i128 0 55 56 #define TCG_TARGET_HAS_tst 0 57 58 /* vector instructions */ 59 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_ZVE64X) 60 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_ZVE64X) 61 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_ZVE64X) 62 #define TCG_TARGET_HAS_andc_vec 0 63 #define TCG_TARGET_HAS_orc_vec 0 64 #define TCG_TARGET_HAS_nand_vec 0 65 #define TCG_TARGET_HAS_nor_vec 0 66 #define TCG_TARGET_HAS_eqv_vec 0 67 #define TCG_TARGET_HAS_not_vec 1 68 #define TCG_TARGET_HAS_neg_vec 1 69 #define TCG_TARGET_HAS_abs_vec 0 70 #define TCG_TARGET_HAS_roti_vec 1 71 #define TCG_TARGET_HAS_rots_vec 1 72 #define TCG_TARGET_HAS_rotv_vec 1 73 #define TCG_TARGET_HAS_shi_vec 1 74 #define TCG_TARGET_HAS_shs_vec 1 75 #define TCG_TARGET_HAS_shv_vec 1 76 #define TCG_TARGET_HAS_mul_vec 1 77 #define TCG_TARGET_HAS_sat_vec 1 78 #define TCG_TARGET_HAS_minmax_vec 1 79 #define TCG_TARGET_HAS_bitsel_vec 0 80 #define TCG_TARGET_HAS_cmpsel_vec 1 81 82 #define TCG_TARGET_HAS_tst_vec 0 83 84 static inline bool 85 tcg_target_extract_valid(TCGType type, unsigned ofs, unsigned len) 86 { 87 if (type == TCG_TYPE_I64 && ofs + len == 32) { 88 /* ofs > 0 uses SRLIW; ofs == 0 uses add.uw. */ 89 return ofs || (cpuinfo & CPUINFO_ZBA); 90 } 91 switch (len) { 92 case 1: 93 return (cpuinfo & CPUINFO_ZBS) && ofs != 0; 94 case 16: 95 return (cpuinfo & CPUINFO_ZBB) && ofs == 0; 96 } 97 return false; 98 } 99 #define TCG_TARGET_extract_valid tcg_target_extract_valid 100 101 static inline bool 102 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 103 { 104 if (type == TCG_TYPE_I64 && ofs + len == 32) { 105 return true; 106 } 107 return (cpuinfo & CPUINFO_ZBB) && ofs == 0 && (len == 8 || len == 16); 108 } 109 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 110 111 #define TCG_TARGET_deposit_valid(type, ofs, len) 0 112 113 #endif 114