1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #ifndef PPC_TCG_TARGET_H 26 #define PPC_TCG_TARGET_H 27 28 #include "host/cpuinfo.h" 29 30 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) 31 32 #define TCG_TARGET_NB_REGS 64 33 #define TCG_TARGET_INSN_UNIT_SIZE 4 34 35 typedef enum { 36 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3, 37 TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7, 38 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11, 39 TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15, 40 TCG_REG_R16, TCG_REG_R17, TCG_REG_R18, TCG_REG_R19, 41 TCG_REG_R20, TCG_REG_R21, TCG_REG_R22, TCG_REG_R23, 42 TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27, 43 TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31, 44 45 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 46 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 47 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 48 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 49 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 50 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 51 TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27, 52 TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31, 53 54 TCG_REG_CALL_STACK = TCG_REG_R1, 55 TCG_AREG0 = TCG_REG_R27 56 } TCGReg; 57 58 typedef enum { 59 tcg_isa_base, 60 tcg_isa_2_06, 61 tcg_isa_2_07, 62 tcg_isa_3_00, 63 tcg_isa_3_10, 64 } TCGPowerISA; 65 66 #define have_isa_2_06 (cpuinfo & CPUINFO_V2_06) 67 #define have_isa_2_07 (cpuinfo & CPUINFO_V2_07) 68 #define have_isa_3_00 (cpuinfo & CPUINFO_V3_0) 69 #define have_isa_3_10 (cpuinfo & CPUINFO_V3_1) 70 #define have_altivec (cpuinfo & CPUINFO_ALTIVEC) 71 #define have_vsx (cpuinfo & CPUINFO_VSX) 72 73 /* optional instructions automatically implemented */ 74 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */ 75 #define TCG_TARGET_HAS_ext16u_i32 0 76 77 /* optional instructions */ 78 #define TCG_TARGET_HAS_div_i32 1 79 #define TCG_TARGET_HAS_rem_i32 have_isa_3_00 80 #define TCG_TARGET_HAS_rot_i32 1 81 #define TCG_TARGET_HAS_ext8s_i32 1 82 #define TCG_TARGET_HAS_ext16s_i32 1 83 #define TCG_TARGET_HAS_bswap16_i32 1 84 #define TCG_TARGET_HAS_bswap32_i32 1 85 #define TCG_TARGET_HAS_not_i32 1 86 #define TCG_TARGET_HAS_neg_i32 1 87 #define TCG_TARGET_HAS_andc_i32 1 88 #define TCG_TARGET_HAS_orc_i32 1 89 #define TCG_TARGET_HAS_eqv_i32 1 90 #define TCG_TARGET_HAS_nand_i32 1 91 #define TCG_TARGET_HAS_nor_i32 1 92 #define TCG_TARGET_HAS_clz_i32 1 93 #define TCG_TARGET_HAS_ctz_i32 have_isa_3_00 94 #define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06 95 #define TCG_TARGET_HAS_deposit_i32 1 96 #define TCG_TARGET_HAS_extract_i32 1 97 #define TCG_TARGET_HAS_sextract_i32 0 98 #define TCG_TARGET_HAS_extract2_i32 0 99 #define TCG_TARGET_HAS_movcond_i32 1 100 #define TCG_TARGET_HAS_negsetcond_i32 1 101 #define TCG_TARGET_HAS_mulu2_i32 0 102 #define TCG_TARGET_HAS_muls2_i32 0 103 #define TCG_TARGET_HAS_muluh_i32 1 104 #define TCG_TARGET_HAS_mulsh_i32 1 105 #define TCG_TARGET_HAS_qemu_st8_i32 0 106 107 #if TCG_TARGET_REG_BITS == 64 108 #define TCG_TARGET_HAS_add2_i32 0 109 #define TCG_TARGET_HAS_sub2_i32 0 110 #define TCG_TARGET_HAS_extr_i64_i32 0 111 #define TCG_TARGET_HAS_div_i64 1 112 #define TCG_TARGET_HAS_rem_i64 have_isa_3_00 113 #define TCG_TARGET_HAS_rot_i64 1 114 #define TCG_TARGET_HAS_ext8s_i64 1 115 #define TCG_TARGET_HAS_ext16s_i64 1 116 #define TCG_TARGET_HAS_ext32s_i64 1 117 #define TCG_TARGET_HAS_ext8u_i64 0 118 #define TCG_TARGET_HAS_ext16u_i64 0 119 #define TCG_TARGET_HAS_ext32u_i64 0 120 #define TCG_TARGET_HAS_bswap16_i64 1 121 #define TCG_TARGET_HAS_bswap32_i64 1 122 #define TCG_TARGET_HAS_bswap64_i64 1 123 #define TCG_TARGET_HAS_not_i64 1 124 #define TCG_TARGET_HAS_neg_i64 1 125 #define TCG_TARGET_HAS_andc_i64 1 126 #define TCG_TARGET_HAS_orc_i64 1 127 #define TCG_TARGET_HAS_eqv_i64 1 128 #define TCG_TARGET_HAS_nand_i64 1 129 #define TCG_TARGET_HAS_nor_i64 1 130 #define TCG_TARGET_HAS_clz_i64 1 131 #define TCG_TARGET_HAS_ctz_i64 have_isa_3_00 132 #define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06 133 #define TCG_TARGET_HAS_deposit_i64 1 134 #define TCG_TARGET_HAS_extract_i64 1 135 #define TCG_TARGET_HAS_sextract_i64 0 136 #define TCG_TARGET_HAS_extract2_i64 0 137 #define TCG_TARGET_HAS_movcond_i64 1 138 #define TCG_TARGET_HAS_negsetcond_i64 1 139 #define TCG_TARGET_HAS_add2_i64 1 140 #define TCG_TARGET_HAS_sub2_i64 1 141 #define TCG_TARGET_HAS_mulu2_i64 0 142 #define TCG_TARGET_HAS_muls2_i64 0 143 #define TCG_TARGET_HAS_muluh_i64 1 144 #define TCG_TARGET_HAS_mulsh_i64 1 145 #endif 146 147 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 148 (TCG_TARGET_REG_BITS == 64 && have_isa_2_07) 149 150 /* 151 * While technically Altivec could support V64, it has no 64-bit store 152 * instruction and substituting two 32-bit stores makes the generated 153 * code quite large. 154 */ 155 #define TCG_TARGET_HAS_v64 have_vsx 156 #define TCG_TARGET_HAS_v128 have_altivec 157 #define TCG_TARGET_HAS_v256 0 158 159 #define TCG_TARGET_HAS_andc_vec 1 160 #define TCG_TARGET_HAS_orc_vec have_isa_2_07 161 #define TCG_TARGET_HAS_nand_vec have_isa_2_07 162 #define TCG_TARGET_HAS_nor_vec 1 163 #define TCG_TARGET_HAS_eqv_vec have_isa_2_07 164 #define TCG_TARGET_HAS_not_vec 1 165 #define TCG_TARGET_HAS_neg_vec have_isa_3_00 166 #define TCG_TARGET_HAS_abs_vec 0 167 #define TCG_TARGET_HAS_roti_vec 0 168 #define TCG_TARGET_HAS_rots_vec 0 169 #define TCG_TARGET_HAS_rotv_vec 1 170 #define TCG_TARGET_HAS_shi_vec 0 171 #define TCG_TARGET_HAS_shs_vec 0 172 #define TCG_TARGET_HAS_shv_vec 1 173 #define TCG_TARGET_HAS_mul_vec 1 174 #define TCG_TARGET_HAS_sat_vec 1 175 #define TCG_TARGET_HAS_minmax_vec 1 176 #define TCG_TARGET_HAS_bitsel_vec have_vsx 177 #define TCG_TARGET_HAS_cmpsel_vec 0 178 179 #define TCG_TARGET_DEFAULT_MO (0) 180 #define TCG_TARGET_NEED_LDST_LABELS 181 #define TCG_TARGET_NEED_POOL_LABELS 182 183 #endif 184