1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26 27/* 28 * Standardize on the _CALL_FOO symbols used by GCC: 29 * Apple XCode does not define _CALL_DARWIN. 30 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV or _CALL_AIX. 31 */ 32#if TCG_TARGET_REG_BITS == 64 33# ifdef _CALL_AIX 34 /* ok */ 35# elif defined(_CALL_ELF) && _CALL_ELF == 1 36# define _CALL_AIX 37# elif defined(_CALL_ELF) && _CALL_ELF == 2 38 /* ok */ 39# else 40# error "Unknown ABI" 41# endif 42#else 43# if defined(_CALL_SYSV) || defined(_CALL_DARWIN) 44 /* ok */ 45# elif defined(__APPLE__) 46# define _CALL_DARWIN 47# elif defined(__ELF__) 48# define _CALL_SYSV 49# else 50# error "Unknown ABI" 51# endif 52#endif 53 54#if TCG_TARGET_REG_BITS == 64 55# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 56# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 57#else 58# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 59# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 60#endif 61#ifdef _CALL_SYSV 62# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 63# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 64#else 65# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 66# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 67#endif 68 69/* For some memory operations, we need a scratch that isn't R0. For the AIX 70 calling convention, we can re-use the TOC register since we'll be reloading 71 it at every call. Otherwise R12 will do nicely as neither a call-saved 72 register nor a parameter register. */ 73#ifdef _CALL_AIX 74# define TCG_REG_TMP1 TCG_REG_R2 75#else 76# define TCG_REG_TMP1 TCG_REG_R12 77#endif 78#define TCG_REG_TMP2 TCG_REG_R11 79 80#define TCG_VEC_TMP1 TCG_REG_V0 81#define TCG_VEC_TMP2 TCG_REG_V1 82 83#define TCG_REG_TB TCG_REG_R31 84#define USE_REG_TB (TCG_TARGET_REG_BITS == 64 && !have_isa_3_00) 85 86/* Shorthand for size of a pointer. Avoid promotion to unsigned. */ 87#define SZP ((int)sizeof(void *)) 88 89/* Shorthand for size of a register. */ 90#define SZR (TCG_TARGET_REG_BITS / 8) 91 92#define TCG_CT_CONST_S16 0x100 93#define TCG_CT_CONST_U16 0x200 94#define TCG_CT_CONST_S32 0x400 95#define TCG_CT_CONST_U32 0x800 96#define TCG_CT_CONST_ZERO 0x1000 97#define TCG_CT_CONST_MONE 0x2000 98#define TCG_CT_CONST_WSZ 0x4000 99#define TCG_CT_CONST_CMP 0x8000 100 101#define ALL_GENERAL_REGS 0xffffffffu 102#define ALL_VECTOR_REGS 0xffffffff00000000ull 103 104#ifndef R_PPC64_PCREL34 105#define R_PPC64_PCREL34 132 106#endif 107 108#define have_isel (cpuinfo & CPUINFO_ISEL) 109 110#define TCG_GUEST_BASE_REG TCG_REG_R30 111 112#ifdef CONFIG_DEBUG_TCG 113static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = { 114 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 115 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 116 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 117 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 118 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 119 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 120 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 121 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 122}; 123#endif 124 125static const int tcg_target_reg_alloc_order[] = { 126 TCG_REG_R14, /* call saved registers */ 127 TCG_REG_R15, 128 TCG_REG_R16, 129 TCG_REG_R17, 130 TCG_REG_R18, 131 TCG_REG_R19, 132 TCG_REG_R20, 133 TCG_REG_R21, 134 TCG_REG_R22, 135 TCG_REG_R23, 136 TCG_REG_R24, 137 TCG_REG_R25, 138 TCG_REG_R26, 139 TCG_REG_R27, 140 TCG_REG_R28, 141 TCG_REG_R29, 142 TCG_REG_R30, 143 TCG_REG_R31, 144 TCG_REG_R12, /* call clobbered, non-arguments */ 145 TCG_REG_R11, 146 TCG_REG_R2, 147 TCG_REG_R13, 148 TCG_REG_R10, /* call clobbered, arguments */ 149 TCG_REG_R9, 150 TCG_REG_R8, 151 TCG_REG_R7, 152 TCG_REG_R6, 153 TCG_REG_R5, 154 TCG_REG_R4, 155 TCG_REG_R3, 156 157 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ 158 TCG_REG_V2, /* call clobbered, vectors */ 159 TCG_REG_V3, 160 TCG_REG_V4, 161 TCG_REG_V5, 162 TCG_REG_V6, 163 TCG_REG_V7, 164 TCG_REG_V8, 165 TCG_REG_V9, 166 TCG_REG_V10, 167 TCG_REG_V11, 168 TCG_REG_V12, 169 TCG_REG_V13, 170 TCG_REG_V14, 171 TCG_REG_V15, 172 TCG_REG_V16, 173 TCG_REG_V17, 174 TCG_REG_V18, 175 TCG_REG_V19, 176}; 177 178static const int tcg_target_call_iarg_regs[] = { 179 TCG_REG_R3, 180 TCG_REG_R4, 181 TCG_REG_R5, 182 TCG_REG_R6, 183 TCG_REG_R7, 184 TCG_REG_R8, 185 TCG_REG_R9, 186 TCG_REG_R10 187}; 188 189static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 190{ 191 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 192 tcg_debug_assert(slot >= 0 && slot <= 1); 193 return TCG_REG_R3 + slot; 194} 195 196static const int tcg_target_callee_save_regs[] = { 197#ifdef _CALL_DARWIN 198 TCG_REG_R11, 199#endif 200 TCG_REG_R14, 201 TCG_REG_R15, 202 TCG_REG_R16, 203 TCG_REG_R17, 204 TCG_REG_R18, 205 TCG_REG_R19, 206 TCG_REG_R20, 207 TCG_REG_R21, 208 TCG_REG_R22, 209 TCG_REG_R23, 210 TCG_REG_R24, 211 TCG_REG_R25, 212 TCG_REG_R26, 213 TCG_REG_R27, /* currently used for the global env */ 214 TCG_REG_R28, 215 TCG_REG_R29, 216 TCG_REG_R30, 217 TCG_REG_R31 218}; 219 220/* For PPC, we use TB+4 instead of TB as the base. */ 221static inline ptrdiff_t ppc_tbrel_diff(TCGContext *s, const void *target) 222{ 223 return tcg_tbrel_diff(s, target) - 4; 224} 225 226static inline bool in_range_b(tcg_target_long target) 227{ 228 return target == sextract64(target, 0, 26); 229} 230 231static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, 232 const tcg_insn_unit *target) 233{ 234 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 235 tcg_debug_assert(in_range_b(disp)); 236 return disp & 0x3fffffc; 237} 238 239static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 240{ 241 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 242 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 243 244 if (in_range_b(disp)) { 245 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc); 246 return true; 247 } 248 return false; 249} 250 251static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, 252 const tcg_insn_unit *target) 253{ 254 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 255 tcg_debug_assert(disp == (int16_t) disp); 256 return disp & 0xfffc; 257} 258 259static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 260{ 261 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 262 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 263 264 if (disp == (int16_t) disp) { 265 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc); 266 return true; 267 } 268 return false; 269} 270 271static bool reloc_pc34(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 272{ 273 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 274 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 275 276 if (disp == sextract64(disp, 0, 34)) { 277 src_rw[0] = (src_rw[0] & ~0x3ffff) | ((disp >> 16) & 0x3ffff); 278 src_rw[1] = (src_rw[1] & ~0xffff) | (disp & 0xffff); 279 return true; 280 } 281 return false; 282} 283 284static bool mask_operand(uint32_t c, int *mb, int *me); 285static bool mask64_operand(uint64_t c, int *mb, int *me); 286 287/* test if a constant matches the constraint */ 288static bool tcg_target_const_match(int64_t sval, int ct, 289 TCGType type, TCGCond cond, int vece) 290{ 291 uint64_t uval = sval; 292 int mb, me; 293 294 if (ct & TCG_CT_CONST) { 295 return 1; 296 } 297 298 if (type == TCG_TYPE_I32) { 299 uval = (uint32_t)sval; 300 sval = (int32_t)sval; 301 } 302 303 if (ct & TCG_CT_CONST_CMP) { 304 switch (cond) { 305 case TCG_COND_EQ: 306 case TCG_COND_NE: 307 ct |= TCG_CT_CONST_S16 | TCG_CT_CONST_U16; 308 break; 309 case TCG_COND_LT: 310 case TCG_COND_GE: 311 case TCG_COND_LE: 312 case TCG_COND_GT: 313 ct |= TCG_CT_CONST_S16; 314 break; 315 case TCG_COND_LTU: 316 case TCG_COND_GEU: 317 case TCG_COND_LEU: 318 case TCG_COND_GTU: 319 ct |= TCG_CT_CONST_U16; 320 break; 321 case TCG_COND_TSTEQ: 322 case TCG_COND_TSTNE: 323 if ((uval & ~0xffff) == 0 || (uval & ~0xffff0000ull) == 0) { 324 return 1; 325 } 326 if (uval == (uint32_t)uval && mask_operand(uval, &mb, &me)) { 327 return 1; 328 } 329 if (TCG_TARGET_REG_BITS == 64 && 330 mask64_operand(uval << clz64(uval), &mb, &me)) { 331 return 1; 332 } 333 return 0; 334 default: 335 g_assert_not_reached(); 336 } 337 } 338 339 if ((ct & TCG_CT_CONST_S16) && sval == (int16_t)sval) { 340 return 1; 341 } 342 if ((ct & TCG_CT_CONST_U16) && uval == (uint16_t)uval) { 343 return 1; 344 } 345 if ((ct & TCG_CT_CONST_S32) && sval == (int32_t)sval) { 346 return 1; 347 } 348 if ((ct & TCG_CT_CONST_U32) && uval == (uint32_t)uval) { 349 return 1; 350 } 351 if ((ct & TCG_CT_CONST_ZERO) && sval == 0) { 352 return 1; 353 } 354 if ((ct & TCG_CT_CONST_MONE) && sval == -1) { 355 return 1; 356 } 357 if ((ct & TCG_CT_CONST_WSZ) && sval == (type == TCG_TYPE_I32 ? 32 : 64)) { 358 return 1; 359 } 360 return 0; 361} 362 363#define OPCD(opc) ((opc)<<26) 364#define XO19(opc) (OPCD(19)|((opc)<<1)) 365#define MD30(opc) (OPCD(30)|((opc)<<2)) 366#define MDS30(opc) (OPCD(30)|((opc)<<1)) 367#define XO31(opc) (OPCD(31)|((opc)<<1)) 368#define XO58(opc) (OPCD(58)|(opc)) 369#define XO62(opc) (OPCD(62)|(opc)) 370#define VX4(opc) (OPCD(4)|(opc)) 371 372#define B OPCD( 18) 373#define BC OPCD( 16) 374 375#define LBZ OPCD( 34) 376#define LHZ OPCD( 40) 377#define LHA OPCD( 42) 378#define LWZ OPCD( 32) 379#define LWZUX XO31( 55) 380#define LD XO58( 0) 381#define LDX XO31( 21) 382#define LDU XO58( 1) 383#define LDUX XO31( 53) 384#define LWA XO58( 2) 385#define LWAX XO31(341) 386#define LQ OPCD( 56) 387 388#define STB OPCD( 38) 389#define STH OPCD( 44) 390#define STW OPCD( 36) 391#define STD XO62( 0) 392#define STDU XO62( 1) 393#define STDX XO31(149) 394#define STQ XO62( 2) 395 396#define PLWA OPCD( 41) 397#define PLD OPCD( 57) 398#define PLXSD OPCD( 42) 399#define PLXV OPCD(25 * 2 + 1) /* force tx=1 */ 400 401#define PSTD OPCD( 61) 402#define PSTXSD OPCD( 46) 403#define PSTXV OPCD(27 * 2 + 1) /* force sx=1 */ 404 405#define ADDIC OPCD( 12) 406#define ADDI OPCD( 14) 407#define ADDIS OPCD( 15) 408#define ORI OPCD( 24) 409#define ORIS OPCD( 25) 410#define XORI OPCD( 26) 411#define XORIS OPCD( 27) 412#define ANDI OPCD( 28) 413#define ANDIS OPCD( 29) 414#define MULLI OPCD( 7) 415#define CMPLI OPCD( 10) 416#define CMPI OPCD( 11) 417#define SUBFIC OPCD( 8) 418 419#define LWZU OPCD( 33) 420#define STWU OPCD( 37) 421 422#define RLWIMI OPCD( 20) 423#define RLWINM OPCD( 21) 424#define RLWNM OPCD( 23) 425 426#define RLDICL MD30( 0) 427#define RLDICR MD30( 1) 428#define RLDIMI MD30( 3) 429#define RLDCL MDS30( 8) 430 431#define BCLR XO19( 16) 432#define BCCTR XO19(528) 433#define CRAND XO19(257) 434#define CRANDC XO19(129) 435#define CRNAND XO19(225) 436#define CROR XO19(449) 437#define CRNOR XO19( 33) 438#define ADDPCIS XO19( 2) 439 440#define EXTSB XO31(954) 441#define EXTSH XO31(922) 442#define EXTSW XO31(986) 443#define ADD XO31(266) 444#define ADDE XO31(138) 445#define ADDME XO31(234) 446#define ADDZE XO31(202) 447#define ADDC XO31( 10) 448#define AND XO31( 28) 449#define SUBF XO31( 40) 450#define SUBFC XO31( 8) 451#define SUBFE XO31(136) 452#define SUBFME XO31(232) 453#define SUBFZE XO31(200) 454#define OR XO31(444) 455#define XOR XO31(316) 456#define MULLW XO31(235) 457#define MULHW XO31( 75) 458#define MULHWU XO31( 11) 459#define DIVW XO31(491) 460#define DIVWU XO31(459) 461#define MODSW XO31(779) 462#define MODUW XO31(267) 463#define CMP XO31( 0) 464#define CMPL XO31( 32) 465#define LHBRX XO31(790) 466#define LWBRX XO31(534) 467#define LDBRX XO31(532) 468#define STHBRX XO31(918) 469#define STWBRX XO31(662) 470#define STDBRX XO31(660) 471#define MFSPR XO31(339) 472#define MTSPR XO31(467) 473#define SRAWI XO31(824) 474#define NEG XO31(104) 475#define MFCR XO31( 19) 476#define MFOCRF (MFCR | (1u << 20)) 477#define NOR XO31(124) 478#define CNTLZW XO31( 26) 479#define CNTLZD XO31( 58) 480#define CNTTZW XO31(538) 481#define CNTTZD XO31(570) 482#define CNTPOPW XO31(378) 483#define CNTPOPD XO31(506) 484#define ANDC XO31( 60) 485#define ORC XO31(412) 486#define EQV XO31(284) 487#define NAND XO31(476) 488#define ISEL XO31( 15) 489 490#define MULLD XO31(233) 491#define MULHD XO31( 73) 492#define MULHDU XO31( 9) 493#define DIVD XO31(489) 494#define DIVDU XO31(457) 495#define MODSD XO31(777) 496#define MODUD XO31(265) 497 498#define LBZX XO31( 87) 499#define LHZX XO31(279) 500#define LHAX XO31(343) 501#define LWZX XO31( 23) 502#define STBX XO31(215) 503#define STHX XO31(407) 504#define STWX XO31(151) 505 506#define EIEIO XO31(854) 507#define HWSYNC XO31(598) 508#define LWSYNC (HWSYNC | (1u << 21)) 509 510#define SPR(a, b) ((((a)<<5)|(b))<<11) 511#define LR SPR(8, 0) 512#define CTR SPR(9, 0) 513 514#define SLW XO31( 24) 515#define SRW XO31(536) 516#define SRAW XO31(792) 517 518#define SLD XO31( 27) 519#define SRD XO31(539) 520#define SRAD XO31(794) 521#define SRADI XO31(413<<1) 522 523#define BRH XO31(219) 524#define BRW XO31(155) 525#define BRD XO31(187) 526 527#define TW XO31( 4) 528#define TRAP (TW | TO(31)) 529 530#define SETBC XO31(384) /* v3.10 */ 531#define SETBCR XO31(416) /* v3.10 */ 532#define SETNBC XO31(448) /* v3.10 */ 533#define SETNBCR XO31(480) /* v3.10 */ 534 535#define NOP ORI /* ori 0,0,0 */ 536 537#define LVX XO31(103) 538#define LVEBX XO31(7) 539#define LVEHX XO31(39) 540#define LVEWX XO31(71) 541#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */ 542#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */ 543#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */ 544#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */ 545#define LXSD (OPCD(57) | 2) /* v3.00 */ 546#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */ 547 548#define STVX XO31(231) 549#define STVEWX XO31(199) 550#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */ 551#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */ 552#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */ 553#define STXSD (OPCD(61) | 2) /* v3.00 */ 554 555#define VADDSBS VX4(768) 556#define VADDUBS VX4(512) 557#define VADDUBM VX4(0) 558#define VADDSHS VX4(832) 559#define VADDUHS VX4(576) 560#define VADDUHM VX4(64) 561#define VADDSWS VX4(896) 562#define VADDUWS VX4(640) 563#define VADDUWM VX4(128) 564#define VADDUDM VX4(192) /* v2.07 */ 565 566#define VSUBSBS VX4(1792) 567#define VSUBUBS VX4(1536) 568#define VSUBUBM VX4(1024) 569#define VSUBSHS VX4(1856) 570#define VSUBUHS VX4(1600) 571#define VSUBUHM VX4(1088) 572#define VSUBSWS VX4(1920) 573#define VSUBUWS VX4(1664) 574#define VSUBUWM VX4(1152) 575#define VSUBUDM VX4(1216) /* v2.07 */ 576 577#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ 578#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ 579 580#define VMAXSB VX4(258) 581#define VMAXSH VX4(322) 582#define VMAXSW VX4(386) 583#define VMAXSD VX4(450) /* v2.07 */ 584#define VMAXUB VX4(2) 585#define VMAXUH VX4(66) 586#define VMAXUW VX4(130) 587#define VMAXUD VX4(194) /* v2.07 */ 588#define VMINSB VX4(770) 589#define VMINSH VX4(834) 590#define VMINSW VX4(898) 591#define VMINSD VX4(962) /* v2.07 */ 592#define VMINUB VX4(514) 593#define VMINUH VX4(578) 594#define VMINUW VX4(642) 595#define VMINUD VX4(706) /* v2.07 */ 596 597#define VCMPEQUB VX4(6) 598#define VCMPEQUH VX4(70) 599#define VCMPEQUW VX4(134) 600#define VCMPEQUD VX4(199) /* v2.07 */ 601#define VCMPGTSB VX4(774) 602#define VCMPGTSH VX4(838) 603#define VCMPGTSW VX4(902) 604#define VCMPGTSD VX4(967) /* v2.07 */ 605#define VCMPGTUB VX4(518) 606#define VCMPGTUH VX4(582) 607#define VCMPGTUW VX4(646) 608#define VCMPGTUD VX4(711) /* v2.07 */ 609#define VCMPNEB VX4(7) /* v3.00 */ 610#define VCMPNEH VX4(71) /* v3.00 */ 611#define VCMPNEW VX4(135) /* v3.00 */ 612 613#define VSLB VX4(260) 614#define VSLH VX4(324) 615#define VSLW VX4(388) 616#define VSLD VX4(1476) /* v2.07 */ 617#define VSRB VX4(516) 618#define VSRH VX4(580) 619#define VSRW VX4(644) 620#define VSRD VX4(1732) /* v2.07 */ 621#define VSRAB VX4(772) 622#define VSRAH VX4(836) 623#define VSRAW VX4(900) 624#define VSRAD VX4(964) /* v2.07 */ 625#define VRLB VX4(4) 626#define VRLH VX4(68) 627#define VRLW VX4(132) 628#define VRLD VX4(196) /* v2.07 */ 629 630#define VMULEUB VX4(520) 631#define VMULEUH VX4(584) 632#define VMULEUW VX4(648) /* v2.07 */ 633#define VMULOUB VX4(8) 634#define VMULOUH VX4(72) 635#define VMULOUW VX4(136) /* v2.07 */ 636#define VMULUWM VX4(137) /* v2.07 */ 637#define VMULLD VX4(457) /* v3.10 */ 638#define VMSUMUHM VX4(38) 639 640#define VMRGHB VX4(12) 641#define VMRGHH VX4(76) 642#define VMRGHW VX4(140) 643#define VMRGLB VX4(268) 644#define VMRGLH VX4(332) 645#define VMRGLW VX4(396) 646 647#define VPKUHUM VX4(14) 648#define VPKUWUM VX4(78) 649 650#define VAND VX4(1028) 651#define VANDC VX4(1092) 652#define VNOR VX4(1284) 653#define VOR VX4(1156) 654#define VXOR VX4(1220) 655#define VEQV VX4(1668) /* v2.07 */ 656#define VNAND VX4(1412) /* v2.07 */ 657#define VORC VX4(1348) /* v2.07 */ 658 659#define VSPLTB VX4(524) 660#define VSPLTH VX4(588) 661#define VSPLTW VX4(652) 662#define VSPLTISB VX4(780) 663#define VSPLTISH VX4(844) 664#define VSPLTISW VX4(908) 665 666#define VSLDOI VX4(44) 667 668#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */ 669#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */ 670#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */ 671 672#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */ 673#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */ 674#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */ 675#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */ 676#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */ 677#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */ 678 679#define RT(r) ((r)<<21) 680#define RS(r) ((r)<<21) 681#define RA(r) ((r)<<16) 682#define RB(r) ((r)<<11) 683#define TO(t) ((t)<<21) 684#define SH(s) ((s)<<11) 685#define MB(b) ((b)<<6) 686#define ME(e) ((e)<<1) 687#define BO(o) ((o)<<21) 688#define MB64(b) ((b)<<5) 689#define FXM(b) (1 << (19 - (b))) 690 691#define VRT(r) (((r) & 31) << 21) 692#define VRA(r) (((r) & 31) << 16) 693#define VRB(r) (((r) & 31) << 11) 694#define VRC(r) (((r) & 31) << 6) 695 696#define LK 1 697 698#define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) 699#define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) 700#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) 701#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) 702 703#define BF(n) ((n)<<23) 704#define BI(n, c) (((c)+((n)*4))<<16) 705#define BT(n, c) (((c)+((n)*4))<<21) 706#define BA(n, c) (((c)+((n)*4))<<16) 707#define BB(n, c) (((c)+((n)*4))<<11) 708#define BC_(n, c) (((c)+((n)*4))<<6) 709 710#define BO_COND_TRUE BO(12) 711#define BO_COND_FALSE BO( 4) 712#define BO_ALWAYS BO(20) 713 714enum { 715 CR_LT, 716 CR_GT, 717 CR_EQ, 718 CR_SO 719}; 720 721static const uint32_t tcg_to_bc[16] = { 722 [TCG_COND_EQ] = BC | BI(0, CR_EQ) | BO_COND_TRUE, 723 [TCG_COND_NE] = BC | BI(0, CR_EQ) | BO_COND_FALSE, 724 [TCG_COND_TSTEQ] = BC | BI(0, CR_EQ) | BO_COND_TRUE, 725 [TCG_COND_TSTNE] = BC | BI(0, CR_EQ) | BO_COND_FALSE, 726 [TCG_COND_LT] = BC | BI(0, CR_LT) | BO_COND_TRUE, 727 [TCG_COND_GE] = BC | BI(0, CR_LT) | BO_COND_FALSE, 728 [TCG_COND_LE] = BC | BI(0, CR_GT) | BO_COND_FALSE, 729 [TCG_COND_GT] = BC | BI(0, CR_GT) | BO_COND_TRUE, 730 [TCG_COND_LTU] = BC | BI(0, CR_LT) | BO_COND_TRUE, 731 [TCG_COND_GEU] = BC | BI(0, CR_LT) | BO_COND_FALSE, 732 [TCG_COND_LEU] = BC | BI(0, CR_GT) | BO_COND_FALSE, 733 [TCG_COND_GTU] = BC | BI(0, CR_GT) | BO_COND_TRUE, 734}; 735 736/* The low bit here is set if the RA and RB fields must be inverted. */ 737static const uint32_t tcg_to_isel[16] = { 738 [TCG_COND_EQ] = ISEL | BC_(0, CR_EQ), 739 [TCG_COND_NE] = ISEL | BC_(0, CR_EQ) | 1, 740 [TCG_COND_TSTEQ] = ISEL | BC_(0, CR_EQ), 741 [TCG_COND_TSTNE] = ISEL | BC_(0, CR_EQ) | 1, 742 [TCG_COND_LT] = ISEL | BC_(0, CR_LT), 743 [TCG_COND_GE] = ISEL | BC_(0, CR_LT) | 1, 744 [TCG_COND_LE] = ISEL | BC_(0, CR_GT) | 1, 745 [TCG_COND_GT] = ISEL | BC_(0, CR_GT), 746 [TCG_COND_LTU] = ISEL | BC_(0, CR_LT), 747 [TCG_COND_GEU] = ISEL | BC_(0, CR_LT) | 1, 748 [TCG_COND_LEU] = ISEL | BC_(0, CR_GT) | 1, 749 [TCG_COND_GTU] = ISEL | BC_(0, CR_GT), 750}; 751 752static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 753 intptr_t value, intptr_t addend) 754{ 755 const tcg_insn_unit *target; 756 int16_t lo; 757 int32_t hi; 758 759 value += addend; 760 target = (const tcg_insn_unit *)value; 761 762 switch (type) { 763 case R_PPC_REL14: 764 return reloc_pc14(code_ptr, target); 765 case R_PPC_REL24: 766 return reloc_pc24(code_ptr, target); 767 case R_PPC64_PCREL34: 768 return reloc_pc34(code_ptr, target); 769 case R_PPC_ADDR16: 770 /* 771 * We are (slightly) abusing this relocation type. In particular, 772 * assert that the low 2 bits are zero, and do not modify them. 773 * That way we can use this with LD et al that have opcode bits 774 * in the low 2 bits of the insn. 775 */ 776 if ((value & 3) || value != (int16_t)value) { 777 return false; 778 } 779 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc); 780 break; 781 case R_PPC_ADDR32: 782 /* 783 * We are abusing this relocation type. Again, this points to 784 * a pair of insns, lis + load. This is an absolute address 785 * relocation for PPC32 so the lis cannot be removed. 786 */ 787 lo = value; 788 hi = value - lo; 789 if (hi + lo != value) { 790 return false; 791 } 792 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); 793 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); 794 break; 795 default: 796 g_assert_not_reached(); 797 } 798 return true; 799} 800 801/* Ensure that the prefixed instruction does not cross a 64-byte boundary. */ 802static bool tcg_out_need_prefix_align(TCGContext *s) 803{ 804 return ((uintptr_t)s->code_ptr & 0x3f) == 0x3c; 805} 806 807static void tcg_out_prefix_align(TCGContext *s) 808{ 809 if (tcg_out_need_prefix_align(s)) { 810 tcg_out32(s, NOP); 811 } 812} 813 814static ptrdiff_t tcg_pcrel_diff_for_prefix(TCGContext *s, const void *target) 815{ 816 return tcg_pcrel_diff(s, target) - (tcg_out_need_prefix_align(s) ? 4 : 0); 817} 818 819/* Output Type 00 Prefix - 8-Byte Load/Store Form (8LS:D) */ 820static void tcg_out_8ls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, 821 unsigned ra, tcg_target_long imm, bool r) 822{ 823 tcg_insn_unit p, i; 824 825 p = OPCD(1) | (r << 20) | ((imm >> 16) & 0x3ffff); 826 i = opc | TAI(rt, ra, imm); 827 828 tcg_out_prefix_align(s); 829 tcg_out32(s, p); 830 tcg_out32(s, i); 831} 832 833/* Output Type 10 Prefix - Modified Load/Store Form (MLS:D) */ 834static void tcg_out_mls_d(TCGContext *s, tcg_insn_unit opc, unsigned rt, 835 unsigned ra, tcg_target_long imm, bool r) 836{ 837 tcg_insn_unit p, i; 838 839 p = OPCD(1) | (2 << 24) | (r << 20) | ((imm >> 16) & 0x3ffff); 840 i = opc | TAI(rt, ra, imm); 841 842 tcg_out_prefix_align(s); 843 tcg_out32(s, p); 844 tcg_out32(s, i); 845} 846 847static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 848 TCGReg base, tcg_target_long offset); 849 850static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 851{ 852 if (ret == arg) { 853 return true; 854 } 855 switch (type) { 856 case TCG_TYPE_I64: 857 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 858 /* fallthru */ 859 case TCG_TYPE_I32: 860 if (ret < TCG_REG_V0) { 861 if (arg < TCG_REG_V0) { 862 tcg_out32(s, OR | SAB(arg, ret, arg)); 863 break; 864 } else if (have_isa_2_07) { 865 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) 866 | VRT(arg) | RA(ret)); 867 break; 868 } else { 869 /* Altivec does not support vector->integer moves. */ 870 return false; 871 } 872 } else if (arg < TCG_REG_V0) { 873 if (have_isa_2_07) { 874 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) 875 | VRT(ret) | RA(arg)); 876 break; 877 } else { 878 /* Altivec does not support integer->vector moves. */ 879 return false; 880 } 881 } 882 /* fallthru */ 883 case TCG_TYPE_V64: 884 case TCG_TYPE_V128: 885 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0); 886 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); 887 break; 888 default: 889 g_assert_not_reached(); 890 } 891 return true; 892} 893 894static void tcg_out_rld_rc(TCGContext *s, int op, TCGReg ra, TCGReg rs, 895 int sh, int mb, bool rc) 896{ 897 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 898 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); 899 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); 900 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb | rc); 901} 902 903static void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, 904 int sh, int mb) 905{ 906 tcg_out_rld_rc(s, op, ra, rs, sh, mb, false); 907} 908 909static void tcg_out_rlw_rc(TCGContext *s, int op, TCGReg ra, TCGReg rs, 910 int sh, int mb, int me, bool rc) 911{ 912 tcg_debug_assert((mb & 0x1f) == mb); 913 tcg_debug_assert((me & 0x1f) == me); 914 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh & 0x1f) | MB(mb) | ME(me) | rc); 915} 916 917static void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, 918 int sh, int mb, int me) 919{ 920 tcg_out_rlw_rc(s, op, ra, rs, sh, mb, me, false); 921} 922 923static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 924{ 925 tcg_out32(s, EXTSB | RA(dst) | RS(src)); 926} 927 928static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src) 929{ 930 tcg_out32(s, ANDI | SAI(src, dst, 0xff)); 931} 932 933static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 934{ 935 tcg_out32(s, EXTSH | RA(dst) | RS(src)); 936} 937 938static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src) 939{ 940 tcg_out32(s, ANDI | SAI(src, dst, 0xffff)); 941} 942 943static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) 944{ 945 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 946 tcg_out32(s, EXTSW | RA(dst) | RS(src)); 947} 948 949static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) 950{ 951 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 952 tcg_out_rld(s, RLDICL, dst, src, 0, 32); 953} 954 955static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 956{ 957 tcg_out_ext32s(s, dst, src); 958} 959 960static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 961{ 962 tcg_out_ext32u(s, dst, src); 963} 964 965static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 966{ 967 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 968 tcg_out_mov(s, TCG_TYPE_I32, rd, rn); 969} 970 971static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) 972{ 973 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); 974} 975 976static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) 977{ 978 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); 979} 980 981static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c) 982{ 983 /* Limit immediate shift count lest we create an illegal insn. */ 984 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31)); 985} 986 987static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) 988{ 989 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); 990} 991 992static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) 993{ 994 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); 995} 996 997static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c) 998{ 999 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2)); 1000} 1001 1002static void tcg_out_addpcis(TCGContext *s, TCGReg dst, intptr_t imm) 1003{ 1004 uint32_t d0, d1, d2; 1005 1006 tcg_debug_assert((imm & 0xffff) == 0); 1007 tcg_debug_assert(imm == (int32_t)imm); 1008 1009 d2 = extract32(imm, 16, 1); 1010 d1 = extract32(imm, 17, 5); 1011 d0 = extract32(imm, 22, 10); 1012 tcg_out32(s, ADDPCIS | RT(dst) | (d1 << 16) | (d0 << 6) | d2); 1013} 1014 1015static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags) 1016{ 1017 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 1018 1019 if (have_isa_3_10) { 1020 tcg_out32(s, BRH | RA(dst) | RS(src)); 1021 if (flags & TCG_BSWAP_OS) { 1022 tcg_out_ext16s(s, TCG_TYPE_REG, dst, dst); 1023 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1024 tcg_out_ext16u(s, dst, dst); 1025 } 1026 return; 1027 } 1028 1029 /* 1030 * In the following, 1031 * dep(a, b, m) -> (a & ~m) | (b & m) 1032 * 1033 * Begin with: src = xxxxabcd 1034 */ 1035 /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */ 1036 tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31); 1037 /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */ 1038 tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23); 1039 1040 if (flags & TCG_BSWAP_OS) { 1041 tcg_out_ext16s(s, TCG_TYPE_REG, dst, tmp); 1042 } else { 1043 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 1044 } 1045} 1046 1047static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags) 1048{ 1049 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 1050 1051 if (have_isa_3_10) { 1052 tcg_out32(s, BRW | RA(dst) | RS(src)); 1053 if (flags & TCG_BSWAP_OS) { 1054 tcg_out_ext32s(s, dst, dst); 1055 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1056 tcg_out_ext32u(s, dst, dst); 1057 } 1058 return; 1059 } 1060 1061 /* 1062 * Stolen from gcc's builtin_bswap32. 1063 * In the following, 1064 * dep(a, b, m) -> (a & ~m) | (b & m) 1065 * 1066 * Begin with: src = xxxxabcd 1067 */ 1068 /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */ 1069 tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31); 1070 /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */ 1071 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7); 1072 /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */ 1073 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23); 1074 1075 if (flags & TCG_BSWAP_OS) { 1076 tcg_out_ext32s(s, dst, tmp); 1077 } else { 1078 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 1079 } 1080} 1081 1082static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src) 1083{ 1084 TCGReg t0 = dst == src ? TCG_REG_R0 : dst; 1085 TCGReg t1 = dst == src ? dst : TCG_REG_R0; 1086 1087 if (have_isa_3_10) { 1088 tcg_out32(s, BRD | RA(dst) | RS(src)); 1089 return; 1090 } 1091 1092 /* 1093 * In the following, 1094 * dep(a, b, m) -> (a & ~m) | (b & m) 1095 * 1096 * Begin with: src = abcdefgh 1097 */ 1098 /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */ 1099 tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31); 1100 /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */ 1101 tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7); 1102 /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */ 1103 tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23); 1104 1105 /* t0 = rol64(t0, 32) = hgfe0000 */ 1106 tcg_out_rld(s, RLDICL, t0, t0, 32, 0); 1107 /* t1 = rol64(src, 32) = efghabcd */ 1108 tcg_out_rld(s, RLDICL, t1, src, 32, 0); 1109 1110 /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */ 1111 tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31); 1112 /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */ 1113 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7); 1114 /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */ 1115 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23); 1116 1117 tcg_out_mov(s, TCG_TYPE_REG, dst, t0); 1118} 1119 1120/* Emit a move into ret of arg, if it can be done in one insn. */ 1121static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 1122{ 1123 if (arg == (int16_t)arg) { 1124 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1125 return true; 1126 } 1127 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 1128 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 1129 return true; 1130 } 1131 return false; 1132} 1133 1134static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 1135 tcg_target_long arg, bool in_prologue) 1136{ 1137 intptr_t tb_diff; 1138 tcg_target_long tmp; 1139 int shift; 1140 1141 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1142 1143 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1144 arg = (int32_t)arg; 1145 } 1146 1147 /* Load 16-bit immediates with one insn. */ 1148 if (tcg_out_movi_one(s, ret, arg)) { 1149 return; 1150 } 1151 1152 /* Load addresses within the TB with one insn. */ 1153 tb_diff = ppc_tbrel_diff(s, (void *)arg); 1154 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { 1155 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); 1156 return; 1157 } 1158 1159 /* 1160 * Load values up to 34 bits, and pc-relative addresses, 1161 * with one prefixed insn. 1162 */ 1163 if (have_isa_3_10) { 1164 if (arg == sextract64(arg, 0, 34)) { 1165 /* pli ret,value = paddi ret,0,value,0 */ 1166 tcg_out_mls_d(s, ADDI, ret, 0, arg, 0); 1167 return; 1168 } 1169 1170 tmp = tcg_pcrel_diff_for_prefix(s, (void *)arg); 1171 if (tmp == sextract64(tmp, 0, 34)) { 1172 /* pla ret,value = paddi ret,0,value,1 */ 1173 tcg_out_mls_d(s, ADDI, ret, 0, tmp, 1); 1174 return; 1175 } 1176 } 1177 1178 /* Load 32-bit immediates with two insns. Note that we've already 1179 eliminated bare ADDIS, so we know both insns are required. */ 1180 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 1181 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 1182 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1183 return; 1184 } 1185 if (arg == (uint32_t)arg && !(arg & 0x8000)) { 1186 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1187 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1188 return; 1189 } 1190 1191 /* Load masked 16-bit value. */ 1192 if (arg > 0 && (arg & 0x8000)) { 1193 tmp = arg | 0x7fff; 1194 if ((tmp & (tmp + 1)) == 0) { 1195 int mb = clz64(tmp + 1) + 1; 1196 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1197 tcg_out_rld(s, RLDICL, ret, ret, 0, mb); 1198 return; 1199 } 1200 } 1201 1202 /* Load common masks with 2 insns. */ 1203 shift = ctz64(arg); 1204 tmp = arg >> shift; 1205 if (tmp == (int16_t)tmp) { 1206 tcg_out32(s, ADDI | TAI(ret, 0, tmp)); 1207 tcg_out_shli64(s, ret, ret, shift); 1208 return; 1209 } 1210 shift = clz64(arg); 1211 if (tcg_out_movi_one(s, ret, arg << shift)) { 1212 tcg_out_shri64(s, ret, ret, shift); 1213 return; 1214 } 1215 1216 /* Load addresses within 2GB with 2 insns. */ 1217 if (have_isa_3_00) { 1218 intptr_t hi = tcg_pcrel_diff(s, (void *)arg) - 4; 1219 int16_t lo = hi; 1220 1221 hi -= lo; 1222 if (hi == (int32_t)hi) { 1223 tcg_out_addpcis(s, TCG_REG_TMP2, hi); 1224 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TMP2, lo)); 1225 return; 1226 } 1227 } 1228 1229 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ 1230 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { 1231 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); 1232 return; 1233 } 1234 1235 /* Use the constant pool, if possible. */ 1236 if (!in_prologue && USE_REG_TB) { 1237 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, 1238 ppc_tbrel_diff(s, NULL)); 1239 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); 1240 return; 1241 } 1242 if (have_isa_3_10) { 1243 tcg_out_8ls_d(s, PLD, ret, 0, 0, 1); 1244 new_pool_label(s, arg, R_PPC64_PCREL34, s->code_ptr - 2, 0); 1245 return; 1246 } 1247 if (have_isa_3_00) { 1248 tcg_out_addpcis(s, TCG_REG_TMP2, 0); 1249 new_pool_label(s, arg, R_PPC_REL14, s->code_ptr, 0); 1250 tcg_out32(s, LD | TAI(ret, TCG_REG_TMP2, 0)); 1251 return; 1252 } 1253 1254 tmp = arg >> 31 >> 1; 1255 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); 1256 if (tmp) { 1257 tcg_out_shli64(s, ret, ret, 32); 1258 } 1259 if (arg & 0xffff0000) { 1260 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1261 } 1262 if (arg & 0xffff) { 1263 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1264 } 1265} 1266 1267static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1268 TCGReg ret, int64_t val) 1269{ 1270 uint32_t load_insn; 1271 int rel, low; 1272 intptr_t add; 1273 1274 switch (vece) { 1275 case MO_8: 1276 low = (int8_t)val; 1277 if (low >= -16 && low < 16) { 1278 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); 1279 return; 1280 } 1281 if (have_isa_3_00) { 1282 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); 1283 return; 1284 } 1285 break; 1286 1287 case MO_16: 1288 low = (int16_t)val; 1289 if (low >= -16 && low < 16) { 1290 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); 1291 return; 1292 } 1293 break; 1294 1295 case MO_32: 1296 low = (int32_t)val; 1297 if (low >= -16 && low < 16) { 1298 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); 1299 return; 1300 } 1301 break; 1302 } 1303 1304 /* 1305 * Otherwise we must load the value from the constant pool. 1306 */ 1307 if (USE_REG_TB) { 1308 rel = R_PPC_ADDR16; 1309 add = ppc_tbrel_diff(s, NULL); 1310 } else if (have_isa_3_10) { 1311 if (type == TCG_TYPE_V64) { 1312 tcg_out_8ls_d(s, PLXSD, ret & 31, 0, 0, 1); 1313 new_pool_label(s, val, R_PPC64_PCREL34, s->code_ptr - 2, 0); 1314 } else { 1315 tcg_out_8ls_d(s, PLXV, ret & 31, 0, 0, 1); 1316 new_pool_l2(s, R_PPC64_PCREL34, s->code_ptr - 2, 0, val, val); 1317 } 1318 return; 1319 } else if (have_isa_3_00) { 1320 tcg_out_addpcis(s, TCG_REG_TMP1, 0); 1321 rel = R_PPC_REL14; 1322 add = 0; 1323 } else { 1324 rel = R_PPC_ADDR32; 1325 add = 0; 1326 } 1327 1328 if (have_vsx) { 1329 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX; 1330 load_insn |= VRT(ret) | RB(TCG_REG_TMP1); 1331 if (TCG_TARGET_REG_BITS == 64) { 1332 new_pool_label(s, val, rel, s->code_ptr, add); 1333 } else { 1334 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); 1335 } 1336 } else { 1337 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); 1338 if (TCG_TARGET_REG_BITS == 64) { 1339 new_pool_l2(s, rel, s->code_ptr, add, val, val); 1340 } else { 1341 new_pool_l4(s, rel, s->code_ptr, add, 1342 val >> 32, val, val >> 32, val); 1343 } 1344 } 1345 1346 if (USE_REG_TB) { 1347 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); 1348 load_insn |= RA(TCG_REG_TB); 1349 } else if (have_isa_3_00) { 1350 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); 1351 } else { 1352 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); 1353 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); 1354 } 1355 tcg_out32(s, load_insn); 1356} 1357 1358static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, 1359 tcg_target_long arg) 1360{ 1361 switch (type) { 1362 case TCG_TYPE_I32: 1363 case TCG_TYPE_I64: 1364 tcg_debug_assert(ret < TCG_REG_V0); 1365 tcg_out_movi_int(s, type, ret, arg, false); 1366 break; 1367 1368 default: 1369 g_assert_not_reached(); 1370 } 1371} 1372 1373static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1374{ 1375 return false; 1376} 1377 1378static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1379 tcg_target_long imm) 1380{ 1381 /* This function is only used for passing structs by reference. */ 1382 g_assert_not_reached(); 1383} 1384 1385static bool mask_operand(uint32_t c, int *mb, int *me) 1386{ 1387 uint32_t lsb, test; 1388 1389 /* Accept a bit pattern like: 1390 0....01....1 1391 1....10....0 1392 0..01..10..0 1393 Keep track of the transitions. */ 1394 if (c == 0 || c == -1) { 1395 return false; 1396 } 1397 test = c; 1398 lsb = test & -test; 1399 test += lsb; 1400 if (test & (test - 1)) { 1401 return false; 1402 } 1403 1404 *me = clz32(lsb); 1405 *mb = test ? clz32(test & -test) + 1 : 0; 1406 return true; 1407} 1408 1409static bool mask64_operand(uint64_t c, int *mb, int *me) 1410{ 1411 uint64_t lsb; 1412 1413 if (c == 0) { 1414 return false; 1415 } 1416 1417 lsb = c & -c; 1418 /* Accept 1..10..0. */ 1419 if (c == -lsb) { 1420 *mb = 0; 1421 *me = clz64(lsb); 1422 return true; 1423 } 1424 /* Accept 0..01..1. */ 1425 if (lsb == 1 && (c & (c + 1)) == 0) { 1426 *mb = clz64(c + 1) + 1; 1427 *me = 63; 1428 return true; 1429 } 1430 return false; 1431} 1432 1433static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1434{ 1435 int mb, me; 1436 1437 if (mask_operand(c, &mb, &me)) { 1438 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); 1439 } else if ((c & 0xffff) == c) { 1440 tcg_out32(s, ANDI | SAI(src, dst, c)); 1441 return; 1442 } else if ((c & 0xffff0000) == c) { 1443 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1444 return; 1445 } else { 1446 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); 1447 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1448 } 1449} 1450 1451static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) 1452{ 1453 int mb, me; 1454 1455 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1456 if (mask64_operand(c, &mb, &me)) { 1457 if (mb == 0) { 1458 tcg_out_rld(s, RLDICR, dst, src, 0, me); 1459 } else { 1460 tcg_out_rld(s, RLDICL, dst, src, 0, mb); 1461 } 1462 } else if ((c & 0xffff) == c) { 1463 tcg_out32(s, ANDI | SAI(src, dst, c)); 1464 return; 1465 } else if ((c & 0xffff0000) == c) { 1466 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1467 return; 1468 } else { 1469 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); 1470 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1471 } 1472} 1473 1474static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, 1475 int op_lo, int op_hi) 1476{ 1477 if (c >> 16) { 1478 tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); 1479 src = dst; 1480 } 1481 if (c & 0xffff) { 1482 tcg_out32(s, op_lo | SAI(src, dst, c)); 1483 src = dst; 1484 } 1485} 1486 1487static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1488{ 1489 tcg_out_zori32(s, dst, src, c, ORI, ORIS); 1490} 1491 1492static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1493{ 1494 tcg_out_zori32(s, dst, src, c, XORI, XORIS); 1495} 1496 1497static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) 1498{ 1499 ptrdiff_t disp = tcg_pcrel_diff(s, target); 1500 if (in_range_b(disp)) { 1501 tcg_out32(s, B | (disp & 0x3fffffc) | mask); 1502 } else { 1503 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); 1504 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); 1505 tcg_out32(s, BCCTR | BO_ALWAYS | mask); 1506 } 1507} 1508 1509static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 1510 TCGReg base, tcg_target_long offset) 1511{ 1512 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; 1513 bool is_int_store = false; 1514 TCGReg rs = TCG_REG_TMP1; 1515 1516 switch (opi) { 1517 case LD: case LWA: 1518 align = 3; 1519 /* FALLTHRU */ 1520 default: 1521 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { 1522 rs = rt; 1523 break; 1524 } 1525 break; 1526 case LXSD: 1527 case STXSD: 1528 align = 3; 1529 break; 1530 case LXV: 1531 case STXV: 1532 align = 15; 1533 break; 1534 case STD: 1535 align = 3; 1536 /* FALLTHRU */ 1537 case STB: case STH: case STW: 1538 is_int_store = true; 1539 break; 1540 } 1541 1542 /* For unaligned or large offsets, use the prefixed form. */ 1543 if (have_isa_3_10 1544 && (offset != (int16_t)offset || (offset & align)) 1545 && offset == sextract64(offset, 0, 34)) { 1546 /* 1547 * Note that the MLS:D insns retain their un-prefixed opcode, 1548 * while the 8LS:D insns use a different opcode space. 1549 */ 1550 switch (opi) { 1551 case LBZ: 1552 case LHZ: 1553 case LHA: 1554 case LWZ: 1555 case STB: 1556 case STH: 1557 case STW: 1558 case ADDI: 1559 tcg_out_mls_d(s, opi, rt, base, offset, 0); 1560 return; 1561 case LWA: 1562 tcg_out_8ls_d(s, PLWA, rt, base, offset, 0); 1563 return; 1564 case LD: 1565 tcg_out_8ls_d(s, PLD, rt, base, offset, 0); 1566 return; 1567 case STD: 1568 tcg_out_8ls_d(s, PSTD, rt, base, offset, 0); 1569 return; 1570 case LXSD: 1571 tcg_out_8ls_d(s, PLXSD, rt & 31, base, offset, 0); 1572 return; 1573 case STXSD: 1574 tcg_out_8ls_d(s, PSTXSD, rt & 31, base, offset, 0); 1575 return; 1576 case LXV: 1577 tcg_out_8ls_d(s, PLXV, rt & 31, base, offset, 0); 1578 return; 1579 case STXV: 1580 tcg_out_8ls_d(s, PSTXV, rt & 31, base, offset, 0); 1581 return; 1582 } 1583 } 1584 1585 /* For unaligned, or very large offsets, use the indexed form. */ 1586 if (offset & align || offset != (int32_t)offset || opi == 0) { 1587 if (rs == base) { 1588 rs = TCG_REG_R0; 1589 } 1590 tcg_debug_assert(!is_int_store || rs != rt); 1591 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); 1592 tcg_out32(s, opx | TAB(rt & 31, base, rs)); 1593 return; 1594 } 1595 1596 l0 = (int16_t)offset; 1597 offset = (offset - l0) >> 16; 1598 l1 = (int16_t)offset; 1599 1600 if (l1 < 0 && orig >= 0) { 1601 extra = 0x4000; 1602 l1 = (int16_t)(offset - 0x4000); 1603 } 1604 if (l1) { 1605 tcg_out32(s, ADDIS | TAI(rs, base, l1)); 1606 base = rs; 1607 } 1608 if (extra) { 1609 tcg_out32(s, ADDIS | TAI(rs, base, extra)); 1610 base = rs; 1611 } 1612 if (opi != ADDI || base != rt || l0 != 0) { 1613 tcg_out32(s, opi | TAI(rt & 31, base, l0)); 1614 } 1615} 1616 1617static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, 1618 TCGReg va, TCGReg vb, int shb) 1619{ 1620 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); 1621} 1622 1623static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1624 TCGReg base, intptr_t offset) 1625{ 1626 int shift; 1627 1628 switch (type) { 1629 case TCG_TYPE_I32: 1630 if (ret < TCG_REG_V0) { 1631 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); 1632 break; 1633 } 1634 if (have_isa_2_07 && have_vsx) { 1635 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); 1636 break; 1637 } 1638 tcg_debug_assert((offset & 3) == 0); 1639 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); 1640 shift = (offset - 4) & 0xc; 1641 if (shift) { 1642 tcg_out_vsldoi(s, ret, ret, ret, shift); 1643 } 1644 break; 1645 case TCG_TYPE_I64: 1646 if (ret < TCG_REG_V0) { 1647 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1648 tcg_out_mem_long(s, LD, LDX, ret, base, offset); 1649 break; 1650 } 1651 /* fallthru */ 1652 case TCG_TYPE_V64: 1653 tcg_debug_assert(ret >= TCG_REG_V0); 1654 if (have_vsx) { 1655 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, 1656 ret, base, offset); 1657 break; 1658 } 1659 tcg_debug_assert((offset & 7) == 0); 1660 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); 1661 if (offset & 8) { 1662 tcg_out_vsldoi(s, ret, ret, ret, 8); 1663 } 1664 break; 1665 case TCG_TYPE_V128: 1666 tcg_debug_assert(ret >= TCG_REG_V0); 1667 tcg_debug_assert((offset & 15) == 0); 1668 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, 1669 LVX, ret, base, offset); 1670 break; 1671 default: 1672 g_assert_not_reached(); 1673 } 1674} 1675 1676static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1677 TCGReg base, intptr_t offset) 1678{ 1679 int shift; 1680 1681 switch (type) { 1682 case TCG_TYPE_I32: 1683 if (arg < TCG_REG_V0) { 1684 tcg_out_mem_long(s, STW, STWX, arg, base, offset); 1685 break; 1686 } 1687 if (have_isa_2_07 && have_vsx) { 1688 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); 1689 break; 1690 } 1691 assert((offset & 3) == 0); 1692 tcg_debug_assert((offset & 3) == 0); 1693 shift = (offset - 4) & 0xc; 1694 if (shift) { 1695 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); 1696 arg = TCG_VEC_TMP1; 1697 } 1698 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1699 break; 1700 case TCG_TYPE_I64: 1701 if (arg < TCG_REG_V0) { 1702 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1703 tcg_out_mem_long(s, STD, STDX, arg, base, offset); 1704 break; 1705 } 1706 /* fallthru */ 1707 case TCG_TYPE_V64: 1708 tcg_debug_assert(arg >= TCG_REG_V0); 1709 if (have_vsx) { 1710 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, 1711 STXSDX, arg, base, offset); 1712 break; 1713 } 1714 tcg_debug_assert((offset & 7) == 0); 1715 if (offset & 8) { 1716 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); 1717 arg = TCG_VEC_TMP1; 1718 } 1719 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1720 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); 1721 break; 1722 case TCG_TYPE_V128: 1723 tcg_debug_assert(arg >= TCG_REG_V0); 1724 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, 1725 STVX, arg, base, offset); 1726 break; 1727 default: 1728 g_assert_not_reached(); 1729 } 1730} 1731 1732static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1733 TCGReg base, intptr_t ofs) 1734{ 1735 return false; 1736} 1737 1738/* 1739 * Set dest non-zero if and only if (arg1 & arg2) is non-zero. 1740 * If RC, then also set RC0. 1741 */ 1742static void tcg_out_test(TCGContext *s, TCGReg dest, TCGReg arg1, TCGArg arg2, 1743 bool const_arg2, TCGType type, bool rc) 1744{ 1745 int mb, me; 1746 1747 if (!const_arg2) { 1748 tcg_out32(s, AND | SAB(arg1, dest, arg2) | rc); 1749 return; 1750 } 1751 1752 if (type == TCG_TYPE_I32) { 1753 arg2 = (uint32_t)arg2; 1754 } 1755 1756 if ((arg2 & ~0xffff) == 0) { 1757 tcg_out32(s, ANDI | SAI(arg1, dest, arg2)); 1758 return; 1759 } 1760 if ((arg2 & ~0xffff0000ull) == 0) { 1761 tcg_out32(s, ANDIS | SAI(arg1, dest, arg2 >> 16)); 1762 return; 1763 } 1764 if (arg2 == (uint32_t)arg2 && mask_operand(arg2, &mb, &me)) { 1765 tcg_out_rlw_rc(s, RLWINM, dest, arg1, 0, mb, me, rc); 1766 return; 1767 } 1768 if (TCG_TARGET_REG_BITS == 64) { 1769 int sh = clz64(arg2); 1770 if (mask64_operand(arg2 << sh, &mb, &me)) { 1771 tcg_out_rld_rc(s, RLDICR, dest, arg1, sh, me, rc); 1772 return; 1773 } 1774 } 1775 /* Constraints should satisfy this. */ 1776 g_assert_not_reached(); 1777} 1778 1779static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, 1780 int const_arg2, int cr, TCGType type) 1781{ 1782 int imm; 1783 uint32_t op; 1784 1785 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1786 1787 /* 1788 * Simplify the comparisons below wrt CMPI. 1789 * All of the tests are 16-bit, so a 32-bit sign extend always works. 1790 */ 1791 if (type == TCG_TYPE_I32) { 1792 arg2 = (int32_t)arg2; 1793 } 1794 1795 switch (cond) { 1796 case TCG_COND_EQ: 1797 case TCG_COND_NE: 1798 if (const_arg2) { 1799 if ((int16_t) arg2 == arg2) { 1800 op = CMPI; 1801 imm = 1; 1802 break; 1803 } else if ((uint16_t) arg2 == arg2) { 1804 op = CMPLI; 1805 imm = 1; 1806 break; 1807 } 1808 } 1809 op = CMPL; 1810 imm = 0; 1811 break; 1812 1813 case TCG_COND_TSTEQ: 1814 case TCG_COND_TSTNE: 1815 tcg_debug_assert(cr == 0); 1816 tcg_out_test(s, TCG_REG_R0, arg1, arg2, const_arg2, type, true); 1817 return; 1818 1819 case TCG_COND_LT: 1820 case TCG_COND_GE: 1821 case TCG_COND_LE: 1822 case TCG_COND_GT: 1823 if (const_arg2) { 1824 if ((int16_t) arg2 == arg2) { 1825 op = CMPI; 1826 imm = 1; 1827 break; 1828 } 1829 } 1830 op = CMP; 1831 imm = 0; 1832 break; 1833 1834 case TCG_COND_LTU: 1835 case TCG_COND_GEU: 1836 case TCG_COND_LEU: 1837 case TCG_COND_GTU: 1838 if (const_arg2) { 1839 if ((uint16_t) arg2 == arg2) { 1840 op = CMPLI; 1841 imm = 1; 1842 break; 1843 } 1844 } 1845 op = CMPL; 1846 imm = 0; 1847 break; 1848 1849 default: 1850 g_assert_not_reached(); 1851 } 1852 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); 1853 1854 if (imm) { 1855 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); 1856 } else { 1857 if (const_arg2) { 1858 tcg_out_movi(s, type, TCG_REG_R0, arg2); 1859 arg2 = TCG_REG_R0; 1860 } 1861 tcg_out32(s, op | RA(arg1) | RB(arg2)); 1862 } 1863} 1864 1865static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, 1866 TCGReg dst, TCGReg src, bool neg) 1867{ 1868 if (neg && (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I64)) { 1869 /* 1870 * X != 0 implies X + -1 generates a carry. 1871 * RT = (~X + X) + CA 1872 * = -1 + CA 1873 * = CA ? 0 : -1 1874 */ 1875 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); 1876 tcg_out32(s, SUBFE | TAB(dst, src, src)); 1877 return; 1878 } 1879 1880 if (type == TCG_TYPE_I32) { 1881 tcg_out32(s, CNTLZW | RS(src) | RA(dst)); 1882 tcg_out_shri32(s, dst, dst, 5); 1883 } else { 1884 tcg_out32(s, CNTLZD | RS(src) | RA(dst)); 1885 tcg_out_shri64(s, dst, dst, 6); 1886 } 1887 if (neg) { 1888 tcg_out32(s, NEG | RT(dst) | RA(dst)); 1889 } 1890} 1891 1892static void tcg_out_setcond_ne0(TCGContext *s, TCGType type, 1893 TCGReg dst, TCGReg src, bool neg) 1894{ 1895 if (!neg && (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I64)) { 1896 /* 1897 * X != 0 implies X + -1 generates a carry. Extra addition 1898 * trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. 1899 */ 1900 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); 1901 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); 1902 return; 1903 } 1904 tcg_out_setcond_eq0(s, type, dst, src, false); 1905 if (neg) { 1906 tcg_out32(s, ADDI | TAI(dst, dst, -1)); 1907 } else { 1908 tcg_out_xori32(s, dst, dst, 1); 1909 } 1910} 1911 1912static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, 1913 bool const_arg2) 1914{ 1915 if (const_arg2) { 1916 if ((uint32_t)arg2 == arg2) { 1917 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); 1918 } else { 1919 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); 1920 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); 1921 } 1922 } else { 1923 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); 1924 } 1925 return TCG_REG_R0; 1926} 1927 1928static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, 1929 TCGArg arg0, TCGArg arg1, TCGArg arg2, 1930 int const_arg2, bool neg) 1931{ 1932 int sh; 1933 bool inv; 1934 1935 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1936 1937 /* Ignore high bits of a potential constant arg2. */ 1938 if (type == TCG_TYPE_I32) { 1939 arg2 = (uint32_t)arg2; 1940 } 1941 1942 /* With SETBC/SETBCR, we can always implement with 2 insns. */ 1943 if (have_isa_3_10) { 1944 tcg_insn_unit bi, opc; 1945 1946 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); 1947 1948 /* Re-use tcg_to_bc for BI and BO_COND_{TRUE,FALSE}. */ 1949 bi = tcg_to_bc[cond] & (0x1f << 16); 1950 if (tcg_to_bc[cond] & BO(8)) { 1951 opc = neg ? SETNBC : SETBC; 1952 } else { 1953 opc = neg ? SETNBCR : SETBCR; 1954 } 1955 tcg_out32(s, opc | RT(arg0) | bi); 1956 return; 1957 } 1958 1959 /* Handle common and trivial cases before handling anything else. */ 1960 if (arg2 == 0) { 1961 switch (cond) { 1962 case TCG_COND_EQ: 1963 tcg_out_setcond_eq0(s, type, arg0, arg1, neg); 1964 return; 1965 case TCG_COND_NE: 1966 tcg_out_setcond_ne0(s, type, arg0, arg1, neg); 1967 return; 1968 case TCG_COND_GE: 1969 tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); 1970 arg1 = arg0; 1971 /* FALLTHRU */ 1972 case TCG_COND_LT: 1973 /* Extract the sign bit. */ 1974 if (type == TCG_TYPE_I32) { 1975 if (neg) { 1976 tcg_out_sari32(s, arg0, arg1, 31); 1977 } else { 1978 tcg_out_shri32(s, arg0, arg1, 31); 1979 } 1980 } else { 1981 if (neg) { 1982 tcg_out_sari64(s, arg0, arg1, 63); 1983 } else { 1984 tcg_out_shri64(s, arg0, arg1, 63); 1985 } 1986 } 1987 return; 1988 default: 1989 break; 1990 } 1991 } 1992 1993 /* If we have ISEL, we can implement everything with 3 or 4 insns. 1994 All other cases below are also at least 3 insns, so speed up the 1995 code generator by not considering them and always using ISEL. */ 1996 if (have_isel) { 1997 int isel, tab; 1998 1999 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); 2000 2001 isel = tcg_to_isel[cond]; 2002 2003 tcg_out_movi(s, type, arg0, neg ? -1 : 1); 2004 if (isel & 1) { 2005 /* arg0 = (bc ? 0 : 1) */ 2006 tab = TAB(arg0, 0, arg0); 2007 isel &= ~1; 2008 } else { 2009 /* arg0 = (bc ? 1 : 0) */ 2010 tcg_out_movi(s, type, TCG_REG_R0, 0); 2011 tab = TAB(arg0, arg0, TCG_REG_R0); 2012 } 2013 tcg_out32(s, isel | tab); 2014 return; 2015 } 2016 2017 inv = false; 2018 switch (cond) { 2019 case TCG_COND_EQ: 2020 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 2021 tcg_out_setcond_eq0(s, type, arg0, arg1, neg); 2022 break; 2023 2024 case TCG_COND_NE: 2025 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 2026 tcg_out_setcond_ne0(s, type, arg0, arg1, neg); 2027 break; 2028 2029 case TCG_COND_TSTEQ: 2030 tcg_out_test(s, TCG_REG_R0, arg1, arg2, const_arg2, type, false); 2031 tcg_out_setcond_eq0(s, type, arg0, TCG_REG_R0, neg); 2032 break; 2033 2034 case TCG_COND_TSTNE: 2035 tcg_out_test(s, TCG_REG_R0, arg1, arg2, const_arg2, type, false); 2036 tcg_out_setcond_ne0(s, type, arg0, TCG_REG_R0, neg); 2037 break; 2038 2039 case TCG_COND_LE: 2040 case TCG_COND_LEU: 2041 inv = true; 2042 /* fall through */ 2043 case TCG_COND_GT: 2044 case TCG_COND_GTU: 2045 sh = 30; /* CR7 CR_GT */ 2046 goto crtest; 2047 2048 case TCG_COND_GE: 2049 case TCG_COND_GEU: 2050 inv = true; 2051 /* fall through */ 2052 case TCG_COND_LT: 2053 case TCG_COND_LTU: 2054 sh = 29; /* CR7 CR_LT */ 2055 goto crtest; 2056 2057 crtest: 2058 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 2059 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 2060 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); 2061 if (neg && inv) { 2062 tcg_out32(s, ADDI | TAI(arg0, arg0, -1)); 2063 } else if (neg) { 2064 tcg_out32(s, NEG | RT(arg0) | RA(arg0)); 2065 } else if (inv) { 2066 tcg_out_xori32(s, arg0, arg0, 1); 2067 } 2068 break; 2069 2070 default: 2071 g_assert_not_reached(); 2072 } 2073} 2074 2075static void tcg_out_bc(TCGContext *s, TCGCond cond, int bd) 2076{ 2077 tcg_out32(s, tcg_to_bc[cond] | bd); 2078} 2079 2080static void tcg_out_bc_lab(TCGContext *s, TCGCond cond, TCGLabel *l) 2081{ 2082 int bd = 0; 2083 if (l->has_value) { 2084 bd = reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr); 2085 } else { 2086 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); 2087 } 2088 tcg_out_bc(s, cond, bd); 2089} 2090 2091static void tcg_out_brcond(TCGContext *s, TCGCond cond, 2092 TCGArg arg1, TCGArg arg2, int const_arg2, 2093 TCGLabel *l, TCGType type) 2094{ 2095 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 0, type); 2096 tcg_out_bc_lab(s, cond, l); 2097} 2098 2099static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, 2100 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, 2101 TCGArg v2, bool const_c2) 2102{ 2103 /* If for some reason both inputs are zero, don't produce bad code. */ 2104 if (v1 == 0 && v2 == 0) { 2105 tcg_out_movi(s, type, dest, 0); 2106 return; 2107 } 2108 2109 tcg_out_cmp(s, cond, c1, c2, const_c2, 0, type); 2110 2111 if (have_isel) { 2112 int isel = tcg_to_isel[cond]; 2113 2114 /* Swap the V operands if the operation indicates inversion. */ 2115 if (isel & 1) { 2116 int t = v1; 2117 v1 = v2; 2118 v2 = t; 2119 isel &= ~1; 2120 } 2121 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ 2122 if (v2 == 0) { 2123 tcg_out_movi(s, type, TCG_REG_R0, 0); 2124 } 2125 tcg_out32(s, isel | TAB(dest, v1, v2)); 2126 } else { 2127 if (dest == v2) { 2128 cond = tcg_invert_cond(cond); 2129 v2 = v1; 2130 } else if (dest != v1) { 2131 if (v1 == 0) { 2132 tcg_out_movi(s, type, dest, 0); 2133 } else { 2134 tcg_out_mov(s, type, dest, v1); 2135 } 2136 } 2137 /* Branch forward over one insn */ 2138 tcg_out_bc(s, cond, 8); 2139 if (v2 == 0) { 2140 tcg_out_movi(s, type, dest, 0); 2141 } else { 2142 tcg_out_mov(s, type, dest, v2); 2143 } 2144 } 2145} 2146 2147static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc, 2148 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2) 2149{ 2150 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { 2151 tcg_out32(s, opc | RA(a0) | RS(a1)); 2152 } else { 2153 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 0, type); 2154 /* Note that the only other valid constant for a2 is 0. */ 2155 if (have_isel) { 2156 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); 2157 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0)); 2158 } else if (!const_a2 && a0 == a2) { 2159 tcg_out_bc(s, TCG_COND_EQ, 8); 2160 tcg_out32(s, opc | RA(a0) | RS(a1)); 2161 } else { 2162 tcg_out32(s, opc | RA(a0) | RS(a1)); 2163 tcg_out_bc(s, TCG_COND_NE, 8); 2164 if (const_a2) { 2165 tcg_out_movi(s, type, a0, 0); 2166 } else { 2167 tcg_out_mov(s, type, a0, a2); 2168 } 2169 } 2170 } 2171} 2172 2173static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, 2174 const int *const_args) 2175{ 2176 static const struct { uint8_t bit1, bit2; } bits[] = { 2177 [TCG_COND_LT ] = { CR_LT, CR_LT }, 2178 [TCG_COND_LE ] = { CR_LT, CR_GT }, 2179 [TCG_COND_GT ] = { CR_GT, CR_GT }, 2180 [TCG_COND_GE ] = { CR_GT, CR_LT }, 2181 [TCG_COND_LTU] = { CR_LT, CR_LT }, 2182 [TCG_COND_LEU] = { CR_LT, CR_GT }, 2183 [TCG_COND_GTU] = { CR_GT, CR_GT }, 2184 [TCG_COND_GEU] = { CR_GT, CR_LT }, 2185 }; 2186 2187 TCGCond cond = args[4], cond2; 2188 TCGArg al, ah, bl, bh; 2189 int blconst, bhconst; 2190 int op, bit1, bit2; 2191 2192 al = args[0]; 2193 ah = args[1]; 2194 bl = args[2]; 2195 bh = args[3]; 2196 blconst = const_args[2]; 2197 bhconst = const_args[3]; 2198 2199 switch (cond) { 2200 case TCG_COND_EQ: 2201 op = CRAND; 2202 goto do_equality; 2203 case TCG_COND_NE: 2204 op = CRNAND; 2205 do_equality: 2206 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); 2207 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); 2208 tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 2209 break; 2210 2211 case TCG_COND_TSTEQ: 2212 case TCG_COND_TSTNE: 2213 if (blconst) { 2214 tcg_out_andi32(s, TCG_REG_R0, al, bl); 2215 } else { 2216 tcg_out32(s, AND | SAB(al, TCG_REG_R0, bl)); 2217 } 2218 if (bhconst) { 2219 tcg_out_andi32(s, TCG_REG_TMP1, ah, bh); 2220 } else { 2221 tcg_out32(s, AND | SAB(ah, TCG_REG_TMP1, bh)); 2222 } 2223 tcg_out32(s, OR | SAB(TCG_REG_R0, TCG_REG_R0, TCG_REG_TMP1) | 1); 2224 break; 2225 2226 case TCG_COND_LT: 2227 case TCG_COND_LE: 2228 case TCG_COND_GT: 2229 case TCG_COND_GE: 2230 case TCG_COND_LTU: 2231 case TCG_COND_LEU: 2232 case TCG_COND_GTU: 2233 case TCG_COND_GEU: 2234 bit1 = bits[cond].bit1; 2235 bit2 = bits[cond].bit2; 2236 op = (bit1 != bit2 ? CRANDC : CRAND); 2237 cond2 = tcg_unsigned_cond(cond); 2238 2239 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); 2240 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); 2241 tcg_out32(s, op | BT(0, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); 2242 tcg_out32(s, CROR | BT(0, CR_EQ) | BA(6, bit1) | BB(0, CR_EQ)); 2243 break; 2244 2245 default: 2246 g_assert_not_reached(); 2247 } 2248} 2249 2250static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 2251 const int *const_args) 2252{ 2253 tcg_out_cmp2(s, args + 1, const_args + 1); 2254 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(0)); 2255 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, CR_EQ + 0*4 + 1, 31, 31); 2256} 2257 2258static void tcg_out_brcond2(TCGContext *s, const TCGArg *args, 2259 const int *const_args) 2260{ 2261 tcg_out_cmp2(s, args, const_args); 2262 tcg_out_bc_lab(s, TCG_COND_EQ, arg_label(args[5])); 2263} 2264 2265static void tcg_out_mb(TCGContext *s, TCGArg a0) 2266{ 2267 uint32_t insn; 2268 2269 if (a0 & TCG_MO_ST_LD) { 2270 insn = HWSYNC; 2271 } else { 2272 insn = LWSYNC; 2273 } 2274 2275 tcg_out32(s, insn); 2276} 2277 2278static void tcg_out_call_int(TCGContext *s, int lk, 2279 const tcg_insn_unit *target) 2280{ 2281#ifdef _CALL_AIX 2282 /* Look through the descriptor. If the branch is in range, and we 2283 don't have to spend too much effort on building the toc. */ 2284 const void *tgt = ((const void * const *)target)[0]; 2285 uintptr_t toc = ((const uintptr_t *)target)[1]; 2286 intptr_t diff = tcg_pcrel_diff(s, tgt); 2287 2288 if (in_range_b(diff) && toc == (uint32_t)toc) { 2289 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); 2290 tcg_out_b(s, lk, tgt); 2291 } else { 2292 /* Fold the low bits of the constant into the addresses below. */ 2293 intptr_t arg = (intptr_t)target; 2294 int ofs = (int16_t)arg; 2295 2296 if (ofs + 8 < 0x8000) { 2297 arg -= ofs; 2298 } else { 2299 ofs = 0; 2300 } 2301 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); 2302 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); 2303 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); 2304 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); 2305 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 2306 } 2307#elif defined(_CALL_ELF) && _CALL_ELF == 2 2308 intptr_t diff; 2309 2310 /* In the ELFv2 ABI, we have to set up r12 to contain the destination 2311 address, which the callee uses to compute its TOC address. */ 2312 /* FIXME: when the branch is in range, we could avoid r12 load if we 2313 knew that the destination uses the same TOC, and what its local 2314 entry point offset is. */ 2315 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); 2316 2317 diff = tcg_pcrel_diff(s, target); 2318 if (in_range_b(diff)) { 2319 tcg_out_b(s, lk, target); 2320 } else { 2321 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); 2322 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 2323 } 2324#else 2325 tcg_out_b(s, lk, target); 2326#endif 2327} 2328 2329static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 2330 const TCGHelperInfo *info) 2331{ 2332 tcg_out_call_int(s, LK, target); 2333} 2334 2335static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = { 2336 [MO_UB] = LBZX, 2337 [MO_UW] = LHZX, 2338 [MO_UL] = LWZX, 2339 [MO_UQ] = LDX, 2340 [MO_SW] = LHAX, 2341 [MO_SL] = LWAX, 2342 [MO_BSWAP | MO_UB] = LBZX, 2343 [MO_BSWAP | MO_UW] = LHBRX, 2344 [MO_BSWAP | MO_UL] = LWBRX, 2345 [MO_BSWAP | MO_UQ] = LDBRX, 2346}; 2347 2348static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = { 2349 [MO_UB] = STBX, 2350 [MO_UW] = STHX, 2351 [MO_UL] = STWX, 2352 [MO_UQ] = STDX, 2353 [MO_BSWAP | MO_UB] = STBX, 2354 [MO_BSWAP | MO_UW] = STHBRX, 2355 [MO_BSWAP | MO_UL] = STWBRX, 2356 [MO_BSWAP | MO_UQ] = STDBRX, 2357}; 2358 2359static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 2360{ 2361 if (arg < 0) { 2362 arg = TCG_REG_TMP1; 2363 } 2364 tcg_out32(s, MFSPR | RT(arg) | LR); 2365 return arg; 2366} 2367 2368/* 2369 * For the purposes of ppc32 sorting 4 input registers into 4 argument 2370 * registers, there is an outside chance we would require 3 temps. 2371 */ 2372static const TCGLdstHelperParam ldst_helper_param = { 2373 .ra_gen = ldst_ra_gen, 2374 .ntmp = 3, 2375 .tmp = { TCG_REG_TMP1, TCG_REG_TMP2, TCG_REG_R0 } 2376}; 2377 2378static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2379{ 2380 MemOp opc = get_memop(lb->oi); 2381 2382 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2383 return false; 2384 } 2385 2386 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 2387 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & MO_SIZE]); 2388 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 2389 2390 tcg_out_b(s, 0, lb->raddr); 2391 return true; 2392} 2393 2394static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2395{ 2396 MemOp opc = get_memop(lb->oi); 2397 2398 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2399 return false; 2400 } 2401 2402 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 2403 tcg_out_call_int(s, LK, qemu_st_helpers[opc & MO_SIZE]); 2404 2405 tcg_out_b(s, 0, lb->raddr); 2406 return true; 2407} 2408 2409typedef struct { 2410 TCGReg base; 2411 TCGReg index; 2412 TCGAtomAlign aa; 2413} HostAddress; 2414 2415bool tcg_target_has_memory_bswap(MemOp memop) 2416{ 2417 TCGAtomAlign aa; 2418 2419 if ((memop & MO_SIZE) <= MO_64) { 2420 return true; 2421 } 2422 2423 /* 2424 * Reject 16-byte memop with 16-byte atomicity, 2425 * but do allow a pair of 64-bit operations. 2426 */ 2427 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 2428 return aa.atom <= MO_64; 2429} 2430 2431/* We expect to use a 16-bit negative offset from ENV. */ 2432#define MIN_TLB_MASK_TABLE_OFS -32768 2433 2434/* 2435 * For system-mode, perform the TLB load and compare. 2436 * For user-mode, perform any required alignment tests. 2437 * In both cases, return a TCGLabelQemuLdst structure if the slow path 2438 * is required and fill in @h with the host address for the fast path. 2439 */ 2440static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 2441 TCGReg addr, MemOpIdx oi, bool is_ld) 2442{ 2443 TCGType addr_type = s->addr_type; 2444 TCGLabelQemuLdst *ldst = NULL; 2445 MemOp opc = get_memop(oi); 2446 MemOp a_bits, s_bits; 2447 2448 /* 2449 * Book II, Section 1.4, Single-Copy Atomicity, specifies: 2450 * 2451 * Before 3.0, "An access that is not atomic is performed as a set of 2452 * smaller disjoint atomic accesses. In general, the number and alignment 2453 * of these accesses are implementation-dependent." Thus MO_ATOM_IFALIGN. 2454 * 2455 * As of 3.0, "the non-atomic access is performed as described in 2456 * the corresponding list", which matches MO_ATOM_SUBALIGN. 2457 */ 2458 s_bits = opc & MO_SIZE; 2459 h->aa = atom_and_align_for_opc(s, opc, 2460 have_isa_3_00 ? MO_ATOM_SUBALIGN 2461 : MO_ATOM_IFALIGN, 2462 s_bits == MO_128); 2463 a_bits = h->aa.align; 2464 2465 if (tcg_use_softmmu) { 2466 int mem_index = get_mmuidx(oi); 2467 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 2468 : offsetof(CPUTLBEntry, addr_write); 2469 int fast_off = tlb_mask_table_ofs(s, mem_index); 2470 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 2471 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 2472 2473 ldst = new_ldst_label(s); 2474 ldst->is_ld = is_ld; 2475 ldst->oi = oi; 2476 ldst->addr_reg = addr; 2477 2478 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 2479 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); 2480 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); 2481 2482 /* Extract the page index, shifted into place for tlb index. */ 2483 if (TCG_TARGET_REG_BITS == 32) { 2484 tcg_out_shri32(s, TCG_REG_R0, addr, 2485 s->page_bits - CPU_TLB_ENTRY_BITS); 2486 } else { 2487 tcg_out_shri64(s, TCG_REG_R0, addr, 2488 s->page_bits - CPU_TLB_ENTRY_BITS); 2489 } 2490 tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); 2491 2492 /* 2493 * Load the TLB comparator into TMP2. 2494 * For 64-bit host, always load the entire 64-bit slot for simplicity. 2495 * We will ignore the high bits with tcg_out_cmp(..., addr_type). 2496 */ 2497 if (cmp_off == 0) { 2498 tcg_out32(s, (TCG_TARGET_REG_BITS == 64 ? LDUX : LWZUX) 2499 | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); 2500 } else { 2501 tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); 2502 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); 2503 } 2504 2505 /* 2506 * Load the TLB addend for use on the fast path. 2507 * Do this asap to minimize any load use delay. 2508 */ 2509 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { 2510 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, 2511 offsetof(CPUTLBEntry, addend)); 2512 } 2513 2514 /* Clear the non-page, non-alignment bits from the address in R0. */ 2515 if (TCG_TARGET_REG_BITS == 32) { 2516 /* 2517 * We don't support unaligned accesses on 32-bits. 2518 * Preserve the bottom bits and thus trigger a comparison 2519 * failure on unaligned accesses. 2520 */ 2521 if (a_bits < s_bits) { 2522 a_bits = s_bits; 2523 } 2524 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr, 0, 2525 (32 - a_bits) & 31, 31 - s->page_bits); 2526 } else { 2527 TCGReg t = addr; 2528 2529 /* 2530 * If the access is unaligned, we need to make sure we fail if we 2531 * cross a page boundary. The trick is to add the access size-1 2532 * to the address before masking the low bits. That will make the 2533 * address overflow to the next page if we cross a page boundary, 2534 * which will then force a mismatch of the TLB compare. 2535 */ 2536 if (a_bits < s_bits) { 2537 unsigned a_mask = (1 << a_bits) - 1; 2538 unsigned s_mask = (1 << s_bits) - 1; 2539 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); 2540 t = TCG_REG_R0; 2541 } 2542 2543 /* Mask the address for the requested alignment. */ 2544 if (addr_type == TCG_TYPE_I32) { 2545 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, 2546 (32 - a_bits) & 31, 31 - s->page_bits); 2547 } else if (a_bits == 0) { 2548 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits); 2549 } else { 2550 tcg_out_rld(s, RLDICL, TCG_REG_R0, t, 2551 64 - s->page_bits, s->page_bits - a_bits); 2552 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0); 2553 } 2554 } 2555 2556 /* Full comparison into cr0. */ 2557 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 0, addr_type); 2558 2559 /* Load a pointer into the current opcode w/conditional branch-link. */ 2560 ldst->label_ptr[0] = s->code_ptr; 2561 tcg_out_bc(s, TCG_COND_NE, LK); 2562 2563 h->base = TCG_REG_TMP1; 2564 } else { 2565 if (a_bits) { 2566 ldst = new_ldst_label(s); 2567 ldst->is_ld = is_ld; 2568 ldst->oi = oi; 2569 ldst->addr_reg = addr; 2570 2571 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 2572 tcg_debug_assert(a_bits < 16); 2573 tcg_out32(s, ANDI | SAI(addr, TCG_REG_R0, (1 << a_bits) - 1)); 2574 2575 ldst->label_ptr[0] = s->code_ptr; 2576 tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); 2577 } 2578 2579 h->base = guest_base ? TCG_GUEST_BASE_REG : 0; 2580 } 2581 2582 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 2583 /* Zero-extend the guest address for use in the host address. */ 2584 tcg_out_ext32u(s, TCG_REG_TMP2, addr); 2585 h->index = TCG_REG_TMP2; 2586 } else { 2587 h->index = addr; 2588 } 2589 2590 return ldst; 2591} 2592 2593static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2594 TCGReg addr, MemOpIdx oi, TCGType data_type) 2595{ 2596 MemOp opc = get_memop(oi); 2597 TCGLabelQemuLdst *ldst; 2598 HostAddress h; 2599 2600 ldst = prepare_host_addr(s, &h, addr, oi, true); 2601 2602 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2603 if (opc & MO_BSWAP) { 2604 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2605 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2606 tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); 2607 } else if (h.base != 0) { 2608 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2609 tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); 2610 tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); 2611 } else if (h.index == datahi) { 2612 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2613 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2614 } else { 2615 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2616 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2617 } 2618 } else { 2619 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; 2620 if (!have_isa_2_06 && insn == LDBRX) { 2621 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2622 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2623 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); 2624 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); 2625 } else if (insn) { 2626 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2627 } else { 2628 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; 2629 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2630 tcg_out_movext(s, TCG_TYPE_REG, datalo, 2631 TCG_TYPE_REG, opc & MO_SSIZE, datalo); 2632 } 2633 } 2634 2635 if (ldst) { 2636 ldst->type = data_type; 2637 ldst->datalo_reg = datalo; 2638 ldst->datahi_reg = datahi; 2639 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2640 } 2641} 2642 2643static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2644 TCGReg addr, MemOpIdx oi, TCGType data_type) 2645{ 2646 MemOp opc = get_memop(oi); 2647 TCGLabelQemuLdst *ldst; 2648 HostAddress h; 2649 2650 ldst = prepare_host_addr(s, &h, addr, oi, false); 2651 2652 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2653 if (opc & MO_BSWAP) { 2654 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2655 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2656 tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); 2657 } else if (h.base != 0) { 2658 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2659 tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); 2660 tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); 2661 } else { 2662 tcg_out32(s, STW | TAI(datahi, h.index, 0)); 2663 tcg_out32(s, STW | TAI(datalo, h.index, 4)); 2664 } 2665 } else { 2666 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; 2667 if (!have_isa_2_06 && insn == STDBRX) { 2668 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2669 tcg_out32(s, ADDI | TAI(TCG_REG_TMP2, h.index, 4)); 2670 tcg_out_shri64(s, TCG_REG_R0, datalo, 32); 2671 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP2)); 2672 } else { 2673 tcg_out32(s, insn | SAB(datalo, h.base, h.index)); 2674 } 2675 } 2676 2677 if (ldst) { 2678 ldst->type = data_type; 2679 ldst->datalo_reg = datalo; 2680 ldst->datahi_reg = datahi; 2681 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2682 } 2683} 2684 2685static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 2686 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 2687{ 2688 TCGLabelQemuLdst *ldst; 2689 HostAddress h; 2690 bool need_bswap; 2691 uint32_t insn; 2692 TCGReg index; 2693 2694 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 2695 2696 /* Compose the final address, as LQ/STQ have no indexing. */ 2697 index = h.index; 2698 if (h.base != 0) { 2699 index = TCG_REG_TMP1; 2700 tcg_out32(s, ADD | TAB(index, h.base, h.index)); 2701 } 2702 need_bswap = get_memop(oi) & MO_BSWAP; 2703 2704 if (h.aa.atom == MO_128) { 2705 tcg_debug_assert(!need_bswap); 2706 tcg_debug_assert(datalo & 1); 2707 tcg_debug_assert(datahi == datalo - 1); 2708 tcg_debug_assert(!is_ld || datahi != index); 2709 insn = is_ld ? LQ : STQ; 2710 tcg_out32(s, insn | TAI(datahi, index, 0)); 2711 } else { 2712 TCGReg d1, d2; 2713 2714 if (HOST_BIG_ENDIAN ^ need_bswap) { 2715 d1 = datahi, d2 = datalo; 2716 } else { 2717 d1 = datalo, d2 = datahi; 2718 } 2719 2720 if (need_bswap) { 2721 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 8); 2722 insn = is_ld ? LDBRX : STDBRX; 2723 tcg_out32(s, insn | TAB(d1, 0, index)); 2724 tcg_out32(s, insn | TAB(d2, index, TCG_REG_R0)); 2725 } else { 2726 insn = is_ld ? LD : STD; 2727 tcg_out32(s, insn | TAI(d1, index, 0)); 2728 tcg_out32(s, insn | TAI(d2, index, 8)); 2729 } 2730 } 2731 2732 if (ldst) { 2733 ldst->type = TCG_TYPE_I128; 2734 ldst->datalo_reg = datalo; 2735 ldst->datahi_reg = datahi; 2736 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2737 } 2738} 2739 2740static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2741{ 2742 int i; 2743 for (i = 0; i < count; ++i) { 2744 p[i] = NOP; 2745 } 2746} 2747 2748/* Parameters for function call generation, used in tcg.c. */ 2749#define TCG_TARGET_STACK_ALIGN 16 2750 2751#ifdef _CALL_AIX 2752# define LINK_AREA_SIZE (6 * SZR) 2753# define LR_OFFSET (1 * SZR) 2754# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) 2755#elif defined(_CALL_DARWIN) 2756# define LINK_AREA_SIZE (6 * SZR) 2757# define LR_OFFSET (2 * SZR) 2758#elif TCG_TARGET_REG_BITS == 64 2759# if defined(_CALL_ELF) && _CALL_ELF == 2 2760# define LINK_AREA_SIZE (4 * SZR) 2761# define LR_OFFSET (1 * SZR) 2762# endif 2763#else /* TCG_TARGET_REG_BITS == 32 */ 2764# if defined(_CALL_SYSV) 2765# define LINK_AREA_SIZE (2 * SZR) 2766# define LR_OFFSET (1 * SZR) 2767# endif 2768#endif 2769#ifndef LR_OFFSET 2770# error "Unhandled abi" 2771#endif 2772#ifndef TCG_TARGET_CALL_STACK_OFFSET 2773# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE 2774#endif 2775 2776#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2777#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) 2778 2779#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ 2780 + TCG_STATIC_CALL_ARGS_SIZE \ 2781 + CPU_TEMP_BUF_SIZE \ 2782 + REG_SAVE_SIZE \ 2783 + TCG_TARGET_STACK_ALIGN - 1) \ 2784 & -TCG_TARGET_STACK_ALIGN) 2785 2786#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) 2787 2788static void tcg_target_qemu_prologue(TCGContext *s) 2789{ 2790 int i; 2791 2792#ifdef _CALL_AIX 2793 const void **desc = (const void **)s->code_ptr; 2794 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */ 2795 desc[1] = 0; /* environment pointer */ 2796 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ 2797#endif 2798 2799 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, 2800 CPU_TEMP_BUF_SIZE); 2801 2802 /* Prologue */ 2803 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); 2804 tcg_out32(s, (SZR == 8 ? STDU : STWU) 2805 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); 2806 2807 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2808 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2809 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2810 } 2811 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2812 2813 if (!tcg_use_softmmu && guest_base) { 2814 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); 2815 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2816 } 2817 2818 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2819 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); 2820 tcg_out32(s, BCCTR | BO_ALWAYS); 2821 2822 /* Epilogue */ 2823 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2824 2825 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2826 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2827 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2828 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2829 } 2830 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); 2831 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); 2832 tcg_out32(s, BCLR | BO_ALWAYS); 2833} 2834 2835static void tcg_out_tb_start(TCGContext *s) 2836{ 2837 /* Load TCG_REG_TB. */ 2838 if (USE_REG_TB) { 2839 if (have_isa_3_00) { 2840 /* lnia REG_TB */ 2841 tcg_out_addpcis(s, TCG_REG_TB, 0); 2842 } else { 2843 /* bcl 20,31,$+4 (preferred form for getting nia) */ 2844 tcg_out32(s, BC | BO_ALWAYS | BI(7, CR_SO) | 0x4 | LK); 2845 tcg_out32(s, MFSPR | RT(TCG_REG_TB) | LR); 2846 } 2847 } 2848} 2849 2850static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 2851{ 2852 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg); 2853 tcg_out_b(s, 0, tcg_code_gen_epilogue); 2854} 2855 2856static void tcg_out_goto_tb(TCGContext *s, int which) 2857{ 2858 uintptr_t ptr = get_jmp_target_addr(s, which); 2859 int16_t lo; 2860 2861 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2862 set_jmp_insn_offset(s, which); 2863 tcg_out32(s, NOP); 2864 2865 /* When branch is out of range, fall through to indirect. */ 2866 if (USE_REG_TB) { 2867 ptrdiff_t offset = ppc_tbrel_diff(s, (void *)ptr); 2868 tcg_out_mem_long(s, LD, LDX, TCG_REG_TMP1, TCG_REG_TB, offset); 2869 } else if (have_isa_3_10) { 2870 ptrdiff_t offset = tcg_pcrel_diff_for_prefix(s, (void *)ptr); 2871 tcg_out_8ls_d(s, PLD, TCG_REG_TMP1, 0, offset, 1); 2872 } else if (have_isa_3_00) { 2873 ptrdiff_t offset = tcg_pcrel_diff(s, (void *)ptr) - 4; 2874 lo = offset; 2875 tcg_out_addpcis(s, TCG_REG_TMP1, offset - lo); 2876 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, lo); 2877 } else { 2878 lo = ptr; 2879 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - lo); 2880 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, lo); 2881 } 2882 2883 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); 2884 tcg_out32(s, BCCTR | BO_ALWAYS); 2885 set_jmp_reset_offset(s, which); 2886} 2887 2888void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2889 uintptr_t jmp_rx, uintptr_t jmp_rw) 2890{ 2891 uintptr_t addr = tb->jmp_target_addr[n]; 2892 intptr_t diff = addr - jmp_rx; 2893 tcg_insn_unit insn; 2894 2895 if (in_range_b(diff)) { 2896 insn = B | (diff & 0x3fffffc); 2897 } else { 2898 insn = NOP; 2899 } 2900 2901 qatomic_set((uint32_t *)jmp_rw, insn); 2902 flush_idcache_range(jmp_rx, jmp_rw, 4); 2903} 2904 2905 2906static void tgen_add(TCGContext *s, TCGType type, 2907 TCGReg a0, TCGReg a1, TCGReg a2) 2908{ 2909 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2910} 2911 2912static void tgen_addi(TCGContext *s, TCGType type, 2913 TCGReg a0, TCGReg a1, tcg_target_long a2) 2914{ 2915 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); 2916} 2917 2918static const TCGOutOpBinary outop_add = { 2919 .base.static_constraint = C_O1_I2(r, r, rT), 2920 .out_rrr = tgen_add, 2921 .out_rri = tgen_addi, 2922}; 2923 2924static void tgen_and(TCGContext *s, TCGType type, 2925 TCGReg a0, TCGReg a1, TCGReg a2) 2926{ 2927 tcg_out32(s, AND | SAB(a1, a0, a2)); 2928} 2929 2930static void tgen_andi(TCGContext *s, TCGType type, 2931 TCGReg a0, TCGReg a1, tcg_target_long a2) 2932{ 2933 if (type == TCG_TYPE_I32) { 2934 tcg_out_andi32(s, a0, a1, a2); 2935 } else { 2936 tcg_out_andi64(s, a0, a1, a2); 2937 } 2938} 2939 2940static const TCGOutOpBinary outop_and = { 2941 .base.static_constraint = C_O1_I2(r, r, ri), 2942 .out_rrr = tgen_and, 2943 .out_rri = tgen_andi, 2944}; 2945 2946static void tgen_andc(TCGContext *s, TCGType type, 2947 TCGReg a0, TCGReg a1, TCGReg a2) 2948{ 2949 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2950} 2951 2952static const TCGOutOpBinary outop_andc = { 2953 .base.static_constraint = C_O1_I2(r, r, r), 2954 .out_rrr = tgen_andc, 2955}; 2956 2957static void tgen_clz(TCGContext *s, TCGType type, 2958 TCGReg a0, TCGReg a1, TCGReg a2) 2959{ 2960 uint32_t insn = type == TCG_TYPE_I32 ? CNTLZW : CNTLZD; 2961 tcg_out_cntxz(s, type, insn, a0, a1, a2, false); 2962} 2963 2964static void tgen_clzi(TCGContext *s, TCGType type, 2965 TCGReg a0, TCGReg a1, tcg_target_long a2) 2966{ 2967 uint32_t insn = type == TCG_TYPE_I32 ? CNTLZW : CNTLZD; 2968 tcg_out_cntxz(s, type, insn, a0, a1, a2, true); 2969} 2970 2971static const TCGOutOpBinary outop_clz = { 2972 .base.static_constraint = C_O1_I2(r, r, rZW), 2973 .out_rrr = tgen_clz, 2974 .out_rri = tgen_clzi, 2975}; 2976 2977static void tgen_ctpop(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2978{ 2979 uint32_t insn = type == TCG_TYPE_I32 ? CNTPOPW : CNTPOPD; 2980 tcg_out32(s, insn | SAB(a1, a0, 0)); 2981} 2982 2983static TCGConstraintSetIndex cset_ctpop(TCGType type, unsigned flags) 2984{ 2985 return have_isa_2_06 ? C_O1_I1(r, r) : C_NotImplemented; 2986} 2987 2988static const TCGOutOpUnary outop_ctpop = { 2989 .base.static_constraint = C_Dynamic, 2990 .base.dynamic_constraint = cset_ctpop, 2991 .out_rr = tgen_ctpop, 2992}; 2993 2994static void tgen_ctz(TCGContext *s, TCGType type, 2995 TCGReg a0, TCGReg a1, TCGReg a2) 2996{ 2997 uint32_t insn = type == TCG_TYPE_I32 ? CNTTZW : CNTTZD; 2998 tcg_out_cntxz(s, type, insn, a0, a1, a2, false); 2999} 3000 3001static void tgen_ctzi(TCGContext *s, TCGType type, 3002 TCGReg a0, TCGReg a1, tcg_target_long a2) 3003{ 3004 uint32_t insn = type == TCG_TYPE_I32 ? CNTTZW : CNTTZD; 3005 tcg_out_cntxz(s, type, insn, a0, a1, a2, true); 3006} 3007 3008static TCGConstraintSetIndex cset_ctz(TCGType type, unsigned flags) 3009{ 3010 return have_isa_3_00 ? C_O1_I2(r, r, rZW) : C_NotImplemented; 3011} 3012 3013static const TCGOutOpBinary outop_ctz = { 3014 .base.static_constraint = C_Dynamic, 3015 .base.dynamic_constraint = cset_ctz, 3016 .out_rrr = tgen_ctz, 3017 .out_rri = tgen_ctzi, 3018}; 3019 3020static void tgen_eqv(TCGContext *s, TCGType type, 3021 TCGReg a0, TCGReg a1, TCGReg a2) 3022{ 3023 tcg_out32(s, EQV | SAB(a1, a0, a2)); 3024} 3025 3026static void tgen_divs(TCGContext *s, TCGType type, 3027 TCGReg a0, TCGReg a1, TCGReg a2) 3028{ 3029 uint32_t insn = type == TCG_TYPE_I32 ? DIVW : DIVD; 3030 tcg_out32(s, insn | TAB(a0, a1, a2)); 3031} 3032 3033static const TCGOutOpBinary outop_divs = { 3034 .base.static_constraint = C_O1_I2(r, r, r), 3035 .out_rrr = tgen_divs, 3036}; 3037 3038static const TCGOutOpDivRem outop_divs2 = { 3039 .base.static_constraint = C_NotImplemented, 3040}; 3041 3042static void tgen_divu(TCGContext *s, TCGType type, 3043 TCGReg a0, TCGReg a1, TCGReg a2) 3044{ 3045 uint32_t insn = type == TCG_TYPE_I32 ? DIVWU : DIVDU; 3046 tcg_out32(s, insn | TAB(a0, a1, a2)); 3047} 3048 3049static const TCGOutOpBinary outop_divu = { 3050 .base.static_constraint = C_O1_I2(r, r, r), 3051 .out_rrr = tgen_divu, 3052}; 3053 3054static const TCGOutOpDivRem outop_divu2 = { 3055 .base.static_constraint = C_NotImplemented, 3056}; 3057 3058static const TCGOutOpBinary outop_eqv = { 3059 .base.static_constraint = C_O1_I2(r, r, r), 3060 .out_rrr = tgen_eqv, 3061}; 3062 3063static void tgen_mul(TCGContext *s, TCGType type, 3064 TCGReg a0, TCGReg a1, TCGReg a2) 3065{ 3066 uint32_t insn = type == TCG_TYPE_I32 ? MULLW : MULLD; 3067 tcg_out32(s, insn | TAB(a0, a1, a2)); 3068} 3069 3070static void tgen_muli(TCGContext *s, TCGType type, 3071 TCGReg a0, TCGReg a1, tcg_target_long a2) 3072{ 3073 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 3074} 3075 3076static const TCGOutOpBinary outop_mul = { 3077 .base.static_constraint = C_O1_I2(r, r, rI), 3078 .out_rrr = tgen_mul, 3079 .out_rri = tgen_muli, 3080}; 3081 3082static const TCGOutOpMul2 outop_muls2 = { 3083 .base.static_constraint = C_NotImplemented, 3084}; 3085 3086static void tgen_mulsh(TCGContext *s, TCGType type, 3087 TCGReg a0, TCGReg a1, TCGReg a2) 3088{ 3089 uint32_t insn = type == TCG_TYPE_I32 ? MULHW : MULHD; 3090 tcg_out32(s, insn | TAB(a0, a1, a2)); 3091} 3092 3093static const TCGOutOpBinary outop_mulsh = { 3094 .base.static_constraint = C_O1_I2(r, r, r), 3095 .out_rrr = tgen_mulsh, 3096}; 3097 3098static const TCGOutOpMul2 outop_mulu2 = { 3099 .base.static_constraint = C_NotImplemented, 3100}; 3101 3102static void tgen_muluh(TCGContext *s, TCGType type, 3103 TCGReg a0, TCGReg a1, TCGReg a2) 3104{ 3105 uint32_t insn = type == TCG_TYPE_I32 ? MULHWU : MULHDU; 3106 tcg_out32(s, insn | TAB(a0, a1, a2)); 3107} 3108 3109static const TCGOutOpBinary outop_muluh = { 3110 .base.static_constraint = C_O1_I2(r, r, r), 3111 .out_rrr = tgen_muluh, 3112}; 3113 3114static void tgen_nand(TCGContext *s, TCGType type, 3115 TCGReg a0, TCGReg a1, TCGReg a2) 3116{ 3117 tcg_out32(s, NAND | SAB(a1, a0, a2)); 3118} 3119 3120static const TCGOutOpBinary outop_nand = { 3121 .base.static_constraint = C_O1_I2(r, r, r), 3122 .out_rrr = tgen_nand, 3123}; 3124 3125static void tgen_nor(TCGContext *s, TCGType type, 3126 TCGReg a0, TCGReg a1, TCGReg a2) 3127{ 3128 tcg_out32(s, NOR | SAB(a1, a0, a2)); 3129} 3130 3131static const TCGOutOpBinary outop_nor = { 3132 .base.static_constraint = C_O1_I2(r, r, r), 3133 .out_rrr = tgen_nor, 3134}; 3135 3136static void tgen_or(TCGContext *s, TCGType type, 3137 TCGReg a0, TCGReg a1, TCGReg a2) 3138{ 3139 tcg_out32(s, OR | SAB(a1, a0, a2)); 3140} 3141 3142static void tgen_ori(TCGContext *s, TCGType type, 3143 TCGReg a0, TCGReg a1, tcg_target_long a2) 3144{ 3145 tcg_out_ori32(s, a0, a1, a2); 3146} 3147 3148static const TCGOutOpBinary outop_or = { 3149 .base.static_constraint = C_O1_I2(r, r, rU), 3150 .out_rrr = tgen_or, 3151 .out_rri = tgen_ori, 3152}; 3153 3154static void tgen_orc(TCGContext *s, TCGType type, 3155 TCGReg a0, TCGReg a1, TCGReg a2) 3156{ 3157 tcg_out32(s, ORC | SAB(a1, a0, a2)); 3158} 3159 3160static const TCGOutOpBinary outop_orc = { 3161 .base.static_constraint = C_O1_I2(r, r, r), 3162 .out_rrr = tgen_orc, 3163}; 3164 3165static TCGConstraintSetIndex cset_mod(TCGType type, unsigned flags) 3166{ 3167 return have_isa_3_00 ? C_O1_I2(r, r, r) : C_NotImplemented; 3168} 3169 3170static void tgen_rems(TCGContext *s, TCGType type, 3171 TCGReg a0, TCGReg a1, TCGReg a2) 3172{ 3173 uint32_t insn = type == TCG_TYPE_I32 ? MODSW : MODSD; 3174 tcg_out32(s, insn | TAB(a0, a1, a2)); 3175} 3176 3177static const TCGOutOpBinary outop_rems = { 3178 .base.static_constraint = C_Dynamic, 3179 .base.dynamic_constraint = cset_mod, 3180 .out_rrr = tgen_rems, 3181}; 3182 3183static void tgen_remu(TCGContext *s, TCGType type, 3184 TCGReg a0, TCGReg a1, TCGReg a2) 3185{ 3186 uint32_t insn = type == TCG_TYPE_I32 ? MODUW : MODUD; 3187 tcg_out32(s, insn | TAB(a0, a1, a2)); 3188} 3189 3190static const TCGOutOpBinary outop_remu = { 3191 .base.static_constraint = C_Dynamic, 3192 .base.dynamic_constraint = cset_mod, 3193 .out_rrr = tgen_remu, 3194}; 3195 3196static void tgen_rotl(TCGContext *s, TCGType type, 3197 TCGReg a0, TCGReg a1, TCGReg a2) 3198{ 3199 if (type == TCG_TYPE_I32) { 3200 tcg_out32(s, RLWNM | SAB(a1, a0, a2) | MB(0) | ME(31)); 3201 } else { 3202 tcg_out32(s, RLDCL | SAB(a1, a0, a2) | MB64(0)); 3203 } 3204} 3205 3206static void tgen_rotli(TCGContext *s, TCGType type, 3207 TCGReg a0, TCGReg a1, tcg_target_long a2) 3208{ 3209 if (type == TCG_TYPE_I32) { 3210 tcg_out_rlw(s, RLWINM, a0, a1, a2, 0, 31); 3211 } else { 3212 tcg_out_rld(s, RLDICL, a0, a1, a2, 0); 3213 } 3214} 3215 3216static const TCGOutOpBinary outop_rotl = { 3217 .base.static_constraint = C_O1_I2(r, r, ri), 3218 .out_rrr = tgen_rotl, 3219 .out_rri = tgen_rotli, 3220}; 3221 3222static const TCGOutOpBinary outop_rotr = { 3223 .base.static_constraint = C_NotImplemented, 3224}; 3225 3226static void tgen_sar(TCGContext *s, TCGType type, 3227 TCGReg a0, TCGReg a1, TCGReg a2) 3228{ 3229 uint32_t insn = type == TCG_TYPE_I32 ? SRAW : SRAD; 3230 tcg_out32(s, insn | SAB(a1, a0, a2)); 3231} 3232 3233static void tgen_sari(TCGContext *s, TCGType type, 3234 TCGReg a0, TCGReg a1, tcg_target_long a2) 3235{ 3236 /* Limit immediate shift count lest we create an illegal insn. */ 3237 if (type == TCG_TYPE_I32) { 3238 tcg_out_sari32(s, a0, a1, a2 & 31); 3239 } else { 3240 tcg_out_sari64(s, a0, a1, a2 & 63); 3241 } 3242} 3243 3244static const TCGOutOpBinary outop_sar = { 3245 .base.static_constraint = C_O1_I2(r, r, ri), 3246 .out_rrr = tgen_sar, 3247 .out_rri = tgen_sari, 3248}; 3249 3250static void tgen_shl(TCGContext *s, TCGType type, 3251 TCGReg a0, TCGReg a1, TCGReg a2) 3252{ 3253 uint32_t insn = type == TCG_TYPE_I32 ? SLW : SLD; 3254 tcg_out32(s, insn | SAB(a1, a0, a2)); 3255} 3256 3257static void tgen_shli(TCGContext *s, TCGType type, 3258 TCGReg a0, TCGReg a1, tcg_target_long a2) 3259{ 3260 /* Limit immediate shift count lest we create an illegal insn. */ 3261 if (type == TCG_TYPE_I32) { 3262 tcg_out_shli32(s, a0, a1, a2 & 31); 3263 } else { 3264 tcg_out_shli64(s, a0, a1, a2 & 63); 3265 } 3266} 3267 3268static const TCGOutOpBinary outop_shl = { 3269 .base.static_constraint = C_O1_I2(r, r, ri), 3270 .out_rrr = tgen_shl, 3271 .out_rri = tgen_shli, 3272}; 3273 3274static void tgen_shr(TCGContext *s, TCGType type, 3275 TCGReg a0, TCGReg a1, TCGReg a2) 3276{ 3277 uint32_t insn = type == TCG_TYPE_I32 ? SRW : SRD; 3278 tcg_out32(s, insn | SAB(a1, a0, a2)); 3279} 3280 3281static void tgen_shri(TCGContext *s, TCGType type, 3282 TCGReg a0, TCGReg a1, tcg_target_long a2) 3283{ 3284 /* Limit immediate shift count lest we create an illegal insn. */ 3285 if (type == TCG_TYPE_I32) { 3286 tcg_out_shri32(s, a0, a1, a2 & 31); 3287 } else { 3288 tcg_out_shri64(s, a0, a1, a2 & 63); 3289 } 3290} 3291 3292static const TCGOutOpBinary outop_shr = { 3293 .base.static_constraint = C_O1_I2(r, r, ri), 3294 .out_rrr = tgen_shr, 3295 .out_rri = tgen_shri, 3296}; 3297 3298static void tgen_sub(TCGContext *s, TCGType type, 3299 TCGReg a0, TCGReg a1, TCGReg a2) 3300{ 3301 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 3302} 3303 3304static void tgen_subfi(TCGContext *s, TCGType type, 3305 TCGReg a0, tcg_target_long a1, TCGReg a2) 3306{ 3307 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 3308} 3309 3310static const TCGOutOpSubtract outop_sub = { 3311 .base.static_constraint = C_O1_I2(r, rI, r), 3312 .out_rrr = tgen_sub, 3313 .out_rir = tgen_subfi, 3314}; 3315 3316static void tgen_xor(TCGContext *s, TCGType type, 3317 TCGReg a0, TCGReg a1, TCGReg a2) 3318{ 3319 tcg_out32(s, XOR | SAB(a1, a0, a2)); 3320} 3321 3322static void tgen_xori(TCGContext *s, TCGType type, 3323 TCGReg a0, TCGReg a1, tcg_target_long a2) 3324{ 3325 tcg_out_xori32(s, a0, a1, a2); 3326} 3327 3328static const TCGOutOpBinary outop_xor = { 3329 .base.static_constraint = C_O1_I2(r, r, rU), 3330 .out_rrr = tgen_xor, 3331 .out_rri = tgen_xori, 3332}; 3333 3334static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 3335{ 3336 tcg_out32(s, NEG | RT(a0) | RA(a1)); 3337} 3338 3339static const TCGOutOpUnary outop_neg = { 3340 .base.static_constraint = C_O1_I1(r, r), 3341 .out_rr = tgen_neg, 3342}; 3343 3344static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 3345{ 3346 tgen_nor(s, type, a0, a1, a1); 3347} 3348 3349static const TCGOutOpUnary outop_not = { 3350 .base.static_constraint = C_O1_I1(r, r), 3351 .out_rr = tgen_not, 3352}; 3353 3354 3355static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 3356 const TCGArg args[TCG_MAX_OP_ARGS], 3357 const int const_args[TCG_MAX_OP_ARGS]) 3358{ 3359 TCGArg a0, a1; 3360 3361 switch (opc) { 3362 case INDEX_op_goto_ptr: 3363 tcg_out32(s, MTSPR | RS(args[0]) | CTR); 3364 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); 3365 tcg_out32(s, BCCTR | BO_ALWAYS); 3366 break; 3367 case INDEX_op_br: 3368 { 3369 TCGLabel *l = arg_label(args[0]); 3370 uint32_t insn = B; 3371 3372 if (l->has_value) { 3373 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr), 3374 l->u.value_ptr); 3375 } else { 3376 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); 3377 } 3378 tcg_out32(s, insn); 3379 } 3380 break; 3381 case INDEX_op_ld8u_i32: 3382 case INDEX_op_ld8u_i64: 3383 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 3384 break; 3385 case INDEX_op_ld8s_i32: 3386 case INDEX_op_ld8s_i64: 3387 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 3388 tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]); 3389 break; 3390 case INDEX_op_ld16u_i32: 3391 case INDEX_op_ld16u_i64: 3392 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); 3393 break; 3394 case INDEX_op_ld16s_i32: 3395 case INDEX_op_ld16s_i64: 3396 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); 3397 break; 3398 case INDEX_op_ld_i32: 3399 case INDEX_op_ld32u_i64: 3400 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); 3401 break; 3402 case INDEX_op_ld32s_i64: 3403 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); 3404 break; 3405 case INDEX_op_ld_i64: 3406 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); 3407 break; 3408 case INDEX_op_st8_i32: 3409 case INDEX_op_st8_i64: 3410 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); 3411 break; 3412 case INDEX_op_st16_i32: 3413 case INDEX_op_st16_i64: 3414 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); 3415 break; 3416 case INDEX_op_st_i32: 3417 case INDEX_op_st32_i64: 3418 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); 3419 break; 3420 case INDEX_op_st_i64: 3421 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); 3422 break; 3423 3424 case INDEX_op_brcond_i32: 3425 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 3426 arg_label(args[3]), TCG_TYPE_I32); 3427 break; 3428 case INDEX_op_brcond_i64: 3429 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 3430 arg_label(args[3]), TCG_TYPE_I64); 3431 break; 3432 case INDEX_op_brcond2_i32: 3433 tcg_out_brcond2(s, args, const_args); 3434 break; 3435 3436 case INDEX_op_qemu_ld_i32: 3437 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 3438 break; 3439 case INDEX_op_qemu_ld_i64: 3440 if (TCG_TARGET_REG_BITS == 64) { 3441 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], TCG_TYPE_I64); 3442 } else { 3443 tcg_out_qemu_ld(s, args[0], args[1], args[2], 3444 args[3], TCG_TYPE_I64); 3445 } 3446 break; 3447 case INDEX_op_qemu_ld_i128: 3448 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3449 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 3450 break; 3451 3452 case INDEX_op_qemu_st_i32: 3453 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I32); 3454 break; 3455 case INDEX_op_qemu_st_i64: 3456 if (TCG_TARGET_REG_BITS == 64) { 3457 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], TCG_TYPE_I64); 3458 } else { 3459 tcg_out_qemu_st(s, args[0], args[1], args[2], 3460 args[3], TCG_TYPE_I64); 3461 } 3462 break; 3463 case INDEX_op_qemu_st_i128: 3464 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3465 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 3466 break; 3467 3468 case INDEX_op_setcond_i32: 3469 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], 3470 const_args[2], false); 3471 break; 3472 case INDEX_op_setcond_i64: 3473 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], 3474 const_args[2], false); 3475 break; 3476 case INDEX_op_negsetcond_i32: 3477 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], 3478 const_args[2], true); 3479 break; 3480 case INDEX_op_negsetcond_i64: 3481 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], 3482 const_args[2], true); 3483 break; 3484 case INDEX_op_setcond2_i32: 3485 tcg_out_setcond2(s, args, const_args); 3486 break; 3487 3488 case INDEX_op_bswap16_i32: 3489 case INDEX_op_bswap16_i64: 3490 tcg_out_bswap16(s, args[0], args[1], args[2]); 3491 break; 3492 case INDEX_op_bswap32_i32: 3493 tcg_out_bswap32(s, args[0], args[1], 0); 3494 break; 3495 case INDEX_op_bswap32_i64: 3496 tcg_out_bswap32(s, args[0], args[1], args[2]); 3497 break; 3498 case INDEX_op_bswap64_i64: 3499 tcg_out_bswap64(s, args[0], args[1]); 3500 break; 3501 3502 case INDEX_op_deposit_i32: 3503 if (const_args[2]) { 3504 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; 3505 tcg_out_andi32(s, args[0], args[0], ~mask); 3506 } else { 3507 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], 3508 32 - args[3] - args[4], 31 - args[3]); 3509 } 3510 break; 3511 case INDEX_op_deposit_i64: 3512 if (const_args[2]) { 3513 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; 3514 tcg_out_andi64(s, args[0], args[0], ~mask); 3515 } else { 3516 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], 3517 64 - args[3] - args[4]); 3518 } 3519 break; 3520 3521 case INDEX_op_extract_i32: 3522 if (args[2] == 0 && args[3] <= 16) { 3523 tcg_out32(s, ANDI | SAI(args[1], args[0], (1 << args[3]) - 1)); 3524 break; 3525 } 3526 tcg_out_rlw(s, RLWINM, args[0], args[1], 3527 32 - args[2], 32 - args[3], 31); 3528 break; 3529 case INDEX_op_extract_i64: 3530 if (args[2] == 0 && args[3] <= 16) { 3531 tcg_out32(s, ANDI | SAI(args[1], args[0], (1 << args[3]) - 1)); 3532 break; 3533 } 3534 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); 3535 break; 3536 3537 case INDEX_op_sextract_i64: 3538 if (args[2] + args[3] == 32) { 3539 if (args[2] == 0) { 3540 tcg_out_ext32s(s, args[0], args[1]); 3541 } else { 3542 tcg_out_sari32(s, args[0], args[1], args[2]); 3543 } 3544 break; 3545 } 3546 /* FALLTHRU */ 3547 case INDEX_op_sextract_i32: 3548 if (args[2] == 0 && args[3] == 8) { 3549 tcg_out_ext8s(s, TCG_TYPE_I32, args[0], args[1]); 3550 } else if (args[2] == 0 && args[3] == 16) { 3551 tcg_out_ext16s(s, TCG_TYPE_I32, args[0], args[1]); 3552 } else { 3553 g_assert_not_reached(); 3554 } 3555 break; 3556 3557 case INDEX_op_movcond_i32: 3558 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], 3559 args[3], args[4], const_args[2]); 3560 break; 3561 case INDEX_op_movcond_i64: 3562 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], 3563 args[3], args[4], const_args[2]); 3564 break; 3565 3566#if TCG_TARGET_REG_BITS == 64 3567 case INDEX_op_add2_i64: 3568#else 3569 case INDEX_op_add2_i32: 3570#endif 3571 /* Note that the CA bit is defined based on the word size of the 3572 environment. So in 64-bit mode it's always carry-out of bit 63. 3573 The fallback code using deposit works just as well for 32-bit. */ 3574 a0 = args[0], a1 = args[1]; 3575 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { 3576 a0 = TCG_REG_R0; 3577 } 3578 if (const_args[4]) { 3579 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); 3580 } else { 3581 tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); 3582 } 3583 if (const_args[5]) { 3584 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); 3585 } else { 3586 tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); 3587 } 3588 if (a0 != args[0]) { 3589 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3590 } 3591 break; 3592 3593#if TCG_TARGET_REG_BITS == 64 3594 case INDEX_op_sub2_i64: 3595#else 3596 case INDEX_op_sub2_i32: 3597#endif 3598 a0 = args[0], a1 = args[1]; 3599 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { 3600 a0 = TCG_REG_R0; 3601 } 3602 if (const_args[2]) { 3603 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); 3604 } else { 3605 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); 3606 } 3607 if (const_args[3]) { 3608 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); 3609 } else { 3610 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); 3611 } 3612 if (a0 != args[0]) { 3613 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3614 } 3615 break; 3616 3617 case INDEX_op_mb: 3618 tcg_out_mb(s, args[0]); 3619 break; 3620 3621 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3622 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3623 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3624 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 3625 case INDEX_op_extu_i32_i64: 3626 case INDEX_op_extrl_i64_i32: 3627 default: 3628 g_assert_not_reached(); 3629 } 3630} 3631 3632int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3633{ 3634 switch (opc) { 3635 case INDEX_op_and_vec: 3636 case INDEX_op_or_vec: 3637 case INDEX_op_xor_vec: 3638 case INDEX_op_andc_vec: 3639 case INDEX_op_not_vec: 3640 case INDEX_op_nor_vec: 3641 case INDEX_op_eqv_vec: 3642 case INDEX_op_nand_vec: 3643 return 1; 3644 case INDEX_op_orc_vec: 3645 return have_isa_2_07; 3646 case INDEX_op_add_vec: 3647 case INDEX_op_sub_vec: 3648 case INDEX_op_smax_vec: 3649 case INDEX_op_smin_vec: 3650 case INDEX_op_umax_vec: 3651 case INDEX_op_umin_vec: 3652 case INDEX_op_shlv_vec: 3653 case INDEX_op_shrv_vec: 3654 case INDEX_op_sarv_vec: 3655 case INDEX_op_rotlv_vec: 3656 return vece <= MO_32 || have_isa_2_07; 3657 case INDEX_op_ssadd_vec: 3658 case INDEX_op_sssub_vec: 3659 case INDEX_op_usadd_vec: 3660 case INDEX_op_ussub_vec: 3661 return vece <= MO_32; 3662 case INDEX_op_shli_vec: 3663 case INDEX_op_shri_vec: 3664 case INDEX_op_sari_vec: 3665 case INDEX_op_rotli_vec: 3666 return vece <= MO_32 || have_isa_2_07 ? -1 : 0; 3667 case INDEX_op_cmp_vec: 3668 case INDEX_op_cmpsel_vec: 3669 return vece <= MO_32 || have_isa_2_07 ? 1 : 0; 3670 case INDEX_op_neg_vec: 3671 return vece >= MO_32 && have_isa_3_00; 3672 case INDEX_op_mul_vec: 3673 switch (vece) { 3674 case MO_8: 3675 case MO_16: 3676 return -1; 3677 case MO_32: 3678 return have_isa_2_07 ? 1 : -1; 3679 case MO_64: 3680 return have_isa_3_10; 3681 } 3682 return 0; 3683 case INDEX_op_bitsel_vec: 3684 return have_vsx; 3685 case INDEX_op_rotrv_vec: 3686 return -1; 3687 default: 3688 return 0; 3689 } 3690} 3691 3692static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 3693 TCGReg dst, TCGReg src) 3694{ 3695 tcg_debug_assert(dst >= TCG_REG_V0); 3696 3697 /* Splat from integer reg allowed via constraints for v3.00. */ 3698 if (src < TCG_REG_V0) { 3699 tcg_debug_assert(have_isa_3_00); 3700 switch (vece) { 3701 case MO_64: 3702 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); 3703 return true; 3704 case MO_32: 3705 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); 3706 return true; 3707 default: 3708 /* Fail, so that we fall back on either dupm or mov+dup. */ 3709 return false; 3710 } 3711 } 3712 3713 /* 3714 * Recall we use (or emulate) VSX integer loads, so the integer is 3715 * right justified within the left (zero-index) double-word. 3716 */ 3717 switch (vece) { 3718 case MO_8: 3719 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); 3720 break; 3721 case MO_16: 3722 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); 3723 break; 3724 case MO_32: 3725 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); 3726 break; 3727 case MO_64: 3728 if (have_vsx) { 3729 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); 3730 break; 3731 } 3732 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); 3733 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); 3734 break; 3735 default: 3736 g_assert_not_reached(); 3737 } 3738 return true; 3739} 3740 3741static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 3742 TCGReg out, TCGReg base, intptr_t offset) 3743{ 3744 int elt; 3745 3746 tcg_debug_assert(out >= TCG_REG_V0); 3747 switch (vece) { 3748 case MO_8: 3749 if (have_isa_3_00) { 3750 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); 3751 } else { 3752 tcg_out_mem_long(s, 0, LVEBX, out, base, offset); 3753 } 3754 elt = extract32(offset, 0, 4); 3755#if !HOST_BIG_ENDIAN 3756 elt ^= 15; 3757#endif 3758 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); 3759 break; 3760 case MO_16: 3761 tcg_debug_assert((offset & 1) == 0); 3762 if (have_isa_3_00) { 3763 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); 3764 } else { 3765 tcg_out_mem_long(s, 0, LVEHX, out, base, offset); 3766 } 3767 elt = extract32(offset, 1, 3); 3768#if !HOST_BIG_ENDIAN 3769 elt ^= 7; 3770#endif 3771 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); 3772 break; 3773 case MO_32: 3774 if (have_isa_3_00) { 3775 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); 3776 break; 3777 } 3778 tcg_debug_assert((offset & 3) == 0); 3779 tcg_out_mem_long(s, 0, LVEWX, out, base, offset); 3780 elt = extract32(offset, 2, 2); 3781#if !HOST_BIG_ENDIAN 3782 elt ^= 3; 3783#endif 3784 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); 3785 break; 3786 case MO_64: 3787 if (have_vsx) { 3788 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); 3789 break; 3790 } 3791 tcg_debug_assert((offset & 7) == 0); 3792 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); 3793 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); 3794 elt = extract32(offset, 3, 1); 3795#if !HOST_BIG_ENDIAN 3796 elt = !elt; 3797#endif 3798 if (elt) { 3799 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); 3800 } else { 3801 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); 3802 } 3803 break; 3804 default: 3805 g_assert_not_reached(); 3806 } 3807 return true; 3808} 3809 3810static void tcg_out_not_vec(TCGContext *s, TCGReg a0, TCGReg a1) 3811{ 3812 tcg_out32(s, VNOR | VRT(a0) | VRA(a1) | VRB(a1)); 3813} 3814 3815static void tcg_out_or_vec(TCGContext *s, TCGReg a0, TCGReg a1, TCGReg a2) 3816{ 3817 tcg_out32(s, VOR | VRT(a0) | VRA(a1) | VRB(a2)); 3818} 3819 3820static void tcg_out_orc_vec(TCGContext *s, TCGReg a0, TCGReg a1, TCGReg a2) 3821{ 3822 tcg_out32(s, VORC | VRT(a0) | VRA(a1) | VRB(a2)); 3823} 3824 3825static void tcg_out_and_vec(TCGContext *s, TCGReg a0, TCGReg a1, TCGReg a2) 3826{ 3827 tcg_out32(s, VAND | VRT(a0) | VRA(a1) | VRB(a2)); 3828} 3829 3830static void tcg_out_andc_vec(TCGContext *s, TCGReg a0, TCGReg a1, TCGReg a2) 3831{ 3832 tcg_out32(s, VANDC | VRT(a0) | VRA(a1) | VRB(a2)); 3833} 3834 3835static void tcg_out_bitsel_vec(TCGContext *s, TCGReg d, 3836 TCGReg c, TCGReg t, TCGReg f) 3837{ 3838 if (TCG_TARGET_HAS_bitsel_vec) { 3839 tcg_out32(s, XXSEL | VRT(d) | VRC(c) | VRB(t) | VRA(f)); 3840 } else { 3841 tcg_out_and_vec(s, TCG_VEC_TMP2, t, c); 3842 tcg_out_andc_vec(s, d, f, c); 3843 tcg_out_or_vec(s, d, d, TCG_VEC_TMP2); 3844 } 3845} 3846 3847static bool tcg_out_cmp_vec_noinv(TCGContext *s, unsigned vece, TCGReg a0, 3848 TCGReg a1, TCGReg a2, TCGCond cond) 3849{ 3850 static const uint32_t 3851 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, 3852 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, 3853 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, 3854 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }; 3855 uint32_t insn; 3856 3857 bool need_swap = false, need_inv = false; 3858 3859 tcg_debug_assert(vece <= MO_32 || have_isa_2_07); 3860 3861 switch (cond) { 3862 case TCG_COND_EQ: 3863 case TCG_COND_GT: 3864 case TCG_COND_GTU: 3865 break; 3866 case TCG_COND_NE: 3867 if (have_isa_3_00 && vece <= MO_32) { 3868 break; 3869 } 3870 /* fall through */ 3871 case TCG_COND_LE: 3872 case TCG_COND_LEU: 3873 need_inv = true; 3874 break; 3875 case TCG_COND_LT: 3876 case TCG_COND_LTU: 3877 need_swap = true; 3878 break; 3879 case TCG_COND_GE: 3880 case TCG_COND_GEU: 3881 need_swap = need_inv = true; 3882 break; 3883 default: 3884 g_assert_not_reached(); 3885 } 3886 3887 if (need_inv) { 3888 cond = tcg_invert_cond(cond); 3889 } 3890 if (need_swap) { 3891 TCGReg swap = a1; 3892 a1 = a2; 3893 a2 = swap; 3894 cond = tcg_swap_cond(cond); 3895 } 3896 3897 switch (cond) { 3898 case TCG_COND_EQ: 3899 insn = eq_op[vece]; 3900 break; 3901 case TCG_COND_NE: 3902 insn = ne_op[vece]; 3903 break; 3904 case TCG_COND_GT: 3905 insn = gts_op[vece]; 3906 break; 3907 case TCG_COND_GTU: 3908 insn = gtu_op[vece]; 3909 break; 3910 default: 3911 g_assert_not_reached(); 3912 } 3913 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); 3914 3915 return need_inv; 3916} 3917 3918static void tcg_out_cmp_vec(TCGContext *s, unsigned vece, TCGReg a0, 3919 TCGReg a1, TCGReg a2, TCGCond cond) 3920{ 3921 if (tcg_out_cmp_vec_noinv(s, vece, a0, a1, a2, cond)) { 3922 tcg_out_not_vec(s, a0, a0); 3923 } 3924} 3925 3926static void tcg_out_cmpsel_vec(TCGContext *s, unsigned vece, TCGReg a0, 3927 TCGReg c1, TCGReg c2, TCGArg v3, int const_v3, 3928 TCGReg v4, TCGCond cond) 3929{ 3930 bool inv = tcg_out_cmp_vec_noinv(s, vece, TCG_VEC_TMP1, c1, c2, cond); 3931 3932 if (!const_v3) { 3933 if (inv) { 3934 tcg_out_bitsel_vec(s, a0, TCG_VEC_TMP1, v4, v3); 3935 } else { 3936 tcg_out_bitsel_vec(s, a0, TCG_VEC_TMP1, v3, v4); 3937 } 3938 } else if (v3) { 3939 if (inv) { 3940 tcg_out_orc_vec(s, a0, v4, TCG_VEC_TMP1); 3941 } else { 3942 tcg_out_or_vec(s, a0, v4, TCG_VEC_TMP1); 3943 } 3944 } else { 3945 if (inv) { 3946 tcg_out_and_vec(s, a0, v4, TCG_VEC_TMP1); 3947 } else { 3948 tcg_out_andc_vec(s, a0, v4, TCG_VEC_TMP1); 3949 } 3950 } 3951} 3952 3953static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3954 unsigned vecl, unsigned vece, 3955 const TCGArg args[TCG_MAX_OP_ARGS], 3956 const int const_args[TCG_MAX_OP_ARGS]) 3957{ 3958 static const uint32_t 3959 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, 3960 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, 3961 mul_op[4] = { 0, 0, VMULUWM, VMULLD }, 3962 neg_op[4] = { 0, 0, VNEGW, VNEGD }, 3963 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, 3964 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, 3965 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, 3966 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, 3967 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, 3968 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, 3969 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, 3970 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, 3971 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD }, 3972 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD }, 3973 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD }, 3974 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 }, 3975 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 }, 3976 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 }, 3977 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 }, 3978 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 }, 3979 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD }; 3980 3981 TCGType type = vecl + TCG_TYPE_V64; 3982 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3983 uint32_t insn; 3984 3985 switch (opc) { 3986 case INDEX_op_ld_vec: 3987 tcg_out_ld(s, type, a0, a1, a2); 3988 return; 3989 case INDEX_op_st_vec: 3990 tcg_out_st(s, type, a0, a1, a2); 3991 return; 3992 case INDEX_op_dupm_vec: 3993 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3994 return; 3995 3996 case INDEX_op_add_vec: 3997 insn = add_op[vece]; 3998 break; 3999 case INDEX_op_sub_vec: 4000 insn = sub_op[vece]; 4001 break; 4002 case INDEX_op_neg_vec: 4003 insn = neg_op[vece]; 4004 a2 = a1; 4005 a1 = 0; 4006 break; 4007 case INDEX_op_mul_vec: 4008 insn = mul_op[vece]; 4009 break; 4010 case INDEX_op_ssadd_vec: 4011 insn = ssadd_op[vece]; 4012 break; 4013 case INDEX_op_sssub_vec: 4014 insn = sssub_op[vece]; 4015 break; 4016 case INDEX_op_usadd_vec: 4017 insn = usadd_op[vece]; 4018 break; 4019 case INDEX_op_ussub_vec: 4020 insn = ussub_op[vece]; 4021 break; 4022 case INDEX_op_smin_vec: 4023 insn = smin_op[vece]; 4024 break; 4025 case INDEX_op_umin_vec: 4026 insn = umin_op[vece]; 4027 break; 4028 case INDEX_op_smax_vec: 4029 insn = smax_op[vece]; 4030 break; 4031 case INDEX_op_umax_vec: 4032 insn = umax_op[vece]; 4033 break; 4034 case INDEX_op_shlv_vec: 4035 insn = shlv_op[vece]; 4036 break; 4037 case INDEX_op_shrv_vec: 4038 insn = shrv_op[vece]; 4039 break; 4040 case INDEX_op_sarv_vec: 4041 insn = sarv_op[vece]; 4042 break; 4043 case INDEX_op_and_vec: 4044 tcg_out_and_vec(s, a0, a1, a2); 4045 return; 4046 case INDEX_op_or_vec: 4047 tcg_out_or_vec(s, a0, a1, a2); 4048 return; 4049 case INDEX_op_xor_vec: 4050 insn = VXOR; 4051 break; 4052 case INDEX_op_andc_vec: 4053 tcg_out_andc_vec(s, a0, a1, a2); 4054 return; 4055 case INDEX_op_not_vec: 4056 tcg_out_not_vec(s, a0, a1); 4057 return; 4058 case INDEX_op_orc_vec: 4059 tcg_out_orc_vec(s, a0, a1, a2); 4060 return; 4061 case INDEX_op_nand_vec: 4062 insn = VNAND; 4063 break; 4064 case INDEX_op_nor_vec: 4065 insn = VNOR; 4066 break; 4067 case INDEX_op_eqv_vec: 4068 insn = VEQV; 4069 break; 4070 4071 case INDEX_op_cmp_vec: 4072 tcg_out_cmp_vec(s, vece, a0, a1, a2, args[3]); 4073 return; 4074 case INDEX_op_cmpsel_vec: 4075 tcg_out_cmpsel_vec(s, vece, a0, a1, a2, 4076 args[3], const_args[3], args[4], args[5]); 4077 return; 4078 case INDEX_op_bitsel_vec: 4079 tcg_out_bitsel_vec(s, a0, a1, a2, args[3]); 4080 return; 4081 4082 case INDEX_op_dup2_vec: 4083 assert(TCG_TARGET_REG_BITS == 32); 4084 /* With inputs a1 = xLxx, a2 = xHxx */ 4085 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ 4086 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ 4087 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ 4088 return; 4089 4090 case INDEX_op_ppc_mrgh_vec: 4091 insn = mrgh_op[vece]; 4092 break; 4093 case INDEX_op_ppc_mrgl_vec: 4094 insn = mrgl_op[vece]; 4095 break; 4096 case INDEX_op_ppc_muleu_vec: 4097 insn = muleu_op[vece]; 4098 break; 4099 case INDEX_op_ppc_mulou_vec: 4100 insn = mulou_op[vece]; 4101 break; 4102 case INDEX_op_ppc_pkum_vec: 4103 insn = pkum_op[vece]; 4104 break; 4105 case INDEX_op_rotlv_vec: 4106 insn = rotl_op[vece]; 4107 break; 4108 case INDEX_op_ppc_msum_vec: 4109 tcg_debug_assert(vece == MO_16); 4110 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])); 4111 return; 4112 4113 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 4114 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 4115 default: 4116 g_assert_not_reached(); 4117 } 4118 4119 tcg_debug_assert(insn != 0); 4120 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); 4121} 4122 4123static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, 4124 TCGv_vec v1, TCGArg imm, TCGOpcode opci) 4125{ 4126 TCGv_vec t1; 4127 4128 if (vece == MO_32) { 4129 /* 4130 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 4131 * So using negative numbers gets us the 4th bit easily. 4132 */ 4133 imm = sextract32(imm, 0, 5); 4134 } else { 4135 imm &= (8 << vece) - 1; 4136 } 4137 4138 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ 4139 t1 = tcg_constant_vec(type, MO_8, imm); 4140 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), 4141 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 4142} 4143 4144static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, 4145 TCGv_vec v1, TCGv_vec v2) 4146{ 4147 TCGv_vec t1 = tcg_temp_new_vec(type); 4148 TCGv_vec t2 = tcg_temp_new_vec(type); 4149 TCGv_vec c0, c16; 4150 4151 switch (vece) { 4152 case MO_8: 4153 case MO_16: 4154 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), 4155 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 4156 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), 4157 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 4158 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), 4159 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 4160 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), 4161 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 4162 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), 4163 tcgv_vec_arg(v0), tcgv_vec_arg(t1)); 4164 break; 4165 4166 case MO_32: 4167 tcg_debug_assert(!have_isa_2_07); 4168 /* 4169 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 4170 * So using -16 is a quick way to represent 16. 4171 */ 4172 c16 = tcg_constant_vec(type, MO_8, -16); 4173 c0 = tcg_constant_vec(type, MO_8, 0); 4174 4175 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), 4176 tcgv_vec_arg(v2), tcgv_vec_arg(c16)); 4177 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), 4178 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 4179 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), 4180 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); 4181 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), 4182 tcgv_vec_arg(t1), tcgv_vec_arg(c16)); 4183 tcg_gen_add_vec(MO_32, v0, t1, t2); 4184 break; 4185 4186 default: 4187 g_assert_not_reached(); 4188 } 4189 tcg_temp_free_vec(t1); 4190 tcg_temp_free_vec(t2); 4191} 4192 4193void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 4194 TCGArg a0, ...) 4195{ 4196 va_list va; 4197 TCGv_vec v0, v1, v2, t0; 4198 TCGArg a2; 4199 4200 va_start(va, a0); 4201 v0 = temp_tcgv_vec(arg_temp(a0)); 4202 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 4203 a2 = va_arg(va, TCGArg); 4204 4205 switch (opc) { 4206 case INDEX_op_shli_vec: 4207 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); 4208 break; 4209 case INDEX_op_shri_vec: 4210 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); 4211 break; 4212 case INDEX_op_sari_vec: 4213 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); 4214 break; 4215 case INDEX_op_rotli_vec: 4216 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); 4217 break; 4218 case INDEX_op_mul_vec: 4219 v2 = temp_tcgv_vec(arg_temp(a2)); 4220 expand_vec_mul(type, vece, v0, v1, v2); 4221 break; 4222 case INDEX_op_rotlv_vec: 4223 v2 = temp_tcgv_vec(arg_temp(a2)); 4224 t0 = tcg_temp_new_vec(type); 4225 tcg_gen_neg_vec(vece, t0, v2); 4226 tcg_gen_rotlv_vec(vece, v0, v1, t0); 4227 tcg_temp_free_vec(t0); 4228 break; 4229 default: 4230 g_assert_not_reached(); 4231 } 4232 va_end(va); 4233} 4234 4235static TCGConstraintSetIndex 4236tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 4237{ 4238 switch (op) { 4239 case INDEX_op_goto_ptr: 4240 return C_O0_I1(r); 4241 4242 case INDEX_op_ld8u_i32: 4243 case INDEX_op_ld8s_i32: 4244 case INDEX_op_ld16u_i32: 4245 case INDEX_op_ld16s_i32: 4246 case INDEX_op_ld_i32: 4247 case INDEX_op_bswap16_i32: 4248 case INDEX_op_bswap32_i32: 4249 case INDEX_op_extract_i32: 4250 case INDEX_op_sextract_i32: 4251 case INDEX_op_ld8u_i64: 4252 case INDEX_op_ld8s_i64: 4253 case INDEX_op_ld16u_i64: 4254 case INDEX_op_ld16s_i64: 4255 case INDEX_op_ld32u_i64: 4256 case INDEX_op_ld32s_i64: 4257 case INDEX_op_ld_i64: 4258 case INDEX_op_ext_i32_i64: 4259 case INDEX_op_extu_i32_i64: 4260 case INDEX_op_bswap16_i64: 4261 case INDEX_op_bswap32_i64: 4262 case INDEX_op_bswap64_i64: 4263 case INDEX_op_extract_i64: 4264 case INDEX_op_sextract_i64: 4265 return C_O1_I1(r, r); 4266 4267 case INDEX_op_st8_i32: 4268 case INDEX_op_st16_i32: 4269 case INDEX_op_st_i32: 4270 case INDEX_op_st8_i64: 4271 case INDEX_op_st16_i64: 4272 case INDEX_op_st32_i64: 4273 case INDEX_op_st_i64: 4274 return C_O0_I2(r, r); 4275 4276 case INDEX_op_brcond_i32: 4277 case INDEX_op_brcond_i64: 4278 return C_O0_I2(r, rC); 4279 case INDEX_op_setcond_i32: 4280 case INDEX_op_setcond_i64: 4281 case INDEX_op_negsetcond_i32: 4282 case INDEX_op_negsetcond_i64: 4283 return C_O1_I2(r, r, rC); 4284 case INDEX_op_movcond_i32: 4285 case INDEX_op_movcond_i64: 4286 return C_O1_I4(r, r, rC, rZ, rZ); 4287 4288 case INDEX_op_deposit_i32: 4289 case INDEX_op_deposit_i64: 4290 return C_O1_I2(r, 0, rZ); 4291 case INDEX_op_brcond2_i32: 4292 return C_O0_I4(r, r, ri, ri); 4293 case INDEX_op_setcond2_i32: 4294 return C_O1_I4(r, r, r, ri, ri); 4295 case INDEX_op_add2_i64: 4296 case INDEX_op_add2_i32: 4297 return C_O2_I4(r, r, r, r, rI, rZM); 4298 case INDEX_op_sub2_i64: 4299 case INDEX_op_sub2_i32: 4300 return C_O2_I4(r, r, rI, rZM, r, r); 4301 4302 case INDEX_op_qemu_ld_i32: 4303 return C_O1_I1(r, r); 4304 case INDEX_op_qemu_ld_i64: 4305 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 4306 4307 case INDEX_op_qemu_st_i32: 4308 return C_O0_I2(r, r); 4309 case INDEX_op_qemu_st_i64: 4310 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r); 4311 4312 case INDEX_op_qemu_ld_i128: 4313 return C_N1O1_I1(o, m, r); 4314 case INDEX_op_qemu_st_i128: 4315 return C_O0_I3(o, m, r); 4316 4317 case INDEX_op_add_vec: 4318 case INDEX_op_sub_vec: 4319 case INDEX_op_mul_vec: 4320 case INDEX_op_and_vec: 4321 case INDEX_op_or_vec: 4322 case INDEX_op_xor_vec: 4323 case INDEX_op_andc_vec: 4324 case INDEX_op_orc_vec: 4325 case INDEX_op_nor_vec: 4326 case INDEX_op_eqv_vec: 4327 case INDEX_op_nand_vec: 4328 case INDEX_op_cmp_vec: 4329 case INDEX_op_ssadd_vec: 4330 case INDEX_op_sssub_vec: 4331 case INDEX_op_usadd_vec: 4332 case INDEX_op_ussub_vec: 4333 case INDEX_op_smax_vec: 4334 case INDEX_op_smin_vec: 4335 case INDEX_op_umax_vec: 4336 case INDEX_op_umin_vec: 4337 case INDEX_op_shlv_vec: 4338 case INDEX_op_shrv_vec: 4339 case INDEX_op_sarv_vec: 4340 case INDEX_op_rotlv_vec: 4341 case INDEX_op_rotrv_vec: 4342 case INDEX_op_ppc_mrgh_vec: 4343 case INDEX_op_ppc_mrgl_vec: 4344 case INDEX_op_ppc_muleu_vec: 4345 case INDEX_op_ppc_mulou_vec: 4346 case INDEX_op_ppc_pkum_vec: 4347 case INDEX_op_dup2_vec: 4348 return C_O1_I2(v, v, v); 4349 4350 case INDEX_op_not_vec: 4351 case INDEX_op_neg_vec: 4352 return C_O1_I1(v, v); 4353 4354 case INDEX_op_dup_vec: 4355 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); 4356 4357 case INDEX_op_ld_vec: 4358 case INDEX_op_dupm_vec: 4359 return C_O1_I1(v, r); 4360 4361 case INDEX_op_st_vec: 4362 return C_O0_I2(v, r); 4363 4364 case INDEX_op_bitsel_vec: 4365 case INDEX_op_ppc_msum_vec: 4366 return C_O1_I3(v, v, v, v); 4367 case INDEX_op_cmpsel_vec: 4368 return C_O1_I4(v, v, v, vZM, v); 4369 4370 default: 4371 return C_NotImplemented; 4372 } 4373} 4374 4375static void tcg_target_init(TCGContext *s) 4376{ 4377 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 4378 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 4379 if (have_altivec) { 4380 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 4381 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 4382 } 4383 4384 tcg_target_call_clobber_regs = 0; 4385 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 4386 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 4387 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 4388 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 4389 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 4390 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 4391 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); 4392 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 4393 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 4394 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 4395 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 4396 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 4397 4398 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 4399 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 4400 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 4401 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 4402 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 4403 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 4404 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 4405 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 4406 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); 4407 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); 4408 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); 4409 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); 4410 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); 4411 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); 4412 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); 4413 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); 4414 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 4415 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 4416 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 4417 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 4418 4419 s->reserved_regs = 0; 4420 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ 4421 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ 4422#if defined(_CALL_SYSV) 4423 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ 4424#endif 4425#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 4426 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ 4427#endif 4428 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 4429 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 4430 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); 4431 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); 4432 if (USE_REG_TB) { 4433 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ 4434 } 4435} 4436 4437#ifdef __ELF__ 4438typedef struct { 4439 DebugFrameCIE cie; 4440 DebugFrameFDEHeader fde; 4441 uint8_t fde_def_cfa[4]; 4442 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; 4443} DebugFrame; 4444 4445/* We're expecting a 2 byte uleb128 encoded value. */ 4446QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 4447 4448#if TCG_TARGET_REG_BITS == 64 4449# define ELF_HOST_MACHINE EM_PPC64 4450#else 4451# define ELF_HOST_MACHINE EM_PPC 4452#endif 4453 4454static DebugFrame debug_frame = { 4455 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4456 .cie.id = -1, 4457 .cie.version = 1, 4458 .cie.code_align = 1, 4459 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ 4460 .cie.return_column = 65, 4461 4462 /* Total FDE size does not include the "len" member. */ 4463 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), 4464 4465 .fde_def_cfa = { 4466 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ 4467 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4468 (FRAME_SIZE >> 7) 4469 }, 4470 .fde_reg_ofs = { 4471 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ 4472 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, 4473 } 4474}; 4475 4476void tcg_register_jit(const void *buf, size_t buf_size) 4477{ 4478 uint8_t *p = &debug_frame.fde_reg_ofs[3]; 4479 int i; 4480 4481 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { 4482 p[0] = 0x80 + tcg_target_callee_save_regs[i]; 4483 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; 4484 } 4485 4486 debug_frame.fde.func_start = (uintptr_t)buf; 4487 debug_frame.fde.func_len = buf_size; 4488 4489 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4490} 4491#endif /* __ELF__ */ 4492#undef VMULEUB 4493#undef VMULEUH 4494#undef VMULEUW 4495#undef VMULOUB 4496#undef VMULOUH 4497#undef VMULOUW 4498#undef VMSUMUHM 4499