1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26#include "../tcg-pool.c.inc" 27#include "../tcg-ldst.c.inc" 28 29/* 30 * Standardize on the _CALL_FOO symbols used by GCC: 31 * Apple XCode does not define _CALL_DARWIN. 32 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit). 33 */ 34#if !defined(_CALL_SYSV) && \ 35 !defined(_CALL_DARWIN) && \ 36 !defined(_CALL_AIX) && \ 37 !defined(_CALL_ELF) 38# if defined(__APPLE__) 39# define _CALL_DARWIN 40# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32 41# define _CALL_SYSV 42# else 43# error "Unknown ABI" 44# endif 45#endif 46 47#if TCG_TARGET_REG_BITS == 64 48# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 49# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 50#else 51# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 52# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 53#endif 54#ifdef _CALL_SYSV 55# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 56# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 57#else 58# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 59# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 60#endif 61 62/* For some memory operations, we need a scratch that isn't R0. For the AIX 63 calling convention, we can re-use the TOC register since we'll be reloading 64 it at every call. Otherwise R12 will do nicely as neither a call-saved 65 register nor a parameter register. */ 66#ifdef _CALL_AIX 67# define TCG_REG_TMP1 TCG_REG_R2 68#else 69# define TCG_REG_TMP1 TCG_REG_R12 70#endif 71 72#define TCG_VEC_TMP1 TCG_REG_V0 73#define TCG_VEC_TMP2 TCG_REG_V1 74 75#define TCG_REG_TB TCG_REG_R31 76#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) 77 78/* Shorthand for size of a pointer. Avoid promotion to unsigned. */ 79#define SZP ((int)sizeof(void *)) 80 81/* Shorthand for size of a register. */ 82#define SZR (TCG_TARGET_REG_BITS / 8) 83 84#define TCG_CT_CONST_S16 0x100 85#define TCG_CT_CONST_U16 0x200 86#define TCG_CT_CONST_S32 0x400 87#define TCG_CT_CONST_U32 0x800 88#define TCG_CT_CONST_ZERO 0x1000 89#define TCG_CT_CONST_MONE 0x2000 90#define TCG_CT_CONST_WSZ 0x4000 91 92#define ALL_GENERAL_REGS 0xffffffffu 93#define ALL_VECTOR_REGS 0xffffffff00000000ull 94 95#ifdef CONFIG_SOFTMMU 96#define ALL_QLOAD_REGS \ 97 (ALL_GENERAL_REGS & \ 98 ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) 99#define ALL_QSTORE_REGS \ 100 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ 101 (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) 102#else 103#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) 104#define ALL_QSTORE_REGS ALL_QLOAD_REGS 105#endif 106 107TCGPowerISA have_isa; 108static bool have_isel; 109bool have_altivec; 110bool have_vsx; 111 112#ifndef CONFIG_SOFTMMU 113#define TCG_GUEST_BASE_REG 30 114#endif 115 116#ifdef CONFIG_DEBUG_TCG 117static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = { 118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 122 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 123 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 124 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 125 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 126}; 127#endif 128 129static const int tcg_target_reg_alloc_order[] = { 130 TCG_REG_R14, /* call saved registers */ 131 TCG_REG_R15, 132 TCG_REG_R16, 133 TCG_REG_R17, 134 TCG_REG_R18, 135 TCG_REG_R19, 136 TCG_REG_R20, 137 TCG_REG_R21, 138 TCG_REG_R22, 139 TCG_REG_R23, 140 TCG_REG_R24, 141 TCG_REG_R25, 142 TCG_REG_R26, 143 TCG_REG_R27, 144 TCG_REG_R28, 145 TCG_REG_R29, 146 TCG_REG_R30, 147 TCG_REG_R31, 148 TCG_REG_R12, /* call clobbered, non-arguments */ 149 TCG_REG_R11, 150 TCG_REG_R2, 151 TCG_REG_R13, 152 TCG_REG_R10, /* call clobbered, arguments */ 153 TCG_REG_R9, 154 TCG_REG_R8, 155 TCG_REG_R7, 156 TCG_REG_R6, 157 TCG_REG_R5, 158 TCG_REG_R4, 159 TCG_REG_R3, 160 161 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ 162 TCG_REG_V2, /* call clobbered, vectors */ 163 TCG_REG_V3, 164 TCG_REG_V4, 165 TCG_REG_V5, 166 TCG_REG_V6, 167 TCG_REG_V7, 168 TCG_REG_V8, 169 TCG_REG_V9, 170 TCG_REG_V10, 171 TCG_REG_V11, 172 TCG_REG_V12, 173 TCG_REG_V13, 174 TCG_REG_V14, 175 TCG_REG_V15, 176 TCG_REG_V16, 177 TCG_REG_V17, 178 TCG_REG_V18, 179 TCG_REG_V19, 180}; 181 182static const int tcg_target_call_iarg_regs[] = { 183 TCG_REG_R3, 184 TCG_REG_R4, 185 TCG_REG_R5, 186 TCG_REG_R6, 187 TCG_REG_R7, 188 TCG_REG_R8, 189 TCG_REG_R9, 190 TCG_REG_R10 191}; 192 193static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 194{ 195 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 196 tcg_debug_assert(slot >= 0 && slot <= 1); 197 return TCG_REG_R3 + slot; 198} 199 200static const int tcg_target_callee_save_regs[] = { 201#ifdef _CALL_DARWIN 202 TCG_REG_R11, 203#endif 204 TCG_REG_R14, 205 TCG_REG_R15, 206 TCG_REG_R16, 207 TCG_REG_R17, 208 TCG_REG_R18, 209 TCG_REG_R19, 210 TCG_REG_R20, 211 TCG_REG_R21, 212 TCG_REG_R22, 213 TCG_REG_R23, 214 TCG_REG_R24, 215 TCG_REG_R25, 216 TCG_REG_R26, 217 TCG_REG_R27, /* currently used for the global env */ 218 TCG_REG_R28, 219 TCG_REG_R29, 220 TCG_REG_R30, 221 TCG_REG_R31 222}; 223 224static inline bool in_range_b(tcg_target_long target) 225{ 226 return target == sextract64(target, 0, 26); 227} 228 229static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, 230 const tcg_insn_unit *target) 231{ 232 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 233 tcg_debug_assert(in_range_b(disp)); 234 return disp & 0x3fffffc; 235} 236 237static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 238{ 239 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 240 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 241 242 if (in_range_b(disp)) { 243 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc); 244 return true; 245 } 246 return false; 247} 248 249static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, 250 const tcg_insn_unit *target) 251{ 252 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 253 tcg_debug_assert(disp == (int16_t) disp); 254 return disp & 0xfffc; 255} 256 257static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 258{ 259 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 260 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 261 262 if (disp == (int16_t) disp) { 263 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc); 264 return true; 265 } 266 return false; 267} 268 269/* test if a constant matches the constraint */ 270static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 271{ 272 if (ct & TCG_CT_CONST) { 273 return 1; 274 } 275 276 /* The only 32-bit constraint we use aside from 277 TCG_CT_CONST is TCG_CT_CONST_S16. */ 278 if (type == TCG_TYPE_I32) { 279 val = (int32_t)val; 280 } 281 282 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 283 return 1; 284 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 285 return 1; 286 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 287 return 1; 288 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 289 return 1; 290 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 291 return 1; 292 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { 293 return 1; 294 } else if ((ct & TCG_CT_CONST_WSZ) 295 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 296 return 1; 297 } 298 return 0; 299} 300 301#define OPCD(opc) ((opc)<<26) 302#define XO19(opc) (OPCD(19)|((opc)<<1)) 303#define MD30(opc) (OPCD(30)|((opc)<<2)) 304#define MDS30(opc) (OPCD(30)|((opc)<<1)) 305#define XO31(opc) (OPCD(31)|((opc)<<1)) 306#define XO58(opc) (OPCD(58)|(opc)) 307#define XO62(opc) (OPCD(62)|(opc)) 308#define VX4(opc) (OPCD(4)|(opc)) 309 310#define B OPCD( 18) 311#define BC OPCD( 16) 312#define LBZ OPCD( 34) 313#define LHZ OPCD( 40) 314#define LHA OPCD( 42) 315#define LWZ OPCD( 32) 316#define LWZUX XO31( 55) 317#define STB OPCD( 38) 318#define STH OPCD( 44) 319#define STW OPCD( 36) 320 321#define STD XO62( 0) 322#define STDU XO62( 1) 323#define STDX XO31(149) 324 325#define LD XO58( 0) 326#define LDX XO31( 21) 327#define LDU XO58( 1) 328#define LDUX XO31( 53) 329#define LWA XO58( 2) 330#define LWAX XO31(341) 331 332#define ADDIC OPCD( 12) 333#define ADDI OPCD( 14) 334#define ADDIS OPCD( 15) 335#define ORI OPCD( 24) 336#define ORIS OPCD( 25) 337#define XORI OPCD( 26) 338#define XORIS OPCD( 27) 339#define ANDI OPCD( 28) 340#define ANDIS OPCD( 29) 341#define MULLI OPCD( 7) 342#define CMPLI OPCD( 10) 343#define CMPI OPCD( 11) 344#define SUBFIC OPCD( 8) 345 346#define LWZU OPCD( 33) 347#define STWU OPCD( 37) 348 349#define RLWIMI OPCD( 20) 350#define RLWINM OPCD( 21) 351#define RLWNM OPCD( 23) 352 353#define RLDICL MD30( 0) 354#define RLDICR MD30( 1) 355#define RLDIMI MD30( 3) 356#define RLDCL MDS30( 8) 357 358#define BCLR XO19( 16) 359#define BCCTR XO19(528) 360#define CRAND XO19(257) 361#define CRANDC XO19(129) 362#define CRNAND XO19(225) 363#define CROR XO19(449) 364#define CRNOR XO19( 33) 365 366#define EXTSB XO31(954) 367#define EXTSH XO31(922) 368#define EXTSW XO31(986) 369#define ADD XO31(266) 370#define ADDE XO31(138) 371#define ADDME XO31(234) 372#define ADDZE XO31(202) 373#define ADDC XO31( 10) 374#define AND XO31( 28) 375#define SUBF XO31( 40) 376#define SUBFC XO31( 8) 377#define SUBFE XO31(136) 378#define SUBFME XO31(232) 379#define SUBFZE XO31(200) 380#define OR XO31(444) 381#define XOR XO31(316) 382#define MULLW XO31(235) 383#define MULHW XO31( 75) 384#define MULHWU XO31( 11) 385#define DIVW XO31(491) 386#define DIVWU XO31(459) 387#define MODSW XO31(779) 388#define MODUW XO31(267) 389#define CMP XO31( 0) 390#define CMPL XO31( 32) 391#define LHBRX XO31(790) 392#define LWBRX XO31(534) 393#define LDBRX XO31(532) 394#define STHBRX XO31(918) 395#define STWBRX XO31(662) 396#define STDBRX XO31(660) 397#define MFSPR XO31(339) 398#define MTSPR XO31(467) 399#define SRAWI XO31(824) 400#define NEG XO31(104) 401#define MFCR XO31( 19) 402#define MFOCRF (MFCR | (1u << 20)) 403#define NOR XO31(124) 404#define CNTLZW XO31( 26) 405#define CNTLZD XO31( 58) 406#define CNTTZW XO31(538) 407#define CNTTZD XO31(570) 408#define CNTPOPW XO31(378) 409#define CNTPOPD XO31(506) 410#define ANDC XO31( 60) 411#define ORC XO31(412) 412#define EQV XO31(284) 413#define NAND XO31(476) 414#define ISEL XO31( 15) 415 416#define MULLD XO31(233) 417#define MULHD XO31( 73) 418#define MULHDU XO31( 9) 419#define DIVD XO31(489) 420#define DIVDU XO31(457) 421#define MODSD XO31(777) 422#define MODUD XO31(265) 423 424#define LBZX XO31( 87) 425#define LHZX XO31(279) 426#define LHAX XO31(343) 427#define LWZX XO31( 23) 428#define STBX XO31(215) 429#define STHX XO31(407) 430#define STWX XO31(151) 431 432#define EIEIO XO31(854) 433#define HWSYNC XO31(598) 434#define LWSYNC (HWSYNC | (1u << 21)) 435 436#define SPR(a, b) ((((a)<<5)|(b))<<11) 437#define LR SPR(8, 0) 438#define CTR SPR(9, 0) 439 440#define SLW XO31( 24) 441#define SRW XO31(536) 442#define SRAW XO31(792) 443 444#define SLD XO31( 27) 445#define SRD XO31(539) 446#define SRAD XO31(794) 447#define SRADI XO31(413<<1) 448 449#define BRH XO31(219) 450#define BRW XO31(155) 451#define BRD XO31(187) 452 453#define TW XO31( 4) 454#define TRAP (TW | TO(31)) 455 456#define NOP ORI /* ori 0,0,0 */ 457 458#define LVX XO31(103) 459#define LVEBX XO31(7) 460#define LVEHX XO31(39) 461#define LVEWX XO31(71) 462#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */ 463#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */ 464#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */ 465#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */ 466#define LXSD (OPCD(57) | 2) /* v3.00 */ 467#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */ 468 469#define STVX XO31(231) 470#define STVEWX XO31(199) 471#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */ 472#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */ 473#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */ 474#define STXSD (OPCD(61) | 2) /* v3.00 */ 475 476#define VADDSBS VX4(768) 477#define VADDUBS VX4(512) 478#define VADDUBM VX4(0) 479#define VADDSHS VX4(832) 480#define VADDUHS VX4(576) 481#define VADDUHM VX4(64) 482#define VADDSWS VX4(896) 483#define VADDUWS VX4(640) 484#define VADDUWM VX4(128) 485#define VADDUDM VX4(192) /* v2.07 */ 486 487#define VSUBSBS VX4(1792) 488#define VSUBUBS VX4(1536) 489#define VSUBUBM VX4(1024) 490#define VSUBSHS VX4(1856) 491#define VSUBUHS VX4(1600) 492#define VSUBUHM VX4(1088) 493#define VSUBSWS VX4(1920) 494#define VSUBUWS VX4(1664) 495#define VSUBUWM VX4(1152) 496#define VSUBUDM VX4(1216) /* v2.07 */ 497 498#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ 499#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ 500 501#define VMAXSB VX4(258) 502#define VMAXSH VX4(322) 503#define VMAXSW VX4(386) 504#define VMAXSD VX4(450) /* v2.07 */ 505#define VMAXUB VX4(2) 506#define VMAXUH VX4(66) 507#define VMAXUW VX4(130) 508#define VMAXUD VX4(194) /* v2.07 */ 509#define VMINSB VX4(770) 510#define VMINSH VX4(834) 511#define VMINSW VX4(898) 512#define VMINSD VX4(962) /* v2.07 */ 513#define VMINUB VX4(514) 514#define VMINUH VX4(578) 515#define VMINUW VX4(642) 516#define VMINUD VX4(706) /* v2.07 */ 517 518#define VCMPEQUB VX4(6) 519#define VCMPEQUH VX4(70) 520#define VCMPEQUW VX4(134) 521#define VCMPEQUD VX4(199) /* v2.07 */ 522#define VCMPGTSB VX4(774) 523#define VCMPGTSH VX4(838) 524#define VCMPGTSW VX4(902) 525#define VCMPGTSD VX4(967) /* v2.07 */ 526#define VCMPGTUB VX4(518) 527#define VCMPGTUH VX4(582) 528#define VCMPGTUW VX4(646) 529#define VCMPGTUD VX4(711) /* v2.07 */ 530#define VCMPNEB VX4(7) /* v3.00 */ 531#define VCMPNEH VX4(71) /* v3.00 */ 532#define VCMPNEW VX4(135) /* v3.00 */ 533 534#define VSLB VX4(260) 535#define VSLH VX4(324) 536#define VSLW VX4(388) 537#define VSLD VX4(1476) /* v2.07 */ 538#define VSRB VX4(516) 539#define VSRH VX4(580) 540#define VSRW VX4(644) 541#define VSRD VX4(1732) /* v2.07 */ 542#define VSRAB VX4(772) 543#define VSRAH VX4(836) 544#define VSRAW VX4(900) 545#define VSRAD VX4(964) /* v2.07 */ 546#define VRLB VX4(4) 547#define VRLH VX4(68) 548#define VRLW VX4(132) 549#define VRLD VX4(196) /* v2.07 */ 550 551#define VMULEUB VX4(520) 552#define VMULEUH VX4(584) 553#define VMULEUW VX4(648) /* v2.07 */ 554#define VMULOUB VX4(8) 555#define VMULOUH VX4(72) 556#define VMULOUW VX4(136) /* v2.07 */ 557#define VMULUWM VX4(137) /* v2.07 */ 558#define VMULLD VX4(457) /* v3.10 */ 559#define VMSUMUHM VX4(38) 560 561#define VMRGHB VX4(12) 562#define VMRGHH VX4(76) 563#define VMRGHW VX4(140) 564#define VMRGLB VX4(268) 565#define VMRGLH VX4(332) 566#define VMRGLW VX4(396) 567 568#define VPKUHUM VX4(14) 569#define VPKUWUM VX4(78) 570 571#define VAND VX4(1028) 572#define VANDC VX4(1092) 573#define VNOR VX4(1284) 574#define VOR VX4(1156) 575#define VXOR VX4(1220) 576#define VEQV VX4(1668) /* v2.07 */ 577#define VNAND VX4(1412) /* v2.07 */ 578#define VORC VX4(1348) /* v2.07 */ 579 580#define VSPLTB VX4(524) 581#define VSPLTH VX4(588) 582#define VSPLTW VX4(652) 583#define VSPLTISB VX4(780) 584#define VSPLTISH VX4(844) 585#define VSPLTISW VX4(908) 586 587#define VSLDOI VX4(44) 588 589#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */ 590#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */ 591#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */ 592 593#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */ 594#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */ 595#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */ 596#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */ 597#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */ 598#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */ 599 600#define RT(r) ((r)<<21) 601#define RS(r) ((r)<<21) 602#define RA(r) ((r)<<16) 603#define RB(r) ((r)<<11) 604#define TO(t) ((t)<<21) 605#define SH(s) ((s)<<11) 606#define MB(b) ((b)<<6) 607#define ME(e) ((e)<<1) 608#define BO(o) ((o)<<21) 609#define MB64(b) ((b)<<5) 610#define FXM(b) (1 << (19 - (b))) 611 612#define VRT(r) (((r) & 31) << 21) 613#define VRA(r) (((r) & 31) << 16) 614#define VRB(r) (((r) & 31) << 11) 615#define VRC(r) (((r) & 31) << 6) 616 617#define LK 1 618 619#define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) 620#define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) 621#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) 622#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) 623 624#define BF(n) ((n)<<23) 625#define BI(n, c) (((c)+((n)*4))<<16) 626#define BT(n, c) (((c)+((n)*4))<<21) 627#define BA(n, c) (((c)+((n)*4))<<16) 628#define BB(n, c) (((c)+((n)*4))<<11) 629#define BC_(n, c) (((c)+((n)*4))<<6) 630 631#define BO_COND_TRUE BO(12) 632#define BO_COND_FALSE BO( 4) 633#define BO_ALWAYS BO(20) 634 635enum { 636 CR_LT, 637 CR_GT, 638 CR_EQ, 639 CR_SO 640}; 641 642static const uint32_t tcg_to_bc[] = { 643 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE, 644 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE, 645 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE, 646 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE, 647 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE, 648 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE, 649 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE, 650 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE, 651 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE, 652 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE, 653}; 654 655/* The low bit here is set if the RA and RB fields must be inverted. */ 656static const uint32_t tcg_to_isel[] = { 657 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ), 658 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1, 659 [TCG_COND_LT] = ISEL | BC_(7, CR_LT), 660 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1, 661 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1, 662 [TCG_COND_GT] = ISEL | BC_(7, CR_GT), 663 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT), 664 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1, 665 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1, 666 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), 667}; 668 669static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 670 intptr_t value, intptr_t addend) 671{ 672 const tcg_insn_unit *target; 673 int16_t lo; 674 int32_t hi; 675 676 value += addend; 677 target = (const tcg_insn_unit *)value; 678 679 switch (type) { 680 case R_PPC_REL14: 681 return reloc_pc14(code_ptr, target); 682 case R_PPC_REL24: 683 return reloc_pc24(code_ptr, target); 684 case R_PPC_ADDR16: 685 /* 686 * We are (slightly) abusing this relocation type. In particular, 687 * assert that the low 2 bits are zero, and do not modify them. 688 * That way we can use this with LD et al that have opcode bits 689 * in the low 2 bits of the insn. 690 */ 691 if ((value & 3) || value != (int16_t)value) { 692 return false; 693 } 694 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc); 695 break; 696 case R_PPC_ADDR32: 697 /* 698 * We are abusing this relocation type. Again, this points to 699 * a pair of insns, lis + load. This is an absolute address 700 * relocation for PPC32 so the lis cannot be removed. 701 */ 702 lo = value; 703 hi = value - lo; 704 if (hi + lo != value) { 705 return false; 706 } 707 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); 708 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); 709 break; 710 default: 711 g_assert_not_reached(); 712 } 713 return true; 714} 715 716static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 717 TCGReg base, tcg_target_long offset); 718 719static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 720{ 721 if (ret == arg) { 722 return true; 723 } 724 switch (type) { 725 case TCG_TYPE_I64: 726 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 727 /* fallthru */ 728 case TCG_TYPE_I32: 729 if (ret < TCG_REG_V0) { 730 if (arg < TCG_REG_V0) { 731 tcg_out32(s, OR | SAB(arg, ret, arg)); 732 break; 733 } else if (have_isa_2_07) { 734 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) 735 | VRT(arg) | RA(ret)); 736 break; 737 } else { 738 /* Altivec does not support vector->integer moves. */ 739 return false; 740 } 741 } else if (arg < TCG_REG_V0) { 742 if (have_isa_2_07) { 743 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) 744 | VRT(ret) | RA(arg)); 745 break; 746 } else { 747 /* Altivec does not support integer->vector moves. */ 748 return false; 749 } 750 } 751 /* fallthru */ 752 case TCG_TYPE_V64: 753 case TCG_TYPE_V128: 754 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0); 755 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); 756 break; 757 default: 758 g_assert_not_reached(); 759 } 760 return true; 761} 762 763static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, 764 int sh, int mb) 765{ 766 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 767 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); 768 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); 769 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); 770} 771 772static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, 773 int sh, int mb, int me) 774{ 775 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); 776} 777 778static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 779{ 780 tcg_out32(s, EXTSB | RA(dst) | RS(src)); 781} 782 783static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src) 784{ 785 tcg_out32(s, ANDI | SAI(src, dst, 0xff)); 786} 787 788static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 789{ 790 tcg_out32(s, EXTSH | RA(dst) | RS(src)); 791} 792 793static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src) 794{ 795 tcg_out32(s, ANDI | SAI(src, dst, 0xffff)); 796} 797 798static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) 799{ 800 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 801 tcg_out32(s, EXTSW | RA(dst) | RS(src)); 802} 803 804static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) 805{ 806 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 807 tcg_out_rld(s, RLDICL, dst, src, 0, 32); 808} 809 810static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 811{ 812 tcg_out_ext32s(s, dst, src); 813} 814 815static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 816{ 817 tcg_out_ext32u(s, dst, src); 818} 819 820static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 821{ 822 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 823 tcg_out_mov(s, TCG_TYPE_I32, rd, rn); 824} 825 826static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) 827{ 828 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); 829} 830 831static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) 832{ 833 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); 834} 835 836static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c) 837{ 838 /* Limit immediate shift count lest we create an illegal insn. */ 839 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31)); 840} 841 842static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) 843{ 844 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); 845} 846 847static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) 848{ 849 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); 850} 851 852static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c) 853{ 854 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2)); 855} 856 857static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags) 858{ 859 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 860 861 if (have_isa_3_10) { 862 tcg_out32(s, BRH | RA(dst) | RS(src)); 863 if (flags & TCG_BSWAP_OS) { 864 tcg_out_ext16s(s, TCG_TYPE_REG, dst, dst); 865 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 866 tcg_out_ext16u(s, dst, dst); 867 } 868 return; 869 } 870 871 /* 872 * In the following, 873 * dep(a, b, m) -> (a & ~m) | (b & m) 874 * 875 * Begin with: src = xxxxabcd 876 */ 877 /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */ 878 tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31); 879 /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */ 880 tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23); 881 882 if (flags & TCG_BSWAP_OS) { 883 tcg_out_ext16s(s, TCG_TYPE_REG, dst, tmp); 884 } else { 885 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 886 } 887} 888 889static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags) 890{ 891 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 892 893 if (have_isa_3_10) { 894 tcg_out32(s, BRW | RA(dst) | RS(src)); 895 if (flags & TCG_BSWAP_OS) { 896 tcg_out_ext32s(s, dst, dst); 897 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 898 tcg_out_ext32u(s, dst, dst); 899 } 900 return; 901 } 902 903 /* 904 * Stolen from gcc's builtin_bswap32. 905 * In the following, 906 * dep(a, b, m) -> (a & ~m) | (b & m) 907 * 908 * Begin with: src = xxxxabcd 909 */ 910 /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */ 911 tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31); 912 /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */ 913 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7); 914 /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */ 915 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23); 916 917 if (flags & TCG_BSWAP_OS) { 918 tcg_out_ext32s(s, dst, tmp); 919 } else { 920 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 921 } 922} 923 924static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src) 925{ 926 TCGReg t0 = dst == src ? TCG_REG_R0 : dst; 927 TCGReg t1 = dst == src ? dst : TCG_REG_R0; 928 929 if (have_isa_3_10) { 930 tcg_out32(s, BRD | RA(dst) | RS(src)); 931 return; 932 } 933 934 /* 935 * In the following, 936 * dep(a, b, m) -> (a & ~m) | (b & m) 937 * 938 * Begin with: src = abcdefgh 939 */ 940 /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */ 941 tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31); 942 /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */ 943 tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7); 944 /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */ 945 tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23); 946 947 /* t0 = rol64(t0, 32) = hgfe0000 */ 948 tcg_out_rld(s, RLDICL, t0, t0, 32, 0); 949 /* t1 = rol64(src, 32) = efghabcd */ 950 tcg_out_rld(s, RLDICL, t1, src, 32, 0); 951 952 /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */ 953 tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31); 954 /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */ 955 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7); 956 /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */ 957 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23); 958 959 tcg_out_mov(s, TCG_TYPE_REG, dst, t0); 960} 961 962/* Emit a move into ret of arg, if it can be done in one insn. */ 963static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 964{ 965 if (arg == (int16_t)arg) { 966 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 967 return true; 968 } 969 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 970 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 971 return true; 972 } 973 return false; 974} 975 976static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 977 tcg_target_long arg, bool in_prologue) 978{ 979 intptr_t tb_diff; 980 tcg_target_long tmp; 981 int shift; 982 983 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 984 985 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 986 arg = (int32_t)arg; 987 } 988 989 /* Load 16-bit immediates with one insn. */ 990 if (tcg_out_movi_one(s, ret, arg)) { 991 return; 992 } 993 994 /* Load addresses within the TB with one insn. */ 995 tb_diff = tcg_tbrel_diff(s, (void *)arg); 996 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { 997 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); 998 return; 999 } 1000 1001 /* Load 32-bit immediates with two insns. Note that we've already 1002 eliminated bare ADDIS, so we know both insns are required. */ 1003 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 1004 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 1005 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1006 return; 1007 } 1008 if (arg == (uint32_t)arg && !(arg & 0x8000)) { 1009 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1010 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1011 return; 1012 } 1013 1014 /* Load masked 16-bit value. */ 1015 if (arg > 0 && (arg & 0x8000)) { 1016 tmp = arg | 0x7fff; 1017 if ((tmp & (tmp + 1)) == 0) { 1018 int mb = clz64(tmp + 1) + 1; 1019 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1020 tcg_out_rld(s, RLDICL, ret, ret, 0, mb); 1021 return; 1022 } 1023 } 1024 1025 /* Load common masks with 2 insns. */ 1026 shift = ctz64(arg); 1027 tmp = arg >> shift; 1028 if (tmp == (int16_t)tmp) { 1029 tcg_out32(s, ADDI | TAI(ret, 0, tmp)); 1030 tcg_out_shli64(s, ret, ret, shift); 1031 return; 1032 } 1033 shift = clz64(arg); 1034 if (tcg_out_movi_one(s, ret, arg << shift)) { 1035 tcg_out_shri64(s, ret, ret, shift); 1036 return; 1037 } 1038 1039 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ 1040 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { 1041 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); 1042 return; 1043 } 1044 1045 /* Use the constant pool, if possible. */ 1046 if (!in_prologue && USE_REG_TB) { 1047 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, 1048 tcg_tbrel_diff(s, NULL)); 1049 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); 1050 return; 1051 } 1052 1053 tmp = arg >> 31 >> 1; 1054 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); 1055 if (tmp) { 1056 tcg_out_shli64(s, ret, ret, 32); 1057 } 1058 if (arg & 0xffff0000) { 1059 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1060 } 1061 if (arg & 0xffff) { 1062 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1063 } 1064} 1065 1066static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1067 TCGReg ret, int64_t val) 1068{ 1069 uint32_t load_insn; 1070 int rel, low; 1071 intptr_t add; 1072 1073 switch (vece) { 1074 case MO_8: 1075 low = (int8_t)val; 1076 if (low >= -16 && low < 16) { 1077 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); 1078 return; 1079 } 1080 if (have_isa_3_00) { 1081 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); 1082 return; 1083 } 1084 break; 1085 1086 case MO_16: 1087 low = (int16_t)val; 1088 if (low >= -16 && low < 16) { 1089 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); 1090 return; 1091 } 1092 break; 1093 1094 case MO_32: 1095 low = (int32_t)val; 1096 if (low >= -16 && low < 16) { 1097 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); 1098 return; 1099 } 1100 break; 1101 } 1102 1103 /* 1104 * Otherwise we must load the value from the constant pool. 1105 */ 1106 if (USE_REG_TB) { 1107 rel = R_PPC_ADDR16; 1108 add = tcg_tbrel_diff(s, NULL); 1109 } else { 1110 rel = R_PPC_ADDR32; 1111 add = 0; 1112 } 1113 1114 if (have_vsx) { 1115 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX; 1116 load_insn |= VRT(ret) | RB(TCG_REG_TMP1); 1117 if (TCG_TARGET_REG_BITS == 64) { 1118 new_pool_label(s, val, rel, s->code_ptr, add); 1119 } else { 1120 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); 1121 } 1122 } else { 1123 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); 1124 if (TCG_TARGET_REG_BITS == 64) { 1125 new_pool_l2(s, rel, s->code_ptr, add, val, val); 1126 } else { 1127 new_pool_l4(s, rel, s->code_ptr, add, 1128 val >> 32, val, val >> 32, val); 1129 } 1130 } 1131 1132 if (USE_REG_TB) { 1133 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); 1134 load_insn |= RA(TCG_REG_TB); 1135 } else { 1136 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); 1137 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); 1138 } 1139 tcg_out32(s, load_insn); 1140} 1141 1142static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, 1143 tcg_target_long arg) 1144{ 1145 switch (type) { 1146 case TCG_TYPE_I32: 1147 case TCG_TYPE_I64: 1148 tcg_debug_assert(ret < TCG_REG_V0); 1149 tcg_out_movi_int(s, type, ret, arg, false); 1150 break; 1151 1152 default: 1153 g_assert_not_reached(); 1154 } 1155} 1156 1157static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1158{ 1159 return false; 1160} 1161 1162static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1163 tcg_target_long imm) 1164{ 1165 /* This function is only used for passing structs by reference. */ 1166 g_assert_not_reached(); 1167} 1168 1169static bool mask_operand(uint32_t c, int *mb, int *me) 1170{ 1171 uint32_t lsb, test; 1172 1173 /* Accept a bit pattern like: 1174 0....01....1 1175 1....10....0 1176 0..01..10..0 1177 Keep track of the transitions. */ 1178 if (c == 0 || c == -1) { 1179 return false; 1180 } 1181 test = c; 1182 lsb = test & -test; 1183 test += lsb; 1184 if (test & (test - 1)) { 1185 return false; 1186 } 1187 1188 *me = clz32(lsb); 1189 *mb = test ? clz32(test & -test) + 1 : 0; 1190 return true; 1191} 1192 1193static bool mask64_operand(uint64_t c, int *mb, int *me) 1194{ 1195 uint64_t lsb; 1196 1197 if (c == 0) { 1198 return false; 1199 } 1200 1201 lsb = c & -c; 1202 /* Accept 1..10..0. */ 1203 if (c == -lsb) { 1204 *mb = 0; 1205 *me = clz64(lsb); 1206 return true; 1207 } 1208 /* Accept 0..01..1. */ 1209 if (lsb == 1 && (c & (c + 1)) == 0) { 1210 *mb = clz64(c + 1) + 1; 1211 *me = 63; 1212 return true; 1213 } 1214 return false; 1215} 1216 1217static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1218{ 1219 int mb, me; 1220 1221 if (mask_operand(c, &mb, &me)) { 1222 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); 1223 } else if ((c & 0xffff) == c) { 1224 tcg_out32(s, ANDI | SAI(src, dst, c)); 1225 return; 1226 } else if ((c & 0xffff0000) == c) { 1227 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1228 return; 1229 } else { 1230 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); 1231 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1232 } 1233} 1234 1235static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) 1236{ 1237 int mb, me; 1238 1239 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1240 if (mask64_operand(c, &mb, &me)) { 1241 if (mb == 0) { 1242 tcg_out_rld(s, RLDICR, dst, src, 0, me); 1243 } else { 1244 tcg_out_rld(s, RLDICL, dst, src, 0, mb); 1245 } 1246 } else if ((c & 0xffff) == c) { 1247 tcg_out32(s, ANDI | SAI(src, dst, c)); 1248 return; 1249 } else if ((c & 0xffff0000) == c) { 1250 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1251 return; 1252 } else { 1253 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); 1254 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1255 } 1256} 1257 1258static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, 1259 int op_lo, int op_hi) 1260{ 1261 if (c >> 16) { 1262 tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); 1263 src = dst; 1264 } 1265 if (c & 0xffff) { 1266 tcg_out32(s, op_lo | SAI(src, dst, c)); 1267 src = dst; 1268 } 1269} 1270 1271static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1272{ 1273 tcg_out_zori32(s, dst, src, c, ORI, ORIS); 1274} 1275 1276static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1277{ 1278 tcg_out_zori32(s, dst, src, c, XORI, XORIS); 1279} 1280 1281static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) 1282{ 1283 ptrdiff_t disp = tcg_pcrel_diff(s, target); 1284 if (in_range_b(disp)) { 1285 tcg_out32(s, B | (disp & 0x3fffffc) | mask); 1286 } else { 1287 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); 1288 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); 1289 tcg_out32(s, BCCTR | BO_ALWAYS | mask); 1290 } 1291} 1292 1293static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 1294 TCGReg base, tcg_target_long offset) 1295{ 1296 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; 1297 bool is_int_store = false; 1298 TCGReg rs = TCG_REG_TMP1; 1299 1300 switch (opi) { 1301 case LD: case LWA: 1302 align = 3; 1303 /* FALLTHRU */ 1304 default: 1305 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { 1306 rs = rt; 1307 break; 1308 } 1309 break; 1310 case LXSD: 1311 case STXSD: 1312 align = 3; 1313 break; 1314 case LXV: 1315 case STXV: 1316 align = 15; 1317 break; 1318 case STD: 1319 align = 3; 1320 /* FALLTHRU */ 1321 case STB: case STH: case STW: 1322 is_int_store = true; 1323 break; 1324 } 1325 1326 /* For unaligned, or very large offsets, use the indexed form. */ 1327 if (offset & align || offset != (int32_t)offset || opi == 0) { 1328 if (rs == base) { 1329 rs = TCG_REG_R0; 1330 } 1331 tcg_debug_assert(!is_int_store || rs != rt); 1332 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); 1333 tcg_out32(s, opx | TAB(rt & 31, base, rs)); 1334 return; 1335 } 1336 1337 l0 = (int16_t)offset; 1338 offset = (offset - l0) >> 16; 1339 l1 = (int16_t)offset; 1340 1341 if (l1 < 0 && orig >= 0) { 1342 extra = 0x4000; 1343 l1 = (int16_t)(offset - 0x4000); 1344 } 1345 if (l1) { 1346 tcg_out32(s, ADDIS | TAI(rs, base, l1)); 1347 base = rs; 1348 } 1349 if (extra) { 1350 tcg_out32(s, ADDIS | TAI(rs, base, extra)); 1351 base = rs; 1352 } 1353 if (opi != ADDI || base != rt || l0 != 0) { 1354 tcg_out32(s, opi | TAI(rt & 31, base, l0)); 1355 } 1356} 1357 1358static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, 1359 TCGReg va, TCGReg vb, int shb) 1360{ 1361 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); 1362} 1363 1364static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1365 TCGReg base, intptr_t offset) 1366{ 1367 int shift; 1368 1369 switch (type) { 1370 case TCG_TYPE_I32: 1371 if (ret < TCG_REG_V0) { 1372 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); 1373 break; 1374 } 1375 if (have_isa_2_07 && have_vsx) { 1376 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); 1377 break; 1378 } 1379 tcg_debug_assert((offset & 3) == 0); 1380 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); 1381 shift = (offset - 4) & 0xc; 1382 if (shift) { 1383 tcg_out_vsldoi(s, ret, ret, ret, shift); 1384 } 1385 break; 1386 case TCG_TYPE_I64: 1387 if (ret < TCG_REG_V0) { 1388 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1389 tcg_out_mem_long(s, LD, LDX, ret, base, offset); 1390 break; 1391 } 1392 /* fallthru */ 1393 case TCG_TYPE_V64: 1394 tcg_debug_assert(ret >= TCG_REG_V0); 1395 if (have_vsx) { 1396 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, 1397 ret, base, offset); 1398 break; 1399 } 1400 tcg_debug_assert((offset & 7) == 0); 1401 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); 1402 if (offset & 8) { 1403 tcg_out_vsldoi(s, ret, ret, ret, 8); 1404 } 1405 break; 1406 case TCG_TYPE_V128: 1407 tcg_debug_assert(ret >= TCG_REG_V0); 1408 tcg_debug_assert((offset & 15) == 0); 1409 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, 1410 LVX, ret, base, offset); 1411 break; 1412 default: 1413 g_assert_not_reached(); 1414 } 1415} 1416 1417static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1418 TCGReg base, intptr_t offset) 1419{ 1420 int shift; 1421 1422 switch (type) { 1423 case TCG_TYPE_I32: 1424 if (arg < TCG_REG_V0) { 1425 tcg_out_mem_long(s, STW, STWX, arg, base, offset); 1426 break; 1427 } 1428 if (have_isa_2_07 && have_vsx) { 1429 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); 1430 break; 1431 } 1432 assert((offset & 3) == 0); 1433 tcg_debug_assert((offset & 3) == 0); 1434 shift = (offset - 4) & 0xc; 1435 if (shift) { 1436 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); 1437 arg = TCG_VEC_TMP1; 1438 } 1439 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1440 break; 1441 case TCG_TYPE_I64: 1442 if (arg < TCG_REG_V0) { 1443 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1444 tcg_out_mem_long(s, STD, STDX, arg, base, offset); 1445 break; 1446 } 1447 /* fallthru */ 1448 case TCG_TYPE_V64: 1449 tcg_debug_assert(arg >= TCG_REG_V0); 1450 if (have_vsx) { 1451 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, 1452 STXSDX, arg, base, offset); 1453 break; 1454 } 1455 tcg_debug_assert((offset & 7) == 0); 1456 if (offset & 8) { 1457 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); 1458 arg = TCG_VEC_TMP1; 1459 } 1460 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1461 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); 1462 break; 1463 case TCG_TYPE_V128: 1464 tcg_debug_assert(arg >= TCG_REG_V0); 1465 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, 1466 STVX, arg, base, offset); 1467 break; 1468 default: 1469 g_assert_not_reached(); 1470 } 1471} 1472 1473static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1474 TCGReg base, intptr_t ofs) 1475{ 1476 return false; 1477} 1478 1479static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, 1480 int const_arg2, int cr, TCGType type) 1481{ 1482 int imm; 1483 uint32_t op; 1484 1485 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1486 1487 /* Simplify the comparisons below wrt CMPI. */ 1488 if (type == TCG_TYPE_I32) { 1489 arg2 = (int32_t)arg2; 1490 } 1491 1492 switch (cond) { 1493 case TCG_COND_EQ: 1494 case TCG_COND_NE: 1495 if (const_arg2) { 1496 if ((int16_t) arg2 == arg2) { 1497 op = CMPI; 1498 imm = 1; 1499 break; 1500 } else if ((uint16_t) arg2 == arg2) { 1501 op = CMPLI; 1502 imm = 1; 1503 break; 1504 } 1505 } 1506 op = CMPL; 1507 imm = 0; 1508 break; 1509 1510 case TCG_COND_LT: 1511 case TCG_COND_GE: 1512 case TCG_COND_LE: 1513 case TCG_COND_GT: 1514 if (const_arg2) { 1515 if ((int16_t) arg2 == arg2) { 1516 op = CMPI; 1517 imm = 1; 1518 break; 1519 } 1520 } 1521 op = CMP; 1522 imm = 0; 1523 break; 1524 1525 case TCG_COND_LTU: 1526 case TCG_COND_GEU: 1527 case TCG_COND_LEU: 1528 case TCG_COND_GTU: 1529 if (const_arg2) { 1530 if ((uint16_t) arg2 == arg2) { 1531 op = CMPLI; 1532 imm = 1; 1533 break; 1534 } 1535 } 1536 op = CMPL; 1537 imm = 0; 1538 break; 1539 1540 default: 1541 g_assert_not_reached(); 1542 } 1543 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); 1544 1545 if (imm) { 1546 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); 1547 } else { 1548 if (const_arg2) { 1549 tcg_out_movi(s, type, TCG_REG_R0, arg2); 1550 arg2 = TCG_REG_R0; 1551 } 1552 tcg_out32(s, op | RA(arg1) | RB(arg2)); 1553 } 1554} 1555 1556static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, 1557 TCGReg dst, TCGReg src) 1558{ 1559 if (type == TCG_TYPE_I32) { 1560 tcg_out32(s, CNTLZW | RS(src) | RA(dst)); 1561 tcg_out_shri32(s, dst, dst, 5); 1562 } else { 1563 tcg_out32(s, CNTLZD | RS(src) | RA(dst)); 1564 tcg_out_shri64(s, dst, dst, 6); 1565 } 1566} 1567 1568static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src) 1569{ 1570 /* X != 0 implies X + -1 generates a carry. Extra addition 1571 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */ 1572 if (dst != src) { 1573 tcg_out32(s, ADDIC | TAI(dst, src, -1)); 1574 tcg_out32(s, SUBFE | TAB(dst, dst, src)); 1575 } else { 1576 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); 1577 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); 1578 } 1579} 1580 1581static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, 1582 bool const_arg2) 1583{ 1584 if (const_arg2) { 1585 if ((uint32_t)arg2 == arg2) { 1586 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); 1587 } else { 1588 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); 1589 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); 1590 } 1591 } else { 1592 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); 1593 } 1594 return TCG_REG_R0; 1595} 1596 1597static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, 1598 TCGArg arg0, TCGArg arg1, TCGArg arg2, 1599 int const_arg2) 1600{ 1601 int crop, sh; 1602 1603 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1604 1605 /* Ignore high bits of a potential constant arg2. */ 1606 if (type == TCG_TYPE_I32) { 1607 arg2 = (uint32_t)arg2; 1608 } 1609 1610 /* Handle common and trivial cases before handling anything else. */ 1611 if (arg2 == 0) { 1612 switch (cond) { 1613 case TCG_COND_EQ: 1614 tcg_out_setcond_eq0(s, type, arg0, arg1); 1615 return; 1616 case TCG_COND_NE: 1617 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1618 tcg_out_ext32u(s, TCG_REG_R0, arg1); 1619 arg1 = TCG_REG_R0; 1620 } 1621 tcg_out_setcond_ne0(s, arg0, arg1); 1622 return; 1623 case TCG_COND_GE: 1624 tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); 1625 arg1 = arg0; 1626 /* FALLTHRU */ 1627 case TCG_COND_LT: 1628 /* Extract the sign bit. */ 1629 if (type == TCG_TYPE_I32) { 1630 tcg_out_shri32(s, arg0, arg1, 31); 1631 } else { 1632 tcg_out_shri64(s, arg0, arg1, 63); 1633 } 1634 return; 1635 default: 1636 break; 1637 } 1638 } 1639 1640 /* If we have ISEL, we can implement everything with 3 or 4 insns. 1641 All other cases below are also at least 3 insns, so speed up the 1642 code generator by not considering them and always using ISEL. */ 1643 if (have_isel) { 1644 int isel, tab; 1645 1646 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1647 1648 isel = tcg_to_isel[cond]; 1649 1650 tcg_out_movi(s, type, arg0, 1); 1651 if (isel & 1) { 1652 /* arg0 = (bc ? 0 : 1) */ 1653 tab = TAB(arg0, 0, arg0); 1654 isel &= ~1; 1655 } else { 1656 /* arg0 = (bc ? 1 : 0) */ 1657 tcg_out_movi(s, type, TCG_REG_R0, 0); 1658 tab = TAB(arg0, arg0, TCG_REG_R0); 1659 } 1660 tcg_out32(s, isel | tab); 1661 return; 1662 } 1663 1664 switch (cond) { 1665 case TCG_COND_EQ: 1666 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1667 tcg_out_setcond_eq0(s, type, arg0, arg1); 1668 return; 1669 1670 case TCG_COND_NE: 1671 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1672 /* Discard the high bits only once, rather than both inputs. */ 1673 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1674 tcg_out_ext32u(s, TCG_REG_R0, arg1); 1675 arg1 = TCG_REG_R0; 1676 } 1677 tcg_out_setcond_ne0(s, arg0, arg1); 1678 return; 1679 1680 case TCG_COND_GT: 1681 case TCG_COND_GTU: 1682 sh = 30; 1683 crop = 0; 1684 goto crtest; 1685 1686 case TCG_COND_LT: 1687 case TCG_COND_LTU: 1688 sh = 29; 1689 crop = 0; 1690 goto crtest; 1691 1692 case TCG_COND_GE: 1693 case TCG_COND_GEU: 1694 sh = 31; 1695 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT); 1696 goto crtest; 1697 1698 case TCG_COND_LE: 1699 case TCG_COND_LEU: 1700 sh = 31; 1701 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT); 1702 crtest: 1703 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1704 if (crop) { 1705 tcg_out32(s, crop); 1706 } 1707 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1708 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); 1709 break; 1710 1711 default: 1712 g_assert_not_reached(); 1713 } 1714} 1715 1716static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) 1717{ 1718 if (l->has_value) { 1719 bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr); 1720 } else { 1721 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); 1722 } 1723 tcg_out32(s, bc); 1724} 1725 1726static void tcg_out_brcond(TCGContext *s, TCGCond cond, 1727 TCGArg arg1, TCGArg arg2, int const_arg2, 1728 TCGLabel *l, TCGType type) 1729{ 1730 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1731 tcg_out_bc(s, tcg_to_bc[cond], l); 1732} 1733 1734static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, 1735 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, 1736 TCGArg v2, bool const_c2) 1737{ 1738 /* If for some reason both inputs are zero, don't produce bad code. */ 1739 if (v1 == 0 && v2 == 0) { 1740 tcg_out_movi(s, type, dest, 0); 1741 return; 1742 } 1743 1744 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); 1745 1746 if (have_isel) { 1747 int isel = tcg_to_isel[cond]; 1748 1749 /* Swap the V operands if the operation indicates inversion. */ 1750 if (isel & 1) { 1751 int t = v1; 1752 v1 = v2; 1753 v2 = t; 1754 isel &= ~1; 1755 } 1756 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ 1757 if (v2 == 0) { 1758 tcg_out_movi(s, type, TCG_REG_R0, 0); 1759 } 1760 tcg_out32(s, isel | TAB(dest, v1, v2)); 1761 } else { 1762 if (dest == v2) { 1763 cond = tcg_invert_cond(cond); 1764 v2 = v1; 1765 } else if (dest != v1) { 1766 if (v1 == 0) { 1767 tcg_out_movi(s, type, dest, 0); 1768 } else { 1769 tcg_out_mov(s, type, dest, v1); 1770 } 1771 } 1772 /* Branch forward over one insn */ 1773 tcg_out32(s, tcg_to_bc[cond] | 8); 1774 if (v2 == 0) { 1775 tcg_out_movi(s, type, dest, 0); 1776 } else { 1777 tcg_out_mov(s, type, dest, v2); 1778 } 1779 } 1780} 1781 1782static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc, 1783 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2) 1784{ 1785 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { 1786 tcg_out32(s, opc | RA(a0) | RS(a1)); 1787 } else { 1788 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); 1789 /* Note that the only other valid constant for a2 is 0. */ 1790 if (have_isel) { 1791 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); 1792 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0)); 1793 } else if (!const_a2 && a0 == a2) { 1794 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8); 1795 tcg_out32(s, opc | RA(a0) | RS(a1)); 1796 } else { 1797 tcg_out32(s, opc | RA(a0) | RS(a1)); 1798 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8); 1799 if (const_a2) { 1800 tcg_out_movi(s, type, a0, 0); 1801 } else { 1802 tcg_out_mov(s, type, a0, a2); 1803 } 1804 } 1805 } 1806} 1807 1808static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1809 const int *const_args) 1810{ 1811 static const struct { uint8_t bit1, bit2; } bits[] = { 1812 [TCG_COND_LT ] = { CR_LT, CR_LT }, 1813 [TCG_COND_LE ] = { CR_LT, CR_GT }, 1814 [TCG_COND_GT ] = { CR_GT, CR_GT }, 1815 [TCG_COND_GE ] = { CR_GT, CR_LT }, 1816 [TCG_COND_LTU] = { CR_LT, CR_LT }, 1817 [TCG_COND_LEU] = { CR_LT, CR_GT }, 1818 [TCG_COND_GTU] = { CR_GT, CR_GT }, 1819 [TCG_COND_GEU] = { CR_GT, CR_LT }, 1820 }; 1821 1822 TCGCond cond = args[4], cond2; 1823 TCGArg al, ah, bl, bh; 1824 int blconst, bhconst; 1825 int op, bit1, bit2; 1826 1827 al = args[0]; 1828 ah = args[1]; 1829 bl = args[2]; 1830 bh = args[3]; 1831 blconst = const_args[2]; 1832 bhconst = const_args[3]; 1833 1834 switch (cond) { 1835 case TCG_COND_EQ: 1836 op = CRAND; 1837 goto do_equality; 1838 case TCG_COND_NE: 1839 op = CRNAND; 1840 do_equality: 1841 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); 1842 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); 1843 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 1844 break; 1845 1846 case TCG_COND_LT: 1847 case TCG_COND_LE: 1848 case TCG_COND_GT: 1849 case TCG_COND_GE: 1850 case TCG_COND_LTU: 1851 case TCG_COND_LEU: 1852 case TCG_COND_GTU: 1853 case TCG_COND_GEU: 1854 bit1 = bits[cond].bit1; 1855 bit2 = bits[cond].bit2; 1856 op = (bit1 != bit2 ? CRANDC : CRAND); 1857 cond2 = tcg_unsigned_cond(cond); 1858 1859 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); 1860 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); 1861 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); 1862 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); 1863 break; 1864 1865 default: 1866 g_assert_not_reached(); 1867 } 1868} 1869 1870static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 1871 const int *const_args) 1872{ 1873 tcg_out_cmp2(s, args + 1, const_args + 1); 1874 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1875 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); 1876} 1877 1878static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, 1879 const int *const_args) 1880{ 1881 tcg_out_cmp2(s, args, const_args); 1882 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5])); 1883} 1884 1885static void tcg_out_mb(TCGContext *s, TCGArg a0) 1886{ 1887 uint32_t insn; 1888 1889 if (a0 & TCG_MO_ST_LD) { 1890 insn = HWSYNC; 1891 } else { 1892 insn = LWSYNC; 1893 } 1894 1895 tcg_out32(s, insn); 1896} 1897 1898static void tcg_out_call_int(TCGContext *s, int lk, 1899 const tcg_insn_unit *target) 1900{ 1901#ifdef _CALL_AIX 1902 /* Look through the descriptor. If the branch is in range, and we 1903 don't have to spend too much effort on building the toc. */ 1904 const void *tgt = ((const void * const *)target)[0]; 1905 uintptr_t toc = ((const uintptr_t *)target)[1]; 1906 intptr_t diff = tcg_pcrel_diff(s, tgt); 1907 1908 if (in_range_b(diff) && toc == (uint32_t)toc) { 1909 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); 1910 tcg_out_b(s, lk, tgt); 1911 } else { 1912 /* Fold the low bits of the constant into the addresses below. */ 1913 intptr_t arg = (intptr_t)target; 1914 int ofs = (int16_t)arg; 1915 1916 if (ofs + 8 < 0x8000) { 1917 arg -= ofs; 1918 } else { 1919 ofs = 0; 1920 } 1921 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); 1922 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); 1923 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); 1924 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); 1925 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1926 } 1927#elif defined(_CALL_ELF) && _CALL_ELF == 2 1928 intptr_t diff; 1929 1930 /* In the ELFv2 ABI, we have to set up r12 to contain the destination 1931 address, which the callee uses to compute its TOC address. */ 1932 /* FIXME: when the branch is in range, we could avoid r12 load if we 1933 knew that the destination uses the same TOC, and what its local 1934 entry point offset is. */ 1935 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); 1936 1937 diff = tcg_pcrel_diff(s, target); 1938 if (in_range_b(diff)) { 1939 tcg_out_b(s, lk, target); 1940 } else { 1941 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); 1942 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1943 } 1944#else 1945 tcg_out_b(s, lk, target); 1946#endif 1947} 1948 1949static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 1950 const TCGHelperInfo *info) 1951{ 1952 tcg_out_call_int(s, LK, target); 1953} 1954 1955static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = { 1956 [MO_UB] = LBZX, 1957 [MO_UW] = LHZX, 1958 [MO_UL] = LWZX, 1959 [MO_UQ] = LDX, 1960 [MO_SW] = LHAX, 1961 [MO_SL] = LWAX, 1962 [MO_BSWAP | MO_UB] = LBZX, 1963 [MO_BSWAP | MO_UW] = LHBRX, 1964 [MO_BSWAP | MO_UL] = LWBRX, 1965 [MO_BSWAP | MO_UQ] = LDBRX, 1966}; 1967 1968static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = { 1969 [MO_UB] = STBX, 1970 [MO_UW] = STHX, 1971 [MO_UL] = STWX, 1972 [MO_UQ] = STDX, 1973 [MO_BSWAP | MO_UB] = STBX, 1974 [MO_BSWAP | MO_UW] = STHBRX, 1975 [MO_BSWAP | MO_UL] = STWBRX, 1976 [MO_BSWAP | MO_UQ] = STDBRX, 1977}; 1978 1979#if defined (CONFIG_SOFTMMU) 1980/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, 1981 * int mmu_idx, uintptr_t ra) 1982 */ 1983static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = { 1984 [MO_UB] = helper_ret_ldub_mmu, 1985 [MO_LEUW] = helper_le_lduw_mmu, 1986 [MO_LEUL] = helper_le_ldul_mmu, 1987 [MO_LEUQ] = helper_le_ldq_mmu, 1988 [MO_BEUW] = helper_be_lduw_mmu, 1989 [MO_BEUL] = helper_be_ldul_mmu, 1990 [MO_BEUQ] = helper_be_ldq_mmu, 1991}; 1992 1993/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, 1994 * uintxx_t val, int mmu_idx, uintptr_t ra) 1995 */ 1996static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = { 1997 [MO_UB] = helper_ret_stb_mmu, 1998 [MO_LEUW] = helper_le_stw_mmu, 1999 [MO_LEUL] = helper_le_stl_mmu, 2000 [MO_LEUQ] = helper_le_stq_mmu, 2001 [MO_BEUW] = helper_be_stw_mmu, 2002 [MO_BEUL] = helper_be_stl_mmu, 2003 [MO_BEUQ] = helper_be_stq_mmu, 2004}; 2005 2006/* We expect to use a 16-bit negative offset from ENV. */ 2007QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 2008QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 2009 2010/* Perform the TLB load and compare. Places the result of the comparison 2011 in CR7, loads the addend of the TLB into R3, and returns the register 2012 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ 2013 2014static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, 2015 TCGReg addrlo, TCGReg addrhi, 2016 int mem_index, bool is_read) 2017{ 2018 int cmp_off 2019 = (is_read 2020 ? offsetof(CPUTLBEntry, addr_read) 2021 : offsetof(CPUTLBEntry, addr_write)); 2022 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 2023 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 2024 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 2025 unsigned s_bits = opc & MO_SIZE; 2026 unsigned a_bits = get_alignment_bits(opc); 2027 2028 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 2029 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); 2030 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); 2031 2032 /* Extract the page index, shifted into place for tlb index. */ 2033 if (TCG_TARGET_REG_BITS == 32) { 2034 tcg_out_shri32(s, TCG_REG_TMP1, addrlo, 2035 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 2036 } else { 2037 tcg_out_shri64(s, TCG_REG_TMP1, addrlo, 2038 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 2039 } 2040 tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); 2041 2042 /* Load the TLB comparator. */ 2043 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2044 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32 2045 ? LWZUX : LDUX); 2046 tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); 2047 } else { 2048 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); 2049 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2050 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4); 2051 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); 2052 } else { 2053 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); 2054 } 2055 } 2056 2057 /* Load the TLB addend for use on the fast path. Do this asap 2058 to minimize any load use delay. */ 2059 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, 2060 offsetof(CPUTLBEntry, addend)); 2061 2062 /* Clear the non-page, non-alignment bits from the address */ 2063 if (TCG_TARGET_REG_BITS == 32) { 2064 /* We don't support unaligned accesses on 32-bits. 2065 * Preserve the bottom bits and thus trigger a comparison 2066 * failure on unaligned accesses. 2067 */ 2068 if (a_bits < s_bits) { 2069 a_bits = s_bits; 2070 } 2071 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, 2072 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); 2073 } else { 2074 TCGReg t = addrlo; 2075 2076 /* If the access is unaligned, we need to make sure we fail if we 2077 * cross a page boundary. The trick is to add the access size-1 2078 * to the address before masking the low bits. That will make the 2079 * address overflow to the next page if we cross a page boundary, 2080 * which will then force a mismatch of the TLB compare. 2081 */ 2082 if (a_bits < s_bits) { 2083 unsigned a_mask = (1 << a_bits) - 1; 2084 unsigned s_mask = (1 << s_bits) - 1; 2085 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); 2086 t = TCG_REG_R0; 2087 } 2088 2089 /* Mask the address for the requested alignment. */ 2090 if (TARGET_LONG_BITS == 32) { 2091 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, 2092 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); 2093 /* Zero-extend the address for use in the final address. */ 2094 tcg_out_ext32u(s, TCG_REG_R4, addrlo); 2095 addrlo = TCG_REG_R4; 2096 } else if (a_bits == 0) { 2097 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS); 2098 } else { 2099 tcg_out_rld(s, RLDICL, TCG_REG_R0, t, 2100 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); 2101 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0); 2102 } 2103 } 2104 2105 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2106 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, 2107 0, 7, TCG_TYPE_I32); 2108 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32); 2109 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 2110 } else { 2111 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, 2112 0, 7, TCG_TYPE_TL); 2113 } 2114 2115 return addrlo; 2116} 2117 2118/* Record the context of a call to the out of line helper code for the slow 2119 path for a load or store, so that we can later generate the correct 2120 helper code. */ 2121static void add_qemu_ldst_label(TCGContext *s, bool is_ld, 2122 TCGType type, MemOpIdx oi, 2123 TCGReg datalo_reg, TCGReg datahi_reg, 2124 TCGReg addrlo_reg, TCGReg addrhi_reg, 2125 tcg_insn_unit *raddr, tcg_insn_unit *lptr) 2126{ 2127 TCGLabelQemuLdst *label = new_ldst_label(s); 2128 2129 label->is_ld = is_ld; 2130 label->type = type; 2131 label->oi = oi; 2132 label->datalo_reg = datalo_reg; 2133 label->datahi_reg = datahi_reg; 2134 label->addrlo_reg = addrlo_reg; 2135 label->addrhi_reg = addrhi_reg; 2136 label->raddr = tcg_splitwx_to_rx(raddr); 2137 label->label_ptr[0] = lptr; 2138} 2139 2140static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2141{ 2142 MemOpIdx oi = lb->oi; 2143 MemOp opc = get_memop(oi); 2144 TCGReg hi, lo, arg = TCG_REG_R3; 2145 2146 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2147 return false; 2148 } 2149 2150 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); 2151 2152 lo = lb->addrlo_reg; 2153 hi = lb->addrhi_reg; 2154 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2155 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2156 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); 2157 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); 2158 } else { 2159 /* If the address needed to be zero-extended, we'll have already 2160 placed it in R4. The only remaining case is 64-bit guest. */ 2161 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); 2162 } 2163 2164 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); 2165 tcg_out32(s, MFSPR | RT(arg) | LR); 2166 2167 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); 2168 2169 lo = lb->datalo_reg; 2170 hi = lb->datahi_reg; 2171 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2172 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); 2173 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); 2174 } else { 2175 tcg_out_movext(s, lb->type, lo, 2176 TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_R3); 2177 } 2178 2179 tcg_out_b(s, 0, lb->raddr); 2180 return true; 2181} 2182 2183static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2184{ 2185 MemOpIdx oi = lb->oi; 2186 MemOp opc = get_memop(oi); 2187 MemOp s_bits = opc & MO_SIZE; 2188 TCGReg hi, lo, arg = TCG_REG_R3; 2189 2190 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2191 return false; 2192 } 2193 2194 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); 2195 2196 lo = lb->addrlo_reg; 2197 hi = lb->addrhi_reg; 2198 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2199 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2200 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); 2201 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); 2202 } else { 2203 /* If the address needed to be zero-extended, we'll have already 2204 placed it in R4. The only remaining case is 64-bit guest. */ 2205 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); 2206 } 2207 2208 lo = lb->datalo_reg; 2209 hi = lb->datahi_reg; 2210 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { 2211 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2212 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); 2213 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); 2214 } else { 2215 tcg_out_movext(s, s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, 2216 arg++, lb->type, s_bits, lo); 2217 } 2218 2219 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); 2220 tcg_out32(s, MFSPR | RT(arg) | LR); 2221 2222 tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); 2223 2224 tcg_out_b(s, 0, lb->raddr); 2225 return true; 2226} 2227#else 2228 2229static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo, 2230 TCGReg addrhi, unsigned a_bits) 2231{ 2232 unsigned a_mask = (1 << a_bits) - 1; 2233 TCGLabelQemuLdst *label = new_ldst_label(s); 2234 2235 label->is_ld = is_ld; 2236 label->addrlo_reg = addrlo; 2237 label->addrhi_reg = addrhi; 2238 2239 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 2240 tcg_debug_assert(a_bits < 16); 2241 tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask)); 2242 2243 label->label_ptr[0] = s->code_ptr; 2244 tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); 2245 2246 label->raddr = tcg_splitwx_to_rx(s->code_ptr); 2247} 2248 2249static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 2250{ 2251 if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2252 return false; 2253 } 2254 2255 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2256 TCGReg arg = TCG_REG_R4; 2257 2258 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2259 if (l->addrlo_reg != arg) { 2260 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); 2261 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); 2262 } else if (l->addrhi_reg != arg + 1) { 2263 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); 2264 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); 2265 } else { 2266 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg); 2267 tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1); 2268 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0); 2269 } 2270 } else { 2271 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg); 2272 } 2273 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0); 2274 2275 /* "Tail call" to the helper, with the return address back inline. */ 2276 tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld 2277 : helper_unaligned_st)); 2278 return true; 2279} 2280 2281static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2282{ 2283 return tcg_out_fail_alignment(s, l); 2284} 2285 2286static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2287{ 2288 return tcg_out_fail_alignment(s, l); 2289} 2290#endif /* SOFTMMU */ 2291 2292typedef struct { 2293 TCGReg base; 2294 TCGReg index; 2295} HostAddress; 2296 2297static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2298 TCGReg addrlo, TCGReg addrhi, 2299 MemOpIdx oi, TCGType data_type) 2300{ 2301 MemOp opc = get_memop(oi); 2302 MemOp s_bits = opc & MO_SIZE; 2303 HostAddress h; 2304 2305#ifdef CONFIG_SOFTMMU 2306 tcg_insn_unit *label_ptr; 2307 2308 h.index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), true); 2309 h.base = TCG_REG_R3; 2310 2311 /* Load a pointer into the current opcode w/conditional branch-link. */ 2312 label_ptr = s->code_ptr; 2313 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); 2314#else /* !CONFIG_SOFTMMU */ 2315 unsigned a_bits = get_alignment_bits(opc); 2316 if (a_bits) { 2317 tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); 2318 } 2319 h.base = guest_base ? TCG_GUEST_BASE_REG : 0; 2320 h.index = addrlo; 2321 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 2322 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); 2323 h.index = TCG_REG_TMP1; 2324 } 2325#endif 2326 2327 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { 2328 if (opc & MO_BSWAP) { 2329 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2330 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2331 tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); 2332 } else if (h.base != 0) { 2333 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2334 tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); 2335 tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); 2336 } else if (h.index == datahi) { 2337 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2338 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2339 } else { 2340 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2341 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2342 } 2343 } else { 2344 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; 2345 if (!have_isa_2_06 && insn == LDBRX) { 2346 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2347 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2348 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); 2349 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); 2350 } else if (insn) { 2351 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2352 } else { 2353 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; 2354 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2355 tcg_out_movext(s, TCG_TYPE_REG, datalo, 2356 TCG_TYPE_REG, opc & MO_SSIZE, datalo); 2357 } 2358 } 2359 2360#ifdef CONFIG_SOFTMMU 2361 add_qemu_ldst_label(s, true, data_type, oi, datalo, datahi, 2362 addrlo, addrhi, s->code_ptr, label_ptr); 2363#endif 2364} 2365 2366static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2367 TCGReg addrlo, TCGReg addrhi, 2368 MemOpIdx oi, TCGType data_type) 2369{ 2370 MemOp opc = get_memop(oi); 2371 MemOp s_bits = opc & MO_SIZE; 2372 HostAddress h; 2373 2374#ifdef CONFIG_SOFTMMU 2375 tcg_insn_unit *label_ptr; 2376 2377 h.index = tcg_out_tlb_read(s, opc, addrlo, addrhi, get_mmuidx(oi), false); 2378 h.base = TCG_REG_R3; 2379 2380 /* Load a pointer into the current opcode w/conditional branch-link. */ 2381 label_ptr = s->code_ptr; 2382 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); 2383#else /* !CONFIG_SOFTMMU */ 2384 unsigned a_bits = get_alignment_bits(opc); 2385 if (a_bits) { 2386 tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); 2387 } 2388 h.base = guest_base ? TCG_GUEST_BASE_REG : 0; 2389 h.index = addrlo; 2390 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 2391 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); 2392 h.index = TCG_REG_TMP1; 2393 } 2394#endif 2395 2396 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { 2397 if (opc & MO_BSWAP) { 2398 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2399 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2400 tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); 2401 } else if (h.base != 0) { 2402 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2403 tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); 2404 tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); 2405 } else { 2406 tcg_out32(s, STW | TAI(datahi, h.index, 0)); 2407 tcg_out32(s, STW | TAI(datalo, h.index, 4)); 2408 } 2409 } else { 2410 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; 2411 if (!have_isa_2_06 && insn == STDBRX) { 2412 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2413 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4)); 2414 tcg_out_shri64(s, TCG_REG_R0, datalo, 32); 2415 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1)); 2416 } else { 2417 tcg_out32(s, insn | SAB(datalo, h.base, h.index)); 2418 } 2419 } 2420 2421#ifdef CONFIG_SOFTMMU 2422 add_qemu_ldst_label(s, false, data_type, oi, datalo, datahi, 2423 addrlo, addrhi, s->code_ptr, label_ptr); 2424#endif 2425} 2426 2427static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2428{ 2429 int i; 2430 for (i = 0; i < count; ++i) { 2431 p[i] = NOP; 2432 } 2433} 2434 2435/* Parameters for function call generation, used in tcg.c. */ 2436#define TCG_TARGET_STACK_ALIGN 16 2437 2438#ifdef _CALL_AIX 2439# define LINK_AREA_SIZE (6 * SZR) 2440# define LR_OFFSET (1 * SZR) 2441# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) 2442#elif defined(_CALL_DARWIN) 2443# define LINK_AREA_SIZE (6 * SZR) 2444# define LR_OFFSET (2 * SZR) 2445#elif TCG_TARGET_REG_BITS == 64 2446# if defined(_CALL_ELF) && _CALL_ELF == 2 2447# define LINK_AREA_SIZE (4 * SZR) 2448# define LR_OFFSET (1 * SZR) 2449# endif 2450#else /* TCG_TARGET_REG_BITS == 32 */ 2451# if defined(_CALL_SYSV) 2452# define LINK_AREA_SIZE (2 * SZR) 2453# define LR_OFFSET (1 * SZR) 2454# endif 2455#endif 2456#ifndef LR_OFFSET 2457# error "Unhandled abi" 2458#endif 2459#ifndef TCG_TARGET_CALL_STACK_OFFSET 2460# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE 2461#endif 2462 2463#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2464#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) 2465 2466#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ 2467 + TCG_STATIC_CALL_ARGS_SIZE \ 2468 + CPU_TEMP_BUF_SIZE \ 2469 + REG_SAVE_SIZE \ 2470 + TCG_TARGET_STACK_ALIGN - 1) \ 2471 & -TCG_TARGET_STACK_ALIGN) 2472 2473#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) 2474 2475static void tcg_target_qemu_prologue(TCGContext *s) 2476{ 2477 int i; 2478 2479#ifdef _CALL_AIX 2480 const void **desc = (const void **)s->code_ptr; 2481 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */ 2482 desc[1] = 0; /* environment pointer */ 2483 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ 2484#endif 2485 2486 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, 2487 CPU_TEMP_BUF_SIZE); 2488 2489 /* Prologue */ 2490 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); 2491 tcg_out32(s, (SZR == 8 ? STDU : STWU) 2492 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); 2493 2494 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2495 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2496 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2497 } 2498 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2499 2500#ifndef CONFIG_SOFTMMU 2501 if (guest_base) { 2502 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); 2503 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2504 } 2505#endif 2506 2507 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2508 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); 2509 if (USE_REG_TB) { 2510 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2511 } 2512 tcg_out32(s, BCCTR | BO_ALWAYS); 2513 2514 /* Epilogue */ 2515 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2516 2517 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2518 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2519 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2520 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2521 } 2522 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); 2523 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); 2524 tcg_out32(s, BCLR | BO_ALWAYS); 2525} 2526 2527static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 2528{ 2529 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg); 2530 tcg_out_b(s, 0, tcg_code_gen_epilogue); 2531} 2532 2533static void tcg_out_goto_tb(TCGContext *s, int which) 2534{ 2535 uintptr_t ptr = get_jmp_target_addr(s, which); 2536 2537 if (USE_REG_TB) { 2538 ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr); 2539 tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); 2540 2541 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2542 set_jmp_insn_offset(s, which); 2543 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); 2544 2545 /* When branch is out of range, fall through to indirect. */ 2546 tcg_out32(s, BCCTR | BO_ALWAYS); 2547 2548 /* For the unlinked case, need to reset TCG_REG_TB. */ 2549 set_jmp_reset_offset(s, which); 2550 tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, 2551 -tcg_current_code_size(s)); 2552 } else { 2553 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2554 set_jmp_insn_offset(s, which); 2555 tcg_out32(s, NOP); 2556 2557 /* When branch is out of range, fall through to indirect. */ 2558 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); 2559 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr); 2560 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); 2561 tcg_out32(s, BCCTR | BO_ALWAYS); 2562 set_jmp_reset_offset(s, which); 2563 } 2564} 2565 2566void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2567 uintptr_t jmp_rx, uintptr_t jmp_rw) 2568{ 2569 uintptr_t addr = tb->jmp_target_addr[n]; 2570 intptr_t diff = addr - jmp_rx; 2571 tcg_insn_unit insn; 2572 2573 if (in_range_b(diff)) { 2574 insn = B | (diff & 0x3fffffc); 2575 } else if (USE_REG_TB) { 2576 insn = MTSPR | RS(TCG_REG_TB) | CTR; 2577 } else { 2578 insn = NOP; 2579 } 2580 2581 qatomic_set((uint32_t *)jmp_rw, insn); 2582 flush_idcache_range(jmp_rx, jmp_rw, 4); 2583} 2584 2585static void tcg_out_op(TCGContext *s, TCGOpcode opc, 2586 const TCGArg args[TCG_MAX_OP_ARGS], 2587 const int const_args[TCG_MAX_OP_ARGS]) 2588{ 2589 TCGArg a0, a1, a2; 2590 2591 switch (opc) { 2592 case INDEX_op_goto_ptr: 2593 tcg_out32(s, MTSPR | RS(args[0]) | CTR); 2594 if (USE_REG_TB) { 2595 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); 2596 } 2597 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); 2598 tcg_out32(s, BCCTR | BO_ALWAYS); 2599 break; 2600 case INDEX_op_br: 2601 { 2602 TCGLabel *l = arg_label(args[0]); 2603 uint32_t insn = B; 2604 2605 if (l->has_value) { 2606 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr), 2607 l->u.value_ptr); 2608 } else { 2609 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); 2610 } 2611 tcg_out32(s, insn); 2612 } 2613 break; 2614 case INDEX_op_ld8u_i32: 2615 case INDEX_op_ld8u_i64: 2616 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2617 break; 2618 case INDEX_op_ld8s_i32: 2619 case INDEX_op_ld8s_i64: 2620 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2621 tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]); 2622 break; 2623 case INDEX_op_ld16u_i32: 2624 case INDEX_op_ld16u_i64: 2625 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); 2626 break; 2627 case INDEX_op_ld16s_i32: 2628 case INDEX_op_ld16s_i64: 2629 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); 2630 break; 2631 case INDEX_op_ld_i32: 2632 case INDEX_op_ld32u_i64: 2633 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); 2634 break; 2635 case INDEX_op_ld32s_i64: 2636 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); 2637 break; 2638 case INDEX_op_ld_i64: 2639 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); 2640 break; 2641 case INDEX_op_st8_i32: 2642 case INDEX_op_st8_i64: 2643 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); 2644 break; 2645 case INDEX_op_st16_i32: 2646 case INDEX_op_st16_i64: 2647 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); 2648 break; 2649 case INDEX_op_st_i32: 2650 case INDEX_op_st32_i64: 2651 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); 2652 break; 2653 case INDEX_op_st_i64: 2654 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); 2655 break; 2656 2657 case INDEX_op_add_i32: 2658 a0 = args[0], a1 = args[1], a2 = args[2]; 2659 if (const_args[2]) { 2660 do_addi_32: 2661 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); 2662 } else { 2663 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2664 } 2665 break; 2666 case INDEX_op_sub_i32: 2667 a0 = args[0], a1 = args[1], a2 = args[2]; 2668 if (const_args[1]) { 2669 if (const_args[2]) { 2670 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); 2671 } else { 2672 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2673 } 2674 } else if (const_args[2]) { 2675 a2 = -a2; 2676 goto do_addi_32; 2677 } else { 2678 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2679 } 2680 break; 2681 2682 case INDEX_op_and_i32: 2683 a0 = args[0], a1 = args[1], a2 = args[2]; 2684 if (const_args[2]) { 2685 tcg_out_andi32(s, a0, a1, a2); 2686 } else { 2687 tcg_out32(s, AND | SAB(a1, a0, a2)); 2688 } 2689 break; 2690 case INDEX_op_and_i64: 2691 a0 = args[0], a1 = args[1], a2 = args[2]; 2692 if (const_args[2]) { 2693 tcg_out_andi64(s, a0, a1, a2); 2694 } else { 2695 tcg_out32(s, AND | SAB(a1, a0, a2)); 2696 } 2697 break; 2698 case INDEX_op_or_i64: 2699 case INDEX_op_or_i32: 2700 a0 = args[0], a1 = args[1], a2 = args[2]; 2701 if (const_args[2]) { 2702 tcg_out_ori32(s, a0, a1, a2); 2703 } else { 2704 tcg_out32(s, OR | SAB(a1, a0, a2)); 2705 } 2706 break; 2707 case INDEX_op_xor_i64: 2708 case INDEX_op_xor_i32: 2709 a0 = args[0], a1 = args[1], a2 = args[2]; 2710 if (const_args[2]) { 2711 tcg_out_xori32(s, a0, a1, a2); 2712 } else { 2713 tcg_out32(s, XOR | SAB(a1, a0, a2)); 2714 } 2715 break; 2716 case INDEX_op_andc_i32: 2717 a0 = args[0], a1 = args[1], a2 = args[2]; 2718 if (const_args[2]) { 2719 tcg_out_andi32(s, a0, a1, ~a2); 2720 } else { 2721 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2722 } 2723 break; 2724 case INDEX_op_andc_i64: 2725 a0 = args[0], a1 = args[1], a2 = args[2]; 2726 if (const_args[2]) { 2727 tcg_out_andi64(s, a0, a1, ~a2); 2728 } else { 2729 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2730 } 2731 break; 2732 case INDEX_op_orc_i32: 2733 if (const_args[2]) { 2734 tcg_out_ori32(s, args[0], args[1], ~args[2]); 2735 break; 2736 } 2737 /* FALLTHRU */ 2738 case INDEX_op_orc_i64: 2739 tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); 2740 break; 2741 case INDEX_op_eqv_i32: 2742 if (const_args[2]) { 2743 tcg_out_xori32(s, args[0], args[1], ~args[2]); 2744 break; 2745 } 2746 /* FALLTHRU */ 2747 case INDEX_op_eqv_i64: 2748 tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); 2749 break; 2750 case INDEX_op_nand_i32: 2751 case INDEX_op_nand_i64: 2752 tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); 2753 break; 2754 case INDEX_op_nor_i32: 2755 case INDEX_op_nor_i64: 2756 tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); 2757 break; 2758 2759 case INDEX_op_clz_i32: 2760 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], 2761 args[2], const_args[2]); 2762 break; 2763 case INDEX_op_ctz_i32: 2764 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], 2765 args[2], const_args[2]); 2766 break; 2767 case INDEX_op_ctpop_i32: 2768 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); 2769 break; 2770 2771 case INDEX_op_clz_i64: 2772 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], 2773 args[2], const_args[2]); 2774 break; 2775 case INDEX_op_ctz_i64: 2776 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], 2777 args[2], const_args[2]); 2778 break; 2779 case INDEX_op_ctpop_i64: 2780 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); 2781 break; 2782 2783 case INDEX_op_mul_i32: 2784 a0 = args[0], a1 = args[1], a2 = args[2]; 2785 if (const_args[2]) { 2786 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2787 } else { 2788 tcg_out32(s, MULLW | TAB(a0, a1, a2)); 2789 } 2790 break; 2791 2792 case INDEX_op_div_i32: 2793 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); 2794 break; 2795 2796 case INDEX_op_divu_i32: 2797 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); 2798 break; 2799 2800 case INDEX_op_rem_i32: 2801 tcg_out32(s, MODSW | TAB(args[0], args[1], args[2])); 2802 break; 2803 2804 case INDEX_op_remu_i32: 2805 tcg_out32(s, MODUW | TAB(args[0], args[1], args[2])); 2806 break; 2807 2808 case INDEX_op_shl_i32: 2809 if (const_args[2]) { 2810 /* Limit immediate shift count lest we create an illegal insn. */ 2811 tcg_out_shli32(s, args[0], args[1], args[2] & 31); 2812 } else { 2813 tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); 2814 } 2815 break; 2816 case INDEX_op_shr_i32: 2817 if (const_args[2]) { 2818 /* Limit immediate shift count lest we create an illegal insn. */ 2819 tcg_out_shri32(s, args[0], args[1], args[2] & 31); 2820 } else { 2821 tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); 2822 } 2823 break; 2824 case INDEX_op_sar_i32: 2825 if (const_args[2]) { 2826 tcg_out_sari32(s, args[0], args[1], args[2]); 2827 } else { 2828 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); 2829 } 2830 break; 2831 case INDEX_op_rotl_i32: 2832 if (const_args[2]) { 2833 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); 2834 } else { 2835 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) 2836 | MB(0) | ME(31)); 2837 } 2838 break; 2839 case INDEX_op_rotr_i32: 2840 if (const_args[2]) { 2841 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); 2842 } else { 2843 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); 2844 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) 2845 | MB(0) | ME(31)); 2846 } 2847 break; 2848 2849 case INDEX_op_brcond_i32: 2850 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2851 arg_label(args[3]), TCG_TYPE_I32); 2852 break; 2853 case INDEX_op_brcond_i64: 2854 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2855 arg_label(args[3]), TCG_TYPE_I64); 2856 break; 2857 case INDEX_op_brcond2_i32: 2858 tcg_out_brcond2(s, args, const_args); 2859 break; 2860 2861 case INDEX_op_neg_i32: 2862 case INDEX_op_neg_i64: 2863 tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); 2864 break; 2865 2866 case INDEX_op_not_i32: 2867 case INDEX_op_not_i64: 2868 tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); 2869 break; 2870 2871 case INDEX_op_add_i64: 2872 a0 = args[0], a1 = args[1], a2 = args[2]; 2873 if (const_args[2]) { 2874 do_addi_64: 2875 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); 2876 } else { 2877 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2878 } 2879 break; 2880 case INDEX_op_sub_i64: 2881 a0 = args[0], a1 = args[1], a2 = args[2]; 2882 if (const_args[1]) { 2883 if (const_args[2]) { 2884 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); 2885 } else { 2886 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2887 } 2888 } else if (const_args[2]) { 2889 a2 = -a2; 2890 goto do_addi_64; 2891 } else { 2892 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2893 } 2894 break; 2895 2896 case INDEX_op_shl_i64: 2897 if (const_args[2]) { 2898 /* Limit immediate shift count lest we create an illegal insn. */ 2899 tcg_out_shli64(s, args[0], args[1], args[2] & 63); 2900 } else { 2901 tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); 2902 } 2903 break; 2904 case INDEX_op_shr_i64: 2905 if (const_args[2]) { 2906 /* Limit immediate shift count lest we create an illegal insn. */ 2907 tcg_out_shri64(s, args[0], args[1], args[2] & 63); 2908 } else { 2909 tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); 2910 } 2911 break; 2912 case INDEX_op_sar_i64: 2913 if (const_args[2]) { 2914 tcg_out_sari64(s, args[0], args[1], args[2]); 2915 } else { 2916 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); 2917 } 2918 break; 2919 case INDEX_op_rotl_i64: 2920 if (const_args[2]) { 2921 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); 2922 } else { 2923 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); 2924 } 2925 break; 2926 case INDEX_op_rotr_i64: 2927 if (const_args[2]) { 2928 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); 2929 } else { 2930 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); 2931 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); 2932 } 2933 break; 2934 2935 case INDEX_op_mul_i64: 2936 a0 = args[0], a1 = args[1], a2 = args[2]; 2937 if (const_args[2]) { 2938 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2939 } else { 2940 tcg_out32(s, MULLD | TAB(a0, a1, a2)); 2941 } 2942 break; 2943 case INDEX_op_div_i64: 2944 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); 2945 break; 2946 case INDEX_op_divu_i64: 2947 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); 2948 break; 2949 case INDEX_op_rem_i64: 2950 tcg_out32(s, MODSD | TAB(args[0], args[1], args[2])); 2951 break; 2952 case INDEX_op_remu_i64: 2953 tcg_out32(s, MODUD | TAB(args[0], args[1], args[2])); 2954 break; 2955 2956 case INDEX_op_qemu_ld_i32: 2957 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2958 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2959 args[2], TCG_TYPE_I32); 2960 } else { 2961 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], 2962 args[3], TCG_TYPE_I32); 2963 } 2964 break; 2965 case INDEX_op_qemu_ld_i64: 2966 if (TCG_TARGET_REG_BITS == 64) { 2967 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2968 args[2], TCG_TYPE_I64); 2969 } else if (TARGET_LONG_BITS == 32) { 2970 tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, 2971 args[3], TCG_TYPE_I64); 2972 } else { 2973 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], 2974 args[4], TCG_TYPE_I64); 2975 } 2976 break; 2977 case INDEX_op_qemu_st_i32: 2978 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2979 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 2980 args[2], TCG_TYPE_I32); 2981 } else { 2982 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], 2983 args[3], TCG_TYPE_I32); 2984 } 2985 break; 2986 case INDEX_op_qemu_st_i64: 2987 if (TCG_TARGET_REG_BITS == 64) { 2988 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 2989 args[2], TCG_TYPE_I64); 2990 } else if (TARGET_LONG_BITS == 32) { 2991 tcg_out_qemu_st(s, args[0], args[1], args[2], -1, 2992 args[3], TCG_TYPE_I64); 2993 } else { 2994 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], 2995 args[4], TCG_TYPE_I64); 2996 } 2997 break; 2998 2999 case INDEX_op_setcond_i32: 3000 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], 3001 const_args[2]); 3002 break; 3003 case INDEX_op_setcond_i64: 3004 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], 3005 const_args[2]); 3006 break; 3007 case INDEX_op_setcond2_i32: 3008 tcg_out_setcond2(s, args, const_args); 3009 break; 3010 3011 case INDEX_op_bswap16_i32: 3012 case INDEX_op_bswap16_i64: 3013 tcg_out_bswap16(s, args[0], args[1], args[2]); 3014 break; 3015 case INDEX_op_bswap32_i32: 3016 tcg_out_bswap32(s, args[0], args[1], 0); 3017 break; 3018 case INDEX_op_bswap32_i64: 3019 tcg_out_bswap32(s, args[0], args[1], args[2]); 3020 break; 3021 case INDEX_op_bswap64_i64: 3022 tcg_out_bswap64(s, args[0], args[1]); 3023 break; 3024 3025 case INDEX_op_deposit_i32: 3026 if (const_args[2]) { 3027 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; 3028 tcg_out_andi32(s, args[0], args[0], ~mask); 3029 } else { 3030 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], 3031 32 - args[3] - args[4], 31 - args[3]); 3032 } 3033 break; 3034 case INDEX_op_deposit_i64: 3035 if (const_args[2]) { 3036 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; 3037 tcg_out_andi64(s, args[0], args[0], ~mask); 3038 } else { 3039 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], 3040 64 - args[3] - args[4]); 3041 } 3042 break; 3043 3044 case INDEX_op_extract_i32: 3045 tcg_out_rlw(s, RLWINM, args[0], args[1], 3046 32 - args[2], 32 - args[3], 31); 3047 break; 3048 case INDEX_op_extract_i64: 3049 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); 3050 break; 3051 3052 case INDEX_op_movcond_i32: 3053 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], 3054 args[3], args[4], const_args[2]); 3055 break; 3056 case INDEX_op_movcond_i64: 3057 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], 3058 args[3], args[4], const_args[2]); 3059 break; 3060 3061#if TCG_TARGET_REG_BITS == 64 3062 case INDEX_op_add2_i64: 3063#else 3064 case INDEX_op_add2_i32: 3065#endif 3066 /* Note that the CA bit is defined based on the word size of the 3067 environment. So in 64-bit mode it's always carry-out of bit 63. 3068 The fallback code using deposit works just as well for 32-bit. */ 3069 a0 = args[0], a1 = args[1]; 3070 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { 3071 a0 = TCG_REG_R0; 3072 } 3073 if (const_args[4]) { 3074 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); 3075 } else { 3076 tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); 3077 } 3078 if (const_args[5]) { 3079 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); 3080 } else { 3081 tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); 3082 } 3083 if (a0 != args[0]) { 3084 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3085 } 3086 break; 3087 3088#if TCG_TARGET_REG_BITS == 64 3089 case INDEX_op_sub2_i64: 3090#else 3091 case INDEX_op_sub2_i32: 3092#endif 3093 a0 = args[0], a1 = args[1]; 3094 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { 3095 a0 = TCG_REG_R0; 3096 } 3097 if (const_args[2]) { 3098 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); 3099 } else { 3100 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); 3101 } 3102 if (const_args[3]) { 3103 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); 3104 } else { 3105 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); 3106 } 3107 if (a0 != args[0]) { 3108 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3109 } 3110 break; 3111 3112 case INDEX_op_muluh_i32: 3113 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); 3114 break; 3115 case INDEX_op_mulsh_i32: 3116 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); 3117 break; 3118 case INDEX_op_muluh_i64: 3119 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); 3120 break; 3121 case INDEX_op_mulsh_i64: 3122 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); 3123 break; 3124 3125 case INDEX_op_mb: 3126 tcg_out_mb(s, args[0]); 3127 break; 3128 3129 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 3130 case INDEX_op_mov_i64: 3131 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3132 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3133 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3134 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 3135 case INDEX_op_ext8s_i64: 3136 case INDEX_op_ext8u_i32: 3137 case INDEX_op_ext8u_i64: 3138 case INDEX_op_ext16s_i32: 3139 case INDEX_op_ext16s_i64: 3140 case INDEX_op_ext16u_i32: 3141 case INDEX_op_ext16u_i64: 3142 case INDEX_op_ext32s_i64: 3143 case INDEX_op_ext32u_i64: 3144 case INDEX_op_ext_i32_i64: 3145 case INDEX_op_extu_i32_i64: 3146 case INDEX_op_extrl_i64_i32: 3147 default: 3148 g_assert_not_reached(); 3149 } 3150} 3151 3152int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3153{ 3154 switch (opc) { 3155 case INDEX_op_and_vec: 3156 case INDEX_op_or_vec: 3157 case INDEX_op_xor_vec: 3158 case INDEX_op_andc_vec: 3159 case INDEX_op_not_vec: 3160 case INDEX_op_nor_vec: 3161 case INDEX_op_eqv_vec: 3162 case INDEX_op_nand_vec: 3163 return 1; 3164 case INDEX_op_orc_vec: 3165 return have_isa_2_07; 3166 case INDEX_op_add_vec: 3167 case INDEX_op_sub_vec: 3168 case INDEX_op_smax_vec: 3169 case INDEX_op_smin_vec: 3170 case INDEX_op_umax_vec: 3171 case INDEX_op_umin_vec: 3172 case INDEX_op_shlv_vec: 3173 case INDEX_op_shrv_vec: 3174 case INDEX_op_sarv_vec: 3175 case INDEX_op_rotlv_vec: 3176 return vece <= MO_32 || have_isa_2_07; 3177 case INDEX_op_ssadd_vec: 3178 case INDEX_op_sssub_vec: 3179 case INDEX_op_usadd_vec: 3180 case INDEX_op_ussub_vec: 3181 return vece <= MO_32; 3182 case INDEX_op_cmp_vec: 3183 case INDEX_op_shli_vec: 3184 case INDEX_op_shri_vec: 3185 case INDEX_op_sari_vec: 3186 case INDEX_op_rotli_vec: 3187 return vece <= MO_32 || have_isa_2_07 ? -1 : 0; 3188 case INDEX_op_neg_vec: 3189 return vece >= MO_32 && have_isa_3_00; 3190 case INDEX_op_mul_vec: 3191 switch (vece) { 3192 case MO_8: 3193 case MO_16: 3194 return -1; 3195 case MO_32: 3196 return have_isa_2_07 ? 1 : -1; 3197 case MO_64: 3198 return have_isa_3_10; 3199 } 3200 return 0; 3201 case INDEX_op_bitsel_vec: 3202 return have_vsx; 3203 case INDEX_op_rotrv_vec: 3204 return -1; 3205 default: 3206 return 0; 3207 } 3208} 3209 3210static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 3211 TCGReg dst, TCGReg src) 3212{ 3213 tcg_debug_assert(dst >= TCG_REG_V0); 3214 3215 /* Splat from integer reg allowed via constraints for v3.00. */ 3216 if (src < TCG_REG_V0) { 3217 tcg_debug_assert(have_isa_3_00); 3218 switch (vece) { 3219 case MO_64: 3220 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); 3221 return true; 3222 case MO_32: 3223 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); 3224 return true; 3225 default: 3226 /* Fail, so that we fall back on either dupm or mov+dup. */ 3227 return false; 3228 } 3229 } 3230 3231 /* 3232 * Recall we use (or emulate) VSX integer loads, so the integer is 3233 * right justified within the left (zero-index) double-word. 3234 */ 3235 switch (vece) { 3236 case MO_8: 3237 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); 3238 break; 3239 case MO_16: 3240 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); 3241 break; 3242 case MO_32: 3243 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); 3244 break; 3245 case MO_64: 3246 if (have_vsx) { 3247 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); 3248 break; 3249 } 3250 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); 3251 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); 3252 break; 3253 default: 3254 g_assert_not_reached(); 3255 } 3256 return true; 3257} 3258 3259static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 3260 TCGReg out, TCGReg base, intptr_t offset) 3261{ 3262 int elt; 3263 3264 tcg_debug_assert(out >= TCG_REG_V0); 3265 switch (vece) { 3266 case MO_8: 3267 if (have_isa_3_00) { 3268 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); 3269 } else { 3270 tcg_out_mem_long(s, 0, LVEBX, out, base, offset); 3271 } 3272 elt = extract32(offset, 0, 4); 3273#if !HOST_BIG_ENDIAN 3274 elt ^= 15; 3275#endif 3276 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); 3277 break; 3278 case MO_16: 3279 tcg_debug_assert((offset & 1) == 0); 3280 if (have_isa_3_00) { 3281 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); 3282 } else { 3283 tcg_out_mem_long(s, 0, LVEHX, out, base, offset); 3284 } 3285 elt = extract32(offset, 1, 3); 3286#if !HOST_BIG_ENDIAN 3287 elt ^= 7; 3288#endif 3289 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); 3290 break; 3291 case MO_32: 3292 if (have_isa_3_00) { 3293 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); 3294 break; 3295 } 3296 tcg_debug_assert((offset & 3) == 0); 3297 tcg_out_mem_long(s, 0, LVEWX, out, base, offset); 3298 elt = extract32(offset, 2, 2); 3299#if !HOST_BIG_ENDIAN 3300 elt ^= 3; 3301#endif 3302 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); 3303 break; 3304 case MO_64: 3305 if (have_vsx) { 3306 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); 3307 break; 3308 } 3309 tcg_debug_assert((offset & 7) == 0); 3310 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); 3311 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); 3312 elt = extract32(offset, 3, 1); 3313#if !HOST_BIG_ENDIAN 3314 elt = !elt; 3315#endif 3316 if (elt) { 3317 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); 3318 } else { 3319 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); 3320 } 3321 break; 3322 default: 3323 g_assert_not_reached(); 3324 } 3325 return true; 3326} 3327 3328static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3329 unsigned vecl, unsigned vece, 3330 const TCGArg args[TCG_MAX_OP_ARGS], 3331 const int const_args[TCG_MAX_OP_ARGS]) 3332{ 3333 static const uint32_t 3334 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, 3335 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, 3336 mul_op[4] = { 0, 0, VMULUWM, VMULLD }, 3337 neg_op[4] = { 0, 0, VNEGW, VNEGD }, 3338 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, 3339 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, 3340 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, 3341 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, 3342 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, 3343 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, 3344 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, 3345 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, 3346 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, 3347 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, 3348 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, 3349 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, 3350 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD }, 3351 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD }, 3352 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD }, 3353 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 }, 3354 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 }, 3355 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 }, 3356 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 }, 3357 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 }, 3358 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD }; 3359 3360 TCGType type = vecl + TCG_TYPE_V64; 3361 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3362 uint32_t insn; 3363 3364 switch (opc) { 3365 case INDEX_op_ld_vec: 3366 tcg_out_ld(s, type, a0, a1, a2); 3367 return; 3368 case INDEX_op_st_vec: 3369 tcg_out_st(s, type, a0, a1, a2); 3370 return; 3371 case INDEX_op_dupm_vec: 3372 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3373 return; 3374 3375 case INDEX_op_add_vec: 3376 insn = add_op[vece]; 3377 break; 3378 case INDEX_op_sub_vec: 3379 insn = sub_op[vece]; 3380 break; 3381 case INDEX_op_neg_vec: 3382 insn = neg_op[vece]; 3383 a2 = a1; 3384 a1 = 0; 3385 break; 3386 case INDEX_op_mul_vec: 3387 insn = mul_op[vece]; 3388 break; 3389 case INDEX_op_ssadd_vec: 3390 insn = ssadd_op[vece]; 3391 break; 3392 case INDEX_op_sssub_vec: 3393 insn = sssub_op[vece]; 3394 break; 3395 case INDEX_op_usadd_vec: 3396 insn = usadd_op[vece]; 3397 break; 3398 case INDEX_op_ussub_vec: 3399 insn = ussub_op[vece]; 3400 break; 3401 case INDEX_op_smin_vec: 3402 insn = smin_op[vece]; 3403 break; 3404 case INDEX_op_umin_vec: 3405 insn = umin_op[vece]; 3406 break; 3407 case INDEX_op_smax_vec: 3408 insn = smax_op[vece]; 3409 break; 3410 case INDEX_op_umax_vec: 3411 insn = umax_op[vece]; 3412 break; 3413 case INDEX_op_shlv_vec: 3414 insn = shlv_op[vece]; 3415 break; 3416 case INDEX_op_shrv_vec: 3417 insn = shrv_op[vece]; 3418 break; 3419 case INDEX_op_sarv_vec: 3420 insn = sarv_op[vece]; 3421 break; 3422 case INDEX_op_and_vec: 3423 insn = VAND; 3424 break; 3425 case INDEX_op_or_vec: 3426 insn = VOR; 3427 break; 3428 case INDEX_op_xor_vec: 3429 insn = VXOR; 3430 break; 3431 case INDEX_op_andc_vec: 3432 insn = VANDC; 3433 break; 3434 case INDEX_op_not_vec: 3435 insn = VNOR; 3436 a2 = a1; 3437 break; 3438 case INDEX_op_orc_vec: 3439 insn = VORC; 3440 break; 3441 case INDEX_op_nand_vec: 3442 insn = VNAND; 3443 break; 3444 case INDEX_op_nor_vec: 3445 insn = VNOR; 3446 break; 3447 case INDEX_op_eqv_vec: 3448 insn = VEQV; 3449 break; 3450 3451 case INDEX_op_cmp_vec: 3452 switch (args[3]) { 3453 case TCG_COND_EQ: 3454 insn = eq_op[vece]; 3455 break; 3456 case TCG_COND_NE: 3457 insn = ne_op[vece]; 3458 break; 3459 case TCG_COND_GT: 3460 insn = gts_op[vece]; 3461 break; 3462 case TCG_COND_GTU: 3463 insn = gtu_op[vece]; 3464 break; 3465 default: 3466 g_assert_not_reached(); 3467 } 3468 break; 3469 3470 case INDEX_op_bitsel_vec: 3471 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); 3472 return; 3473 3474 case INDEX_op_dup2_vec: 3475 assert(TCG_TARGET_REG_BITS == 32); 3476 /* With inputs a1 = xLxx, a2 = xHxx */ 3477 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ 3478 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ 3479 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ 3480 return; 3481 3482 case INDEX_op_ppc_mrgh_vec: 3483 insn = mrgh_op[vece]; 3484 break; 3485 case INDEX_op_ppc_mrgl_vec: 3486 insn = mrgl_op[vece]; 3487 break; 3488 case INDEX_op_ppc_muleu_vec: 3489 insn = muleu_op[vece]; 3490 break; 3491 case INDEX_op_ppc_mulou_vec: 3492 insn = mulou_op[vece]; 3493 break; 3494 case INDEX_op_ppc_pkum_vec: 3495 insn = pkum_op[vece]; 3496 break; 3497 case INDEX_op_rotlv_vec: 3498 insn = rotl_op[vece]; 3499 break; 3500 case INDEX_op_ppc_msum_vec: 3501 tcg_debug_assert(vece == MO_16); 3502 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])); 3503 return; 3504 3505 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3506 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3507 default: 3508 g_assert_not_reached(); 3509 } 3510 3511 tcg_debug_assert(insn != 0); 3512 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); 3513} 3514 3515static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, 3516 TCGv_vec v1, TCGArg imm, TCGOpcode opci) 3517{ 3518 TCGv_vec t1; 3519 3520 if (vece == MO_32) { 3521 /* 3522 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3523 * So using negative numbers gets us the 4th bit easily. 3524 */ 3525 imm = sextract32(imm, 0, 5); 3526 } else { 3527 imm &= (8 << vece) - 1; 3528 } 3529 3530 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ 3531 t1 = tcg_constant_vec(type, MO_8, imm); 3532 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), 3533 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3534} 3535 3536static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 3537 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 3538{ 3539 bool need_swap = false, need_inv = false; 3540 3541 tcg_debug_assert(vece <= MO_32 || have_isa_2_07); 3542 3543 switch (cond) { 3544 case TCG_COND_EQ: 3545 case TCG_COND_GT: 3546 case TCG_COND_GTU: 3547 break; 3548 case TCG_COND_NE: 3549 if (have_isa_3_00 && vece <= MO_32) { 3550 break; 3551 } 3552 /* fall through */ 3553 case TCG_COND_LE: 3554 case TCG_COND_LEU: 3555 need_inv = true; 3556 break; 3557 case TCG_COND_LT: 3558 case TCG_COND_LTU: 3559 need_swap = true; 3560 break; 3561 case TCG_COND_GE: 3562 case TCG_COND_GEU: 3563 need_swap = need_inv = true; 3564 break; 3565 default: 3566 g_assert_not_reached(); 3567 } 3568 3569 if (need_inv) { 3570 cond = tcg_invert_cond(cond); 3571 } 3572 if (need_swap) { 3573 TCGv_vec t1; 3574 t1 = v1, v1 = v2, v2 = t1; 3575 cond = tcg_swap_cond(cond); 3576 } 3577 3578 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), 3579 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 3580 3581 if (need_inv) { 3582 tcg_gen_not_vec(vece, v0, v0); 3583 } 3584} 3585 3586static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, 3587 TCGv_vec v1, TCGv_vec v2) 3588{ 3589 TCGv_vec t1 = tcg_temp_new_vec(type); 3590 TCGv_vec t2 = tcg_temp_new_vec(type); 3591 TCGv_vec c0, c16; 3592 3593 switch (vece) { 3594 case MO_8: 3595 case MO_16: 3596 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), 3597 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3598 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), 3599 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3600 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), 3601 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3602 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), 3603 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3604 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), 3605 tcgv_vec_arg(v0), tcgv_vec_arg(t1)); 3606 break; 3607 3608 case MO_32: 3609 tcg_debug_assert(!have_isa_2_07); 3610 /* 3611 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3612 * So using -16 is a quick way to represent 16. 3613 */ 3614 c16 = tcg_constant_vec(type, MO_8, -16); 3615 c0 = tcg_constant_vec(type, MO_8, 0); 3616 3617 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), 3618 tcgv_vec_arg(v2), tcgv_vec_arg(c16)); 3619 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), 3620 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3621 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), 3622 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); 3623 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), 3624 tcgv_vec_arg(t1), tcgv_vec_arg(c16)); 3625 tcg_gen_add_vec(MO_32, v0, t1, t2); 3626 break; 3627 3628 default: 3629 g_assert_not_reached(); 3630 } 3631 tcg_temp_free_vec(t1); 3632 tcg_temp_free_vec(t2); 3633} 3634 3635void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3636 TCGArg a0, ...) 3637{ 3638 va_list va; 3639 TCGv_vec v0, v1, v2, t0; 3640 TCGArg a2; 3641 3642 va_start(va, a0); 3643 v0 = temp_tcgv_vec(arg_temp(a0)); 3644 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3645 a2 = va_arg(va, TCGArg); 3646 3647 switch (opc) { 3648 case INDEX_op_shli_vec: 3649 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); 3650 break; 3651 case INDEX_op_shri_vec: 3652 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); 3653 break; 3654 case INDEX_op_sari_vec: 3655 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); 3656 break; 3657 case INDEX_op_rotli_vec: 3658 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); 3659 break; 3660 case INDEX_op_cmp_vec: 3661 v2 = temp_tcgv_vec(arg_temp(a2)); 3662 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 3663 break; 3664 case INDEX_op_mul_vec: 3665 v2 = temp_tcgv_vec(arg_temp(a2)); 3666 expand_vec_mul(type, vece, v0, v1, v2); 3667 break; 3668 case INDEX_op_rotlv_vec: 3669 v2 = temp_tcgv_vec(arg_temp(a2)); 3670 t0 = tcg_temp_new_vec(type); 3671 tcg_gen_neg_vec(vece, t0, v2); 3672 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3673 tcg_temp_free_vec(t0); 3674 break; 3675 default: 3676 g_assert_not_reached(); 3677 } 3678 va_end(va); 3679} 3680 3681static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3682{ 3683 switch (op) { 3684 case INDEX_op_goto_ptr: 3685 return C_O0_I1(r); 3686 3687 case INDEX_op_ld8u_i32: 3688 case INDEX_op_ld8s_i32: 3689 case INDEX_op_ld16u_i32: 3690 case INDEX_op_ld16s_i32: 3691 case INDEX_op_ld_i32: 3692 case INDEX_op_ctpop_i32: 3693 case INDEX_op_neg_i32: 3694 case INDEX_op_not_i32: 3695 case INDEX_op_ext8s_i32: 3696 case INDEX_op_ext16s_i32: 3697 case INDEX_op_bswap16_i32: 3698 case INDEX_op_bswap32_i32: 3699 case INDEX_op_extract_i32: 3700 case INDEX_op_ld8u_i64: 3701 case INDEX_op_ld8s_i64: 3702 case INDEX_op_ld16u_i64: 3703 case INDEX_op_ld16s_i64: 3704 case INDEX_op_ld32u_i64: 3705 case INDEX_op_ld32s_i64: 3706 case INDEX_op_ld_i64: 3707 case INDEX_op_ctpop_i64: 3708 case INDEX_op_neg_i64: 3709 case INDEX_op_not_i64: 3710 case INDEX_op_ext8s_i64: 3711 case INDEX_op_ext16s_i64: 3712 case INDEX_op_ext32s_i64: 3713 case INDEX_op_ext_i32_i64: 3714 case INDEX_op_extu_i32_i64: 3715 case INDEX_op_bswap16_i64: 3716 case INDEX_op_bswap32_i64: 3717 case INDEX_op_bswap64_i64: 3718 case INDEX_op_extract_i64: 3719 return C_O1_I1(r, r); 3720 3721 case INDEX_op_st8_i32: 3722 case INDEX_op_st16_i32: 3723 case INDEX_op_st_i32: 3724 case INDEX_op_st8_i64: 3725 case INDEX_op_st16_i64: 3726 case INDEX_op_st32_i64: 3727 case INDEX_op_st_i64: 3728 return C_O0_I2(r, r); 3729 3730 case INDEX_op_add_i32: 3731 case INDEX_op_and_i32: 3732 case INDEX_op_or_i32: 3733 case INDEX_op_xor_i32: 3734 case INDEX_op_andc_i32: 3735 case INDEX_op_orc_i32: 3736 case INDEX_op_eqv_i32: 3737 case INDEX_op_shl_i32: 3738 case INDEX_op_shr_i32: 3739 case INDEX_op_sar_i32: 3740 case INDEX_op_rotl_i32: 3741 case INDEX_op_rotr_i32: 3742 case INDEX_op_setcond_i32: 3743 case INDEX_op_and_i64: 3744 case INDEX_op_andc_i64: 3745 case INDEX_op_shl_i64: 3746 case INDEX_op_shr_i64: 3747 case INDEX_op_sar_i64: 3748 case INDEX_op_rotl_i64: 3749 case INDEX_op_rotr_i64: 3750 case INDEX_op_setcond_i64: 3751 return C_O1_I2(r, r, ri); 3752 3753 case INDEX_op_mul_i32: 3754 case INDEX_op_mul_i64: 3755 return C_O1_I2(r, r, rI); 3756 3757 case INDEX_op_div_i32: 3758 case INDEX_op_divu_i32: 3759 case INDEX_op_rem_i32: 3760 case INDEX_op_remu_i32: 3761 case INDEX_op_nand_i32: 3762 case INDEX_op_nor_i32: 3763 case INDEX_op_muluh_i32: 3764 case INDEX_op_mulsh_i32: 3765 case INDEX_op_orc_i64: 3766 case INDEX_op_eqv_i64: 3767 case INDEX_op_nand_i64: 3768 case INDEX_op_nor_i64: 3769 case INDEX_op_div_i64: 3770 case INDEX_op_divu_i64: 3771 case INDEX_op_rem_i64: 3772 case INDEX_op_remu_i64: 3773 case INDEX_op_mulsh_i64: 3774 case INDEX_op_muluh_i64: 3775 return C_O1_I2(r, r, r); 3776 3777 case INDEX_op_sub_i32: 3778 return C_O1_I2(r, rI, ri); 3779 case INDEX_op_add_i64: 3780 return C_O1_I2(r, r, rT); 3781 case INDEX_op_or_i64: 3782 case INDEX_op_xor_i64: 3783 return C_O1_I2(r, r, rU); 3784 case INDEX_op_sub_i64: 3785 return C_O1_I2(r, rI, rT); 3786 case INDEX_op_clz_i32: 3787 case INDEX_op_ctz_i32: 3788 case INDEX_op_clz_i64: 3789 case INDEX_op_ctz_i64: 3790 return C_O1_I2(r, r, rZW); 3791 3792 case INDEX_op_brcond_i32: 3793 case INDEX_op_brcond_i64: 3794 return C_O0_I2(r, ri); 3795 3796 case INDEX_op_movcond_i32: 3797 case INDEX_op_movcond_i64: 3798 return C_O1_I4(r, r, ri, rZ, rZ); 3799 case INDEX_op_deposit_i32: 3800 case INDEX_op_deposit_i64: 3801 return C_O1_I2(r, 0, rZ); 3802 case INDEX_op_brcond2_i32: 3803 return C_O0_I4(r, r, ri, ri); 3804 case INDEX_op_setcond2_i32: 3805 return C_O1_I4(r, r, r, ri, ri); 3806 case INDEX_op_add2_i64: 3807 case INDEX_op_add2_i32: 3808 return C_O2_I4(r, r, r, r, rI, rZM); 3809 case INDEX_op_sub2_i64: 3810 case INDEX_op_sub2_i32: 3811 return C_O2_I4(r, r, rI, rZM, r, r); 3812 3813 case INDEX_op_qemu_ld_i32: 3814 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 3815 ? C_O1_I1(r, L) 3816 : C_O1_I2(r, L, L)); 3817 3818 case INDEX_op_qemu_st_i32: 3819 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 3820 ? C_O0_I2(S, S) 3821 : C_O0_I3(S, S, S)); 3822 3823 case INDEX_op_qemu_ld_i64: 3824 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) 3825 : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L) 3826 : C_O2_I2(L, L, L, L)); 3827 3828 case INDEX_op_qemu_st_i64: 3829 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S) 3830 : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S) 3831 : C_O0_I4(S, S, S, S)); 3832 3833 case INDEX_op_add_vec: 3834 case INDEX_op_sub_vec: 3835 case INDEX_op_mul_vec: 3836 case INDEX_op_and_vec: 3837 case INDEX_op_or_vec: 3838 case INDEX_op_xor_vec: 3839 case INDEX_op_andc_vec: 3840 case INDEX_op_orc_vec: 3841 case INDEX_op_nor_vec: 3842 case INDEX_op_eqv_vec: 3843 case INDEX_op_nand_vec: 3844 case INDEX_op_cmp_vec: 3845 case INDEX_op_ssadd_vec: 3846 case INDEX_op_sssub_vec: 3847 case INDEX_op_usadd_vec: 3848 case INDEX_op_ussub_vec: 3849 case INDEX_op_smax_vec: 3850 case INDEX_op_smin_vec: 3851 case INDEX_op_umax_vec: 3852 case INDEX_op_umin_vec: 3853 case INDEX_op_shlv_vec: 3854 case INDEX_op_shrv_vec: 3855 case INDEX_op_sarv_vec: 3856 case INDEX_op_rotlv_vec: 3857 case INDEX_op_rotrv_vec: 3858 case INDEX_op_ppc_mrgh_vec: 3859 case INDEX_op_ppc_mrgl_vec: 3860 case INDEX_op_ppc_muleu_vec: 3861 case INDEX_op_ppc_mulou_vec: 3862 case INDEX_op_ppc_pkum_vec: 3863 case INDEX_op_dup2_vec: 3864 return C_O1_I2(v, v, v); 3865 3866 case INDEX_op_not_vec: 3867 case INDEX_op_neg_vec: 3868 return C_O1_I1(v, v); 3869 3870 case INDEX_op_dup_vec: 3871 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); 3872 3873 case INDEX_op_ld_vec: 3874 case INDEX_op_dupm_vec: 3875 return C_O1_I1(v, r); 3876 3877 case INDEX_op_st_vec: 3878 return C_O0_I2(v, r); 3879 3880 case INDEX_op_bitsel_vec: 3881 case INDEX_op_ppc_msum_vec: 3882 return C_O1_I3(v, v, v, v); 3883 3884 default: 3885 g_assert_not_reached(); 3886 } 3887} 3888 3889static void tcg_target_init(TCGContext *s) 3890{ 3891 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3892 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); 3893 3894 have_isa = tcg_isa_base; 3895 if (hwcap & PPC_FEATURE_ARCH_2_06) { 3896 have_isa = tcg_isa_2_06; 3897 } 3898#ifdef PPC_FEATURE2_ARCH_2_07 3899 if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { 3900 have_isa = tcg_isa_2_07; 3901 } 3902#endif 3903#ifdef PPC_FEATURE2_ARCH_3_00 3904 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { 3905 have_isa = tcg_isa_3_00; 3906 } 3907#endif 3908#ifdef PPC_FEATURE2_ARCH_3_10 3909 if (hwcap2 & PPC_FEATURE2_ARCH_3_10) { 3910 have_isa = tcg_isa_3_10; 3911 } 3912#endif 3913 3914#ifdef PPC_FEATURE2_HAS_ISEL 3915 /* Prefer explicit instruction from the kernel. */ 3916 have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0; 3917#else 3918 /* Fall back to knowing Power7 (2.06) has ISEL. */ 3919 have_isel = have_isa_2_06; 3920#endif 3921 3922 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { 3923 have_altivec = true; 3924 /* We only care about the portion of VSX that overlaps Altivec. */ 3925 if (hwcap & PPC_FEATURE_HAS_VSX) { 3926 have_vsx = true; 3927 } 3928 } 3929 3930 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 3931 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 3932 if (have_altivec) { 3933 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3934 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3935 } 3936 3937 tcg_target_call_clobber_regs = 0; 3938 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3939 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3940 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3941 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3942 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3943 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3944 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); 3945 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 3946 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 3947 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 3948 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 3949 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 3950 3951 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3952 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3953 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3954 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3955 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3956 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3957 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3958 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3959 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); 3960 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); 3961 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); 3962 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); 3963 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); 3964 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); 3965 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); 3966 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); 3967 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3968 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3969 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3970 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3971 3972 s->reserved_regs = 0; 3973 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ 3974 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ 3975#if defined(_CALL_SYSV) 3976 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ 3977#endif 3978#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 3979 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ 3980#endif 3981 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ 3982 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); 3983 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); 3984 if (USE_REG_TB) { 3985 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ 3986 } 3987} 3988 3989#ifdef __ELF__ 3990typedef struct { 3991 DebugFrameCIE cie; 3992 DebugFrameFDEHeader fde; 3993 uint8_t fde_def_cfa[4]; 3994 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; 3995} DebugFrame; 3996 3997/* We're expecting a 2 byte uleb128 encoded value. */ 3998QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3999 4000#if TCG_TARGET_REG_BITS == 64 4001# define ELF_HOST_MACHINE EM_PPC64 4002#else 4003# define ELF_HOST_MACHINE EM_PPC 4004#endif 4005 4006static DebugFrame debug_frame = { 4007 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4008 .cie.id = -1, 4009 .cie.version = 1, 4010 .cie.code_align = 1, 4011 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ 4012 .cie.return_column = 65, 4013 4014 /* Total FDE size does not include the "len" member. */ 4015 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), 4016 4017 .fde_def_cfa = { 4018 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ 4019 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4020 (FRAME_SIZE >> 7) 4021 }, 4022 .fde_reg_ofs = { 4023 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ 4024 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, 4025 } 4026}; 4027 4028void tcg_register_jit(const void *buf, size_t buf_size) 4029{ 4030 uint8_t *p = &debug_frame.fde_reg_ofs[3]; 4031 int i; 4032 4033 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { 4034 p[0] = 0x80 + tcg_target_callee_save_regs[i]; 4035 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; 4036 } 4037 4038 debug_frame.fde.func_start = (uintptr_t)buf; 4039 debug_frame.fde.func_len = buf_size; 4040 4041 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4042} 4043#endif /* __ELF__ */ 4044#undef VMULEUB 4045#undef VMULEUH 4046#undef VMULEUW 4047#undef VMULOUB 4048#undef VMULOUH 4049#undef VMULOUW 4050#undef VMSUMUHM 4051