1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26#include "../tcg-pool.c.inc" 27#include "../tcg-ldst.c.inc" 28 29/* 30 * Standardize on the _CALL_FOO symbols used by GCC: 31 * Apple XCode does not define _CALL_DARWIN. 32 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit). 33 */ 34#if !defined(_CALL_SYSV) && \ 35 !defined(_CALL_DARWIN) && \ 36 !defined(_CALL_AIX) && \ 37 !defined(_CALL_ELF) 38# if defined(__APPLE__) 39# define _CALL_DARWIN 40# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32 41# define _CALL_SYSV 42# else 43# error "Unknown ABI" 44# endif 45#endif 46 47#if TCG_TARGET_REG_BITS == 64 48# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 49# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 50#else 51# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 52# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 53#endif 54#ifdef _CALL_SYSV 55# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 56# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 57#else 58# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 59# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 60#endif 61 62/* For some memory operations, we need a scratch that isn't R0. For the AIX 63 calling convention, we can re-use the TOC register since we'll be reloading 64 it at every call. Otherwise R12 will do nicely as neither a call-saved 65 register nor a parameter register. */ 66#ifdef _CALL_AIX 67# define TCG_REG_TMP1 TCG_REG_R2 68#else 69# define TCG_REG_TMP1 TCG_REG_R12 70#endif 71#define TCG_REG_TMP2 TCG_REG_R11 72 73#define TCG_VEC_TMP1 TCG_REG_V0 74#define TCG_VEC_TMP2 TCG_REG_V1 75 76#define TCG_REG_TB TCG_REG_R31 77#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) 78 79/* Shorthand for size of a pointer. Avoid promotion to unsigned. */ 80#define SZP ((int)sizeof(void *)) 81 82/* Shorthand for size of a register. */ 83#define SZR (TCG_TARGET_REG_BITS / 8) 84 85#define TCG_CT_CONST_S16 0x100 86#define TCG_CT_CONST_S32 0x400 87#define TCG_CT_CONST_U32 0x800 88#define TCG_CT_CONST_ZERO 0x1000 89#define TCG_CT_CONST_MONE 0x2000 90#define TCG_CT_CONST_WSZ 0x4000 91 92#define ALL_GENERAL_REGS 0xffffffffu 93#define ALL_VECTOR_REGS 0xffffffff00000000ull 94 95TCGPowerISA have_isa; 96static bool have_isel; 97bool have_altivec; 98bool have_vsx; 99 100#ifndef CONFIG_SOFTMMU 101#define TCG_GUEST_BASE_REG 30 102#endif 103 104#ifdef CONFIG_DEBUG_TCG 105static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = { 106 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 107 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 108 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 109 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 110 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 111 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 112 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 113 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 114}; 115#endif 116 117static const int tcg_target_reg_alloc_order[] = { 118 TCG_REG_R14, /* call saved registers */ 119 TCG_REG_R15, 120 TCG_REG_R16, 121 TCG_REG_R17, 122 TCG_REG_R18, 123 TCG_REG_R19, 124 TCG_REG_R20, 125 TCG_REG_R21, 126 TCG_REG_R22, 127 TCG_REG_R23, 128 TCG_REG_R24, 129 TCG_REG_R25, 130 TCG_REG_R26, 131 TCG_REG_R27, 132 TCG_REG_R28, 133 TCG_REG_R29, 134 TCG_REG_R30, 135 TCG_REG_R31, 136 TCG_REG_R12, /* call clobbered, non-arguments */ 137 TCG_REG_R11, 138 TCG_REG_R2, 139 TCG_REG_R13, 140 TCG_REG_R10, /* call clobbered, arguments */ 141 TCG_REG_R9, 142 TCG_REG_R8, 143 TCG_REG_R7, 144 TCG_REG_R6, 145 TCG_REG_R5, 146 TCG_REG_R4, 147 TCG_REG_R3, 148 149 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ 150 TCG_REG_V2, /* call clobbered, vectors */ 151 TCG_REG_V3, 152 TCG_REG_V4, 153 TCG_REG_V5, 154 TCG_REG_V6, 155 TCG_REG_V7, 156 TCG_REG_V8, 157 TCG_REG_V9, 158 TCG_REG_V10, 159 TCG_REG_V11, 160 TCG_REG_V12, 161 TCG_REG_V13, 162 TCG_REG_V14, 163 TCG_REG_V15, 164 TCG_REG_V16, 165 TCG_REG_V17, 166 TCG_REG_V18, 167 TCG_REG_V19, 168}; 169 170static const int tcg_target_call_iarg_regs[] = { 171 TCG_REG_R3, 172 TCG_REG_R4, 173 TCG_REG_R5, 174 TCG_REG_R6, 175 TCG_REG_R7, 176 TCG_REG_R8, 177 TCG_REG_R9, 178 TCG_REG_R10 179}; 180 181static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 182{ 183 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 184 tcg_debug_assert(slot >= 0 && slot <= 1); 185 return TCG_REG_R3 + slot; 186} 187 188static const int tcg_target_callee_save_regs[] = { 189#ifdef _CALL_DARWIN 190 TCG_REG_R11, 191#endif 192 TCG_REG_R14, 193 TCG_REG_R15, 194 TCG_REG_R16, 195 TCG_REG_R17, 196 TCG_REG_R18, 197 TCG_REG_R19, 198 TCG_REG_R20, 199 TCG_REG_R21, 200 TCG_REG_R22, 201 TCG_REG_R23, 202 TCG_REG_R24, 203 TCG_REG_R25, 204 TCG_REG_R26, 205 TCG_REG_R27, /* currently used for the global env */ 206 TCG_REG_R28, 207 TCG_REG_R29, 208 TCG_REG_R30, 209 TCG_REG_R31 210}; 211 212static inline bool in_range_b(tcg_target_long target) 213{ 214 return target == sextract64(target, 0, 26); 215} 216 217static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, 218 const tcg_insn_unit *target) 219{ 220 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 221 tcg_debug_assert(in_range_b(disp)); 222 return disp & 0x3fffffc; 223} 224 225static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 226{ 227 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 228 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 229 230 if (in_range_b(disp)) { 231 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc); 232 return true; 233 } 234 return false; 235} 236 237static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, 238 const tcg_insn_unit *target) 239{ 240 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 241 tcg_debug_assert(disp == (int16_t) disp); 242 return disp & 0xfffc; 243} 244 245static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 246{ 247 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 248 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 249 250 if (disp == (int16_t) disp) { 251 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc); 252 return true; 253 } 254 return false; 255} 256 257/* test if a constant matches the constraint */ 258static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 259{ 260 if (ct & TCG_CT_CONST) { 261 return 1; 262 } 263 264 /* The only 32-bit constraint we use aside from 265 TCG_CT_CONST is TCG_CT_CONST_S16. */ 266 if (type == TCG_TYPE_I32) { 267 val = (int32_t)val; 268 } 269 270 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 271 return 1; 272 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 273 return 1; 274 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 275 return 1; 276 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 277 return 1; 278 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { 279 return 1; 280 } else if ((ct & TCG_CT_CONST_WSZ) 281 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 282 return 1; 283 } 284 return 0; 285} 286 287#define OPCD(opc) ((opc)<<26) 288#define XO19(opc) (OPCD(19)|((opc)<<1)) 289#define MD30(opc) (OPCD(30)|((opc)<<2)) 290#define MDS30(opc) (OPCD(30)|((opc)<<1)) 291#define XO31(opc) (OPCD(31)|((opc)<<1)) 292#define XO58(opc) (OPCD(58)|(opc)) 293#define XO62(opc) (OPCD(62)|(opc)) 294#define VX4(opc) (OPCD(4)|(opc)) 295 296#define B OPCD( 18) 297#define BC OPCD( 16) 298 299#define LBZ OPCD( 34) 300#define LHZ OPCD( 40) 301#define LHA OPCD( 42) 302#define LWZ OPCD( 32) 303#define LWZUX XO31( 55) 304#define LD XO58( 0) 305#define LDX XO31( 21) 306#define LDU XO58( 1) 307#define LDUX XO31( 53) 308#define LWA XO58( 2) 309#define LWAX XO31(341) 310#define LQ OPCD( 56) 311 312#define STB OPCD( 38) 313#define STH OPCD( 44) 314#define STW OPCD( 36) 315#define STD XO62( 0) 316#define STDU XO62( 1) 317#define STDX XO31(149) 318#define STQ XO62( 2) 319 320#define ADDIC OPCD( 12) 321#define ADDI OPCD( 14) 322#define ADDIS OPCD( 15) 323#define ORI OPCD( 24) 324#define ORIS OPCD( 25) 325#define XORI OPCD( 26) 326#define XORIS OPCD( 27) 327#define ANDI OPCD( 28) 328#define ANDIS OPCD( 29) 329#define MULLI OPCD( 7) 330#define CMPLI OPCD( 10) 331#define CMPI OPCD( 11) 332#define SUBFIC OPCD( 8) 333 334#define LWZU OPCD( 33) 335#define STWU OPCD( 37) 336 337#define RLWIMI OPCD( 20) 338#define RLWINM OPCD( 21) 339#define RLWNM OPCD( 23) 340 341#define RLDICL MD30( 0) 342#define RLDICR MD30( 1) 343#define RLDIMI MD30( 3) 344#define RLDCL MDS30( 8) 345 346#define BCLR XO19( 16) 347#define BCCTR XO19(528) 348#define CRAND XO19(257) 349#define CRANDC XO19(129) 350#define CRNAND XO19(225) 351#define CROR XO19(449) 352#define CRNOR XO19( 33) 353 354#define EXTSB XO31(954) 355#define EXTSH XO31(922) 356#define EXTSW XO31(986) 357#define ADD XO31(266) 358#define ADDE XO31(138) 359#define ADDME XO31(234) 360#define ADDZE XO31(202) 361#define ADDC XO31( 10) 362#define AND XO31( 28) 363#define SUBF XO31( 40) 364#define SUBFC XO31( 8) 365#define SUBFE XO31(136) 366#define SUBFME XO31(232) 367#define SUBFZE XO31(200) 368#define OR XO31(444) 369#define XOR XO31(316) 370#define MULLW XO31(235) 371#define MULHW XO31( 75) 372#define MULHWU XO31( 11) 373#define DIVW XO31(491) 374#define DIVWU XO31(459) 375#define MODSW XO31(779) 376#define MODUW XO31(267) 377#define CMP XO31( 0) 378#define CMPL XO31( 32) 379#define LHBRX XO31(790) 380#define LWBRX XO31(534) 381#define LDBRX XO31(532) 382#define STHBRX XO31(918) 383#define STWBRX XO31(662) 384#define STDBRX XO31(660) 385#define MFSPR XO31(339) 386#define MTSPR XO31(467) 387#define SRAWI XO31(824) 388#define NEG XO31(104) 389#define MFCR XO31( 19) 390#define MFOCRF (MFCR | (1u << 20)) 391#define NOR XO31(124) 392#define CNTLZW XO31( 26) 393#define CNTLZD XO31( 58) 394#define CNTTZW XO31(538) 395#define CNTTZD XO31(570) 396#define CNTPOPW XO31(378) 397#define CNTPOPD XO31(506) 398#define ANDC XO31( 60) 399#define ORC XO31(412) 400#define EQV XO31(284) 401#define NAND XO31(476) 402#define ISEL XO31( 15) 403 404#define MULLD XO31(233) 405#define MULHD XO31( 73) 406#define MULHDU XO31( 9) 407#define DIVD XO31(489) 408#define DIVDU XO31(457) 409#define MODSD XO31(777) 410#define MODUD XO31(265) 411 412#define LBZX XO31( 87) 413#define LHZX XO31(279) 414#define LHAX XO31(343) 415#define LWZX XO31( 23) 416#define STBX XO31(215) 417#define STHX XO31(407) 418#define STWX XO31(151) 419 420#define EIEIO XO31(854) 421#define HWSYNC XO31(598) 422#define LWSYNC (HWSYNC | (1u << 21)) 423 424#define SPR(a, b) ((((a)<<5)|(b))<<11) 425#define LR SPR(8, 0) 426#define CTR SPR(9, 0) 427 428#define SLW XO31( 24) 429#define SRW XO31(536) 430#define SRAW XO31(792) 431 432#define SLD XO31( 27) 433#define SRD XO31(539) 434#define SRAD XO31(794) 435#define SRADI XO31(413<<1) 436 437#define BRH XO31(219) 438#define BRW XO31(155) 439#define BRD XO31(187) 440 441#define TW XO31( 4) 442#define TRAP (TW | TO(31)) 443 444#define NOP ORI /* ori 0,0,0 */ 445 446#define LVX XO31(103) 447#define LVEBX XO31(7) 448#define LVEHX XO31(39) 449#define LVEWX XO31(71) 450#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */ 451#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */ 452#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */ 453#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */ 454#define LXSD (OPCD(57) | 2) /* v3.00 */ 455#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */ 456 457#define STVX XO31(231) 458#define STVEWX XO31(199) 459#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */ 460#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */ 461#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */ 462#define STXSD (OPCD(61) | 2) /* v3.00 */ 463 464#define VADDSBS VX4(768) 465#define VADDUBS VX4(512) 466#define VADDUBM VX4(0) 467#define VADDSHS VX4(832) 468#define VADDUHS VX4(576) 469#define VADDUHM VX4(64) 470#define VADDSWS VX4(896) 471#define VADDUWS VX4(640) 472#define VADDUWM VX4(128) 473#define VADDUDM VX4(192) /* v2.07 */ 474 475#define VSUBSBS VX4(1792) 476#define VSUBUBS VX4(1536) 477#define VSUBUBM VX4(1024) 478#define VSUBSHS VX4(1856) 479#define VSUBUHS VX4(1600) 480#define VSUBUHM VX4(1088) 481#define VSUBSWS VX4(1920) 482#define VSUBUWS VX4(1664) 483#define VSUBUWM VX4(1152) 484#define VSUBUDM VX4(1216) /* v2.07 */ 485 486#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ 487#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ 488 489#define VMAXSB VX4(258) 490#define VMAXSH VX4(322) 491#define VMAXSW VX4(386) 492#define VMAXSD VX4(450) /* v2.07 */ 493#define VMAXUB VX4(2) 494#define VMAXUH VX4(66) 495#define VMAXUW VX4(130) 496#define VMAXUD VX4(194) /* v2.07 */ 497#define VMINSB VX4(770) 498#define VMINSH VX4(834) 499#define VMINSW VX4(898) 500#define VMINSD VX4(962) /* v2.07 */ 501#define VMINUB VX4(514) 502#define VMINUH VX4(578) 503#define VMINUW VX4(642) 504#define VMINUD VX4(706) /* v2.07 */ 505 506#define VCMPEQUB VX4(6) 507#define VCMPEQUH VX4(70) 508#define VCMPEQUW VX4(134) 509#define VCMPEQUD VX4(199) /* v2.07 */ 510#define VCMPGTSB VX4(774) 511#define VCMPGTSH VX4(838) 512#define VCMPGTSW VX4(902) 513#define VCMPGTSD VX4(967) /* v2.07 */ 514#define VCMPGTUB VX4(518) 515#define VCMPGTUH VX4(582) 516#define VCMPGTUW VX4(646) 517#define VCMPGTUD VX4(711) /* v2.07 */ 518#define VCMPNEB VX4(7) /* v3.00 */ 519#define VCMPNEH VX4(71) /* v3.00 */ 520#define VCMPNEW VX4(135) /* v3.00 */ 521 522#define VSLB VX4(260) 523#define VSLH VX4(324) 524#define VSLW VX4(388) 525#define VSLD VX4(1476) /* v2.07 */ 526#define VSRB VX4(516) 527#define VSRH VX4(580) 528#define VSRW VX4(644) 529#define VSRD VX4(1732) /* v2.07 */ 530#define VSRAB VX4(772) 531#define VSRAH VX4(836) 532#define VSRAW VX4(900) 533#define VSRAD VX4(964) /* v2.07 */ 534#define VRLB VX4(4) 535#define VRLH VX4(68) 536#define VRLW VX4(132) 537#define VRLD VX4(196) /* v2.07 */ 538 539#define VMULEUB VX4(520) 540#define VMULEUH VX4(584) 541#define VMULEUW VX4(648) /* v2.07 */ 542#define VMULOUB VX4(8) 543#define VMULOUH VX4(72) 544#define VMULOUW VX4(136) /* v2.07 */ 545#define VMULUWM VX4(137) /* v2.07 */ 546#define VMULLD VX4(457) /* v3.10 */ 547#define VMSUMUHM VX4(38) 548 549#define VMRGHB VX4(12) 550#define VMRGHH VX4(76) 551#define VMRGHW VX4(140) 552#define VMRGLB VX4(268) 553#define VMRGLH VX4(332) 554#define VMRGLW VX4(396) 555 556#define VPKUHUM VX4(14) 557#define VPKUWUM VX4(78) 558 559#define VAND VX4(1028) 560#define VANDC VX4(1092) 561#define VNOR VX4(1284) 562#define VOR VX4(1156) 563#define VXOR VX4(1220) 564#define VEQV VX4(1668) /* v2.07 */ 565#define VNAND VX4(1412) /* v2.07 */ 566#define VORC VX4(1348) /* v2.07 */ 567 568#define VSPLTB VX4(524) 569#define VSPLTH VX4(588) 570#define VSPLTW VX4(652) 571#define VSPLTISB VX4(780) 572#define VSPLTISH VX4(844) 573#define VSPLTISW VX4(908) 574 575#define VSLDOI VX4(44) 576 577#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */ 578#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */ 579#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */ 580 581#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */ 582#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */ 583#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */ 584#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */ 585#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */ 586#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */ 587 588#define RT(r) ((r)<<21) 589#define RS(r) ((r)<<21) 590#define RA(r) ((r)<<16) 591#define RB(r) ((r)<<11) 592#define TO(t) ((t)<<21) 593#define SH(s) ((s)<<11) 594#define MB(b) ((b)<<6) 595#define ME(e) ((e)<<1) 596#define BO(o) ((o)<<21) 597#define MB64(b) ((b)<<5) 598#define FXM(b) (1 << (19 - (b))) 599 600#define VRT(r) (((r) & 31) << 21) 601#define VRA(r) (((r) & 31) << 16) 602#define VRB(r) (((r) & 31) << 11) 603#define VRC(r) (((r) & 31) << 6) 604 605#define LK 1 606 607#define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) 608#define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) 609#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) 610#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) 611 612#define BF(n) ((n)<<23) 613#define BI(n, c) (((c)+((n)*4))<<16) 614#define BT(n, c) (((c)+((n)*4))<<21) 615#define BA(n, c) (((c)+((n)*4))<<16) 616#define BB(n, c) (((c)+((n)*4))<<11) 617#define BC_(n, c) (((c)+((n)*4))<<6) 618 619#define BO_COND_TRUE BO(12) 620#define BO_COND_FALSE BO( 4) 621#define BO_ALWAYS BO(20) 622 623enum { 624 CR_LT, 625 CR_GT, 626 CR_EQ, 627 CR_SO 628}; 629 630static const uint32_t tcg_to_bc[] = { 631 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE, 632 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE, 633 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE, 634 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE, 635 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE, 636 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE, 637 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE, 638 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE, 639 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE, 640 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE, 641}; 642 643/* The low bit here is set if the RA and RB fields must be inverted. */ 644static const uint32_t tcg_to_isel[] = { 645 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ), 646 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1, 647 [TCG_COND_LT] = ISEL | BC_(7, CR_LT), 648 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1, 649 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1, 650 [TCG_COND_GT] = ISEL | BC_(7, CR_GT), 651 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT), 652 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1, 653 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1, 654 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), 655}; 656 657static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 658 intptr_t value, intptr_t addend) 659{ 660 const tcg_insn_unit *target; 661 int16_t lo; 662 int32_t hi; 663 664 value += addend; 665 target = (const tcg_insn_unit *)value; 666 667 switch (type) { 668 case R_PPC_REL14: 669 return reloc_pc14(code_ptr, target); 670 case R_PPC_REL24: 671 return reloc_pc24(code_ptr, target); 672 case R_PPC_ADDR16: 673 /* 674 * We are (slightly) abusing this relocation type. In particular, 675 * assert that the low 2 bits are zero, and do not modify them. 676 * That way we can use this with LD et al that have opcode bits 677 * in the low 2 bits of the insn. 678 */ 679 if ((value & 3) || value != (int16_t)value) { 680 return false; 681 } 682 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc); 683 break; 684 case R_PPC_ADDR32: 685 /* 686 * We are abusing this relocation type. Again, this points to 687 * a pair of insns, lis + load. This is an absolute address 688 * relocation for PPC32 so the lis cannot be removed. 689 */ 690 lo = value; 691 hi = value - lo; 692 if (hi + lo != value) { 693 return false; 694 } 695 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); 696 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); 697 break; 698 default: 699 g_assert_not_reached(); 700 } 701 return true; 702} 703 704static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 705 TCGReg base, tcg_target_long offset); 706 707static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 708{ 709 if (ret == arg) { 710 return true; 711 } 712 switch (type) { 713 case TCG_TYPE_I64: 714 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 715 /* fallthru */ 716 case TCG_TYPE_I32: 717 if (ret < TCG_REG_V0) { 718 if (arg < TCG_REG_V0) { 719 tcg_out32(s, OR | SAB(arg, ret, arg)); 720 break; 721 } else if (have_isa_2_07) { 722 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) 723 | VRT(arg) | RA(ret)); 724 break; 725 } else { 726 /* Altivec does not support vector->integer moves. */ 727 return false; 728 } 729 } else if (arg < TCG_REG_V0) { 730 if (have_isa_2_07) { 731 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) 732 | VRT(ret) | RA(arg)); 733 break; 734 } else { 735 /* Altivec does not support integer->vector moves. */ 736 return false; 737 } 738 } 739 /* fallthru */ 740 case TCG_TYPE_V64: 741 case TCG_TYPE_V128: 742 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0); 743 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); 744 break; 745 default: 746 g_assert_not_reached(); 747 } 748 return true; 749} 750 751static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, 752 int sh, int mb) 753{ 754 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 755 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); 756 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); 757 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); 758} 759 760static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, 761 int sh, int mb, int me) 762{ 763 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); 764} 765 766static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 767{ 768 tcg_out32(s, EXTSB | RA(dst) | RS(src)); 769} 770 771static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src) 772{ 773 tcg_out32(s, ANDI | SAI(src, dst, 0xff)); 774} 775 776static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 777{ 778 tcg_out32(s, EXTSH | RA(dst) | RS(src)); 779} 780 781static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src) 782{ 783 tcg_out32(s, ANDI | SAI(src, dst, 0xffff)); 784} 785 786static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) 787{ 788 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 789 tcg_out32(s, EXTSW | RA(dst) | RS(src)); 790} 791 792static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) 793{ 794 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 795 tcg_out_rld(s, RLDICL, dst, src, 0, 32); 796} 797 798static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 799{ 800 tcg_out_ext32s(s, dst, src); 801} 802 803static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 804{ 805 tcg_out_ext32u(s, dst, src); 806} 807 808static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 809{ 810 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 811 tcg_out_mov(s, TCG_TYPE_I32, rd, rn); 812} 813 814static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) 815{ 816 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); 817} 818 819static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) 820{ 821 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); 822} 823 824static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c) 825{ 826 /* Limit immediate shift count lest we create an illegal insn. */ 827 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31)); 828} 829 830static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) 831{ 832 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); 833} 834 835static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) 836{ 837 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); 838} 839 840static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c) 841{ 842 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2)); 843} 844 845static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags) 846{ 847 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 848 849 if (have_isa_3_10) { 850 tcg_out32(s, BRH | RA(dst) | RS(src)); 851 if (flags & TCG_BSWAP_OS) { 852 tcg_out_ext16s(s, TCG_TYPE_REG, dst, dst); 853 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 854 tcg_out_ext16u(s, dst, dst); 855 } 856 return; 857 } 858 859 /* 860 * In the following, 861 * dep(a, b, m) -> (a & ~m) | (b & m) 862 * 863 * Begin with: src = xxxxabcd 864 */ 865 /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */ 866 tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31); 867 /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */ 868 tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23); 869 870 if (flags & TCG_BSWAP_OS) { 871 tcg_out_ext16s(s, TCG_TYPE_REG, dst, tmp); 872 } else { 873 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 874 } 875} 876 877static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags) 878{ 879 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 880 881 if (have_isa_3_10) { 882 tcg_out32(s, BRW | RA(dst) | RS(src)); 883 if (flags & TCG_BSWAP_OS) { 884 tcg_out_ext32s(s, dst, dst); 885 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 886 tcg_out_ext32u(s, dst, dst); 887 } 888 return; 889 } 890 891 /* 892 * Stolen from gcc's builtin_bswap32. 893 * In the following, 894 * dep(a, b, m) -> (a & ~m) | (b & m) 895 * 896 * Begin with: src = xxxxabcd 897 */ 898 /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */ 899 tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31); 900 /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */ 901 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7); 902 /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */ 903 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23); 904 905 if (flags & TCG_BSWAP_OS) { 906 tcg_out_ext32s(s, dst, tmp); 907 } else { 908 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 909 } 910} 911 912static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src) 913{ 914 TCGReg t0 = dst == src ? TCG_REG_R0 : dst; 915 TCGReg t1 = dst == src ? dst : TCG_REG_R0; 916 917 if (have_isa_3_10) { 918 tcg_out32(s, BRD | RA(dst) | RS(src)); 919 return; 920 } 921 922 /* 923 * In the following, 924 * dep(a, b, m) -> (a & ~m) | (b & m) 925 * 926 * Begin with: src = abcdefgh 927 */ 928 /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */ 929 tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31); 930 /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */ 931 tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7); 932 /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */ 933 tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23); 934 935 /* t0 = rol64(t0, 32) = hgfe0000 */ 936 tcg_out_rld(s, RLDICL, t0, t0, 32, 0); 937 /* t1 = rol64(src, 32) = efghabcd */ 938 tcg_out_rld(s, RLDICL, t1, src, 32, 0); 939 940 /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */ 941 tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31); 942 /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */ 943 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7); 944 /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */ 945 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23); 946 947 tcg_out_mov(s, TCG_TYPE_REG, dst, t0); 948} 949 950/* Emit a move into ret of arg, if it can be done in one insn. */ 951static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 952{ 953 if (arg == (int16_t)arg) { 954 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 955 return true; 956 } 957 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 958 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 959 return true; 960 } 961 return false; 962} 963 964static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 965 tcg_target_long arg, bool in_prologue) 966{ 967 intptr_t tb_diff; 968 tcg_target_long tmp; 969 int shift; 970 971 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 972 973 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 974 arg = (int32_t)arg; 975 } 976 977 /* Load 16-bit immediates with one insn. */ 978 if (tcg_out_movi_one(s, ret, arg)) { 979 return; 980 } 981 982 /* Load addresses within the TB with one insn. */ 983 tb_diff = tcg_tbrel_diff(s, (void *)arg); 984 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { 985 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); 986 return; 987 } 988 989 /* Load 32-bit immediates with two insns. Note that we've already 990 eliminated bare ADDIS, so we know both insns are required. */ 991 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 992 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 993 tcg_out32(s, ORI | SAI(ret, ret, arg)); 994 return; 995 } 996 if (arg == (uint32_t)arg && !(arg & 0x8000)) { 997 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 998 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 999 return; 1000 } 1001 1002 /* Load masked 16-bit value. */ 1003 if (arg > 0 && (arg & 0x8000)) { 1004 tmp = arg | 0x7fff; 1005 if ((tmp & (tmp + 1)) == 0) { 1006 int mb = clz64(tmp + 1) + 1; 1007 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1008 tcg_out_rld(s, RLDICL, ret, ret, 0, mb); 1009 return; 1010 } 1011 } 1012 1013 /* Load common masks with 2 insns. */ 1014 shift = ctz64(arg); 1015 tmp = arg >> shift; 1016 if (tmp == (int16_t)tmp) { 1017 tcg_out32(s, ADDI | TAI(ret, 0, tmp)); 1018 tcg_out_shli64(s, ret, ret, shift); 1019 return; 1020 } 1021 shift = clz64(arg); 1022 if (tcg_out_movi_one(s, ret, arg << shift)) { 1023 tcg_out_shri64(s, ret, ret, shift); 1024 return; 1025 } 1026 1027 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ 1028 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { 1029 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); 1030 return; 1031 } 1032 1033 /* Use the constant pool, if possible. */ 1034 if (!in_prologue && USE_REG_TB) { 1035 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, 1036 tcg_tbrel_diff(s, NULL)); 1037 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); 1038 return; 1039 } 1040 1041 tmp = arg >> 31 >> 1; 1042 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); 1043 if (tmp) { 1044 tcg_out_shli64(s, ret, ret, 32); 1045 } 1046 if (arg & 0xffff0000) { 1047 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1048 } 1049 if (arg & 0xffff) { 1050 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1051 } 1052} 1053 1054static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1055 TCGReg ret, int64_t val) 1056{ 1057 uint32_t load_insn; 1058 int rel, low; 1059 intptr_t add; 1060 1061 switch (vece) { 1062 case MO_8: 1063 low = (int8_t)val; 1064 if (low >= -16 && low < 16) { 1065 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); 1066 return; 1067 } 1068 if (have_isa_3_00) { 1069 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); 1070 return; 1071 } 1072 break; 1073 1074 case MO_16: 1075 low = (int16_t)val; 1076 if (low >= -16 && low < 16) { 1077 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); 1078 return; 1079 } 1080 break; 1081 1082 case MO_32: 1083 low = (int32_t)val; 1084 if (low >= -16 && low < 16) { 1085 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); 1086 return; 1087 } 1088 break; 1089 } 1090 1091 /* 1092 * Otherwise we must load the value from the constant pool. 1093 */ 1094 if (USE_REG_TB) { 1095 rel = R_PPC_ADDR16; 1096 add = tcg_tbrel_diff(s, NULL); 1097 } else { 1098 rel = R_PPC_ADDR32; 1099 add = 0; 1100 } 1101 1102 if (have_vsx) { 1103 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX; 1104 load_insn |= VRT(ret) | RB(TCG_REG_TMP1); 1105 if (TCG_TARGET_REG_BITS == 64) { 1106 new_pool_label(s, val, rel, s->code_ptr, add); 1107 } else { 1108 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); 1109 } 1110 } else { 1111 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); 1112 if (TCG_TARGET_REG_BITS == 64) { 1113 new_pool_l2(s, rel, s->code_ptr, add, val, val); 1114 } else { 1115 new_pool_l4(s, rel, s->code_ptr, add, 1116 val >> 32, val, val >> 32, val); 1117 } 1118 } 1119 1120 if (USE_REG_TB) { 1121 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); 1122 load_insn |= RA(TCG_REG_TB); 1123 } else { 1124 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); 1125 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); 1126 } 1127 tcg_out32(s, load_insn); 1128} 1129 1130static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, 1131 tcg_target_long arg) 1132{ 1133 switch (type) { 1134 case TCG_TYPE_I32: 1135 case TCG_TYPE_I64: 1136 tcg_debug_assert(ret < TCG_REG_V0); 1137 tcg_out_movi_int(s, type, ret, arg, false); 1138 break; 1139 1140 default: 1141 g_assert_not_reached(); 1142 } 1143} 1144 1145static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1146{ 1147 return false; 1148} 1149 1150static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1151 tcg_target_long imm) 1152{ 1153 /* This function is only used for passing structs by reference. */ 1154 g_assert_not_reached(); 1155} 1156 1157static bool mask_operand(uint32_t c, int *mb, int *me) 1158{ 1159 uint32_t lsb, test; 1160 1161 /* Accept a bit pattern like: 1162 0....01....1 1163 1....10....0 1164 0..01..10..0 1165 Keep track of the transitions. */ 1166 if (c == 0 || c == -1) { 1167 return false; 1168 } 1169 test = c; 1170 lsb = test & -test; 1171 test += lsb; 1172 if (test & (test - 1)) { 1173 return false; 1174 } 1175 1176 *me = clz32(lsb); 1177 *mb = test ? clz32(test & -test) + 1 : 0; 1178 return true; 1179} 1180 1181static bool mask64_operand(uint64_t c, int *mb, int *me) 1182{ 1183 uint64_t lsb; 1184 1185 if (c == 0) { 1186 return false; 1187 } 1188 1189 lsb = c & -c; 1190 /* Accept 1..10..0. */ 1191 if (c == -lsb) { 1192 *mb = 0; 1193 *me = clz64(lsb); 1194 return true; 1195 } 1196 /* Accept 0..01..1. */ 1197 if (lsb == 1 && (c & (c + 1)) == 0) { 1198 *mb = clz64(c + 1) + 1; 1199 *me = 63; 1200 return true; 1201 } 1202 return false; 1203} 1204 1205static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1206{ 1207 int mb, me; 1208 1209 if (mask_operand(c, &mb, &me)) { 1210 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); 1211 } else if ((c & 0xffff) == c) { 1212 tcg_out32(s, ANDI | SAI(src, dst, c)); 1213 return; 1214 } else if ((c & 0xffff0000) == c) { 1215 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1216 return; 1217 } else { 1218 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); 1219 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1220 } 1221} 1222 1223static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) 1224{ 1225 int mb, me; 1226 1227 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1228 if (mask64_operand(c, &mb, &me)) { 1229 if (mb == 0) { 1230 tcg_out_rld(s, RLDICR, dst, src, 0, me); 1231 } else { 1232 tcg_out_rld(s, RLDICL, dst, src, 0, mb); 1233 } 1234 } else if ((c & 0xffff) == c) { 1235 tcg_out32(s, ANDI | SAI(src, dst, c)); 1236 return; 1237 } else if ((c & 0xffff0000) == c) { 1238 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1239 return; 1240 } else { 1241 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); 1242 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1243 } 1244} 1245 1246static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, 1247 int op_lo, int op_hi) 1248{ 1249 if (c >> 16) { 1250 tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); 1251 src = dst; 1252 } 1253 if (c & 0xffff) { 1254 tcg_out32(s, op_lo | SAI(src, dst, c)); 1255 src = dst; 1256 } 1257} 1258 1259static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1260{ 1261 tcg_out_zori32(s, dst, src, c, ORI, ORIS); 1262} 1263 1264static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1265{ 1266 tcg_out_zori32(s, dst, src, c, XORI, XORIS); 1267} 1268 1269static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) 1270{ 1271 ptrdiff_t disp = tcg_pcrel_diff(s, target); 1272 if (in_range_b(disp)) { 1273 tcg_out32(s, B | (disp & 0x3fffffc) | mask); 1274 } else { 1275 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); 1276 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); 1277 tcg_out32(s, BCCTR | BO_ALWAYS | mask); 1278 } 1279} 1280 1281static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 1282 TCGReg base, tcg_target_long offset) 1283{ 1284 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; 1285 bool is_int_store = false; 1286 TCGReg rs = TCG_REG_TMP1; 1287 1288 switch (opi) { 1289 case LD: case LWA: 1290 align = 3; 1291 /* FALLTHRU */ 1292 default: 1293 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { 1294 rs = rt; 1295 break; 1296 } 1297 break; 1298 case LXSD: 1299 case STXSD: 1300 align = 3; 1301 break; 1302 case LXV: 1303 case STXV: 1304 align = 15; 1305 break; 1306 case STD: 1307 align = 3; 1308 /* FALLTHRU */ 1309 case STB: case STH: case STW: 1310 is_int_store = true; 1311 break; 1312 } 1313 1314 /* For unaligned, or very large offsets, use the indexed form. */ 1315 if (offset & align || offset != (int32_t)offset || opi == 0) { 1316 if (rs == base) { 1317 rs = TCG_REG_R0; 1318 } 1319 tcg_debug_assert(!is_int_store || rs != rt); 1320 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); 1321 tcg_out32(s, opx | TAB(rt & 31, base, rs)); 1322 return; 1323 } 1324 1325 l0 = (int16_t)offset; 1326 offset = (offset - l0) >> 16; 1327 l1 = (int16_t)offset; 1328 1329 if (l1 < 0 && orig >= 0) { 1330 extra = 0x4000; 1331 l1 = (int16_t)(offset - 0x4000); 1332 } 1333 if (l1) { 1334 tcg_out32(s, ADDIS | TAI(rs, base, l1)); 1335 base = rs; 1336 } 1337 if (extra) { 1338 tcg_out32(s, ADDIS | TAI(rs, base, extra)); 1339 base = rs; 1340 } 1341 if (opi != ADDI || base != rt || l0 != 0) { 1342 tcg_out32(s, opi | TAI(rt & 31, base, l0)); 1343 } 1344} 1345 1346static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, 1347 TCGReg va, TCGReg vb, int shb) 1348{ 1349 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); 1350} 1351 1352static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1353 TCGReg base, intptr_t offset) 1354{ 1355 int shift; 1356 1357 switch (type) { 1358 case TCG_TYPE_I32: 1359 if (ret < TCG_REG_V0) { 1360 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); 1361 break; 1362 } 1363 if (have_isa_2_07 && have_vsx) { 1364 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); 1365 break; 1366 } 1367 tcg_debug_assert((offset & 3) == 0); 1368 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); 1369 shift = (offset - 4) & 0xc; 1370 if (shift) { 1371 tcg_out_vsldoi(s, ret, ret, ret, shift); 1372 } 1373 break; 1374 case TCG_TYPE_I64: 1375 if (ret < TCG_REG_V0) { 1376 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1377 tcg_out_mem_long(s, LD, LDX, ret, base, offset); 1378 break; 1379 } 1380 /* fallthru */ 1381 case TCG_TYPE_V64: 1382 tcg_debug_assert(ret >= TCG_REG_V0); 1383 if (have_vsx) { 1384 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, 1385 ret, base, offset); 1386 break; 1387 } 1388 tcg_debug_assert((offset & 7) == 0); 1389 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); 1390 if (offset & 8) { 1391 tcg_out_vsldoi(s, ret, ret, ret, 8); 1392 } 1393 break; 1394 case TCG_TYPE_V128: 1395 tcg_debug_assert(ret >= TCG_REG_V0); 1396 tcg_debug_assert((offset & 15) == 0); 1397 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, 1398 LVX, ret, base, offset); 1399 break; 1400 default: 1401 g_assert_not_reached(); 1402 } 1403} 1404 1405static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1406 TCGReg base, intptr_t offset) 1407{ 1408 int shift; 1409 1410 switch (type) { 1411 case TCG_TYPE_I32: 1412 if (arg < TCG_REG_V0) { 1413 tcg_out_mem_long(s, STW, STWX, arg, base, offset); 1414 break; 1415 } 1416 if (have_isa_2_07 && have_vsx) { 1417 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); 1418 break; 1419 } 1420 assert((offset & 3) == 0); 1421 tcg_debug_assert((offset & 3) == 0); 1422 shift = (offset - 4) & 0xc; 1423 if (shift) { 1424 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); 1425 arg = TCG_VEC_TMP1; 1426 } 1427 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1428 break; 1429 case TCG_TYPE_I64: 1430 if (arg < TCG_REG_V0) { 1431 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1432 tcg_out_mem_long(s, STD, STDX, arg, base, offset); 1433 break; 1434 } 1435 /* fallthru */ 1436 case TCG_TYPE_V64: 1437 tcg_debug_assert(arg >= TCG_REG_V0); 1438 if (have_vsx) { 1439 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, 1440 STXSDX, arg, base, offset); 1441 break; 1442 } 1443 tcg_debug_assert((offset & 7) == 0); 1444 if (offset & 8) { 1445 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); 1446 arg = TCG_VEC_TMP1; 1447 } 1448 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1449 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); 1450 break; 1451 case TCG_TYPE_V128: 1452 tcg_debug_assert(arg >= TCG_REG_V0); 1453 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, 1454 STVX, arg, base, offset); 1455 break; 1456 default: 1457 g_assert_not_reached(); 1458 } 1459} 1460 1461static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1462 TCGReg base, intptr_t ofs) 1463{ 1464 return false; 1465} 1466 1467static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, 1468 int const_arg2, int cr, TCGType type) 1469{ 1470 int imm; 1471 uint32_t op; 1472 1473 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1474 1475 /* Simplify the comparisons below wrt CMPI. */ 1476 if (type == TCG_TYPE_I32) { 1477 arg2 = (int32_t)arg2; 1478 } 1479 1480 switch (cond) { 1481 case TCG_COND_EQ: 1482 case TCG_COND_NE: 1483 if (const_arg2) { 1484 if ((int16_t) arg2 == arg2) { 1485 op = CMPI; 1486 imm = 1; 1487 break; 1488 } else if ((uint16_t) arg2 == arg2) { 1489 op = CMPLI; 1490 imm = 1; 1491 break; 1492 } 1493 } 1494 op = CMPL; 1495 imm = 0; 1496 break; 1497 1498 case TCG_COND_LT: 1499 case TCG_COND_GE: 1500 case TCG_COND_LE: 1501 case TCG_COND_GT: 1502 if (const_arg2) { 1503 if ((int16_t) arg2 == arg2) { 1504 op = CMPI; 1505 imm = 1; 1506 break; 1507 } 1508 } 1509 op = CMP; 1510 imm = 0; 1511 break; 1512 1513 case TCG_COND_LTU: 1514 case TCG_COND_GEU: 1515 case TCG_COND_LEU: 1516 case TCG_COND_GTU: 1517 if (const_arg2) { 1518 if ((uint16_t) arg2 == arg2) { 1519 op = CMPLI; 1520 imm = 1; 1521 break; 1522 } 1523 } 1524 op = CMPL; 1525 imm = 0; 1526 break; 1527 1528 default: 1529 g_assert_not_reached(); 1530 } 1531 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); 1532 1533 if (imm) { 1534 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); 1535 } else { 1536 if (const_arg2) { 1537 tcg_out_movi(s, type, TCG_REG_R0, arg2); 1538 arg2 = TCG_REG_R0; 1539 } 1540 tcg_out32(s, op | RA(arg1) | RB(arg2)); 1541 } 1542} 1543 1544static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, 1545 TCGReg dst, TCGReg src) 1546{ 1547 if (type == TCG_TYPE_I32) { 1548 tcg_out32(s, CNTLZW | RS(src) | RA(dst)); 1549 tcg_out_shri32(s, dst, dst, 5); 1550 } else { 1551 tcg_out32(s, CNTLZD | RS(src) | RA(dst)); 1552 tcg_out_shri64(s, dst, dst, 6); 1553 } 1554} 1555 1556static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src) 1557{ 1558 /* X != 0 implies X + -1 generates a carry. Extra addition 1559 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */ 1560 if (dst != src) { 1561 tcg_out32(s, ADDIC | TAI(dst, src, -1)); 1562 tcg_out32(s, SUBFE | TAB(dst, dst, src)); 1563 } else { 1564 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); 1565 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); 1566 } 1567} 1568 1569static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, 1570 bool const_arg2) 1571{ 1572 if (const_arg2) { 1573 if ((uint32_t)arg2 == arg2) { 1574 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); 1575 } else { 1576 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); 1577 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); 1578 } 1579 } else { 1580 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); 1581 } 1582 return TCG_REG_R0; 1583} 1584 1585static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, 1586 TCGArg arg0, TCGArg arg1, TCGArg arg2, 1587 int const_arg2) 1588{ 1589 int crop, sh; 1590 1591 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1592 1593 /* Ignore high bits of a potential constant arg2. */ 1594 if (type == TCG_TYPE_I32) { 1595 arg2 = (uint32_t)arg2; 1596 } 1597 1598 /* Handle common and trivial cases before handling anything else. */ 1599 if (arg2 == 0) { 1600 switch (cond) { 1601 case TCG_COND_EQ: 1602 tcg_out_setcond_eq0(s, type, arg0, arg1); 1603 return; 1604 case TCG_COND_NE: 1605 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1606 tcg_out_ext32u(s, TCG_REG_R0, arg1); 1607 arg1 = TCG_REG_R0; 1608 } 1609 tcg_out_setcond_ne0(s, arg0, arg1); 1610 return; 1611 case TCG_COND_GE: 1612 tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); 1613 arg1 = arg0; 1614 /* FALLTHRU */ 1615 case TCG_COND_LT: 1616 /* Extract the sign bit. */ 1617 if (type == TCG_TYPE_I32) { 1618 tcg_out_shri32(s, arg0, arg1, 31); 1619 } else { 1620 tcg_out_shri64(s, arg0, arg1, 63); 1621 } 1622 return; 1623 default: 1624 break; 1625 } 1626 } 1627 1628 /* If we have ISEL, we can implement everything with 3 or 4 insns. 1629 All other cases below are also at least 3 insns, so speed up the 1630 code generator by not considering them and always using ISEL. */ 1631 if (have_isel) { 1632 int isel, tab; 1633 1634 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1635 1636 isel = tcg_to_isel[cond]; 1637 1638 tcg_out_movi(s, type, arg0, 1); 1639 if (isel & 1) { 1640 /* arg0 = (bc ? 0 : 1) */ 1641 tab = TAB(arg0, 0, arg0); 1642 isel &= ~1; 1643 } else { 1644 /* arg0 = (bc ? 1 : 0) */ 1645 tcg_out_movi(s, type, TCG_REG_R0, 0); 1646 tab = TAB(arg0, arg0, TCG_REG_R0); 1647 } 1648 tcg_out32(s, isel | tab); 1649 return; 1650 } 1651 1652 switch (cond) { 1653 case TCG_COND_EQ: 1654 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1655 tcg_out_setcond_eq0(s, type, arg0, arg1); 1656 return; 1657 1658 case TCG_COND_NE: 1659 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1660 /* Discard the high bits only once, rather than both inputs. */ 1661 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1662 tcg_out_ext32u(s, TCG_REG_R0, arg1); 1663 arg1 = TCG_REG_R0; 1664 } 1665 tcg_out_setcond_ne0(s, arg0, arg1); 1666 return; 1667 1668 case TCG_COND_GT: 1669 case TCG_COND_GTU: 1670 sh = 30; 1671 crop = 0; 1672 goto crtest; 1673 1674 case TCG_COND_LT: 1675 case TCG_COND_LTU: 1676 sh = 29; 1677 crop = 0; 1678 goto crtest; 1679 1680 case TCG_COND_GE: 1681 case TCG_COND_GEU: 1682 sh = 31; 1683 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT); 1684 goto crtest; 1685 1686 case TCG_COND_LE: 1687 case TCG_COND_LEU: 1688 sh = 31; 1689 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT); 1690 crtest: 1691 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1692 if (crop) { 1693 tcg_out32(s, crop); 1694 } 1695 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1696 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); 1697 break; 1698 1699 default: 1700 g_assert_not_reached(); 1701 } 1702} 1703 1704static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) 1705{ 1706 if (l->has_value) { 1707 bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr); 1708 } else { 1709 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); 1710 } 1711 tcg_out32(s, bc); 1712} 1713 1714static void tcg_out_brcond(TCGContext *s, TCGCond cond, 1715 TCGArg arg1, TCGArg arg2, int const_arg2, 1716 TCGLabel *l, TCGType type) 1717{ 1718 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1719 tcg_out_bc(s, tcg_to_bc[cond], l); 1720} 1721 1722static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, 1723 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, 1724 TCGArg v2, bool const_c2) 1725{ 1726 /* If for some reason both inputs are zero, don't produce bad code. */ 1727 if (v1 == 0 && v2 == 0) { 1728 tcg_out_movi(s, type, dest, 0); 1729 return; 1730 } 1731 1732 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); 1733 1734 if (have_isel) { 1735 int isel = tcg_to_isel[cond]; 1736 1737 /* Swap the V operands if the operation indicates inversion. */ 1738 if (isel & 1) { 1739 int t = v1; 1740 v1 = v2; 1741 v2 = t; 1742 isel &= ~1; 1743 } 1744 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ 1745 if (v2 == 0) { 1746 tcg_out_movi(s, type, TCG_REG_R0, 0); 1747 } 1748 tcg_out32(s, isel | TAB(dest, v1, v2)); 1749 } else { 1750 if (dest == v2) { 1751 cond = tcg_invert_cond(cond); 1752 v2 = v1; 1753 } else if (dest != v1) { 1754 if (v1 == 0) { 1755 tcg_out_movi(s, type, dest, 0); 1756 } else { 1757 tcg_out_mov(s, type, dest, v1); 1758 } 1759 } 1760 /* Branch forward over one insn */ 1761 tcg_out32(s, tcg_to_bc[cond] | 8); 1762 if (v2 == 0) { 1763 tcg_out_movi(s, type, dest, 0); 1764 } else { 1765 tcg_out_mov(s, type, dest, v2); 1766 } 1767 } 1768} 1769 1770static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc, 1771 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2) 1772{ 1773 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { 1774 tcg_out32(s, opc | RA(a0) | RS(a1)); 1775 } else { 1776 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); 1777 /* Note that the only other valid constant for a2 is 0. */ 1778 if (have_isel) { 1779 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); 1780 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0)); 1781 } else if (!const_a2 && a0 == a2) { 1782 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8); 1783 tcg_out32(s, opc | RA(a0) | RS(a1)); 1784 } else { 1785 tcg_out32(s, opc | RA(a0) | RS(a1)); 1786 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8); 1787 if (const_a2) { 1788 tcg_out_movi(s, type, a0, 0); 1789 } else { 1790 tcg_out_mov(s, type, a0, a2); 1791 } 1792 } 1793 } 1794} 1795 1796static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1797 const int *const_args) 1798{ 1799 static const struct { uint8_t bit1, bit2; } bits[] = { 1800 [TCG_COND_LT ] = { CR_LT, CR_LT }, 1801 [TCG_COND_LE ] = { CR_LT, CR_GT }, 1802 [TCG_COND_GT ] = { CR_GT, CR_GT }, 1803 [TCG_COND_GE ] = { CR_GT, CR_LT }, 1804 [TCG_COND_LTU] = { CR_LT, CR_LT }, 1805 [TCG_COND_LEU] = { CR_LT, CR_GT }, 1806 [TCG_COND_GTU] = { CR_GT, CR_GT }, 1807 [TCG_COND_GEU] = { CR_GT, CR_LT }, 1808 }; 1809 1810 TCGCond cond = args[4], cond2; 1811 TCGArg al, ah, bl, bh; 1812 int blconst, bhconst; 1813 int op, bit1, bit2; 1814 1815 al = args[0]; 1816 ah = args[1]; 1817 bl = args[2]; 1818 bh = args[3]; 1819 blconst = const_args[2]; 1820 bhconst = const_args[3]; 1821 1822 switch (cond) { 1823 case TCG_COND_EQ: 1824 op = CRAND; 1825 goto do_equality; 1826 case TCG_COND_NE: 1827 op = CRNAND; 1828 do_equality: 1829 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); 1830 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); 1831 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 1832 break; 1833 1834 case TCG_COND_LT: 1835 case TCG_COND_LE: 1836 case TCG_COND_GT: 1837 case TCG_COND_GE: 1838 case TCG_COND_LTU: 1839 case TCG_COND_LEU: 1840 case TCG_COND_GTU: 1841 case TCG_COND_GEU: 1842 bit1 = bits[cond].bit1; 1843 bit2 = bits[cond].bit2; 1844 op = (bit1 != bit2 ? CRANDC : CRAND); 1845 cond2 = tcg_unsigned_cond(cond); 1846 1847 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); 1848 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); 1849 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); 1850 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); 1851 break; 1852 1853 default: 1854 g_assert_not_reached(); 1855 } 1856} 1857 1858static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 1859 const int *const_args) 1860{ 1861 tcg_out_cmp2(s, args + 1, const_args + 1); 1862 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1863 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); 1864} 1865 1866static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, 1867 const int *const_args) 1868{ 1869 tcg_out_cmp2(s, args, const_args); 1870 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5])); 1871} 1872 1873static void tcg_out_mb(TCGContext *s, TCGArg a0) 1874{ 1875 uint32_t insn; 1876 1877 if (a0 & TCG_MO_ST_LD) { 1878 insn = HWSYNC; 1879 } else { 1880 insn = LWSYNC; 1881 } 1882 1883 tcg_out32(s, insn); 1884} 1885 1886static void tcg_out_call_int(TCGContext *s, int lk, 1887 const tcg_insn_unit *target) 1888{ 1889#ifdef _CALL_AIX 1890 /* Look through the descriptor. If the branch is in range, and we 1891 don't have to spend too much effort on building the toc. */ 1892 const void *tgt = ((const void * const *)target)[0]; 1893 uintptr_t toc = ((const uintptr_t *)target)[1]; 1894 intptr_t diff = tcg_pcrel_diff(s, tgt); 1895 1896 if (in_range_b(diff) && toc == (uint32_t)toc) { 1897 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); 1898 tcg_out_b(s, lk, tgt); 1899 } else { 1900 /* Fold the low bits of the constant into the addresses below. */ 1901 intptr_t arg = (intptr_t)target; 1902 int ofs = (int16_t)arg; 1903 1904 if (ofs + 8 < 0x8000) { 1905 arg -= ofs; 1906 } else { 1907 ofs = 0; 1908 } 1909 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); 1910 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); 1911 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); 1912 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); 1913 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1914 } 1915#elif defined(_CALL_ELF) && _CALL_ELF == 2 1916 intptr_t diff; 1917 1918 /* In the ELFv2 ABI, we have to set up r12 to contain the destination 1919 address, which the callee uses to compute its TOC address. */ 1920 /* FIXME: when the branch is in range, we could avoid r12 load if we 1921 knew that the destination uses the same TOC, and what its local 1922 entry point offset is. */ 1923 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); 1924 1925 diff = tcg_pcrel_diff(s, target); 1926 if (in_range_b(diff)) { 1927 tcg_out_b(s, lk, target); 1928 } else { 1929 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); 1930 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1931 } 1932#else 1933 tcg_out_b(s, lk, target); 1934#endif 1935} 1936 1937static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 1938 const TCGHelperInfo *info) 1939{ 1940 tcg_out_call_int(s, LK, target); 1941} 1942 1943static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = { 1944 [MO_UB] = LBZX, 1945 [MO_UW] = LHZX, 1946 [MO_UL] = LWZX, 1947 [MO_UQ] = LDX, 1948 [MO_SW] = LHAX, 1949 [MO_SL] = LWAX, 1950 [MO_BSWAP | MO_UB] = LBZX, 1951 [MO_BSWAP | MO_UW] = LHBRX, 1952 [MO_BSWAP | MO_UL] = LWBRX, 1953 [MO_BSWAP | MO_UQ] = LDBRX, 1954}; 1955 1956static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = { 1957 [MO_UB] = STBX, 1958 [MO_UW] = STHX, 1959 [MO_UL] = STWX, 1960 [MO_UQ] = STDX, 1961 [MO_BSWAP | MO_UB] = STBX, 1962 [MO_BSWAP | MO_UW] = STHBRX, 1963 [MO_BSWAP | MO_UL] = STWBRX, 1964 [MO_BSWAP | MO_UQ] = STDBRX, 1965}; 1966 1967static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 1968{ 1969 if (arg < 0) { 1970 arg = TCG_REG_TMP1; 1971 } 1972 tcg_out32(s, MFSPR | RT(arg) | LR); 1973 return arg; 1974} 1975 1976/* 1977 * For the purposes of ppc32 sorting 4 input registers into 4 argument 1978 * registers, there is an outside chance we would require 3 temps. 1979 */ 1980static const TCGLdstHelperParam ldst_helper_param = { 1981 .ra_gen = ldst_ra_gen, 1982 .ntmp = 3, 1983 .tmp = { TCG_REG_TMP1, TCG_REG_TMP2, TCG_REG_R0 } 1984}; 1985 1986static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 1987{ 1988 MemOp opc = get_memop(lb->oi); 1989 1990 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1991 return false; 1992 } 1993 1994 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 1995 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & MO_SIZE]); 1996 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 1997 1998 tcg_out_b(s, 0, lb->raddr); 1999 return true; 2000} 2001 2002static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2003{ 2004 MemOp opc = get_memop(lb->oi); 2005 2006 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2007 return false; 2008 } 2009 2010 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 2011 tcg_out_call_int(s, LK, qemu_st_helpers[opc & MO_SIZE]); 2012 2013 tcg_out_b(s, 0, lb->raddr); 2014 return true; 2015} 2016 2017typedef struct { 2018 TCGReg base; 2019 TCGReg index; 2020 TCGAtomAlign aa; 2021} HostAddress; 2022 2023bool tcg_target_has_memory_bswap(MemOp memop) 2024{ 2025 TCGAtomAlign aa; 2026 2027 if ((memop & MO_SIZE) <= MO_64) { 2028 return true; 2029 } 2030 2031 /* 2032 * Reject 16-byte memop with 16-byte atomicity, 2033 * but do allow a pair of 64-bit operations. 2034 */ 2035 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 2036 return aa.atom <= MO_64; 2037} 2038 2039/* 2040 * For softmmu, perform the TLB load and compare. 2041 * For useronly, perform any required alignment tests. 2042 * In both cases, return a TCGLabelQemuLdst structure if the slow path 2043 * is required and fill in @h with the host address for the fast path. 2044 */ 2045static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 2046 TCGReg addrlo, TCGReg addrhi, 2047 MemOpIdx oi, bool is_ld) 2048{ 2049 TCGLabelQemuLdst *ldst = NULL; 2050 MemOp opc = get_memop(oi); 2051 MemOp a_bits, s_bits; 2052 2053 /* 2054 * Book II, Section 1.4, Single-Copy Atomicity, specifies: 2055 * 2056 * Before 3.0, "An access that is not atomic is performed as a set of 2057 * smaller disjoint atomic accesses. In general, the number and alignment 2058 * of these accesses are implementation-dependent." Thus MO_ATOM_IFALIGN. 2059 * 2060 * As of 3.0, "the non-atomic access is performed as described in 2061 * the corresponding list", which matches MO_ATOM_SUBALIGN. 2062 */ 2063 s_bits = opc & MO_SIZE; 2064 h->aa = atom_and_align_for_opc(s, opc, 2065 have_isa_3_00 ? MO_ATOM_SUBALIGN 2066 : MO_ATOM_IFALIGN, 2067 s_bits == MO_128); 2068 a_bits = h->aa.align; 2069 2070#ifdef CONFIG_SOFTMMU 2071 int mem_index = get_mmuidx(oi); 2072 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 2073 : offsetof(CPUTLBEntry, addr_write); 2074 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 2075 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 2076 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 2077 2078 ldst = new_ldst_label(s); 2079 ldst->is_ld = is_ld; 2080 ldst->oi = oi; 2081 ldst->addrlo_reg = addrlo; 2082 ldst->addrhi_reg = addrhi; 2083 2084 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 2085 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 2086 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 2087 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); 2088 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); 2089 2090 /* Extract the page index, shifted into place for tlb index. */ 2091 if (TCG_TARGET_REG_BITS == 32) { 2092 tcg_out_shri32(s, TCG_REG_R0, addrlo, 2093 s->page_bits - CPU_TLB_ENTRY_BITS); 2094 } else { 2095 tcg_out_shri64(s, TCG_REG_R0, addrlo, 2096 s->page_bits - CPU_TLB_ENTRY_BITS); 2097 } 2098 tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); 2099 2100 /* Load the (low part) TLB comparator into TMP2. */ 2101 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2102 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32 2103 ? LWZUX : LDUX); 2104 tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); 2105 } else { 2106 tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); 2107 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2108 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, 2109 TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); 2110 } else { 2111 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); 2112 } 2113 } 2114 2115 /* 2116 * Load the TLB addend for use on the fast path. 2117 * Do this asap to minimize any load use delay. 2118 */ 2119 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2120 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, 2121 offsetof(CPUTLBEntry, addend)); 2122 } 2123 2124 /* Clear the non-page, non-alignment bits from the address in R0. */ 2125 if (TCG_TARGET_REG_BITS == 32) { 2126 /* 2127 * We don't support unaligned accesses on 32-bits. 2128 * Preserve the bottom bits and thus trigger a comparison 2129 * failure on unaligned accesses. 2130 */ 2131 if (a_bits < s_bits) { 2132 a_bits = s_bits; 2133 } 2134 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, 2135 (32 - a_bits) & 31, 31 - s->page_bits); 2136 } else { 2137 TCGReg t = addrlo; 2138 2139 /* 2140 * If the access is unaligned, we need to make sure we fail if we 2141 * cross a page boundary. The trick is to add the access size-1 2142 * to the address before masking the low bits. That will make the 2143 * address overflow to the next page if we cross a page boundary, 2144 * which will then force a mismatch of the TLB compare. 2145 */ 2146 if (a_bits < s_bits) { 2147 unsigned a_mask = (1 << a_bits) - 1; 2148 unsigned s_mask = (1 << s_bits) - 1; 2149 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); 2150 t = TCG_REG_R0; 2151 } 2152 2153 /* Mask the address for the requested alignment. */ 2154 if (TARGET_LONG_BITS == 32) { 2155 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, 2156 (32 - a_bits) & 31, 31 - s->page_bits); 2157 } else if (a_bits == 0) { 2158 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits); 2159 } else { 2160 tcg_out_rld(s, RLDICL, TCG_REG_R0, t, 2161 64 - s->page_bits, s->page_bits - a_bits); 2162 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0); 2163 } 2164 } 2165 2166 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2167 /* Low part comparison into cr7. */ 2168 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 2169 0, 7, TCG_TYPE_I32); 2170 2171 /* Load the high part TLB comparator into TMP2. */ 2172 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, 2173 cmp_off + 4 * !HOST_BIG_ENDIAN); 2174 2175 /* Load addend, deferred for this case. */ 2176 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, 2177 offsetof(CPUTLBEntry, addend)); 2178 2179 /* High part comparison into cr6. */ 2180 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I32); 2181 2182 /* Combine comparisons into cr7. */ 2183 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 2184 } else { 2185 /* Full comparison into cr7. */ 2186 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 2187 0, 7, TCG_TYPE_TL); 2188 } 2189 2190 /* Load a pointer into the current opcode w/conditional branch-link. */ 2191 ldst->label_ptr[0] = s->code_ptr; 2192 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); 2193 2194 h->base = TCG_REG_TMP1; 2195#else 2196 if (a_bits) { 2197 ldst = new_ldst_label(s); 2198 ldst->is_ld = is_ld; 2199 ldst->oi = oi; 2200 ldst->addrlo_reg = addrlo; 2201 ldst->addrhi_reg = addrhi; 2202 2203 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 2204 tcg_debug_assert(a_bits < 16); 2205 tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)); 2206 2207 ldst->label_ptr[0] = s->code_ptr; 2208 tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); 2209 } 2210 2211 h->base = guest_base ? TCG_GUEST_BASE_REG : 0; 2212#endif 2213 2214 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 2215 /* Zero-extend the guest address for use in the host address. */ 2216 tcg_out_ext32u(s, TCG_REG_R0, addrlo); 2217 h->index = TCG_REG_R0; 2218 } else { 2219 h->index = addrlo; 2220 } 2221 2222 return ldst; 2223} 2224 2225static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2226 TCGReg addrlo, TCGReg addrhi, 2227 MemOpIdx oi, TCGType data_type) 2228{ 2229 MemOp opc = get_memop(oi); 2230 TCGLabelQemuLdst *ldst; 2231 HostAddress h; 2232 2233 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 2234 2235 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2236 if (opc & MO_BSWAP) { 2237 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2238 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2239 tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); 2240 } else if (h.base != 0) { 2241 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2242 tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); 2243 tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); 2244 } else if (h.index == datahi) { 2245 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2246 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2247 } else { 2248 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2249 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2250 } 2251 } else { 2252 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; 2253 if (!have_isa_2_06 && insn == LDBRX) { 2254 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2255 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2256 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); 2257 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); 2258 } else if (insn) { 2259 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2260 } else { 2261 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; 2262 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2263 tcg_out_movext(s, TCG_TYPE_REG, datalo, 2264 TCG_TYPE_REG, opc & MO_SSIZE, datalo); 2265 } 2266 } 2267 2268 if (ldst) { 2269 ldst->type = data_type; 2270 ldst->datalo_reg = datalo; 2271 ldst->datahi_reg = datahi; 2272 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2273 } 2274} 2275 2276static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2277 TCGReg addrlo, TCGReg addrhi, 2278 MemOpIdx oi, TCGType data_type) 2279{ 2280 MemOp opc = get_memop(oi); 2281 TCGLabelQemuLdst *ldst; 2282 HostAddress h; 2283 2284 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 2285 2286 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2287 if (opc & MO_BSWAP) { 2288 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2289 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2290 tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); 2291 } else if (h.base != 0) { 2292 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2293 tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); 2294 tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); 2295 } else { 2296 tcg_out32(s, STW | TAI(datahi, h.index, 0)); 2297 tcg_out32(s, STW | TAI(datalo, h.index, 4)); 2298 } 2299 } else { 2300 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; 2301 if (!have_isa_2_06 && insn == STDBRX) { 2302 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2303 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4)); 2304 tcg_out_shri64(s, TCG_REG_R0, datalo, 32); 2305 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1)); 2306 } else { 2307 tcg_out32(s, insn | SAB(datalo, h.base, h.index)); 2308 } 2309 } 2310 2311 if (ldst) { 2312 ldst->type = data_type; 2313 ldst->datalo_reg = datalo; 2314 ldst->datahi_reg = datahi; 2315 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2316 } 2317} 2318 2319static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 2320 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 2321{ 2322 TCGLabelQemuLdst *ldst; 2323 HostAddress h; 2324 bool need_bswap; 2325 uint32_t insn; 2326 TCGReg index; 2327 2328 ldst = prepare_host_addr(s, &h, addr_reg, -1, oi, is_ld); 2329 2330 /* Compose the final address, as LQ/STQ have no indexing. */ 2331 index = h.index; 2332 if (h.base != 0) { 2333 index = TCG_REG_TMP1; 2334 tcg_out32(s, ADD | TAB(index, h.base, h.index)); 2335 } 2336 need_bswap = get_memop(oi) & MO_BSWAP; 2337 2338 if (h.aa.atom == MO_128) { 2339 tcg_debug_assert(!need_bswap); 2340 tcg_debug_assert(datalo & 1); 2341 tcg_debug_assert(datahi == datalo - 1); 2342 insn = is_ld ? LQ : STQ; 2343 tcg_out32(s, insn | TAI(datahi, index, 0)); 2344 } else { 2345 TCGReg d1, d2; 2346 2347 if (HOST_BIG_ENDIAN ^ need_bswap) { 2348 d1 = datahi, d2 = datalo; 2349 } else { 2350 d1 = datalo, d2 = datahi; 2351 } 2352 2353 if (need_bswap) { 2354 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 8); 2355 insn = is_ld ? LDBRX : STDBRX; 2356 tcg_out32(s, insn | TAB(d1, 0, index)); 2357 tcg_out32(s, insn | TAB(d2, index, TCG_REG_R0)); 2358 } else { 2359 insn = is_ld ? LD : STD; 2360 tcg_out32(s, insn | TAI(d1, index, 0)); 2361 tcg_out32(s, insn | TAI(d2, index, 8)); 2362 } 2363 } 2364 2365 if (ldst) { 2366 ldst->type = TCG_TYPE_I128; 2367 ldst->datalo_reg = datalo; 2368 ldst->datahi_reg = datahi; 2369 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2370 } 2371} 2372 2373static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2374{ 2375 int i; 2376 for (i = 0; i < count; ++i) { 2377 p[i] = NOP; 2378 } 2379} 2380 2381/* Parameters for function call generation, used in tcg.c. */ 2382#define TCG_TARGET_STACK_ALIGN 16 2383 2384#ifdef _CALL_AIX 2385# define LINK_AREA_SIZE (6 * SZR) 2386# define LR_OFFSET (1 * SZR) 2387# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) 2388#elif defined(_CALL_DARWIN) 2389# define LINK_AREA_SIZE (6 * SZR) 2390# define LR_OFFSET (2 * SZR) 2391#elif TCG_TARGET_REG_BITS == 64 2392# if defined(_CALL_ELF) && _CALL_ELF == 2 2393# define LINK_AREA_SIZE (4 * SZR) 2394# define LR_OFFSET (1 * SZR) 2395# endif 2396#else /* TCG_TARGET_REG_BITS == 32 */ 2397# if defined(_CALL_SYSV) 2398# define LINK_AREA_SIZE (2 * SZR) 2399# define LR_OFFSET (1 * SZR) 2400# endif 2401#endif 2402#ifndef LR_OFFSET 2403# error "Unhandled abi" 2404#endif 2405#ifndef TCG_TARGET_CALL_STACK_OFFSET 2406# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE 2407#endif 2408 2409#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2410#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) 2411 2412#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ 2413 + TCG_STATIC_CALL_ARGS_SIZE \ 2414 + CPU_TEMP_BUF_SIZE \ 2415 + REG_SAVE_SIZE \ 2416 + TCG_TARGET_STACK_ALIGN - 1) \ 2417 & -TCG_TARGET_STACK_ALIGN) 2418 2419#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) 2420 2421static void tcg_target_qemu_prologue(TCGContext *s) 2422{ 2423 int i; 2424 2425#ifdef _CALL_AIX 2426 const void **desc = (const void **)s->code_ptr; 2427 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */ 2428 desc[1] = 0; /* environment pointer */ 2429 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ 2430#endif 2431 2432 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, 2433 CPU_TEMP_BUF_SIZE); 2434 2435 /* Prologue */ 2436 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); 2437 tcg_out32(s, (SZR == 8 ? STDU : STWU) 2438 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); 2439 2440 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2441 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2442 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2443 } 2444 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2445 2446#ifndef CONFIG_SOFTMMU 2447 if (guest_base) { 2448 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); 2449 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2450 } 2451#endif 2452 2453 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2454 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); 2455 if (USE_REG_TB) { 2456 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2457 } 2458 tcg_out32(s, BCCTR | BO_ALWAYS); 2459 2460 /* Epilogue */ 2461 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2462 2463 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2464 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2465 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2466 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2467 } 2468 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); 2469 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); 2470 tcg_out32(s, BCLR | BO_ALWAYS); 2471} 2472 2473static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 2474{ 2475 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg); 2476 tcg_out_b(s, 0, tcg_code_gen_epilogue); 2477} 2478 2479static void tcg_out_goto_tb(TCGContext *s, int which) 2480{ 2481 uintptr_t ptr = get_jmp_target_addr(s, which); 2482 2483 if (USE_REG_TB) { 2484 ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr); 2485 tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); 2486 2487 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2488 set_jmp_insn_offset(s, which); 2489 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); 2490 2491 /* When branch is out of range, fall through to indirect. */ 2492 tcg_out32(s, BCCTR | BO_ALWAYS); 2493 2494 /* For the unlinked case, need to reset TCG_REG_TB. */ 2495 set_jmp_reset_offset(s, which); 2496 tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, 2497 -tcg_current_code_size(s)); 2498 } else { 2499 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2500 set_jmp_insn_offset(s, which); 2501 tcg_out32(s, NOP); 2502 2503 /* When branch is out of range, fall through to indirect. */ 2504 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); 2505 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr); 2506 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); 2507 tcg_out32(s, BCCTR | BO_ALWAYS); 2508 set_jmp_reset_offset(s, which); 2509 } 2510} 2511 2512void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2513 uintptr_t jmp_rx, uintptr_t jmp_rw) 2514{ 2515 uintptr_t addr = tb->jmp_target_addr[n]; 2516 intptr_t diff = addr - jmp_rx; 2517 tcg_insn_unit insn; 2518 2519 if (in_range_b(diff)) { 2520 insn = B | (diff & 0x3fffffc); 2521 } else if (USE_REG_TB) { 2522 insn = MTSPR | RS(TCG_REG_TB) | CTR; 2523 } else { 2524 insn = NOP; 2525 } 2526 2527 qatomic_set((uint32_t *)jmp_rw, insn); 2528 flush_idcache_range(jmp_rx, jmp_rw, 4); 2529} 2530 2531static void tcg_out_op(TCGContext *s, TCGOpcode opc, 2532 const TCGArg args[TCG_MAX_OP_ARGS], 2533 const int const_args[TCG_MAX_OP_ARGS]) 2534{ 2535 TCGArg a0, a1, a2; 2536 2537 switch (opc) { 2538 case INDEX_op_goto_ptr: 2539 tcg_out32(s, MTSPR | RS(args[0]) | CTR); 2540 if (USE_REG_TB) { 2541 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); 2542 } 2543 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); 2544 tcg_out32(s, BCCTR | BO_ALWAYS); 2545 break; 2546 case INDEX_op_br: 2547 { 2548 TCGLabel *l = arg_label(args[0]); 2549 uint32_t insn = B; 2550 2551 if (l->has_value) { 2552 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr), 2553 l->u.value_ptr); 2554 } else { 2555 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); 2556 } 2557 tcg_out32(s, insn); 2558 } 2559 break; 2560 case INDEX_op_ld8u_i32: 2561 case INDEX_op_ld8u_i64: 2562 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2563 break; 2564 case INDEX_op_ld8s_i32: 2565 case INDEX_op_ld8s_i64: 2566 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2567 tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]); 2568 break; 2569 case INDEX_op_ld16u_i32: 2570 case INDEX_op_ld16u_i64: 2571 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); 2572 break; 2573 case INDEX_op_ld16s_i32: 2574 case INDEX_op_ld16s_i64: 2575 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); 2576 break; 2577 case INDEX_op_ld_i32: 2578 case INDEX_op_ld32u_i64: 2579 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); 2580 break; 2581 case INDEX_op_ld32s_i64: 2582 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); 2583 break; 2584 case INDEX_op_ld_i64: 2585 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); 2586 break; 2587 case INDEX_op_st8_i32: 2588 case INDEX_op_st8_i64: 2589 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); 2590 break; 2591 case INDEX_op_st16_i32: 2592 case INDEX_op_st16_i64: 2593 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); 2594 break; 2595 case INDEX_op_st_i32: 2596 case INDEX_op_st32_i64: 2597 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); 2598 break; 2599 case INDEX_op_st_i64: 2600 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); 2601 break; 2602 2603 case INDEX_op_add_i32: 2604 a0 = args[0], a1 = args[1], a2 = args[2]; 2605 if (const_args[2]) { 2606 do_addi_32: 2607 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); 2608 } else { 2609 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2610 } 2611 break; 2612 case INDEX_op_sub_i32: 2613 a0 = args[0], a1 = args[1], a2 = args[2]; 2614 if (const_args[1]) { 2615 if (const_args[2]) { 2616 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); 2617 } else { 2618 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2619 } 2620 } else if (const_args[2]) { 2621 a2 = -a2; 2622 goto do_addi_32; 2623 } else { 2624 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2625 } 2626 break; 2627 2628 case INDEX_op_and_i32: 2629 a0 = args[0], a1 = args[1], a2 = args[2]; 2630 if (const_args[2]) { 2631 tcg_out_andi32(s, a0, a1, a2); 2632 } else { 2633 tcg_out32(s, AND | SAB(a1, a0, a2)); 2634 } 2635 break; 2636 case INDEX_op_and_i64: 2637 a0 = args[0], a1 = args[1], a2 = args[2]; 2638 if (const_args[2]) { 2639 tcg_out_andi64(s, a0, a1, a2); 2640 } else { 2641 tcg_out32(s, AND | SAB(a1, a0, a2)); 2642 } 2643 break; 2644 case INDEX_op_or_i64: 2645 case INDEX_op_or_i32: 2646 a0 = args[0], a1 = args[1], a2 = args[2]; 2647 if (const_args[2]) { 2648 tcg_out_ori32(s, a0, a1, a2); 2649 } else { 2650 tcg_out32(s, OR | SAB(a1, a0, a2)); 2651 } 2652 break; 2653 case INDEX_op_xor_i64: 2654 case INDEX_op_xor_i32: 2655 a0 = args[0], a1 = args[1], a2 = args[2]; 2656 if (const_args[2]) { 2657 tcg_out_xori32(s, a0, a1, a2); 2658 } else { 2659 tcg_out32(s, XOR | SAB(a1, a0, a2)); 2660 } 2661 break; 2662 case INDEX_op_andc_i32: 2663 a0 = args[0], a1 = args[1], a2 = args[2]; 2664 if (const_args[2]) { 2665 tcg_out_andi32(s, a0, a1, ~a2); 2666 } else { 2667 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2668 } 2669 break; 2670 case INDEX_op_andc_i64: 2671 a0 = args[0], a1 = args[1], a2 = args[2]; 2672 if (const_args[2]) { 2673 tcg_out_andi64(s, a0, a1, ~a2); 2674 } else { 2675 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2676 } 2677 break; 2678 case INDEX_op_orc_i32: 2679 if (const_args[2]) { 2680 tcg_out_ori32(s, args[0], args[1], ~args[2]); 2681 break; 2682 } 2683 /* FALLTHRU */ 2684 case INDEX_op_orc_i64: 2685 tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); 2686 break; 2687 case INDEX_op_eqv_i32: 2688 if (const_args[2]) { 2689 tcg_out_xori32(s, args[0], args[1], ~args[2]); 2690 break; 2691 } 2692 /* FALLTHRU */ 2693 case INDEX_op_eqv_i64: 2694 tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); 2695 break; 2696 case INDEX_op_nand_i32: 2697 case INDEX_op_nand_i64: 2698 tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); 2699 break; 2700 case INDEX_op_nor_i32: 2701 case INDEX_op_nor_i64: 2702 tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); 2703 break; 2704 2705 case INDEX_op_clz_i32: 2706 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], 2707 args[2], const_args[2]); 2708 break; 2709 case INDEX_op_ctz_i32: 2710 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], 2711 args[2], const_args[2]); 2712 break; 2713 case INDEX_op_ctpop_i32: 2714 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); 2715 break; 2716 2717 case INDEX_op_clz_i64: 2718 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], 2719 args[2], const_args[2]); 2720 break; 2721 case INDEX_op_ctz_i64: 2722 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], 2723 args[2], const_args[2]); 2724 break; 2725 case INDEX_op_ctpop_i64: 2726 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); 2727 break; 2728 2729 case INDEX_op_mul_i32: 2730 a0 = args[0], a1 = args[1], a2 = args[2]; 2731 if (const_args[2]) { 2732 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2733 } else { 2734 tcg_out32(s, MULLW | TAB(a0, a1, a2)); 2735 } 2736 break; 2737 2738 case INDEX_op_div_i32: 2739 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); 2740 break; 2741 2742 case INDEX_op_divu_i32: 2743 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); 2744 break; 2745 2746 case INDEX_op_rem_i32: 2747 tcg_out32(s, MODSW | TAB(args[0], args[1], args[2])); 2748 break; 2749 2750 case INDEX_op_remu_i32: 2751 tcg_out32(s, MODUW | TAB(args[0], args[1], args[2])); 2752 break; 2753 2754 case INDEX_op_shl_i32: 2755 if (const_args[2]) { 2756 /* Limit immediate shift count lest we create an illegal insn. */ 2757 tcg_out_shli32(s, args[0], args[1], args[2] & 31); 2758 } else { 2759 tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); 2760 } 2761 break; 2762 case INDEX_op_shr_i32: 2763 if (const_args[2]) { 2764 /* Limit immediate shift count lest we create an illegal insn. */ 2765 tcg_out_shri32(s, args[0], args[1], args[2] & 31); 2766 } else { 2767 tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); 2768 } 2769 break; 2770 case INDEX_op_sar_i32: 2771 if (const_args[2]) { 2772 tcg_out_sari32(s, args[0], args[1], args[2]); 2773 } else { 2774 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); 2775 } 2776 break; 2777 case INDEX_op_rotl_i32: 2778 if (const_args[2]) { 2779 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); 2780 } else { 2781 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) 2782 | MB(0) | ME(31)); 2783 } 2784 break; 2785 case INDEX_op_rotr_i32: 2786 if (const_args[2]) { 2787 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); 2788 } else { 2789 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); 2790 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) 2791 | MB(0) | ME(31)); 2792 } 2793 break; 2794 2795 case INDEX_op_brcond_i32: 2796 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2797 arg_label(args[3]), TCG_TYPE_I32); 2798 break; 2799 case INDEX_op_brcond_i64: 2800 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2801 arg_label(args[3]), TCG_TYPE_I64); 2802 break; 2803 case INDEX_op_brcond2_i32: 2804 tcg_out_brcond2(s, args, const_args); 2805 break; 2806 2807 case INDEX_op_neg_i32: 2808 case INDEX_op_neg_i64: 2809 tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); 2810 break; 2811 2812 case INDEX_op_not_i32: 2813 case INDEX_op_not_i64: 2814 tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); 2815 break; 2816 2817 case INDEX_op_add_i64: 2818 a0 = args[0], a1 = args[1], a2 = args[2]; 2819 if (const_args[2]) { 2820 do_addi_64: 2821 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); 2822 } else { 2823 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2824 } 2825 break; 2826 case INDEX_op_sub_i64: 2827 a0 = args[0], a1 = args[1], a2 = args[2]; 2828 if (const_args[1]) { 2829 if (const_args[2]) { 2830 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); 2831 } else { 2832 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2833 } 2834 } else if (const_args[2]) { 2835 a2 = -a2; 2836 goto do_addi_64; 2837 } else { 2838 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2839 } 2840 break; 2841 2842 case INDEX_op_shl_i64: 2843 if (const_args[2]) { 2844 /* Limit immediate shift count lest we create an illegal insn. */ 2845 tcg_out_shli64(s, args[0], args[1], args[2] & 63); 2846 } else { 2847 tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); 2848 } 2849 break; 2850 case INDEX_op_shr_i64: 2851 if (const_args[2]) { 2852 /* Limit immediate shift count lest we create an illegal insn. */ 2853 tcg_out_shri64(s, args[0], args[1], args[2] & 63); 2854 } else { 2855 tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); 2856 } 2857 break; 2858 case INDEX_op_sar_i64: 2859 if (const_args[2]) { 2860 tcg_out_sari64(s, args[0], args[1], args[2]); 2861 } else { 2862 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); 2863 } 2864 break; 2865 case INDEX_op_rotl_i64: 2866 if (const_args[2]) { 2867 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); 2868 } else { 2869 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); 2870 } 2871 break; 2872 case INDEX_op_rotr_i64: 2873 if (const_args[2]) { 2874 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); 2875 } else { 2876 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); 2877 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); 2878 } 2879 break; 2880 2881 case INDEX_op_mul_i64: 2882 a0 = args[0], a1 = args[1], a2 = args[2]; 2883 if (const_args[2]) { 2884 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2885 } else { 2886 tcg_out32(s, MULLD | TAB(a0, a1, a2)); 2887 } 2888 break; 2889 case INDEX_op_div_i64: 2890 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); 2891 break; 2892 case INDEX_op_divu_i64: 2893 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); 2894 break; 2895 case INDEX_op_rem_i64: 2896 tcg_out32(s, MODSD | TAB(args[0], args[1], args[2])); 2897 break; 2898 case INDEX_op_remu_i64: 2899 tcg_out32(s, MODUD | TAB(args[0], args[1], args[2])); 2900 break; 2901 2902 case INDEX_op_qemu_ld_a64_i32: 2903 if (TCG_TARGET_REG_BITS == 32) { 2904 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], 2905 args[3], TCG_TYPE_I32); 2906 break; 2907 } 2908 /* fall through */ 2909 case INDEX_op_qemu_ld_a32_i32: 2910 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32); 2911 break; 2912 case INDEX_op_qemu_ld_a32_i64: 2913 if (TCG_TARGET_REG_BITS == 64) { 2914 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2915 args[2], TCG_TYPE_I64); 2916 } else { 2917 tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, 2918 args[3], TCG_TYPE_I64); 2919 } 2920 break; 2921 case INDEX_op_qemu_ld_a64_i64: 2922 if (TCG_TARGET_REG_BITS == 64) { 2923 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2924 args[2], TCG_TYPE_I64); 2925 } else { 2926 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], 2927 args[4], TCG_TYPE_I64); 2928 } 2929 break; 2930 case INDEX_op_qemu_ld_a32_i128: 2931 case INDEX_op_qemu_ld_a64_i128: 2932 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2933 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 2934 break; 2935 2936 case INDEX_op_qemu_st_a64_i32: 2937 if (TCG_TARGET_REG_BITS == 32) { 2938 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], 2939 args[3], TCG_TYPE_I32); 2940 break; 2941 } 2942 /* fall through */ 2943 case INDEX_op_qemu_st_a32_i32: 2944 tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32); 2945 break; 2946 case INDEX_op_qemu_st_a32_i64: 2947 if (TCG_TARGET_REG_BITS == 64) { 2948 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 2949 args[2], TCG_TYPE_I64); 2950 } else { 2951 tcg_out_qemu_st(s, args[0], args[1], args[2], -1, 2952 args[3], TCG_TYPE_I64); 2953 } 2954 break; 2955 case INDEX_op_qemu_st_a64_i64: 2956 if (TCG_TARGET_REG_BITS == 64) { 2957 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 2958 args[2], TCG_TYPE_I64); 2959 } else { 2960 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], 2961 args[4], TCG_TYPE_I64); 2962 } 2963 break; 2964 case INDEX_op_qemu_st_a32_i128: 2965 case INDEX_op_qemu_st_a64_i128: 2966 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2967 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 2968 break; 2969 2970 case INDEX_op_setcond_i32: 2971 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], 2972 const_args[2]); 2973 break; 2974 case INDEX_op_setcond_i64: 2975 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], 2976 const_args[2]); 2977 break; 2978 case INDEX_op_setcond2_i32: 2979 tcg_out_setcond2(s, args, const_args); 2980 break; 2981 2982 case INDEX_op_bswap16_i32: 2983 case INDEX_op_bswap16_i64: 2984 tcg_out_bswap16(s, args[0], args[1], args[2]); 2985 break; 2986 case INDEX_op_bswap32_i32: 2987 tcg_out_bswap32(s, args[0], args[1], 0); 2988 break; 2989 case INDEX_op_bswap32_i64: 2990 tcg_out_bswap32(s, args[0], args[1], args[2]); 2991 break; 2992 case INDEX_op_bswap64_i64: 2993 tcg_out_bswap64(s, args[0], args[1]); 2994 break; 2995 2996 case INDEX_op_deposit_i32: 2997 if (const_args[2]) { 2998 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; 2999 tcg_out_andi32(s, args[0], args[0], ~mask); 3000 } else { 3001 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], 3002 32 - args[3] - args[4], 31 - args[3]); 3003 } 3004 break; 3005 case INDEX_op_deposit_i64: 3006 if (const_args[2]) { 3007 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; 3008 tcg_out_andi64(s, args[0], args[0], ~mask); 3009 } else { 3010 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], 3011 64 - args[3] - args[4]); 3012 } 3013 break; 3014 3015 case INDEX_op_extract_i32: 3016 tcg_out_rlw(s, RLWINM, args[0], args[1], 3017 32 - args[2], 32 - args[3], 31); 3018 break; 3019 case INDEX_op_extract_i64: 3020 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); 3021 break; 3022 3023 case INDEX_op_movcond_i32: 3024 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], 3025 args[3], args[4], const_args[2]); 3026 break; 3027 case INDEX_op_movcond_i64: 3028 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], 3029 args[3], args[4], const_args[2]); 3030 break; 3031 3032#if TCG_TARGET_REG_BITS == 64 3033 case INDEX_op_add2_i64: 3034#else 3035 case INDEX_op_add2_i32: 3036#endif 3037 /* Note that the CA bit is defined based on the word size of the 3038 environment. So in 64-bit mode it's always carry-out of bit 63. 3039 The fallback code using deposit works just as well for 32-bit. */ 3040 a0 = args[0], a1 = args[1]; 3041 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { 3042 a0 = TCG_REG_R0; 3043 } 3044 if (const_args[4]) { 3045 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); 3046 } else { 3047 tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); 3048 } 3049 if (const_args[5]) { 3050 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); 3051 } else { 3052 tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); 3053 } 3054 if (a0 != args[0]) { 3055 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3056 } 3057 break; 3058 3059#if TCG_TARGET_REG_BITS == 64 3060 case INDEX_op_sub2_i64: 3061#else 3062 case INDEX_op_sub2_i32: 3063#endif 3064 a0 = args[0], a1 = args[1]; 3065 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { 3066 a0 = TCG_REG_R0; 3067 } 3068 if (const_args[2]) { 3069 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); 3070 } else { 3071 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); 3072 } 3073 if (const_args[3]) { 3074 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); 3075 } else { 3076 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); 3077 } 3078 if (a0 != args[0]) { 3079 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3080 } 3081 break; 3082 3083 case INDEX_op_muluh_i32: 3084 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); 3085 break; 3086 case INDEX_op_mulsh_i32: 3087 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); 3088 break; 3089 case INDEX_op_muluh_i64: 3090 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); 3091 break; 3092 case INDEX_op_mulsh_i64: 3093 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); 3094 break; 3095 3096 case INDEX_op_mb: 3097 tcg_out_mb(s, args[0]); 3098 break; 3099 3100 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 3101 case INDEX_op_mov_i64: 3102 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3103 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3104 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3105 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 3106 case INDEX_op_ext8s_i64: 3107 case INDEX_op_ext8u_i32: 3108 case INDEX_op_ext8u_i64: 3109 case INDEX_op_ext16s_i32: 3110 case INDEX_op_ext16s_i64: 3111 case INDEX_op_ext16u_i32: 3112 case INDEX_op_ext16u_i64: 3113 case INDEX_op_ext32s_i64: 3114 case INDEX_op_ext32u_i64: 3115 case INDEX_op_ext_i32_i64: 3116 case INDEX_op_extu_i32_i64: 3117 case INDEX_op_extrl_i64_i32: 3118 default: 3119 g_assert_not_reached(); 3120 } 3121} 3122 3123int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3124{ 3125 switch (opc) { 3126 case INDEX_op_and_vec: 3127 case INDEX_op_or_vec: 3128 case INDEX_op_xor_vec: 3129 case INDEX_op_andc_vec: 3130 case INDEX_op_not_vec: 3131 case INDEX_op_nor_vec: 3132 case INDEX_op_eqv_vec: 3133 case INDEX_op_nand_vec: 3134 return 1; 3135 case INDEX_op_orc_vec: 3136 return have_isa_2_07; 3137 case INDEX_op_add_vec: 3138 case INDEX_op_sub_vec: 3139 case INDEX_op_smax_vec: 3140 case INDEX_op_smin_vec: 3141 case INDEX_op_umax_vec: 3142 case INDEX_op_umin_vec: 3143 case INDEX_op_shlv_vec: 3144 case INDEX_op_shrv_vec: 3145 case INDEX_op_sarv_vec: 3146 case INDEX_op_rotlv_vec: 3147 return vece <= MO_32 || have_isa_2_07; 3148 case INDEX_op_ssadd_vec: 3149 case INDEX_op_sssub_vec: 3150 case INDEX_op_usadd_vec: 3151 case INDEX_op_ussub_vec: 3152 return vece <= MO_32; 3153 case INDEX_op_cmp_vec: 3154 case INDEX_op_shli_vec: 3155 case INDEX_op_shri_vec: 3156 case INDEX_op_sari_vec: 3157 case INDEX_op_rotli_vec: 3158 return vece <= MO_32 || have_isa_2_07 ? -1 : 0; 3159 case INDEX_op_neg_vec: 3160 return vece >= MO_32 && have_isa_3_00; 3161 case INDEX_op_mul_vec: 3162 switch (vece) { 3163 case MO_8: 3164 case MO_16: 3165 return -1; 3166 case MO_32: 3167 return have_isa_2_07 ? 1 : -1; 3168 case MO_64: 3169 return have_isa_3_10; 3170 } 3171 return 0; 3172 case INDEX_op_bitsel_vec: 3173 return have_vsx; 3174 case INDEX_op_rotrv_vec: 3175 return -1; 3176 default: 3177 return 0; 3178 } 3179} 3180 3181static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 3182 TCGReg dst, TCGReg src) 3183{ 3184 tcg_debug_assert(dst >= TCG_REG_V0); 3185 3186 /* Splat from integer reg allowed via constraints for v3.00. */ 3187 if (src < TCG_REG_V0) { 3188 tcg_debug_assert(have_isa_3_00); 3189 switch (vece) { 3190 case MO_64: 3191 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); 3192 return true; 3193 case MO_32: 3194 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); 3195 return true; 3196 default: 3197 /* Fail, so that we fall back on either dupm or mov+dup. */ 3198 return false; 3199 } 3200 } 3201 3202 /* 3203 * Recall we use (or emulate) VSX integer loads, so the integer is 3204 * right justified within the left (zero-index) double-word. 3205 */ 3206 switch (vece) { 3207 case MO_8: 3208 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); 3209 break; 3210 case MO_16: 3211 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); 3212 break; 3213 case MO_32: 3214 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); 3215 break; 3216 case MO_64: 3217 if (have_vsx) { 3218 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); 3219 break; 3220 } 3221 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); 3222 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); 3223 break; 3224 default: 3225 g_assert_not_reached(); 3226 } 3227 return true; 3228} 3229 3230static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 3231 TCGReg out, TCGReg base, intptr_t offset) 3232{ 3233 int elt; 3234 3235 tcg_debug_assert(out >= TCG_REG_V0); 3236 switch (vece) { 3237 case MO_8: 3238 if (have_isa_3_00) { 3239 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); 3240 } else { 3241 tcg_out_mem_long(s, 0, LVEBX, out, base, offset); 3242 } 3243 elt = extract32(offset, 0, 4); 3244#if !HOST_BIG_ENDIAN 3245 elt ^= 15; 3246#endif 3247 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); 3248 break; 3249 case MO_16: 3250 tcg_debug_assert((offset & 1) == 0); 3251 if (have_isa_3_00) { 3252 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); 3253 } else { 3254 tcg_out_mem_long(s, 0, LVEHX, out, base, offset); 3255 } 3256 elt = extract32(offset, 1, 3); 3257#if !HOST_BIG_ENDIAN 3258 elt ^= 7; 3259#endif 3260 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); 3261 break; 3262 case MO_32: 3263 if (have_isa_3_00) { 3264 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); 3265 break; 3266 } 3267 tcg_debug_assert((offset & 3) == 0); 3268 tcg_out_mem_long(s, 0, LVEWX, out, base, offset); 3269 elt = extract32(offset, 2, 2); 3270#if !HOST_BIG_ENDIAN 3271 elt ^= 3; 3272#endif 3273 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); 3274 break; 3275 case MO_64: 3276 if (have_vsx) { 3277 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); 3278 break; 3279 } 3280 tcg_debug_assert((offset & 7) == 0); 3281 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); 3282 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); 3283 elt = extract32(offset, 3, 1); 3284#if !HOST_BIG_ENDIAN 3285 elt = !elt; 3286#endif 3287 if (elt) { 3288 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); 3289 } else { 3290 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); 3291 } 3292 break; 3293 default: 3294 g_assert_not_reached(); 3295 } 3296 return true; 3297} 3298 3299static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3300 unsigned vecl, unsigned vece, 3301 const TCGArg args[TCG_MAX_OP_ARGS], 3302 const int const_args[TCG_MAX_OP_ARGS]) 3303{ 3304 static const uint32_t 3305 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, 3306 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, 3307 mul_op[4] = { 0, 0, VMULUWM, VMULLD }, 3308 neg_op[4] = { 0, 0, VNEGW, VNEGD }, 3309 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, 3310 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, 3311 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, 3312 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, 3313 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, 3314 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, 3315 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, 3316 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, 3317 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, 3318 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, 3319 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, 3320 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, 3321 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD }, 3322 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD }, 3323 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD }, 3324 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 }, 3325 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 }, 3326 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 }, 3327 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 }, 3328 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 }, 3329 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD }; 3330 3331 TCGType type = vecl + TCG_TYPE_V64; 3332 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3333 uint32_t insn; 3334 3335 switch (opc) { 3336 case INDEX_op_ld_vec: 3337 tcg_out_ld(s, type, a0, a1, a2); 3338 return; 3339 case INDEX_op_st_vec: 3340 tcg_out_st(s, type, a0, a1, a2); 3341 return; 3342 case INDEX_op_dupm_vec: 3343 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3344 return; 3345 3346 case INDEX_op_add_vec: 3347 insn = add_op[vece]; 3348 break; 3349 case INDEX_op_sub_vec: 3350 insn = sub_op[vece]; 3351 break; 3352 case INDEX_op_neg_vec: 3353 insn = neg_op[vece]; 3354 a2 = a1; 3355 a1 = 0; 3356 break; 3357 case INDEX_op_mul_vec: 3358 insn = mul_op[vece]; 3359 break; 3360 case INDEX_op_ssadd_vec: 3361 insn = ssadd_op[vece]; 3362 break; 3363 case INDEX_op_sssub_vec: 3364 insn = sssub_op[vece]; 3365 break; 3366 case INDEX_op_usadd_vec: 3367 insn = usadd_op[vece]; 3368 break; 3369 case INDEX_op_ussub_vec: 3370 insn = ussub_op[vece]; 3371 break; 3372 case INDEX_op_smin_vec: 3373 insn = smin_op[vece]; 3374 break; 3375 case INDEX_op_umin_vec: 3376 insn = umin_op[vece]; 3377 break; 3378 case INDEX_op_smax_vec: 3379 insn = smax_op[vece]; 3380 break; 3381 case INDEX_op_umax_vec: 3382 insn = umax_op[vece]; 3383 break; 3384 case INDEX_op_shlv_vec: 3385 insn = shlv_op[vece]; 3386 break; 3387 case INDEX_op_shrv_vec: 3388 insn = shrv_op[vece]; 3389 break; 3390 case INDEX_op_sarv_vec: 3391 insn = sarv_op[vece]; 3392 break; 3393 case INDEX_op_and_vec: 3394 insn = VAND; 3395 break; 3396 case INDEX_op_or_vec: 3397 insn = VOR; 3398 break; 3399 case INDEX_op_xor_vec: 3400 insn = VXOR; 3401 break; 3402 case INDEX_op_andc_vec: 3403 insn = VANDC; 3404 break; 3405 case INDEX_op_not_vec: 3406 insn = VNOR; 3407 a2 = a1; 3408 break; 3409 case INDEX_op_orc_vec: 3410 insn = VORC; 3411 break; 3412 case INDEX_op_nand_vec: 3413 insn = VNAND; 3414 break; 3415 case INDEX_op_nor_vec: 3416 insn = VNOR; 3417 break; 3418 case INDEX_op_eqv_vec: 3419 insn = VEQV; 3420 break; 3421 3422 case INDEX_op_cmp_vec: 3423 switch (args[3]) { 3424 case TCG_COND_EQ: 3425 insn = eq_op[vece]; 3426 break; 3427 case TCG_COND_NE: 3428 insn = ne_op[vece]; 3429 break; 3430 case TCG_COND_GT: 3431 insn = gts_op[vece]; 3432 break; 3433 case TCG_COND_GTU: 3434 insn = gtu_op[vece]; 3435 break; 3436 default: 3437 g_assert_not_reached(); 3438 } 3439 break; 3440 3441 case INDEX_op_bitsel_vec: 3442 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); 3443 return; 3444 3445 case INDEX_op_dup2_vec: 3446 assert(TCG_TARGET_REG_BITS == 32); 3447 /* With inputs a1 = xLxx, a2 = xHxx */ 3448 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ 3449 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ 3450 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ 3451 return; 3452 3453 case INDEX_op_ppc_mrgh_vec: 3454 insn = mrgh_op[vece]; 3455 break; 3456 case INDEX_op_ppc_mrgl_vec: 3457 insn = mrgl_op[vece]; 3458 break; 3459 case INDEX_op_ppc_muleu_vec: 3460 insn = muleu_op[vece]; 3461 break; 3462 case INDEX_op_ppc_mulou_vec: 3463 insn = mulou_op[vece]; 3464 break; 3465 case INDEX_op_ppc_pkum_vec: 3466 insn = pkum_op[vece]; 3467 break; 3468 case INDEX_op_rotlv_vec: 3469 insn = rotl_op[vece]; 3470 break; 3471 case INDEX_op_ppc_msum_vec: 3472 tcg_debug_assert(vece == MO_16); 3473 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])); 3474 return; 3475 3476 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3477 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3478 default: 3479 g_assert_not_reached(); 3480 } 3481 3482 tcg_debug_assert(insn != 0); 3483 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); 3484} 3485 3486static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, 3487 TCGv_vec v1, TCGArg imm, TCGOpcode opci) 3488{ 3489 TCGv_vec t1; 3490 3491 if (vece == MO_32) { 3492 /* 3493 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3494 * So using negative numbers gets us the 4th bit easily. 3495 */ 3496 imm = sextract32(imm, 0, 5); 3497 } else { 3498 imm &= (8 << vece) - 1; 3499 } 3500 3501 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ 3502 t1 = tcg_constant_vec(type, MO_8, imm); 3503 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), 3504 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3505} 3506 3507static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 3508 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 3509{ 3510 bool need_swap = false, need_inv = false; 3511 3512 tcg_debug_assert(vece <= MO_32 || have_isa_2_07); 3513 3514 switch (cond) { 3515 case TCG_COND_EQ: 3516 case TCG_COND_GT: 3517 case TCG_COND_GTU: 3518 break; 3519 case TCG_COND_NE: 3520 if (have_isa_3_00 && vece <= MO_32) { 3521 break; 3522 } 3523 /* fall through */ 3524 case TCG_COND_LE: 3525 case TCG_COND_LEU: 3526 need_inv = true; 3527 break; 3528 case TCG_COND_LT: 3529 case TCG_COND_LTU: 3530 need_swap = true; 3531 break; 3532 case TCG_COND_GE: 3533 case TCG_COND_GEU: 3534 need_swap = need_inv = true; 3535 break; 3536 default: 3537 g_assert_not_reached(); 3538 } 3539 3540 if (need_inv) { 3541 cond = tcg_invert_cond(cond); 3542 } 3543 if (need_swap) { 3544 TCGv_vec t1; 3545 t1 = v1, v1 = v2, v2 = t1; 3546 cond = tcg_swap_cond(cond); 3547 } 3548 3549 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), 3550 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 3551 3552 if (need_inv) { 3553 tcg_gen_not_vec(vece, v0, v0); 3554 } 3555} 3556 3557static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, 3558 TCGv_vec v1, TCGv_vec v2) 3559{ 3560 TCGv_vec t1 = tcg_temp_new_vec(type); 3561 TCGv_vec t2 = tcg_temp_new_vec(type); 3562 TCGv_vec c0, c16; 3563 3564 switch (vece) { 3565 case MO_8: 3566 case MO_16: 3567 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), 3568 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3569 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), 3570 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3571 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), 3572 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3573 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), 3574 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3575 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), 3576 tcgv_vec_arg(v0), tcgv_vec_arg(t1)); 3577 break; 3578 3579 case MO_32: 3580 tcg_debug_assert(!have_isa_2_07); 3581 /* 3582 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3583 * So using -16 is a quick way to represent 16. 3584 */ 3585 c16 = tcg_constant_vec(type, MO_8, -16); 3586 c0 = tcg_constant_vec(type, MO_8, 0); 3587 3588 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), 3589 tcgv_vec_arg(v2), tcgv_vec_arg(c16)); 3590 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), 3591 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3592 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), 3593 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); 3594 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), 3595 tcgv_vec_arg(t1), tcgv_vec_arg(c16)); 3596 tcg_gen_add_vec(MO_32, v0, t1, t2); 3597 break; 3598 3599 default: 3600 g_assert_not_reached(); 3601 } 3602 tcg_temp_free_vec(t1); 3603 tcg_temp_free_vec(t2); 3604} 3605 3606void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3607 TCGArg a0, ...) 3608{ 3609 va_list va; 3610 TCGv_vec v0, v1, v2, t0; 3611 TCGArg a2; 3612 3613 va_start(va, a0); 3614 v0 = temp_tcgv_vec(arg_temp(a0)); 3615 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3616 a2 = va_arg(va, TCGArg); 3617 3618 switch (opc) { 3619 case INDEX_op_shli_vec: 3620 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); 3621 break; 3622 case INDEX_op_shri_vec: 3623 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); 3624 break; 3625 case INDEX_op_sari_vec: 3626 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); 3627 break; 3628 case INDEX_op_rotli_vec: 3629 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); 3630 break; 3631 case INDEX_op_cmp_vec: 3632 v2 = temp_tcgv_vec(arg_temp(a2)); 3633 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 3634 break; 3635 case INDEX_op_mul_vec: 3636 v2 = temp_tcgv_vec(arg_temp(a2)); 3637 expand_vec_mul(type, vece, v0, v1, v2); 3638 break; 3639 case INDEX_op_rotlv_vec: 3640 v2 = temp_tcgv_vec(arg_temp(a2)); 3641 t0 = tcg_temp_new_vec(type); 3642 tcg_gen_neg_vec(vece, t0, v2); 3643 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3644 tcg_temp_free_vec(t0); 3645 break; 3646 default: 3647 g_assert_not_reached(); 3648 } 3649 va_end(va); 3650} 3651 3652static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3653{ 3654 switch (op) { 3655 case INDEX_op_goto_ptr: 3656 return C_O0_I1(r); 3657 3658 case INDEX_op_ld8u_i32: 3659 case INDEX_op_ld8s_i32: 3660 case INDEX_op_ld16u_i32: 3661 case INDEX_op_ld16s_i32: 3662 case INDEX_op_ld_i32: 3663 case INDEX_op_ctpop_i32: 3664 case INDEX_op_neg_i32: 3665 case INDEX_op_not_i32: 3666 case INDEX_op_ext8s_i32: 3667 case INDEX_op_ext16s_i32: 3668 case INDEX_op_bswap16_i32: 3669 case INDEX_op_bswap32_i32: 3670 case INDEX_op_extract_i32: 3671 case INDEX_op_ld8u_i64: 3672 case INDEX_op_ld8s_i64: 3673 case INDEX_op_ld16u_i64: 3674 case INDEX_op_ld16s_i64: 3675 case INDEX_op_ld32u_i64: 3676 case INDEX_op_ld32s_i64: 3677 case INDEX_op_ld_i64: 3678 case INDEX_op_ctpop_i64: 3679 case INDEX_op_neg_i64: 3680 case INDEX_op_not_i64: 3681 case INDEX_op_ext8s_i64: 3682 case INDEX_op_ext16s_i64: 3683 case INDEX_op_ext32s_i64: 3684 case INDEX_op_ext_i32_i64: 3685 case INDEX_op_extu_i32_i64: 3686 case INDEX_op_bswap16_i64: 3687 case INDEX_op_bswap32_i64: 3688 case INDEX_op_bswap64_i64: 3689 case INDEX_op_extract_i64: 3690 return C_O1_I1(r, r); 3691 3692 case INDEX_op_st8_i32: 3693 case INDEX_op_st16_i32: 3694 case INDEX_op_st_i32: 3695 case INDEX_op_st8_i64: 3696 case INDEX_op_st16_i64: 3697 case INDEX_op_st32_i64: 3698 case INDEX_op_st_i64: 3699 return C_O0_I2(r, r); 3700 3701 case INDEX_op_add_i32: 3702 case INDEX_op_and_i32: 3703 case INDEX_op_or_i32: 3704 case INDEX_op_xor_i32: 3705 case INDEX_op_andc_i32: 3706 case INDEX_op_orc_i32: 3707 case INDEX_op_eqv_i32: 3708 case INDEX_op_shl_i32: 3709 case INDEX_op_shr_i32: 3710 case INDEX_op_sar_i32: 3711 case INDEX_op_rotl_i32: 3712 case INDEX_op_rotr_i32: 3713 case INDEX_op_setcond_i32: 3714 case INDEX_op_and_i64: 3715 case INDEX_op_andc_i64: 3716 case INDEX_op_shl_i64: 3717 case INDEX_op_shr_i64: 3718 case INDEX_op_sar_i64: 3719 case INDEX_op_rotl_i64: 3720 case INDEX_op_rotr_i64: 3721 case INDEX_op_setcond_i64: 3722 return C_O1_I2(r, r, ri); 3723 3724 case INDEX_op_mul_i32: 3725 case INDEX_op_mul_i64: 3726 return C_O1_I2(r, r, rI); 3727 3728 case INDEX_op_div_i32: 3729 case INDEX_op_divu_i32: 3730 case INDEX_op_rem_i32: 3731 case INDEX_op_remu_i32: 3732 case INDEX_op_nand_i32: 3733 case INDEX_op_nor_i32: 3734 case INDEX_op_muluh_i32: 3735 case INDEX_op_mulsh_i32: 3736 case INDEX_op_orc_i64: 3737 case INDEX_op_eqv_i64: 3738 case INDEX_op_nand_i64: 3739 case INDEX_op_nor_i64: 3740 case INDEX_op_div_i64: 3741 case INDEX_op_divu_i64: 3742 case INDEX_op_rem_i64: 3743 case INDEX_op_remu_i64: 3744 case INDEX_op_mulsh_i64: 3745 case INDEX_op_muluh_i64: 3746 return C_O1_I2(r, r, r); 3747 3748 case INDEX_op_sub_i32: 3749 return C_O1_I2(r, rI, ri); 3750 case INDEX_op_add_i64: 3751 return C_O1_I2(r, r, rT); 3752 case INDEX_op_or_i64: 3753 case INDEX_op_xor_i64: 3754 return C_O1_I2(r, r, rU); 3755 case INDEX_op_sub_i64: 3756 return C_O1_I2(r, rI, rT); 3757 case INDEX_op_clz_i32: 3758 case INDEX_op_ctz_i32: 3759 case INDEX_op_clz_i64: 3760 case INDEX_op_ctz_i64: 3761 return C_O1_I2(r, r, rZW); 3762 3763 case INDEX_op_brcond_i32: 3764 case INDEX_op_brcond_i64: 3765 return C_O0_I2(r, ri); 3766 3767 case INDEX_op_movcond_i32: 3768 case INDEX_op_movcond_i64: 3769 return C_O1_I4(r, r, ri, rZ, rZ); 3770 case INDEX_op_deposit_i32: 3771 case INDEX_op_deposit_i64: 3772 return C_O1_I2(r, 0, rZ); 3773 case INDEX_op_brcond2_i32: 3774 return C_O0_I4(r, r, ri, ri); 3775 case INDEX_op_setcond2_i32: 3776 return C_O1_I4(r, r, r, ri, ri); 3777 case INDEX_op_add2_i64: 3778 case INDEX_op_add2_i32: 3779 return C_O2_I4(r, r, r, r, rI, rZM); 3780 case INDEX_op_sub2_i64: 3781 case INDEX_op_sub2_i32: 3782 return C_O2_I4(r, r, rI, rZM, r, r); 3783 3784 case INDEX_op_qemu_ld_a32_i32: 3785 return C_O1_I1(r, r); 3786 case INDEX_op_qemu_ld_a64_i32: 3787 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r); 3788 case INDEX_op_qemu_ld_a32_i64: 3789 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 3790 case INDEX_op_qemu_ld_a64_i64: 3791 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r); 3792 3793 case INDEX_op_qemu_st_a32_i32: 3794 return C_O0_I2(r, r); 3795 case INDEX_op_qemu_st_a64_i32: 3796 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r); 3797 case INDEX_op_qemu_st_a32_i64: 3798 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r); 3799 case INDEX_op_qemu_st_a64_i64: 3800 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r); 3801 3802 case INDEX_op_qemu_ld_a32_i128: 3803 case INDEX_op_qemu_ld_a64_i128: 3804 return C_O2_I1(o, m, r); 3805 case INDEX_op_qemu_st_a32_i128: 3806 case INDEX_op_qemu_st_a64_i128: 3807 return C_O0_I3(o, m, r); 3808 3809 case INDEX_op_add_vec: 3810 case INDEX_op_sub_vec: 3811 case INDEX_op_mul_vec: 3812 case INDEX_op_and_vec: 3813 case INDEX_op_or_vec: 3814 case INDEX_op_xor_vec: 3815 case INDEX_op_andc_vec: 3816 case INDEX_op_orc_vec: 3817 case INDEX_op_nor_vec: 3818 case INDEX_op_eqv_vec: 3819 case INDEX_op_nand_vec: 3820 case INDEX_op_cmp_vec: 3821 case INDEX_op_ssadd_vec: 3822 case INDEX_op_sssub_vec: 3823 case INDEX_op_usadd_vec: 3824 case INDEX_op_ussub_vec: 3825 case INDEX_op_smax_vec: 3826 case INDEX_op_smin_vec: 3827 case INDEX_op_umax_vec: 3828 case INDEX_op_umin_vec: 3829 case INDEX_op_shlv_vec: 3830 case INDEX_op_shrv_vec: 3831 case INDEX_op_sarv_vec: 3832 case INDEX_op_rotlv_vec: 3833 case INDEX_op_rotrv_vec: 3834 case INDEX_op_ppc_mrgh_vec: 3835 case INDEX_op_ppc_mrgl_vec: 3836 case INDEX_op_ppc_muleu_vec: 3837 case INDEX_op_ppc_mulou_vec: 3838 case INDEX_op_ppc_pkum_vec: 3839 case INDEX_op_dup2_vec: 3840 return C_O1_I2(v, v, v); 3841 3842 case INDEX_op_not_vec: 3843 case INDEX_op_neg_vec: 3844 return C_O1_I1(v, v); 3845 3846 case INDEX_op_dup_vec: 3847 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); 3848 3849 case INDEX_op_ld_vec: 3850 case INDEX_op_dupm_vec: 3851 return C_O1_I1(v, r); 3852 3853 case INDEX_op_st_vec: 3854 return C_O0_I2(v, r); 3855 3856 case INDEX_op_bitsel_vec: 3857 case INDEX_op_ppc_msum_vec: 3858 return C_O1_I3(v, v, v, v); 3859 3860 default: 3861 g_assert_not_reached(); 3862 } 3863} 3864 3865static void tcg_target_init(TCGContext *s) 3866{ 3867 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3868 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); 3869 3870 have_isa = tcg_isa_base; 3871 if (hwcap & PPC_FEATURE_ARCH_2_06) { 3872 have_isa = tcg_isa_2_06; 3873 } 3874#ifdef PPC_FEATURE2_ARCH_2_07 3875 if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { 3876 have_isa = tcg_isa_2_07; 3877 } 3878#endif 3879#ifdef PPC_FEATURE2_ARCH_3_00 3880 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { 3881 have_isa = tcg_isa_3_00; 3882 } 3883#endif 3884#ifdef PPC_FEATURE2_ARCH_3_10 3885 if (hwcap2 & PPC_FEATURE2_ARCH_3_10) { 3886 have_isa = tcg_isa_3_10; 3887 } 3888#endif 3889 3890#ifdef PPC_FEATURE2_HAS_ISEL 3891 /* Prefer explicit instruction from the kernel. */ 3892 have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0; 3893#else 3894 /* Fall back to knowing Power7 (2.06) has ISEL. */ 3895 have_isel = have_isa_2_06; 3896#endif 3897 3898 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { 3899 have_altivec = true; 3900 /* We only care about the portion of VSX that overlaps Altivec. */ 3901 if (hwcap & PPC_FEATURE_HAS_VSX) { 3902 have_vsx = true; 3903 } 3904 } 3905 3906 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 3907 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 3908 if (have_altivec) { 3909 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3910 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3911 } 3912 3913 tcg_target_call_clobber_regs = 0; 3914 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3915 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3916 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3917 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3918 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3919 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3920 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); 3921 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 3922 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 3923 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 3924 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 3925 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 3926 3927 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3928 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3929 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3930 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3931 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3932 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3933 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3934 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3935 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); 3936 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); 3937 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); 3938 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); 3939 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); 3940 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); 3941 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); 3942 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); 3943 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3944 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3945 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3946 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3947 3948 s->reserved_regs = 0; 3949 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ 3950 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ 3951#if defined(_CALL_SYSV) 3952 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ 3953#endif 3954#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 3955 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ 3956#endif 3957 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 3958 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 3959 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); 3960 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); 3961 if (USE_REG_TB) { 3962 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ 3963 } 3964} 3965 3966#ifdef __ELF__ 3967typedef struct { 3968 DebugFrameCIE cie; 3969 DebugFrameFDEHeader fde; 3970 uint8_t fde_def_cfa[4]; 3971 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; 3972} DebugFrame; 3973 3974/* We're expecting a 2 byte uleb128 encoded value. */ 3975QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3976 3977#if TCG_TARGET_REG_BITS == 64 3978# define ELF_HOST_MACHINE EM_PPC64 3979#else 3980# define ELF_HOST_MACHINE EM_PPC 3981#endif 3982 3983static DebugFrame debug_frame = { 3984 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3985 .cie.id = -1, 3986 .cie.version = 1, 3987 .cie.code_align = 1, 3988 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ 3989 .cie.return_column = 65, 3990 3991 /* Total FDE size does not include the "len" member. */ 3992 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), 3993 3994 .fde_def_cfa = { 3995 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ 3996 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 3997 (FRAME_SIZE >> 7) 3998 }, 3999 .fde_reg_ofs = { 4000 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ 4001 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, 4002 } 4003}; 4004 4005void tcg_register_jit(const void *buf, size_t buf_size) 4006{ 4007 uint8_t *p = &debug_frame.fde_reg_ofs[3]; 4008 int i; 4009 4010 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { 4011 p[0] = 0x80 + tcg_target_callee_save_regs[i]; 4012 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; 4013 } 4014 4015 debug_frame.fde.func_start = (uintptr_t)buf; 4016 debug_frame.fde.func_len = buf_size; 4017 4018 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4019} 4020#endif /* __ELF__ */ 4021#undef VMULEUB 4022#undef VMULEUH 4023#undef VMULEUW 4024#undef VMULOUB 4025#undef VMULOUH 4026#undef VMULOUW 4027#undef VMSUMUHM 4028