1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26#include "../tcg-pool.c.inc" 27#include "../tcg-ldst.c.inc" 28 29/* 30 * Standardize on the _CALL_FOO symbols used by GCC: 31 * Apple XCode does not define _CALL_DARWIN. 32 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV (32-bit). 33 */ 34#if !defined(_CALL_SYSV) && \ 35 !defined(_CALL_DARWIN) && \ 36 !defined(_CALL_AIX) && \ 37 !defined(_CALL_ELF) 38# if defined(__APPLE__) 39# define _CALL_DARWIN 40# elif defined(__ELF__) && TCG_TARGET_REG_BITS == 32 41# define _CALL_SYSV 42# else 43# error "Unknown ABI" 44# endif 45#endif 46 47#if TCG_TARGET_REG_BITS == 64 48# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 49# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 50#else 51# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 52# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 53#endif 54#ifdef _CALL_SYSV 55# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 56# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 57#else 58# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 59# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 60#endif 61 62/* For some memory operations, we need a scratch that isn't R0. For the AIX 63 calling convention, we can re-use the TOC register since we'll be reloading 64 it at every call. Otherwise R12 will do nicely as neither a call-saved 65 register nor a parameter register. */ 66#ifdef _CALL_AIX 67# define TCG_REG_TMP1 TCG_REG_R2 68#else 69# define TCG_REG_TMP1 TCG_REG_R12 70#endif 71 72#define TCG_VEC_TMP1 TCG_REG_V0 73#define TCG_VEC_TMP2 TCG_REG_V1 74 75#define TCG_REG_TB TCG_REG_R31 76#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) 77 78/* Shorthand for size of a pointer. Avoid promotion to unsigned. */ 79#define SZP ((int)sizeof(void *)) 80 81/* Shorthand for size of a register. */ 82#define SZR (TCG_TARGET_REG_BITS / 8) 83 84#define TCG_CT_CONST_S16 0x100 85#define TCG_CT_CONST_U16 0x200 86#define TCG_CT_CONST_S32 0x400 87#define TCG_CT_CONST_U32 0x800 88#define TCG_CT_CONST_ZERO 0x1000 89#define TCG_CT_CONST_MONE 0x2000 90#define TCG_CT_CONST_WSZ 0x4000 91 92#define ALL_GENERAL_REGS 0xffffffffu 93#define ALL_VECTOR_REGS 0xffffffff00000000ull 94 95#ifdef CONFIG_SOFTMMU 96#define ALL_QLOAD_REGS \ 97 (ALL_GENERAL_REGS & \ 98 ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | (1 << TCG_REG_R5))) 99#define ALL_QSTORE_REGS \ 100 (ALL_GENERAL_REGS & ~((1 << TCG_REG_R3) | (1 << TCG_REG_R4) | \ 101 (1 << TCG_REG_R5) | (1 << TCG_REG_R6))) 102#else 103#define ALL_QLOAD_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_R3)) 104#define ALL_QSTORE_REGS ALL_QLOAD_REGS 105#endif 106 107TCGPowerISA have_isa; 108static bool have_isel; 109bool have_altivec; 110bool have_vsx; 111 112#ifndef CONFIG_SOFTMMU 113#define TCG_GUEST_BASE_REG 30 114#endif 115 116#ifdef CONFIG_DEBUG_TCG 117static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = { 118 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 119 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 120 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 121 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 122 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 123 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 124 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 125 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 126}; 127#endif 128 129static const int tcg_target_reg_alloc_order[] = { 130 TCG_REG_R14, /* call saved registers */ 131 TCG_REG_R15, 132 TCG_REG_R16, 133 TCG_REG_R17, 134 TCG_REG_R18, 135 TCG_REG_R19, 136 TCG_REG_R20, 137 TCG_REG_R21, 138 TCG_REG_R22, 139 TCG_REG_R23, 140 TCG_REG_R24, 141 TCG_REG_R25, 142 TCG_REG_R26, 143 TCG_REG_R27, 144 TCG_REG_R28, 145 TCG_REG_R29, 146 TCG_REG_R30, 147 TCG_REG_R31, 148 TCG_REG_R12, /* call clobbered, non-arguments */ 149 TCG_REG_R11, 150 TCG_REG_R2, 151 TCG_REG_R13, 152 TCG_REG_R10, /* call clobbered, arguments */ 153 TCG_REG_R9, 154 TCG_REG_R8, 155 TCG_REG_R7, 156 TCG_REG_R6, 157 TCG_REG_R5, 158 TCG_REG_R4, 159 TCG_REG_R3, 160 161 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ 162 TCG_REG_V2, /* call clobbered, vectors */ 163 TCG_REG_V3, 164 TCG_REG_V4, 165 TCG_REG_V5, 166 TCG_REG_V6, 167 TCG_REG_V7, 168 TCG_REG_V8, 169 TCG_REG_V9, 170 TCG_REG_V10, 171 TCG_REG_V11, 172 TCG_REG_V12, 173 TCG_REG_V13, 174 TCG_REG_V14, 175 TCG_REG_V15, 176 TCG_REG_V16, 177 TCG_REG_V17, 178 TCG_REG_V18, 179 TCG_REG_V19, 180}; 181 182static const int tcg_target_call_iarg_regs[] = { 183 TCG_REG_R3, 184 TCG_REG_R4, 185 TCG_REG_R5, 186 TCG_REG_R6, 187 TCG_REG_R7, 188 TCG_REG_R8, 189 TCG_REG_R9, 190 TCG_REG_R10 191}; 192 193static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 194{ 195 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 196 tcg_debug_assert(slot >= 0 && slot <= 1); 197 return TCG_REG_R3 + slot; 198} 199 200static const int tcg_target_callee_save_regs[] = { 201#ifdef _CALL_DARWIN 202 TCG_REG_R11, 203#endif 204 TCG_REG_R14, 205 TCG_REG_R15, 206 TCG_REG_R16, 207 TCG_REG_R17, 208 TCG_REG_R18, 209 TCG_REG_R19, 210 TCG_REG_R20, 211 TCG_REG_R21, 212 TCG_REG_R22, 213 TCG_REG_R23, 214 TCG_REG_R24, 215 TCG_REG_R25, 216 TCG_REG_R26, 217 TCG_REG_R27, /* currently used for the global env */ 218 TCG_REG_R28, 219 TCG_REG_R29, 220 TCG_REG_R30, 221 TCG_REG_R31 222}; 223 224static inline bool in_range_b(tcg_target_long target) 225{ 226 return target == sextract64(target, 0, 26); 227} 228 229static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, 230 const tcg_insn_unit *target) 231{ 232 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 233 tcg_debug_assert(in_range_b(disp)); 234 return disp & 0x3fffffc; 235} 236 237static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 238{ 239 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 240 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 241 242 if (in_range_b(disp)) { 243 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc); 244 return true; 245 } 246 return false; 247} 248 249static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, 250 const tcg_insn_unit *target) 251{ 252 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 253 tcg_debug_assert(disp == (int16_t) disp); 254 return disp & 0xfffc; 255} 256 257static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 258{ 259 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 260 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 261 262 if (disp == (int16_t) disp) { 263 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc); 264 return true; 265 } 266 return false; 267} 268 269/* test if a constant matches the constraint */ 270static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 271{ 272 if (ct & TCG_CT_CONST) { 273 return 1; 274 } 275 276 /* The only 32-bit constraint we use aside from 277 TCG_CT_CONST is TCG_CT_CONST_S16. */ 278 if (type == TCG_TYPE_I32) { 279 val = (int32_t)val; 280 } 281 282 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 283 return 1; 284 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 285 return 1; 286 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 287 return 1; 288 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 289 return 1; 290 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 291 return 1; 292 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { 293 return 1; 294 } else if ((ct & TCG_CT_CONST_WSZ) 295 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 296 return 1; 297 } 298 return 0; 299} 300 301#define OPCD(opc) ((opc)<<26) 302#define XO19(opc) (OPCD(19)|((opc)<<1)) 303#define MD30(opc) (OPCD(30)|((opc)<<2)) 304#define MDS30(opc) (OPCD(30)|((opc)<<1)) 305#define XO31(opc) (OPCD(31)|((opc)<<1)) 306#define XO58(opc) (OPCD(58)|(opc)) 307#define XO62(opc) (OPCD(62)|(opc)) 308#define VX4(opc) (OPCD(4)|(opc)) 309 310#define B OPCD( 18) 311#define BC OPCD( 16) 312#define LBZ OPCD( 34) 313#define LHZ OPCD( 40) 314#define LHA OPCD( 42) 315#define LWZ OPCD( 32) 316#define LWZUX XO31( 55) 317#define STB OPCD( 38) 318#define STH OPCD( 44) 319#define STW OPCD( 36) 320 321#define STD XO62( 0) 322#define STDU XO62( 1) 323#define STDX XO31(149) 324 325#define LD XO58( 0) 326#define LDX XO31( 21) 327#define LDU XO58( 1) 328#define LDUX XO31( 53) 329#define LWA XO58( 2) 330#define LWAX XO31(341) 331 332#define ADDIC OPCD( 12) 333#define ADDI OPCD( 14) 334#define ADDIS OPCD( 15) 335#define ORI OPCD( 24) 336#define ORIS OPCD( 25) 337#define XORI OPCD( 26) 338#define XORIS OPCD( 27) 339#define ANDI OPCD( 28) 340#define ANDIS OPCD( 29) 341#define MULLI OPCD( 7) 342#define CMPLI OPCD( 10) 343#define CMPI OPCD( 11) 344#define SUBFIC OPCD( 8) 345 346#define LWZU OPCD( 33) 347#define STWU OPCD( 37) 348 349#define RLWIMI OPCD( 20) 350#define RLWINM OPCD( 21) 351#define RLWNM OPCD( 23) 352 353#define RLDICL MD30( 0) 354#define RLDICR MD30( 1) 355#define RLDIMI MD30( 3) 356#define RLDCL MDS30( 8) 357 358#define BCLR XO19( 16) 359#define BCCTR XO19(528) 360#define CRAND XO19(257) 361#define CRANDC XO19(129) 362#define CRNAND XO19(225) 363#define CROR XO19(449) 364#define CRNOR XO19( 33) 365 366#define EXTSB XO31(954) 367#define EXTSH XO31(922) 368#define EXTSW XO31(986) 369#define ADD XO31(266) 370#define ADDE XO31(138) 371#define ADDME XO31(234) 372#define ADDZE XO31(202) 373#define ADDC XO31( 10) 374#define AND XO31( 28) 375#define SUBF XO31( 40) 376#define SUBFC XO31( 8) 377#define SUBFE XO31(136) 378#define SUBFME XO31(232) 379#define SUBFZE XO31(200) 380#define OR XO31(444) 381#define XOR XO31(316) 382#define MULLW XO31(235) 383#define MULHW XO31( 75) 384#define MULHWU XO31( 11) 385#define DIVW XO31(491) 386#define DIVWU XO31(459) 387#define MODSW XO31(779) 388#define MODUW XO31(267) 389#define CMP XO31( 0) 390#define CMPL XO31( 32) 391#define LHBRX XO31(790) 392#define LWBRX XO31(534) 393#define LDBRX XO31(532) 394#define STHBRX XO31(918) 395#define STWBRX XO31(662) 396#define STDBRX XO31(660) 397#define MFSPR XO31(339) 398#define MTSPR XO31(467) 399#define SRAWI XO31(824) 400#define NEG XO31(104) 401#define MFCR XO31( 19) 402#define MFOCRF (MFCR | (1u << 20)) 403#define NOR XO31(124) 404#define CNTLZW XO31( 26) 405#define CNTLZD XO31( 58) 406#define CNTTZW XO31(538) 407#define CNTTZD XO31(570) 408#define CNTPOPW XO31(378) 409#define CNTPOPD XO31(506) 410#define ANDC XO31( 60) 411#define ORC XO31(412) 412#define EQV XO31(284) 413#define NAND XO31(476) 414#define ISEL XO31( 15) 415 416#define MULLD XO31(233) 417#define MULHD XO31( 73) 418#define MULHDU XO31( 9) 419#define DIVD XO31(489) 420#define DIVDU XO31(457) 421#define MODSD XO31(777) 422#define MODUD XO31(265) 423 424#define LBZX XO31( 87) 425#define LHZX XO31(279) 426#define LHAX XO31(343) 427#define LWZX XO31( 23) 428#define STBX XO31(215) 429#define STHX XO31(407) 430#define STWX XO31(151) 431 432#define EIEIO XO31(854) 433#define HWSYNC XO31(598) 434#define LWSYNC (HWSYNC | (1u << 21)) 435 436#define SPR(a, b) ((((a)<<5)|(b))<<11) 437#define LR SPR(8, 0) 438#define CTR SPR(9, 0) 439 440#define SLW XO31( 24) 441#define SRW XO31(536) 442#define SRAW XO31(792) 443 444#define SLD XO31( 27) 445#define SRD XO31(539) 446#define SRAD XO31(794) 447#define SRADI XO31(413<<1) 448 449#define BRH XO31(219) 450#define BRW XO31(155) 451#define BRD XO31(187) 452 453#define TW XO31( 4) 454#define TRAP (TW | TO(31)) 455 456#define NOP ORI /* ori 0,0,0 */ 457 458#define LVX XO31(103) 459#define LVEBX XO31(7) 460#define LVEHX XO31(39) 461#define LVEWX XO31(71) 462#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */ 463#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */ 464#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */ 465#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */ 466#define LXSD (OPCD(57) | 2) /* v3.00 */ 467#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */ 468 469#define STVX XO31(231) 470#define STVEWX XO31(199) 471#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */ 472#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */ 473#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */ 474#define STXSD (OPCD(61) | 2) /* v3.00 */ 475 476#define VADDSBS VX4(768) 477#define VADDUBS VX4(512) 478#define VADDUBM VX4(0) 479#define VADDSHS VX4(832) 480#define VADDUHS VX4(576) 481#define VADDUHM VX4(64) 482#define VADDSWS VX4(896) 483#define VADDUWS VX4(640) 484#define VADDUWM VX4(128) 485#define VADDUDM VX4(192) /* v2.07 */ 486 487#define VSUBSBS VX4(1792) 488#define VSUBUBS VX4(1536) 489#define VSUBUBM VX4(1024) 490#define VSUBSHS VX4(1856) 491#define VSUBUHS VX4(1600) 492#define VSUBUHM VX4(1088) 493#define VSUBSWS VX4(1920) 494#define VSUBUWS VX4(1664) 495#define VSUBUWM VX4(1152) 496#define VSUBUDM VX4(1216) /* v2.07 */ 497 498#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ 499#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ 500 501#define VMAXSB VX4(258) 502#define VMAXSH VX4(322) 503#define VMAXSW VX4(386) 504#define VMAXSD VX4(450) /* v2.07 */ 505#define VMAXUB VX4(2) 506#define VMAXUH VX4(66) 507#define VMAXUW VX4(130) 508#define VMAXUD VX4(194) /* v2.07 */ 509#define VMINSB VX4(770) 510#define VMINSH VX4(834) 511#define VMINSW VX4(898) 512#define VMINSD VX4(962) /* v2.07 */ 513#define VMINUB VX4(514) 514#define VMINUH VX4(578) 515#define VMINUW VX4(642) 516#define VMINUD VX4(706) /* v2.07 */ 517 518#define VCMPEQUB VX4(6) 519#define VCMPEQUH VX4(70) 520#define VCMPEQUW VX4(134) 521#define VCMPEQUD VX4(199) /* v2.07 */ 522#define VCMPGTSB VX4(774) 523#define VCMPGTSH VX4(838) 524#define VCMPGTSW VX4(902) 525#define VCMPGTSD VX4(967) /* v2.07 */ 526#define VCMPGTUB VX4(518) 527#define VCMPGTUH VX4(582) 528#define VCMPGTUW VX4(646) 529#define VCMPGTUD VX4(711) /* v2.07 */ 530#define VCMPNEB VX4(7) /* v3.00 */ 531#define VCMPNEH VX4(71) /* v3.00 */ 532#define VCMPNEW VX4(135) /* v3.00 */ 533 534#define VSLB VX4(260) 535#define VSLH VX4(324) 536#define VSLW VX4(388) 537#define VSLD VX4(1476) /* v2.07 */ 538#define VSRB VX4(516) 539#define VSRH VX4(580) 540#define VSRW VX4(644) 541#define VSRD VX4(1732) /* v2.07 */ 542#define VSRAB VX4(772) 543#define VSRAH VX4(836) 544#define VSRAW VX4(900) 545#define VSRAD VX4(964) /* v2.07 */ 546#define VRLB VX4(4) 547#define VRLH VX4(68) 548#define VRLW VX4(132) 549#define VRLD VX4(196) /* v2.07 */ 550 551#define VMULEUB VX4(520) 552#define VMULEUH VX4(584) 553#define VMULEUW VX4(648) /* v2.07 */ 554#define VMULOUB VX4(8) 555#define VMULOUH VX4(72) 556#define VMULOUW VX4(136) /* v2.07 */ 557#define VMULUWM VX4(137) /* v2.07 */ 558#define VMULLD VX4(457) /* v3.10 */ 559#define VMSUMUHM VX4(38) 560 561#define VMRGHB VX4(12) 562#define VMRGHH VX4(76) 563#define VMRGHW VX4(140) 564#define VMRGLB VX4(268) 565#define VMRGLH VX4(332) 566#define VMRGLW VX4(396) 567 568#define VPKUHUM VX4(14) 569#define VPKUWUM VX4(78) 570 571#define VAND VX4(1028) 572#define VANDC VX4(1092) 573#define VNOR VX4(1284) 574#define VOR VX4(1156) 575#define VXOR VX4(1220) 576#define VEQV VX4(1668) /* v2.07 */ 577#define VNAND VX4(1412) /* v2.07 */ 578#define VORC VX4(1348) /* v2.07 */ 579 580#define VSPLTB VX4(524) 581#define VSPLTH VX4(588) 582#define VSPLTW VX4(652) 583#define VSPLTISB VX4(780) 584#define VSPLTISH VX4(844) 585#define VSPLTISW VX4(908) 586 587#define VSLDOI VX4(44) 588 589#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */ 590#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */ 591#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */ 592 593#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */ 594#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */ 595#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */ 596#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */ 597#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */ 598#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */ 599 600#define RT(r) ((r)<<21) 601#define RS(r) ((r)<<21) 602#define RA(r) ((r)<<16) 603#define RB(r) ((r)<<11) 604#define TO(t) ((t)<<21) 605#define SH(s) ((s)<<11) 606#define MB(b) ((b)<<6) 607#define ME(e) ((e)<<1) 608#define BO(o) ((o)<<21) 609#define MB64(b) ((b)<<5) 610#define FXM(b) (1 << (19 - (b))) 611 612#define VRT(r) (((r) & 31) << 21) 613#define VRA(r) (((r) & 31) << 16) 614#define VRB(r) (((r) & 31) << 11) 615#define VRC(r) (((r) & 31) << 6) 616 617#define LK 1 618 619#define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) 620#define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) 621#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) 622#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) 623 624#define BF(n) ((n)<<23) 625#define BI(n, c) (((c)+((n)*4))<<16) 626#define BT(n, c) (((c)+((n)*4))<<21) 627#define BA(n, c) (((c)+((n)*4))<<16) 628#define BB(n, c) (((c)+((n)*4))<<11) 629#define BC_(n, c) (((c)+((n)*4))<<6) 630 631#define BO_COND_TRUE BO(12) 632#define BO_COND_FALSE BO( 4) 633#define BO_ALWAYS BO(20) 634 635enum { 636 CR_LT, 637 CR_GT, 638 CR_EQ, 639 CR_SO 640}; 641 642static const uint32_t tcg_to_bc[] = { 643 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE, 644 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE, 645 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE, 646 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE, 647 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE, 648 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE, 649 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE, 650 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE, 651 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE, 652 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE, 653}; 654 655/* The low bit here is set if the RA and RB fields must be inverted. */ 656static const uint32_t tcg_to_isel[] = { 657 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ), 658 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1, 659 [TCG_COND_LT] = ISEL | BC_(7, CR_LT), 660 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1, 661 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1, 662 [TCG_COND_GT] = ISEL | BC_(7, CR_GT), 663 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT), 664 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1, 665 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1, 666 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), 667}; 668 669static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 670 intptr_t value, intptr_t addend) 671{ 672 const tcg_insn_unit *target; 673 int16_t lo; 674 int32_t hi; 675 676 value += addend; 677 target = (const tcg_insn_unit *)value; 678 679 switch (type) { 680 case R_PPC_REL14: 681 return reloc_pc14(code_ptr, target); 682 case R_PPC_REL24: 683 return reloc_pc24(code_ptr, target); 684 case R_PPC_ADDR16: 685 /* 686 * We are (slightly) abusing this relocation type. In particular, 687 * assert that the low 2 bits are zero, and do not modify them. 688 * That way we can use this with LD et al that have opcode bits 689 * in the low 2 bits of the insn. 690 */ 691 if ((value & 3) || value != (int16_t)value) { 692 return false; 693 } 694 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc); 695 break; 696 case R_PPC_ADDR32: 697 /* 698 * We are abusing this relocation type. Again, this points to 699 * a pair of insns, lis + load. This is an absolute address 700 * relocation for PPC32 so the lis cannot be removed. 701 */ 702 lo = value; 703 hi = value - lo; 704 if (hi + lo != value) { 705 return false; 706 } 707 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); 708 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); 709 break; 710 default: 711 g_assert_not_reached(); 712 } 713 return true; 714} 715 716static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 717 TCGReg base, tcg_target_long offset); 718 719static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 720{ 721 if (ret == arg) { 722 return true; 723 } 724 switch (type) { 725 case TCG_TYPE_I64: 726 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 727 /* fallthru */ 728 case TCG_TYPE_I32: 729 if (ret < TCG_REG_V0) { 730 if (arg < TCG_REG_V0) { 731 tcg_out32(s, OR | SAB(arg, ret, arg)); 732 break; 733 } else if (have_isa_2_07) { 734 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) 735 | VRT(arg) | RA(ret)); 736 break; 737 } else { 738 /* Altivec does not support vector->integer moves. */ 739 return false; 740 } 741 } else if (arg < TCG_REG_V0) { 742 if (have_isa_2_07) { 743 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) 744 | VRT(ret) | RA(arg)); 745 break; 746 } else { 747 /* Altivec does not support integer->vector moves. */ 748 return false; 749 } 750 } 751 /* fallthru */ 752 case TCG_TYPE_V64: 753 case TCG_TYPE_V128: 754 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0); 755 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); 756 break; 757 default: 758 g_assert_not_reached(); 759 } 760 return true; 761} 762 763static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, 764 int sh, int mb) 765{ 766 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 767 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); 768 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); 769 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); 770} 771 772static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, 773 int sh, int mb, int me) 774{ 775 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); 776} 777 778static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 779{ 780 tcg_out32(s, EXTSB | RA(dst) | RS(src)); 781} 782 783static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src) 784{ 785 tcg_out32(s, ANDI | SAI(src, dst, 0xff)); 786} 787 788static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 789{ 790 tcg_out32(s, EXTSH | RA(dst) | RS(src)); 791} 792 793static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src) 794{ 795 tcg_out32(s, ANDI | SAI(src, dst, 0xffff)); 796} 797 798static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) 799{ 800 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 801 tcg_out32(s, EXTSW | RA(dst) | RS(src)); 802} 803 804static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) 805{ 806 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 807 tcg_out_rld(s, RLDICL, dst, src, 0, 32); 808} 809 810static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 811{ 812 tcg_out_ext32s(s, dst, src); 813} 814 815static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 816{ 817 tcg_out_ext32u(s, dst, src); 818} 819 820static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 821{ 822 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 823 tcg_out_mov(s, TCG_TYPE_I32, rd, rn); 824} 825 826static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) 827{ 828 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); 829} 830 831static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) 832{ 833 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); 834} 835 836static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c) 837{ 838 /* Limit immediate shift count lest we create an illegal insn. */ 839 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31)); 840} 841 842static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) 843{ 844 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); 845} 846 847static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) 848{ 849 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); 850} 851 852static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c) 853{ 854 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2)); 855} 856 857static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags) 858{ 859 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 860 861 if (have_isa_3_10) { 862 tcg_out32(s, BRH | RA(dst) | RS(src)); 863 if (flags & TCG_BSWAP_OS) { 864 tcg_out_ext16s(s, TCG_TYPE_REG, dst, dst); 865 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 866 tcg_out_ext16u(s, dst, dst); 867 } 868 return; 869 } 870 871 /* 872 * In the following, 873 * dep(a, b, m) -> (a & ~m) | (b & m) 874 * 875 * Begin with: src = xxxxabcd 876 */ 877 /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */ 878 tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31); 879 /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */ 880 tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23); 881 882 if (flags & TCG_BSWAP_OS) { 883 tcg_out_ext16s(s, TCG_TYPE_REG, dst, tmp); 884 } else { 885 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 886 } 887} 888 889static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags) 890{ 891 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 892 893 if (have_isa_3_10) { 894 tcg_out32(s, BRW | RA(dst) | RS(src)); 895 if (flags & TCG_BSWAP_OS) { 896 tcg_out_ext32s(s, dst, dst); 897 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 898 tcg_out_ext32u(s, dst, dst); 899 } 900 return; 901 } 902 903 /* 904 * Stolen from gcc's builtin_bswap32. 905 * In the following, 906 * dep(a, b, m) -> (a & ~m) | (b & m) 907 * 908 * Begin with: src = xxxxabcd 909 */ 910 /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */ 911 tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31); 912 /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */ 913 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7); 914 /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */ 915 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23); 916 917 if (flags & TCG_BSWAP_OS) { 918 tcg_out_ext32s(s, dst, tmp); 919 } else { 920 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 921 } 922} 923 924static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src) 925{ 926 TCGReg t0 = dst == src ? TCG_REG_R0 : dst; 927 TCGReg t1 = dst == src ? dst : TCG_REG_R0; 928 929 if (have_isa_3_10) { 930 tcg_out32(s, BRD | RA(dst) | RS(src)); 931 return; 932 } 933 934 /* 935 * In the following, 936 * dep(a, b, m) -> (a & ~m) | (b & m) 937 * 938 * Begin with: src = abcdefgh 939 */ 940 /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */ 941 tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31); 942 /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */ 943 tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7); 944 /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */ 945 tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23); 946 947 /* t0 = rol64(t0, 32) = hgfe0000 */ 948 tcg_out_rld(s, RLDICL, t0, t0, 32, 0); 949 /* t1 = rol64(src, 32) = efghabcd */ 950 tcg_out_rld(s, RLDICL, t1, src, 32, 0); 951 952 /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */ 953 tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31); 954 /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */ 955 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7); 956 /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */ 957 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23); 958 959 tcg_out_mov(s, TCG_TYPE_REG, dst, t0); 960} 961 962/* Emit a move into ret of arg, if it can be done in one insn. */ 963static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 964{ 965 if (arg == (int16_t)arg) { 966 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 967 return true; 968 } 969 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 970 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 971 return true; 972 } 973 return false; 974} 975 976static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 977 tcg_target_long arg, bool in_prologue) 978{ 979 intptr_t tb_diff; 980 tcg_target_long tmp; 981 int shift; 982 983 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 984 985 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 986 arg = (int32_t)arg; 987 } 988 989 /* Load 16-bit immediates with one insn. */ 990 if (tcg_out_movi_one(s, ret, arg)) { 991 return; 992 } 993 994 /* Load addresses within the TB with one insn. */ 995 tb_diff = tcg_tbrel_diff(s, (void *)arg); 996 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { 997 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); 998 return; 999 } 1000 1001 /* Load 32-bit immediates with two insns. Note that we've already 1002 eliminated bare ADDIS, so we know both insns are required. */ 1003 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 1004 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 1005 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1006 return; 1007 } 1008 if (arg == (uint32_t)arg && !(arg & 0x8000)) { 1009 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1010 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1011 return; 1012 } 1013 1014 /* Load masked 16-bit value. */ 1015 if (arg > 0 && (arg & 0x8000)) { 1016 tmp = arg | 0x7fff; 1017 if ((tmp & (tmp + 1)) == 0) { 1018 int mb = clz64(tmp + 1) + 1; 1019 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1020 tcg_out_rld(s, RLDICL, ret, ret, 0, mb); 1021 return; 1022 } 1023 } 1024 1025 /* Load common masks with 2 insns. */ 1026 shift = ctz64(arg); 1027 tmp = arg >> shift; 1028 if (tmp == (int16_t)tmp) { 1029 tcg_out32(s, ADDI | TAI(ret, 0, tmp)); 1030 tcg_out_shli64(s, ret, ret, shift); 1031 return; 1032 } 1033 shift = clz64(arg); 1034 if (tcg_out_movi_one(s, ret, arg << shift)) { 1035 tcg_out_shri64(s, ret, ret, shift); 1036 return; 1037 } 1038 1039 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ 1040 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { 1041 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); 1042 return; 1043 } 1044 1045 /* Use the constant pool, if possible. */ 1046 if (!in_prologue && USE_REG_TB) { 1047 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, 1048 tcg_tbrel_diff(s, NULL)); 1049 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); 1050 return; 1051 } 1052 1053 tmp = arg >> 31 >> 1; 1054 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); 1055 if (tmp) { 1056 tcg_out_shli64(s, ret, ret, 32); 1057 } 1058 if (arg & 0xffff0000) { 1059 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1060 } 1061 if (arg & 0xffff) { 1062 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1063 } 1064} 1065 1066static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1067 TCGReg ret, int64_t val) 1068{ 1069 uint32_t load_insn; 1070 int rel, low; 1071 intptr_t add; 1072 1073 switch (vece) { 1074 case MO_8: 1075 low = (int8_t)val; 1076 if (low >= -16 && low < 16) { 1077 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); 1078 return; 1079 } 1080 if (have_isa_3_00) { 1081 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); 1082 return; 1083 } 1084 break; 1085 1086 case MO_16: 1087 low = (int16_t)val; 1088 if (low >= -16 && low < 16) { 1089 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); 1090 return; 1091 } 1092 break; 1093 1094 case MO_32: 1095 low = (int32_t)val; 1096 if (low >= -16 && low < 16) { 1097 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); 1098 return; 1099 } 1100 break; 1101 } 1102 1103 /* 1104 * Otherwise we must load the value from the constant pool. 1105 */ 1106 if (USE_REG_TB) { 1107 rel = R_PPC_ADDR16; 1108 add = tcg_tbrel_diff(s, NULL); 1109 } else { 1110 rel = R_PPC_ADDR32; 1111 add = 0; 1112 } 1113 1114 if (have_vsx) { 1115 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX; 1116 load_insn |= VRT(ret) | RB(TCG_REG_TMP1); 1117 if (TCG_TARGET_REG_BITS == 64) { 1118 new_pool_label(s, val, rel, s->code_ptr, add); 1119 } else { 1120 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); 1121 } 1122 } else { 1123 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); 1124 if (TCG_TARGET_REG_BITS == 64) { 1125 new_pool_l2(s, rel, s->code_ptr, add, val, val); 1126 } else { 1127 new_pool_l4(s, rel, s->code_ptr, add, 1128 val >> 32, val, val >> 32, val); 1129 } 1130 } 1131 1132 if (USE_REG_TB) { 1133 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); 1134 load_insn |= RA(TCG_REG_TB); 1135 } else { 1136 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); 1137 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); 1138 } 1139 tcg_out32(s, load_insn); 1140} 1141 1142static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, 1143 tcg_target_long arg) 1144{ 1145 switch (type) { 1146 case TCG_TYPE_I32: 1147 case TCG_TYPE_I64: 1148 tcg_debug_assert(ret < TCG_REG_V0); 1149 tcg_out_movi_int(s, type, ret, arg, false); 1150 break; 1151 1152 default: 1153 g_assert_not_reached(); 1154 } 1155} 1156 1157static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1158{ 1159 return false; 1160} 1161 1162static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1163 tcg_target_long imm) 1164{ 1165 /* This function is only used for passing structs by reference. */ 1166 g_assert_not_reached(); 1167} 1168 1169static bool mask_operand(uint32_t c, int *mb, int *me) 1170{ 1171 uint32_t lsb, test; 1172 1173 /* Accept a bit pattern like: 1174 0....01....1 1175 1....10....0 1176 0..01..10..0 1177 Keep track of the transitions. */ 1178 if (c == 0 || c == -1) { 1179 return false; 1180 } 1181 test = c; 1182 lsb = test & -test; 1183 test += lsb; 1184 if (test & (test - 1)) { 1185 return false; 1186 } 1187 1188 *me = clz32(lsb); 1189 *mb = test ? clz32(test & -test) + 1 : 0; 1190 return true; 1191} 1192 1193static bool mask64_operand(uint64_t c, int *mb, int *me) 1194{ 1195 uint64_t lsb; 1196 1197 if (c == 0) { 1198 return false; 1199 } 1200 1201 lsb = c & -c; 1202 /* Accept 1..10..0. */ 1203 if (c == -lsb) { 1204 *mb = 0; 1205 *me = clz64(lsb); 1206 return true; 1207 } 1208 /* Accept 0..01..1. */ 1209 if (lsb == 1 && (c & (c + 1)) == 0) { 1210 *mb = clz64(c + 1) + 1; 1211 *me = 63; 1212 return true; 1213 } 1214 return false; 1215} 1216 1217static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1218{ 1219 int mb, me; 1220 1221 if (mask_operand(c, &mb, &me)) { 1222 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); 1223 } else if ((c & 0xffff) == c) { 1224 tcg_out32(s, ANDI | SAI(src, dst, c)); 1225 return; 1226 } else if ((c & 0xffff0000) == c) { 1227 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1228 return; 1229 } else { 1230 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); 1231 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1232 } 1233} 1234 1235static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) 1236{ 1237 int mb, me; 1238 1239 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1240 if (mask64_operand(c, &mb, &me)) { 1241 if (mb == 0) { 1242 tcg_out_rld(s, RLDICR, dst, src, 0, me); 1243 } else { 1244 tcg_out_rld(s, RLDICL, dst, src, 0, mb); 1245 } 1246 } else if ((c & 0xffff) == c) { 1247 tcg_out32(s, ANDI | SAI(src, dst, c)); 1248 return; 1249 } else if ((c & 0xffff0000) == c) { 1250 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1251 return; 1252 } else { 1253 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); 1254 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1255 } 1256} 1257 1258static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, 1259 int op_lo, int op_hi) 1260{ 1261 if (c >> 16) { 1262 tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); 1263 src = dst; 1264 } 1265 if (c & 0xffff) { 1266 tcg_out32(s, op_lo | SAI(src, dst, c)); 1267 src = dst; 1268 } 1269} 1270 1271static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1272{ 1273 tcg_out_zori32(s, dst, src, c, ORI, ORIS); 1274} 1275 1276static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1277{ 1278 tcg_out_zori32(s, dst, src, c, XORI, XORIS); 1279} 1280 1281static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) 1282{ 1283 ptrdiff_t disp = tcg_pcrel_diff(s, target); 1284 if (in_range_b(disp)) { 1285 tcg_out32(s, B | (disp & 0x3fffffc) | mask); 1286 } else { 1287 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); 1288 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); 1289 tcg_out32(s, BCCTR | BO_ALWAYS | mask); 1290 } 1291} 1292 1293static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 1294 TCGReg base, tcg_target_long offset) 1295{ 1296 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; 1297 bool is_int_store = false; 1298 TCGReg rs = TCG_REG_TMP1; 1299 1300 switch (opi) { 1301 case LD: case LWA: 1302 align = 3; 1303 /* FALLTHRU */ 1304 default: 1305 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { 1306 rs = rt; 1307 break; 1308 } 1309 break; 1310 case LXSD: 1311 case STXSD: 1312 align = 3; 1313 break; 1314 case LXV: 1315 case STXV: 1316 align = 15; 1317 break; 1318 case STD: 1319 align = 3; 1320 /* FALLTHRU */ 1321 case STB: case STH: case STW: 1322 is_int_store = true; 1323 break; 1324 } 1325 1326 /* For unaligned, or very large offsets, use the indexed form. */ 1327 if (offset & align || offset != (int32_t)offset || opi == 0) { 1328 if (rs == base) { 1329 rs = TCG_REG_R0; 1330 } 1331 tcg_debug_assert(!is_int_store || rs != rt); 1332 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); 1333 tcg_out32(s, opx | TAB(rt & 31, base, rs)); 1334 return; 1335 } 1336 1337 l0 = (int16_t)offset; 1338 offset = (offset - l0) >> 16; 1339 l1 = (int16_t)offset; 1340 1341 if (l1 < 0 && orig >= 0) { 1342 extra = 0x4000; 1343 l1 = (int16_t)(offset - 0x4000); 1344 } 1345 if (l1) { 1346 tcg_out32(s, ADDIS | TAI(rs, base, l1)); 1347 base = rs; 1348 } 1349 if (extra) { 1350 tcg_out32(s, ADDIS | TAI(rs, base, extra)); 1351 base = rs; 1352 } 1353 if (opi != ADDI || base != rt || l0 != 0) { 1354 tcg_out32(s, opi | TAI(rt & 31, base, l0)); 1355 } 1356} 1357 1358static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, 1359 TCGReg va, TCGReg vb, int shb) 1360{ 1361 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); 1362} 1363 1364static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1365 TCGReg base, intptr_t offset) 1366{ 1367 int shift; 1368 1369 switch (type) { 1370 case TCG_TYPE_I32: 1371 if (ret < TCG_REG_V0) { 1372 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); 1373 break; 1374 } 1375 if (have_isa_2_07 && have_vsx) { 1376 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); 1377 break; 1378 } 1379 tcg_debug_assert((offset & 3) == 0); 1380 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); 1381 shift = (offset - 4) & 0xc; 1382 if (shift) { 1383 tcg_out_vsldoi(s, ret, ret, ret, shift); 1384 } 1385 break; 1386 case TCG_TYPE_I64: 1387 if (ret < TCG_REG_V0) { 1388 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1389 tcg_out_mem_long(s, LD, LDX, ret, base, offset); 1390 break; 1391 } 1392 /* fallthru */ 1393 case TCG_TYPE_V64: 1394 tcg_debug_assert(ret >= TCG_REG_V0); 1395 if (have_vsx) { 1396 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, 1397 ret, base, offset); 1398 break; 1399 } 1400 tcg_debug_assert((offset & 7) == 0); 1401 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); 1402 if (offset & 8) { 1403 tcg_out_vsldoi(s, ret, ret, ret, 8); 1404 } 1405 break; 1406 case TCG_TYPE_V128: 1407 tcg_debug_assert(ret >= TCG_REG_V0); 1408 tcg_debug_assert((offset & 15) == 0); 1409 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, 1410 LVX, ret, base, offset); 1411 break; 1412 default: 1413 g_assert_not_reached(); 1414 } 1415} 1416 1417static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1418 TCGReg base, intptr_t offset) 1419{ 1420 int shift; 1421 1422 switch (type) { 1423 case TCG_TYPE_I32: 1424 if (arg < TCG_REG_V0) { 1425 tcg_out_mem_long(s, STW, STWX, arg, base, offset); 1426 break; 1427 } 1428 if (have_isa_2_07 && have_vsx) { 1429 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); 1430 break; 1431 } 1432 assert((offset & 3) == 0); 1433 tcg_debug_assert((offset & 3) == 0); 1434 shift = (offset - 4) & 0xc; 1435 if (shift) { 1436 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); 1437 arg = TCG_VEC_TMP1; 1438 } 1439 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1440 break; 1441 case TCG_TYPE_I64: 1442 if (arg < TCG_REG_V0) { 1443 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1444 tcg_out_mem_long(s, STD, STDX, arg, base, offset); 1445 break; 1446 } 1447 /* fallthru */ 1448 case TCG_TYPE_V64: 1449 tcg_debug_assert(arg >= TCG_REG_V0); 1450 if (have_vsx) { 1451 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, 1452 STXSDX, arg, base, offset); 1453 break; 1454 } 1455 tcg_debug_assert((offset & 7) == 0); 1456 if (offset & 8) { 1457 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); 1458 arg = TCG_VEC_TMP1; 1459 } 1460 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1461 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); 1462 break; 1463 case TCG_TYPE_V128: 1464 tcg_debug_assert(arg >= TCG_REG_V0); 1465 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, 1466 STVX, arg, base, offset); 1467 break; 1468 default: 1469 g_assert_not_reached(); 1470 } 1471} 1472 1473static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1474 TCGReg base, intptr_t ofs) 1475{ 1476 return false; 1477} 1478 1479static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, 1480 int const_arg2, int cr, TCGType type) 1481{ 1482 int imm; 1483 uint32_t op; 1484 1485 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1486 1487 /* Simplify the comparisons below wrt CMPI. */ 1488 if (type == TCG_TYPE_I32) { 1489 arg2 = (int32_t)arg2; 1490 } 1491 1492 switch (cond) { 1493 case TCG_COND_EQ: 1494 case TCG_COND_NE: 1495 if (const_arg2) { 1496 if ((int16_t) arg2 == arg2) { 1497 op = CMPI; 1498 imm = 1; 1499 break; 1500 } else if ((uint16_t) arg2 == arg2) { 1501 op = CMPLI; 1502 imm = 1; 1503 break; 1504 } 1505 } 1506 op = CMPL; 1507 imm = 0; 1508 break; 1509 1510 case TCG_COND_LT: 1511 case TCG_COND_GE: 1512 case TCG_COND_LE: 1513 case TCG_COND_GT: 1514 if (const_arg2) { 1515 if ((int16_t) arg2 == arg2) { 1516 op = CMPI; 1517 imm = 1; 1518 break; 1519 } 1520 } 1521 op = CMP; 1522 imm = 0; 1523 break; 1524 1525 case TCG_COND_LTU: 1526 case TCG_COND_GEU: 1527 case TCG_COND_LEU: 1528 case TCG_COND_GTU: 1529 if (const_arg2) { 1530 if ((uint16_t) arg2 == arg2) { 1531 op = CMPLI; 1532 imm = 1; 1533 break; 1534 } 1535 } 1536 op = CMPL; 1537 imm = 0; 1538 break; 1539 1540 default: 1541 g_assert_not_reached(); 1542 } 1543 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); 1544 1545 if (imm) { 1546 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); 1547 } else { 1548 if (const_arg2) { 1549 tcg_out_movi(s, type, TCG_REG_R0, arg2); 1550 arg2 = TCG_REG_R0; 1551 } 1552 tcg_out32(s, op | RA(arg1) | RB(arg2)); 1553 } 1554} 1555 1556static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, 1557 TCGReg dst, TCGReg src) 1558{ 1559 if (type == TCG_TYPE_I32) { 1560 tcg_out32(s, CNTLZW | RS(src) | RA(dst)); 1561 tcg_out_shri32(s, dst, dst, 5); 1562 } else { 1563 tcg_out32(s, CNTLZD | RS(src) | RA(dst)); 1564 tcg_out_shri64(s, dst, dst, 6); 1565 } 1566} 1567 1568static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src) 1569{ 1570 /* X != 0 implies X + -1 generates a carry. Extra addition 1571 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */ 1572 if (dst != src) { 1573 tcg_out32(s, ADDIC | TAI(dst, src, -1)); 1574 tcg_out32(s, SUBFE | TAB(dst, dst, src)); 1575 } else { 1576 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); 1577 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); 1578 } 1579} 1580 1581static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, 1582 bool const_arg2) 1583{ 1584 if (const_arg2) { 1585 if ((uint32_t)arg2 == arg2) { 1586 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); 1587 } else { 1588 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); 1589 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); 1590 } 1591 } else { 1592 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); 1593 } 1594 return TCG_REG_R0; 1595} 1596 1597static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, 1598 TCGArg arg0, TCGArg arg1, TCGArg arg2, 1599 int const_arg2) 1600{ 1601 int crop, sh; 1602 1603 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1604 1605 /* Ignore high bits of a potential constant arg2. */ 1606 if (type == TCG_TYPE_I32) { 1607 arg2 = (uint32_t)arg2; 1608 } 1609 1610 /* Handle common and trivial cases before handling anything else. */ 1611 if (arg2 == 0) { 1612 switch (cond) { 1613 case TCG_COND_EQ: 1614 tcg_out_setcond_eq0(s, type, arg0, arg1); 1615 return; 1616 case TCG_COND_NE: 1617 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1618 tcg_out_ext32u(s, TCG_REG_R0, arg1); 1619 arg1 = TCG_REG_R0; 1620 } 1621 tcg_out_setcond_ne0(s, arg0, arg1); 1622 return; 1623 case TCG_COND_GE: 1624 tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); 1625 arg1 = arg0; 1626 /* FALLTHRU */ 1627 case TCG_COND_LT: 1628 /* Extract the sign bit. */ 1629 if (type == TCG_TYPE_I32) { 1630 tcg_out_shri32(s, arg0, arg1, 31); 1631 } else { 1632 tcg_out_shri64(s, arg0, arg1, 63); 1633 } 1634 return; 1635 default: 1636 break; 1637 } 1638 } 1639 1640 /* If we have ISEL, we can implement everything with 3 or 4 insns. 1641 All other cases below are also at least 3 insns, so speed up the 1642 code generator by not considering them and always using ISEL. */ 1643 if (have_isel) { 1644 int isel, tab; 1645 1646 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1647 1648 isel = tcg_to_isel[cond]; 1649 1650 tcg_out_movi(s, type, arg0, 1); 1651 if (isel & 1) { 1652 /* arg0 = (bc ? 0 : 1) */ 1653 tab = TAB(arg0, 0, arg0); 1654 isel &= ~1; 1655 } else { 1656 /* arg0 = (bc ? 1 : 0) */ 1657 tcg_out_movi(s, type, TCG_REG_R0, 0); 1658 tab = TAB(arg0, arg0, TCG_REG_R0); 1659 } 1660 tcg_out32(s, isel | tab); 1661 return; 1662 } 1663 1664 switch (cond) { 1665 case TCG_COND_EQ: 1666 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1667 tcg_out_setcond_eq0(s, type, arg0, arg1); 1668 return; 1669 1670 case TCG_COND_NE: 1671 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1672 /* Discard the high bits only once, rather than both inputs. */ 1673 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 1674 tcg_out_ext32u(s, TCG_REG_R0, arg1); 1675 arg1 = TCG_REG_R0; 1676 } 1677 tcg_out_setcond_ne0(s, arg0, arg1); 1678 return; 1679 1680 case TCG_COND_GT: 1681 case TCG_COND_GTU: 1682 sh = 30; 1683 crop = 0; 1684 goto crtest; 1685 1686 case TCG_COND_LT: 1687 case TCG_COND_LTU: 1688 sh = 29; 1689 crop = 0; 1690 goto crtest; 1691 1692 case TCG_COND_GE: 1693 case TCG_COND_GEU: 1694 sh = 31; 1695 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT); 1696 goto crtest; 1697 1698 case TCG_COND_LE: 1699 case TCG_COND_LEU: 1700 sh = 31; 1701 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT); 1702 crtest: 1703 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1704 if (crop) { 1705 tcg_out32(s, crop); 1706 } 1707 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1708 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); 1709 break; 1710 1711 default: 1712 g_assert_not_reached(); 1713 } 1714} 1715 1716static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) 1717{ 1718 if (l->has_value) { 1719 bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr); 1720 } else { 1721 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); 1722 } 1723 tcg_out32(s, bc); 1724} 1725 1726static void tcg_out_brcond(TCGContext *s, TCGCond cond, 1727 TCGArg arg1, TCGArg arg2, int const_arg2, 1728 TCGLabel *l, TCGType type) 1729{ 1730 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1731 tcg_out_bc(s, tcg_to_bc[cond], l); 1732} 1733 1734static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, 1735 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, 1736 TCGArg v2, bool const_c2) 1737{ 1738 /* If for some reason both inputs are zero, don't produce bad code. */ 1739 if (v1 == 0 && v2 == 0) { 1740 tcg_out_movi(s, type, dest, 0); 1741 return; 1742 } 1743 1744 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); 1745 1746 if (have_isel) { 1747 int isel = tcg_to_isel[cond]; 1748 1749 /* Swap the V operands if the operation indicates inversion. */ 1750 if (isel & 1) { 1751 int t = v1; 1752 v1 = v2; 1753 v2 = t; 1754 isel &= ~1; 1755 } 1756 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ 1757 if (v2 == 0) { 1758 tcg_out_movi(s, type, TCG_REG_R0, 0); 1759 } 1760 tcg_out32(s, isel | TAB(dest, v1, v2)); 1761 } else { 1762 if (dest == v2) { 1763 cond = tcg_invert_cond(cond); 1764 v2 = v1; 1765 } else if (dest != v1) { 1766 if (v1 == 0) { 1767 tcg_out_movi(s, type, dest, 0); 1768 } else { 1769 tcg_out_mov(s, type, dest, v1); 1770 } 1771 } 1772 /* Branch forward over one insn */ 1773 tcg_out32(s, tcg_to_bc[cond] | 8); 1774 if (v2 == 0) { 1775 tcg_out_movi(s, type, dest, 0); 1776 } else { 1777 tcg_out_mov(s, type, dest, v2); 1778 } 1779 } 1780} 1781 1782static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc, 1783 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2) 1784{ 1785 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { 1786 tcg_out32(s, opc | RA(a0) | RS(a1)); 1787 } else { 1788 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); 1789 /* Note that the only other valid constant for a2 is 0. */ 1790 if (have_isel) { 1791 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); 1792 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0)); 1793 } else if (!const_a2 && a0 == a2) { 1794 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8); 1795 tcg_out32(s, opc | RA(a0) | RS(a1)); 1796 } else { 1797 tcg_out32(s, opc | RA(a0) | RS(a1)); 1798 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8); 1799 if (const_a2) { 1800 tcg_out_movi(s, type, a0, 0); 1801 } else { 1802 tcg_out_mov(s, type, a0, a2); 1803 } 1804 } 1805 } 1806} 1807 1808static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1809 const int *const_args) 1810{ 1811 static const struct { uint8_t bit1, bit2; } bits[] = { 1812 [TCG_COND_LT ] = { CR_LT, CR_LT }, 1813 [TCG_COND_LE ] = { CR_LT, CR_GT }, 1814 [TCG_COND_GT ] = { CR_GT, CR_GT }, 1815 [TCG_COND_GE ] = { CR_GT, CR_LT }, 1816 [TCG_COND_LTU] = { CR_LT, CR_LT }, 1817 [TCG_COND_LEU] = { CR_LT, CR_GT }, 1818 [TCG_COND_GTU] = { CR_GT, CR_GT }, 1819 [TCG_COND_GEU] = { CR_GT, CR_LT }, 1820 }; 1821 1822 TCGCond cond = args[4], cond2; 1823 TCGArg al, ah, bl, bh; 1824 int blconst, bhconst; 1825 int op, bit1, bit2; 1826 1827 al = args[0]; 1828 ah = args[1]; 1829 bl = args[2]; 1830 bh = args[3]; 1831 blconst = const_args[2]; 1832 bhconst = const_args[3]; 1833 1834 switch (cond) { 1835 case TCG_COND_EQ: 1836 op = CRAND; 1837 goto do_equality; 1838 case TCG_COND_NE: 1839 op = CRNAND; 1840 do_equality: 1841 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); 1842 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); 1843 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 1844 break; 1845 1846 case TCG_COND_LT: 1847 case TCG_COND_LE: 1848 case TCG_COND_GT: 1849 case TCG_COND_GE: 1850 case TCG_COND_LTU: 1851 case TCG_COND_LEU: 1852 case TCG_COND_GTU: 1853 case TCG_COND_GEU: 1854 bit1 = bits[cond].bit1; 1855 bit2 = bits[cond].bit2; 1856 op = (bit1 != bit2 ? CRANDC : CRAND); 1857 cond2 = tcg_unsigned_cond(cond); 1858 1859 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); 1860 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); 1861 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); 1862 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); 1863 break; 1864 1865 default: 1866 g_assert_not_reached(); 1867 } 1868} 1869 1870static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 1871 const int *const_args) 1872{ 1873 tcg_out_cmp2(s, args + 1, const_args + 1); 1874 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1875 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); 1876} 1877 1878static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, 1879 const int *const_args) 1880{ 1881 tcg_out_cmp2(s, args, const_args); 1882 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5])); 1883} 1884 1885static void tcg_out_mb(TCGContext *s, TCGArg a0) 1886{ 1887 uint32_t insn; 1888 1889 if (a0 & TCG_MO_ST_LD) { 1890 insn = HWSYNC; 1891 } else { 1892 insn = LWSYNC; 1893 } 1894 1895 tcg_out32(s, insn); 1896} 1897 1898static void tcg_out_call_int(TCGContext *s, int lk, 1899 const tcg_insn_unit *target) 1900{ 1901#ifdef _CALL_AIX 1902 /* Look through the descriptor. If the branch is in range, and we 1903 don't have to spend too much effort on building the toc. */ 1904 const void *tgt = ((const void * const *)target)[0]; 1905 uintptr_t toc = ((const uintptr_t *)target)[1]; 1906 intptr_t diff = tcg_pcrel_diff(s, tgt); 1907 1908 if (in_range_b(diff) && toc == (uint32_t)toc) { 1909 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); 1910 tcg_out_b(s, lk, tgt); 1911 } else { 1912 /* Fold the low bits of the constant into the addresses below. */ 1913 intptr_t arg = (intptr_t)target; 1914 int ofs = (int16_t)arg; 1915 1916 if (ofs + 8 < 0x8000) { 1917 arg -= ofs; 1918 } else { 1919 ofs = 0; 1920 } 1921 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); 1922 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); 1923 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); 1924 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); 1925 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1926 } 1927#elif defined(_CALL_ELF) && _CALL_ELF == 2 1928 intptr_t diff; 1929 1930 /* In the ELFv2 ABI, we have to set up r12 to contain the destination 1931 address, which the callee uses to compute its TOC address. */ 1932 /* FIXME: when the branch is in range, we could avoid r12 load if we 1933 knew that the destination uses the same TOC, and what its local 1934 entry point offset is. */ 1935 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); 1936 1937 diff = tcg_pcrel_diff(s, target); 1938 if (in_range_b(diff)) { 1939 tcg_out_b(s, lk, target); 1940 } else { 1941 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); 1942 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1943 } 1944#else 1945 tcg_out_b(s, lk, target); 1946#endif 1947} 1948 1949static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 1950 const TCGHelperInfo *info) 1951{ 1952 tcg_out_call_int(s, LK, target); 1953} 1954 1955static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = { 1956 [MO_UB] = LBZX, 1957 [MO_UW] = LHZX, 1958 [MO_UL] = LWZX, 1959 [MO_UQ] = LDX, 1960 [MO_SW] = LHAX, 1961 [MO_SL] = LWAX, 1962 [MO_BSWAP | MO_UB] = LBZX, 1963 [MO_BSWAP | MO_UW] = LHBRX, 1964 [MO_BSWAP | MO_UL] = LWBRX, 1965 [MO_BSWAP | MO_UQ] = LDBRX, 1966}; 1967 1968static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = { 1969 [MO_UB] = STBX, 1970 [MO_UW] = STHX, 1971 [MO_UL] = STWX, 1972 [MO_UQ] = STDX, 1973 [MO_BSWAP | MO_UB] = STBX, 1974 [MO_BSWAP | MO_UW] = STHBRX, 1975 [MO_BSWAP | MO_UL] = STWBRX, 1976 [MO_BSWAP | MO_UQ] = STDBRX, 1977}; 1978 1979#if defined (CONFIG_SOFTMMU) 1980/* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, 1981 * int mmu_idx, uintptr_t ra) 1982 */ 1983static void * const qemu_ld_helpers[(MO_SIZE | MO_BSWAP) + 1] = { 1984 [MO_UB] = helper_ret_ldub_mmu, 1985 [MO_LEUW] = helper_le_lduw_mmu, 1986 [MO_LEUL] = helper_le_ldul_mmu, 1987 [MO_LEUQ] = helper_le_ldq_mmu, 1988 [MO_BEUW] = helper_be_lduw_mmu, 1989 [MO_BEUL] = helper_be_ldul_mmu, 1990 [MO_BEUQ] = helper_be_ldq_mmu, 1991}; 1992 1993/* helper signature: helper_st_mmu(CPUState *env, target_ulong addr, 1994 * uintxx_t val, int mmu_idx, uintptr_t ra) 1995 */ 1996static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = { 1997 [MO_UB] = helper_ret_stb_mmu, 1998 [MO_LEUW] = helper_le_stw_mmu, 1999 [MO_LEUL] = helper_le_stl_mmu, 2000 [MO_LEUQ] = helper_le_stq_mmu, 2001 [MO_BEUW] = helper_be_stw_mmu, 2002 [MO_BEUL] = helper_be_stl_mmu, 2003 [MO_BEUQ] = helper_be_stq_mmu, 2004}; 2005 2006/* We expect to use a 16-bit negative offset from ENV. */ 2007QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 2008QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 2009 2010/* Perform the TLB load and compare. Places the result of the comparison 2011 in CR7, loads the addend of the TLB into R3, and returns the register 2012 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */ 2013 2014static TCGReg tcg_out_tlb_read(TCGContext *s, MemOp opc, 2015 TCGReg addrlo, TCGReg addrhi, 2016 int mem_index, bool is_read) 2017{ 2018 int cmp_off 2019 = (is_read 2020 ? offsetof(CPUTLBEntry, addr_read) 2021 : offsetof(CPUTLBEntry, addr_write)); 2022 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 2023 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 2024 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 2025 unsigned s_bits = opc & MO_SIZE; 2026 unsigned a_bits = get_alignment_bits(opc); 2027 2028 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 2029 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0, mask_off); 2030 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R4, TCG_AREG0, table_off); 2031 2032 /* Extract the page index, shifted into place for tlb index. */ 2033 if (TCG_TARGET_REG_BITS == 32) { 2034 tcg_out_shri32(s, TCG_REG_TMP1, addrlo, 2035 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 2036 } else { 2037 tcg_out_shri64(s, TCG_REG_TMP1, addrlo, 2038 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 2039 } 2040 tcg_out32(s, AND | SAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_TMP1)); 2041 2042 /* Load the TLB comparator. */ 2043 if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 2044 uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32 2045 ? LWZUX : LDUX); 2046 tcg_out32(s, lxu | TAB(TCG_REG_TMP1, TCG_REG_R3, TCG_REG_R4)); 2047 } else { 2048 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, TCG_REG_R4)); 2049 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2050 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP1, TCG_REG_R3, cmp_off + 4); 2051 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_R4, TCG_REG_R3, cmp_off); 2052 } else { 2053 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP1, TCG_REG_R3, cmp_off); 2054 } 2055 } 2056 2057 /* Load the TLB addend for use on the fast path. Do this asap 2058 to minimize any load use delay. */ 2059 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, 2060 offsetof(CPUTLBEntry, addend)); 2061 2062 /* Clear the non-page, non-alignment bits from the address */ 2063 if (TCG_TARGET_REG_BITS == 32) { 2064 /* We don't support unaligned accesses on 32-bits. 2065 * Preserve the bottom bits and thus trigger a comparison 2066 * failure on unaligned accesses. 2067 */ 2068 if (a_bits < s_bits) { 2069 a_bits = s_bits; 2070 } 2071 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, 2072 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); 2073 } else { 2074 TCGReg t = addrlo; 2075 2076 /* If the access is unaligned, we need to make sure we fail if we 2077 * cross a page boundary. The trick is to add the access size-1 2078 * to the address before masking the low bits. That will make the 2079 * address overflow to the next page if we cross a page boundary, 2080 * which will then force a mismatch of the TLB compare. 2081 */ 2082 if (a_bits < s_bits) { 2083 unsigned a_mask = (1 << a_bits) - 1; 2084 unsigned s_mask = (1 << s_bits) - 1; 2085 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); 2086 t = TCG_REG_R0; 2087 } 2088 2089 /* Mask the address for the requested alignment. */ 2090 if (TARGET_LONG_BITS == 32) { 2091 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, 2092 (32 - a_bits) & 31, 31 - TARGET_PAGE_BITS); 2093 /* Zero-extend the address for use in the final address. */ 2094 tcg_out_ext32u(s, TCG_REG_R4, addrlo); 2095 addrlo = TCG_REG_R4; 2096 } else if (a_bits == 0) { 2097 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - TARGET_PAGE_BITS); 2098 } else { 2099 tcg_out_rld(s, RLDICL, TCG_REG_R0, t, 2100 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - a_bits); 2101 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0); 2102 } 2103 } 2104 2105 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2106 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, 2107 0, 7, TCG_TYPE_I32); 2108 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_R4, 0, 6, TCG_TYPE_I32); 2109 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 2110 } else { 2111 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP1, 2112 0, 7, TCG_TYPE_TL); 2113 } 2114 2115 return addrlo; 2116} 2117 2118/* Record the context of a call to the out of line helper code for the slow 2119 path for a load or store, so that we can later generate the correct 2120 helper code. */ 2121static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi, 2122 TCGReg datalo_reg, TCGReg datahi_reg, 2123 TCGReg addrlo_reg, TCGReg addrhi_reg, 2124 tcg_insn_unit *raddr, tcg_insn_unit *lptr) 2125{ 2126 TCGLabelQemuLdst *label = new_ldst_label(s); 2127 2128 label->is_ld = is_ld; 2129 label->oi = oi; 2130 label->datalo_reg = datalo_reg; 2131 label->datahi_reg = datahi_reg; 2132 label->addrlo_reg = addrlo_reg; 2133 label->addrhi_reg = addrhi_reg; 2134 label->raddr = tcg_splitwx_to_rx(raddr); 2135 label->label_ptr[0] = lptr; 2136} 2137 2138static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2139{ 2140 MemOpIdx oi = lb->oi; 2141 MemOp opc = get_memop(oi); 2142 TCGReg hi, lo, arg = TCG_REG_R3; 2143 2144 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2145 return false; 2146 } 2147 2148 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); 2149 2150 lo = lb->addrlo_reg; 2151 hi = lb->addrhi_reg; 2152 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2153 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2154 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); 2155 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); 2156 } else { 2157 /* If the address needed to be zero-extended, we'll have already 2158 placed it in R4. The only remaining case is 64-bit guest. */ 2159 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); 2160 } 2161 2162 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); 2163 tcg_out32(s, MFSPR | RT(arg) | LR); 2164 2165 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & (MO_BSWAP | MO_SIZE)]); 2166 2167 lo = lb->datalo_reg; 2168 hi = lb->datahi_reg; 2169 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2170 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_REG_R4); 2171 tcg_out_mov(s, TCG_TYPE_I32, hi, TCG_REG_R3); 2172 } else { 2173 tcg_out_movext(s, lb->type, lo, 2174 TCG_TYPE_REG, opc & MO_SSIZE, TCG_REG_R3); 2175 } 2176 2177 tcg_out_b(s, 0, lb->raddr); 2178 return true; 2179} 2180 2181static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2182{ 2183 MemOpIdx oi = lb->oi; 2184 MemOp opc = get_memop(oi); 2185 MemOp s_bits = opc & MO_SIZE; 2186 TCGReg hi, lo, arg = TCG_REG_R3; 2187 2188 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2189 return false; 2190 } 2191 2192 tcg_out_mov(s, TCG_TYPE_PTR, arg++, TCG_AREG0); 2193 2194 lo = lb->addrlo_reg; 2195 hi = lb->addrhi_reg; 2196 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2197 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2198 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); 2199 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); 2200 } else { 2201 /* If the address needed to be zero-extended, we'll have already 2202 placed it in R4. The only remaining case is 64-bit guest. */ 2203 tcg_out_mov(s, TCG_TYPE_TL, arg++, lo); 2204 } 2205 2206 lo = lb->datalo_reg; 2207 hi = lb->datahi_reg; 2208 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { 2209 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2210 tcg_out_mov(s, TCG_TYPE_I32, arg++, hi); 2211 tcg_out_mov(s, TCG_TYPE_I32, arg++, lo); 2212 } else { 2213 tcg_out_movext(s, s_bits == MO_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, 2214 arg++, lb->type, s_bits, lo); 2215 } 2216 2217 tcg_out_movi(s, TCG_TYPE_I32, arg++, oi); 2218 tcg_out32(s, MFSPR | RT(arg) | LR); 2219 2220 tcg_out_call_int(s, LK, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)]); 2221 2222 tcg_out_b(s, 0, lb->raddr); 2223 return true; 2224} 2225#else 2226 2227static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo, 2228 TCGReg addrhi, unsigned a_bits) 2229{ 2230 unsigned a_mask = (1 << a_bits) - 1; 2231 TCGLabelQemuLdst *label = new_ldst_label(s); 2232 2233 label->is_ld = is_ld; 2234 label->addrlo_reg = addrlo; 2235 label->addrhi_reg = addrhi; 2236 2237 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 2238 tcg_debug_assert(a_bits < 16); 2239 tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, a_mask)); 2240 2241 label->label_ptr[0] = s->code_ptr; 2242 tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); 2243 2244 label->raddr = tcg_splitwx_to_rx(s->code_ptr); 2245} 2246 2247static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 2248{ 2249 if (!reloc_pc14(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2250 return false; 2251 } 2252 2253 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 2254 TCGReg arg = TCG_REG_R4; 2255 2256 arg |= (TCG_TARGET_CALL_ARG_I64 == TCG_CALL_ARG_EVEN); 2257 if (l->addrlo_reg != arg) { 2258 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); 2259 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); 2260 } else if (l->addrhi_reg != arg + 1) { 2261 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, l->addrlo_reg); 2262 tcg_out_mov(s, TCG_TYPE_I32, arg, l->addrhi_reg); 2263 } else { 2264 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_R0, arg); 2265 tcg_out_mov(s, TCG_TYPE_I32, arg, arg + 1); 2266 tcg_out_mov(s, TCG_TYPE_I32, arg + 1, TCG_REG_R0); 2267 } 2268 } else { 2269 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R4, l->addrlo_reg); 2270 } 2271 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_R3, TCG_AREG0); 2272 2273 /* "Tail call" to the helper, with the return address back inline. */ 2274 tcg_out_call_int(s, 0, (const void *)(l->is_ld ? helper_unaligned_ld 2275 : helper_unaligned_st)); 2276 return true; 2277} 2278 2279static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2280{ 2281 return tcg_out_fail_alignment(s, l); 2282} 2283 2284static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 2285{ 2286 return tcg_out_fail_alignment(s, l); 2287} 2288 2289#endif /* SOFTMMU */ 2290 2291static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 2292{ 2293 TCGReg datalo, datahi, addrlo, rbase; 2294 TCGReg addrhi __attribute__((unused)); 2295 MemOpIdx oi; 2296 MemOp opc, s_bits; 2297#ifdef CONFIG_SOFTMMU 2298 int mem_index; 2299 tcg_insn_unit *label_ptr; 2300#else 2301 unsigned a_bits; 2302#endif 2303 2304 datalo = *args++; 2305 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 2306 addrlo = *args++; 2307 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 2308 oi = *args++; 2309 opc = get_memop(oi); 2310 s_bits = opc & MO_SIZE; 2311 2312#ifdef CONFIG_SOFTMMU 2313 mem_index = get_mmuidx(oi); 2314 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, true); 2315 2316 /* Load a pointer into the current opcode w/conditional branch-link. */ 2317 label_ptr = s->code_ptr; 2318 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); 2319 2320 rbase = TCG_REG_R3; 2321#else /* !CONFIG_SOFTMMU */ 2322 a_bits = get_alignment_bits(opc); 2323 if (a_bits) { 2324 tcg_out_test_alignment(s, true, addrlo, addrhi, a_bits); 2325 } 2326 rbase = guest_base ? TCG_GUEST_BASE_REG : 0; 2327 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 2328 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); 2329 addrlo = TCG_REG_TMP1; 2330 } 2331#endif 2332 2333 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { 2334 if (opc & MO_BSWAP) { 2335 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); 2336 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); 2337 tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0)); 2338 } else if (rbase != 0) { 2339 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); 2340 tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo)); 2341 tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0)); 2342 } else if (addrlo == datahi) { 2343 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); 2344 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); 2345 } else { 2346 tcg_out32(s, LWZ | TAI(datahi, addrlo, 0)); 2347 tcg_out32(s, LWZ | TAI(datalo, addrlo, 4)); 2348 } 2349 } else { 2350 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; 2351 if (!have_isa_2_06 && insn == LDBRX) { 2352 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); 2353 tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo)); 2354 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0)); 2355 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); 2356 } else if (insn) { 2357 tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); 2358 } else { 2359 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; 2360 tcg_out32(s, insn | TAB(datalo, rbase, addrlo)); 2361 tcg_out_movext(s, TCG_TYPE_REG, datalo, 2362 TCG_TYPE_REG, opc & MO_SSIZE, datalo); 2363 } 2364 } 2365 2366#ifdef CONFIG_SOFTMMU 2367 add_qemu_ldst_label(s, true, oi, datalo, datahi, addrlo, addrhi, 2368 s->code_ptr, label_ptr); 2369#endif 2370} 2371 2372static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 2373{ 2374 TCGReg datalo, datahi, addrlo, rbase; 2375 TCGReg addrhi __attribute__((unused)); 2376 MemOpIdx oi; 2377 MemOp opc, s_bits; 2378#ifdef CONFIG_SOFTMMU 2379 int mem_index; 2380 tcg_insn_unit *label_ptr; 2381#else 2382 unsigned a_bits; 2383#endif 2384 2385 datalo = *args++; 2386 datahi = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 2387 addrlo = *args++; 2388 addrhi = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 2389 oi = *args++; 2390 opc = get_memop(oi); 2391 s_bits = opc & MO_SIZE; 2392 2393#ifdef CONFIG_SOFTMMU 2394 mem_index = get_mmuidx(oi); 2395 addrlo = tcg_out_tlb_read(s, opc, addrlo, addrhi, mem_index, false); 2396 2397 /* Load a pointer into the current opcode w/conditional branch-link. */ 2398 label_ptr = s->code_ptr; 2399 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); 2400 2401 rbase = TCG_REG_R3; 2402#else /* !CONFIG_SOFTMMU */ 2403 a_bits = get_alignment_bits(opc); 2404 if (a_bits) { 2405 tcg_out_test_alignment(s, false, addrlo, addrhi, a_bits); 2406 } 2407 rbase = guest_base ? TCG_GUEST_BASE_REG : 0; 2408 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 2409 tcg_out_ext32u(s, TCG_REG_TMP1, addrlo); 2410 addrlo = TCG_REG_TMP1; 2411 } 2412#endif 2413 2414 if (TCG_TARGET_REG_BITS == 32 && s_bits == MO_64) { 2415 if (opc & MO_BSWAP) { 2416 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); 2417 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); 2418 tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0)); 2419 } else if (rbase != 0) { 2420 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addrlo, 4)); 2421 tcg_out32(s, STWX | SAB(datahi, rbase, addrlo)); 2422 tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0)); 2423 } else { 2424 tcg_out32(s, STW | TAI(datahi, addrlo, 0)); 2425 tcg_out32(s, STW | TAI(datalo, addrlo, 4)); 2426 } 2427 } else { 2428 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; 2429 if (!have_isa_2_06 && insn == STDBRX) { 2430 tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo)); 2431 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, addrlo, 4)); 2432 tcg_out_shri64(s, TCG_REG_R0, datalo, 32); 2433 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_TMP1)); 2434 } else { 2435 tcg_out32(s, insn | SAB(datalo, rbase, addrlo)); 2436 } 2437 } 2438 2439#ifdef CONFIG_SOFTMMU 2440 add_qemu_ldst_label(s, false, oi, datalo, datahi, addrlo, addrhi, 2441 s->code_ptr, label_ptr); 2442#endif 2443} 2444 2445static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2446{ 2447 int i; 2448 for (i = 0; i < count; ++i) { 2449 p[i] = NOP; 2450 } 2451} 2452 2453/* Parameters for function call generation, used in tcg.c. */ 2454#define TCG_TARGET_STACK_ALIGN 16 2455 2456#ifdef _CALL_AIX 2457# define LINK_AREA_SIZE (6 * SZR) 2458# define LR_OFFSET (1 * SZR) 2459# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) 2460#elif defined(_CALL_DARWIN) 2461# define LINK_AREA_SIZE (6 * SZR) 2462# define LR_OFFSET (2 * SZR) 2463#elif TCG_TARGET_REG_BITS == 64 2464# if defined(_CALL_ELF) && _CALL_ELF == 2 2465# define LINK_AREA_SIZE (4 * SZR) 2466# define LR_OFFSET (1 * SZR) 2467# endif 2468#else /* TCG_TARGET_REG_BITS == 32 */ 2469# if defined(_CALL_SYSV) 2470# define LINK_AREA_SIZE (2 * SZR) 2471# define LR_OFFSET (1 * SZR) 2472# endif 2473#endif 2474#ifndef LR_OFFSET 2475# error "Unhandled abi" 2476#endif 2477#ifndef TCG_TARGET_CALL_STACK_OFFSET 2478# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE 2479#endif 2480 2481#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2482#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) 2483 2484#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ 2485 + TCG_STATIC_CALL_ARGS_SIZE \ 2486 + CPU_TEMP_BUF_SIZE \ 2487 + REG_SAVE_SIZE \ 2488 + TCG_TARGET_STACK_ALIGN - 1) \ 2489 & -TCG_TARGET_STACK_ALIGN) 2490 2491#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) 2492 2493static void tcg_target_qemu_prologue(TCGContext *s) 2494{ 2495 int i; 2496 2497#ifdef _CALL_AIX 2498 const void **desc = (const void **)s->code_ptr; 2499 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */ 2500 desc[1] = 0; /* environment pointer */ 2501 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ 2502#endif 2503 2504 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, 2505 CPU_TEMP_BUF_SIZE); 2506 2507 /* Prologue */ 2508 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); 2509 tcg_out32(s, (SZR == 8 ? STDU : STWU) 2510 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); 2511 2512 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2513 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2514 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2515 } 2516 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2517 2518#ifndef CONFIG_SOFTMMU 2519 if (guest_base) { 2520 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); 2521 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2522 } 2523#endif 2524 2525 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2526 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); 2527 if (USE_REG_TB) { 2528 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2529 } 2530 tcg_out32(s, BCCTR | BO_ALWAYS); 2531 2532 /* Epilogue */ 2533 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2534 2535 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2536 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2537 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2538 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2539 } 2540 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); 2541 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); 2542 tcg_out32(s, BCLR | BO_ALWAYS); 2543} 2544 2545static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 2546{ 2547 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg); 2548 tcg_out_b(s, 0, tcg_code_gen_epilogue); 2549} 2550 2551static void tcg_out_goto_tb(TCGContext *s, int which) 2552{ 2553 uintptr_t ptr = get_jmp_target_addr(s, which); 2554 2555 if (USE_REG_TB) { 2556 ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr); 2557 tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); 2558 2559 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2560 set_jmp_insn_offset(s, which); 2561 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); 2562 2563 /* When branch is out of range, fall through to indirect. */ 2564 tcg_out32(s, BCCTR | BO_ALWAYS); 2565 2566 /* For the unlinked case, need to reset TCG_REG_TB. */ 2567 set_jmp_reset_offset(s, which); 2568 tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, 2569 -tcg_current_code_size(s)); 2570 } else { 2571 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2572 set_jmp_insn_offset(s, which); 2573 tcg_out32(s, NOP); 2574 2575 /* When branch is out of range, fall through to indirect. */ 2576 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); 2577 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr); 2578 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); 2579 tcg_out32(s, BCCTR | BO_ALWAYS); 2580 set_jmp_reset_offset(s, which); 2581 } 2582} 2583 2584void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2585 uintptr_t jmp_rx, uintptr_t jmp_rw) 2586{ 2587 uintptr_t addr = tb->jmp_target_addr[n]; 2588 intptr_t diff = addr - jmp_rx; 2589 tcg_insn_unit insn; 2590 2591 if (in_range_b(diff)) { 2592 insn = B | (diff & 0x3fffffc); 2593 } else if (USE_REG_TB) { 2594 insn = MTSPR | RS(TCG_REG_TB) | CTR; 2595 } else { 2596 insn = NOP; 2597 } 2598 2599 qatomic_set((uint32_t *)jmp_rw, insn); 2600 flush_idcache_range(jmp_rx, jmp_rw, 4); 2601} 2602 2603static void tcg_out_op(TCGContext *s, TCGOpcode opc, 2604 const TCGArg args[TCG_MAX_OP_ARGS], 2605 const int const_args[TCG_MAX_OP_ARGS]) 2606{ 2607 TCGArg a0, a1, a2; 2608 2609 switch (opc) { 2610 case INDEX_op_goto_ptr: 2611 tcg_out32(s, MTSPR | RS(args[0]) | CTR); 2612 if (USE_REG_TB) { 2613 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); 2614 } 2615 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); 2616 tcg_out32(s, BCCTR | BO_ALWAYS); 2617 break; 2618 case INDEX_op_br: 2619 { 2620 TCGLabel *l = arg_label(args[0]); 2621 uint32_t insn = B; 2622 2623 if (l->has_value) { 2624 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr), 2625 l->u.value_ptr); 2626 } else { 2627 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); 2628 } 2629 tcg_out32(s, insn); 2630 } 2631 break; 2632 case INDEX_op_ld8u_i32: 2633 case INDEX_op_ld8u_i64: 2634 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2635 break; 2636 case INDEX_op_ld8s_i32: 2637 case INDEX_op_ld8s_i64: 2638 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2639 tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]); 2640 break; 2641 case INDEX_op_ld16u_i32: 2642 case INDEX_op_ld16u_i64: 2643 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); 2644 break; 2645 case INDEX_op_ld16s_i32: 2646 case INDEX_op_ld16s_i64: 2647 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); 2648 break; 2649 case INDEX_op_ld_i32: 2650 case INDEX_op_ld32u_i64: 2651 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); 2652 break; 2653 case INDEX_op_ld32s_i64: 2654 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); 2655 break; 2656 case INDEX_op_ld_i64: 2657 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); 2658 break; 2659 case INDEX_op_st8_i32: 2660 case INDEX_op_st8_i64: 2661 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); 2662 break; 2663 case INDEX_op_st16_i32: 2664 case INDEX_op_st16_i64: 2665 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); 2666 break; 2667 case INDEX_op_st_i32: 2668 case INDEX_op_st32_i64: 2669 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); 2670 break; 2671 case INDEX_op_st_i64: 2672 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); 2673 break; 2674 2675 case INDEX_op_add_i32: 2676 a0 = args[0], a1 = args[1], a2 = args[2]; 2677 if (const_args[2]) { 2678 do_addi_32: 2679 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); 2680 } else { 2681 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2682 } 2683 break; 2684 case INDEX_op_sub_i32: 2685 a0 = args[0], a1 = args[1], a2 = args[2]; 2686 if (const_args[1]) { 2687 if (const_args[2]) { 2688 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); 2689 } else { 2690 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2691 } 2692 } else if (const_args[2]) { 2693 a2 = -a2; 2694 goto do_addi_32; 2695 } else { 2696 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2697 } 2698 break; 2699 2700 case INDEX_op_and_i32: 2701 a0 = args[0], a1 = args[1], a2 = args[2]; 2702 if (const_args[2]) { 2703 tcg_out_andi32(s, a0, a1, a2); 2704 } else { 2705 tcg_out32(s, AND | SAB(a1, a0, a2)); 2706 } 2707 break; 2708 case INDEX_op_and_i64: 2709 a0 = args[0], a1 = args[1], a2 = args[2]; 2710 if (const_args[2]) { 2711 tcg_out_andi64(s, a0, a1, a2); 2712 } else { 2713 tcg_out32(s, AND | SAB(a1, a0, a2)); 2714 } 2715 break; 2716 case INDEX_op_or_i64: 2717 case INDEX_op_or_i32: 2718 a0 = args[0], a1 = args[1], a2 = args[2]; 2719 if (const_args[2]) { 2720 tcg_out_ori32(s, a0, a1, a2); 2721 } else { 2722 tcg_out32(s, OR | SAB(a1, a0, a2)); 2723 } 2724 break; 2725 case INDEX_op_xor_i64: 2726 case INDEX_op_xor_i32: 2727 a0 = args[0], a1 = args[1], a2 = args[2]; 2728 if (const_args[2]) { 2729 tcg_out_xori32(s, a0, a1, a2); 2730 } else { 2731 tcg_out32(s, XOR | SAB(a1, a0, a2)); 2732 } 2733 break; 2734 case INDEX_op_andc_i32: 2735 a0 = args[0], a1 = args[1], a2 = args[2]; 2736 if (const_args[2]) { 2737 tcg_out_andi32(s, a0, a1, ~a2); 2738 } else { 2739 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2740 } 2741 break; 2742 case INDEX_op_andc_i64: 2743 a0 = args[0], a1 = args[1], a2 = args[2]; 2744 if (const_args[2]) { 2745 tcg_out_andi64(s, a0, a1, ~a2); 2746 } else { 2747 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2748 } 2749 break; 2750 case INDEX_op_orc_i32: 2751 if (const_args[2]) { 2752 tcg_out_ori32(s, args[0], args[1], ~args[2]); 2753 break; 2754 } 2755 /* FALLTHRU */ 2756 case INDEX_op_orc_i64: 2757 tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); 2758 break; 2759 case INDEX_op_eqv_i32: 2760 if (const_args[2]) { 2761 tcg_out_xori32(s, args[0], args[1], ~args[2]); 2762 break; 2763 } 2764 /* FALLTHRU */ 2765 case INDEX_op_eqv_i64: 2766 tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); 2767 break; 2768 case INDEX_op_nand_i32: 2769 case INDEX_op_nand_i64: 2770 tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); 2771 break; 2772 case INDEX_op_nor_i32: 2773 case INDEX_op_nor_i64: 2774 tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); 2775 break; 2776 2777 case INDEX_op_clz_i32: 2778 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], 2779 args[2], const_args[2]); 2780 break; 2781 case INDEX_op_ctz_i32: 2782 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], 2783 args[2], const_args[2]); 2784 break; 2785 case INDEX_op_ctpop_i32: 2786 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); 2787 break; 2788 2789 case INDEX_op_clz_i64: 2790 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], 2791 args[2], const_args[2]); 2792 break; 2793 case INDEX_op_ctz_i64: 2794 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], 2795 args[2], const_args[2]); 2796 break; 2797 case INDEX_op_ctpop_i64: 2798 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); 2799 break; 2800 2801 case INDEX_op_mul_i32: 2802 a0 = args[0], a1 = args[1], a2 = args[2]; 2803 if (const_args[2]) { 2804 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2805 } else { 2806 tcg_out32(s, MULLW | TAB(a0, a1, a2)); 2807 } 2808 break; 2809 2810 case INDEX_op_div_i32: 2811 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); 2812 break; 2813 2814 case INDEX_op_divu_i32: 2815 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); 2816 break; 2817 2818 case INDEX_op_rem_i32: 2819 tcg_out32(s, MODSW | TAB(args[0], args[1], args[2])); 2820 break; 2821 2822 case INDEX_op_remu_i32: 2823 tcg_out32(s, MODUW | TAB(args[0], args[1], args[2])); 2824 break; 2825 2826 case INDEX_op_shl_i32: 2827 if (const_args[2]) { 2828 /* Limit immediate shift count lest we create an illegal insn. */ 2829 tcg_out_shli32(s, args[0], args[1], args[2] & 31); 2830 } else { 2831 tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); 2832 } 2833 break; 2834 case INDEX_op_shr_i32: 2835 if (const_args[2]) { 2836 /* Limit immediate shift count lest we create an illegal insn. */ 2837 tcg_out_shri32(s, args[0], args[1], args[2] & 31); 2838 } else { 2839 tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); 2840 } 2841 break; 2842 case INDEX_op_sar_i32: 2843 if (const_args[2]) { 2844 tcg_out_sari32(s, args[0], args[1], args[2]); 2845 } else { 2846 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); 2847 } 2848 break; 2849 case INDEX_op_rotl_i32: 2850 if (const_args[2]) { 2851 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); 2852 } else { 2853 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) 2854 | MB(0) | ME(31)); 2855 } 2856 break; 2857 case INDEX_op_rotr_i32: 2858 if (const_args[2]) { 2859 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); 2860 } else { 2861 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); 2862 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) 2863 | MB(0) | ME(31)); 2864 } 2865 break; 2866 2867 case INDEX_op_brcond_i32: 2868 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2869 arg_label(args[3]), TCG_TYPE_I32); 2870 break; 2871 case INDEX_op_brcond_i64: 2872 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2873 arg_label(args[3]), TCG_TYPE_I64); 2874 break; 2875 case INDEX_op_brcond2_i32: 2876 tcg_out_brcond2(s, args, const_args); 2877 break; 2878 2879 case INDEX_op_neg_i32: 2880 case INDEX_op_neg_i64: 2881 tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); 2882 break; 2883 2884 case INDEX_op_not_i32: 2885 case INDEX_op_not_i64: 2886 tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); 2887 break; 2888 2889 case INDEX_op_add_i64: 2890 a0 = args[0], a1 = args[1], a2 = args[2]; 2891 if (const_args[2]) { 2892 do_addi_64: 2893 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); 2894 } else { 2895 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2896 } 2897 break; 2898 case INDEX_op_sub_i64: 2899 a0 = args[0], a1 = args[1], a2 = args[2]; 2900 if (const_args[1]) { 2901 if (const_args[2]) { 2902 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); 2903 } else { 2904 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2905 } 2906 } else if (const_args[2]) { 2907 a2 = -a2; 2908 goto do_addi_64; 2909 } else { 2910 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2911 } 2912 break; 2913 2914 case INDEX_op_shl_i64: 2915 if (const_args[2]) { 2916 /* Limit immediate shift count lest we create an illegal insn. */ 2917 tcg_out_shli64(s, args[0], args[1], args[2] & 63); 2918 } else { 2919 tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); 2920 } 2921 break; 2922 case INDEX_op_shr_i64: 2923 if (const_args[2]) { 2924 /* Limit immediate shift count lest we create an illegal insn. */ 2925 tcg_out_shri64(s, args[0], args[1], args[2] & 63); 2926 } else { 2927 tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); 2928 } 2929 break; 2930 case INDEX_op_sar_i64: 2931 if (const_args[2]) { 2932 tcg_out_sari64(s, args[0], args[1], args[2]); 2933 } else { 2934 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); 2935 } 2936 break; 2937 case INDEX_op_rotl_i64: 2938 if (const_args[2]) { 2939 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); 2940 } else { 2941 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); 2942 } 2943 break; 2944 case INDEX_op_rotr_i64: 2945 if (const_args[2]) { 2946 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); 2947 } else { 2948 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); 2949 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); 2950 } 2951 break; 2952 2953 case INDEX_op_mul_i64: 2954 a0 = args[0], a1 = args[1], a2 = args[2]; 2955 if (const_args[2]) { 2956 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2957 } else { 2958 tcg_out32(s, MULLD | TAB(a0, a1, a2)); 2959 } 2960 break; 2961 case INDEX_op_div_i64: 2962 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); 2963 break; 2964 case INDEX_op_divu_i64: 2965 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); 2966 break; 2967 case INDEX_op_rem_i64: 2968 tcg_out32(s, MODSD | TAB(args[0], args[1], args[2])); 2969 break; 2970 case INDEX_op_remu_i64: 2971 tcg_out32(s, MODUD | TAB(args[0], args[1], args[2])); 2972 break; 2973 2974 case INDEX_op_qemu_ld_i32: 2975 tcg_out_qemu_ld(s, args, false); 2976 break; 2977 case INDEX_op_qemu_ld_i64: 2978 tcg_out_qemu_ld(s, args, true); 2979 break; 2980 case INDEX_op_qemu_st_i32: 2981 tcg_out_qemu_st(s, args, false); 2982 break; 2983 case INDEX_op_qemu_st_i64: 2984 tcg_out_qemu_st(s, args, true); 2985 break; 2986 2987 case INDEX_op_setcond_i32: 2988 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], 2989 const_args[2]); 2990 break; 2991 case INDEX_op_setcond_i64: 2992 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], 2993 const_args[2]); 2994 break; 2995 case INDEX_op_setcond2_i32: 2996 tcg_out_setcond2(s, args, const_args); 2997 break; 2998 2999 case INDEX_op_bswap16_i32: 3000 case INDEX_op_bswap16_i64: 3001 tcg_out_bswap16(s, args[0], args[1], args[2]); 3002 break; 3003 case INDEX_op_bswap32_i32: 3004 tcg_out_bswap32(s, args[0], args[1], 0); 3005 break; 3006 case INDEX_op_bswap32_i64: 3007 tcg_out_bswap32(s, args[0], args[1], args[2]); 3008 break; 3009 case INDEX_op_bswap64_i64: 3010 tcg_out_bswap64(s, args[0], args[1]); 3011 break; 3012 3013 case INDEX_op_deposit_i32: 3014 if (const_args[2]) { 3015 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; 3016 tcg_out_andi32(s, args[0], args[0], ~mask); 3017 } else { 3018 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], 3019 32 - args[3] - args[4], 31 - args[3]); 3020 } 3021 break; 3022 case INDEX_op_deposit_i64: 3023 if (const_args[2]) { 3024 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; 3025 tcg_out_andi64(s, args[0], args[0], ~mask); 3026 } else { 3027 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], 3028 64 - args[3] - args[4]); 3029 } 3030 break; 3031 3032 case INDEX_op_extract_i32: 3033 tcg_out_rlw(s, RLWINM, args[0], args[1], 3034 32 - args[2], 32 - args[3], 31); 3035 break; 3036 case INDEX_op_extract_i64: 3037 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); 3038 break; 3039 3040 case INDEX_op_movcond_i32: 3041 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], 3042 args[3], args[4], const_args[2]); 3043 break; 3044 case INDEX_op_movcond_i64: 3045 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], 3046 args[3], args[4], const_args[2]); 3047 break; 3048 3049#if TCG_TARGET_REG_BITS == 64 3050 case INDEX_op_add2_i64: 3051#else 3052 case INDEX_op_add2_i32: 3053#endif 3054 /* Note that the CA bit is defined based on the word size of the 3055 environment. So in 64-bit mode it's always carry-out of bit 63. 3056 The fallback code using deposit works just as well for 32-bit. */ 3057 a0 = args[0], a1 = args[1]; 3058 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { 3059 a0 = TCG_REG_R0; 3060 } 3061 if (const_args[4]) { 3062 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); 3063 } else { 3064 tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); 3065 } 3066 if (const_args[5]) { 3067 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); 3068 } else { 3069 tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); 3070 } 3071 if (a0 != args[0]) { 3072 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3073 } 3074 break; 3075 3076#if TCG_TARGET_REG_BITS == 64 3077 case INDEX_op_sub2_i64: 3078#else 3079 case INDEX_op_sub2_i32: 3080#endif 3081 a0 = args[0], a1 = args[1]; 3082 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { 3083 a0 = TCG_REG_R0; 3084 } 3085 if (const_args[2]) { 3086 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); 3087 } else { 3088 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); 3089 } 3090 if (const_args[3]) { 3091 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); 3092 } else { 3093 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); 3094 } 3095 if (a0 != args[0]) { 3096 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3097 } 3098 break; 3099 3100 case INDEX_op_muluh_i32: 3101 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); 3102 break; 3103 case INDEX_op_mulsh_i32: 3104 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); 3105 break; 3106 case INDEX_op_muluh_i64: 3107 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); 3108 break; 3109 case INDEX_op_mulsh_i64: 3110 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); 3111 break; 3112 3113 case INDEX_op_mb: 3114 tcg_out_mb(s, args[0]); 3115 break; 3116 3117 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 3118 case INDEX_op_mov_i64: 3119 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3120 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3121 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3122 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 3123 case INDEX_op_ext8s_i64: 3124 case INDEX_op_ext8u_i32: 3125 case INDEX_op_ext8u_i64: 3126 case INDEX_op_ext16s_i32: 3127 case INDEX_op_ext16s_i64: 3128 case INDEX_op_ext16u_i32: 3129 case INDEX_op_ext16u_i64: 3130 case INDEX_op_ext32s_i64: 3131 case INDEX_op_ext32u_i64: 3132 case INDEX_op_ext_i32_i64: 3133 case INDEX_op_extu_i32_i64: 3134 case INDEX_op_extrl_i64_i32: 3135 default: 3136 g_assert_not_reached(); 3137 } 3138} 3139 3140int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3141{ 3142 switch (opc) { 3143 case INDEX_op_and_vec: 3144 case INDEX_op_or_vec: 3145 case INDEX_op_xor_vec: 3146 case INDEX_op_andc_vec: 3147 case INDEX_op_not_vec: 3148 case INDEX_op_nor_vec: 3149 case INDEX_op_eqv_vec: 3150 case INDEX_op_nand_vec: 3151 return 1; 3152 case INDEX_op_orc_vec: 3153 return have_isa_2_07; 3154 case INDEX_op_add_vec: 3155 case INDEX_op_sub_vec: 3156 case INDEX_op_smax_vec: 3157 case INDEX_op_smin_vec: 3158 case INDEX_op_umax_vec: 3159 case INDEX_op_umin_vec: 3160 case INDEX_op_shlv_vec: 3161 case INDEX_op_shrv_vec: 3162 case INDEX_op_sarv_vec: 3163 case INDEX_op_rotlv_vec: 3164 return vece <= MO_32 || have_isa_2_07; 3165 case INDEX_op_ssadd_vec: 3166 case INDEX_op_sssub_vec: 3167 case INDEX_op_usadd_vec: 3168 case INDEX_op_ussub_vec: 3169 return vece <= MO_32; 3170 case INDEX_op_cmp_vec: 3171 case INDEX_op_shli_vec: 3172 case INDEX_op_shri_vec: 3173 case INDEX_op_sari_vec: 3174 case INDEX_op_rotli_vec: 3175 return vece <= MO_32 || have_isa_2_07 ? -1 : 0; 3176 case INDEX_op_neg_vec: 3177 return vece >= MO_32 && have_isa_3_00; 3178 case INDEX_op_mul_vec: 3179 switch (vece) { 3180 case MO_8: 3181 case MO_16: 3182 return -1; 3183 case MO_32: 3184 return have_isa_2_07 ? 1 : -1; 3185 case MO_64: 3186 return have_isa_3_10; 3187 } 3188 return 0; 3189 case INDEX_op_bitsel_vec: 3190 return have_vsx; 3191 case INDEX_op_rotrv_vec: 3192 return -1; 3193 default: 3194 return 0; 3195 } 3196} 3197 3198static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 3199 TCGReg dst, TCGReg src) 3200{ 3201 tcg_debug_assert(dst >= TCG_REG_V0); 3202 3203 /* Splat from integer reg allowed via constraints for v3.00. */ 3204 if (src < TCG_REG_V0) { 3205 tcg_debug_assert(have_isa_3_00); 3206 switch (vece) { 3207 case MO_64: 3208 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); 3209 return true; 3210 case MO_32: 3211 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); 3212 return true; 3213 default: 3214 /* Fail, so that we fall back on either dupm or mov+dup. */ 3215 return false; 3216 } 3217 } 3218 3219 /* 3220 * Recall we use (or emulate) VSX integer loads, so the integer is 3221 * right justified within the left (zero-index) double-word. 3222 */ 3223 switch (vece) { 3224 case MO_8: 3225 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); 3226 break; 3227 case MO_16: 3228 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); 3229 break; 3230 case MO_32: 3231 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); 3232 break; 3233 case MO_64: 3234 if (have_vsx) { 3235 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); 3236 break; 3237 } 3238 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); 3239 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); 3240 break; 3241 default: 3242 g_assert_not_reached(); 3243 } 3244 return true; 3245} 3246 3247static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 3248 TCGReg out, TCGReg base, intptr_t offset) 3249{ 3250 int elt; 3251 3252 tcg_debug_assert(out >= TCG_REG_V0); 3253 switch (vece) { 3254 case MO_8: 3255 if (have_isa_3_00) { 3256 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); 3257 } else { 3258 tcg_out_mem_long(s, 0, LVEBX, out, base, offset); 3259 } 3260 elt = extract32(offset, 0, 4); 3261#if !HOST_BIG_ENDIAN 3262 elt ^= 15; 3263#endif 3264 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); 3265 break; 3266 case MO_16: 3267 tcg_debug_assert((offset & 1) == 0); 3268 if (have_isa_3_00) { 3269 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); 3270 } else { 3271 tcg_out_mem_long(s, 0, LVEHX, out, base, offset); 3272 } 3273 elt = extract32(offset, 1, 3); 3274#if !HOST_BIG_ENDIAN 3275 elt ^= 7; 3276#endif 3277 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); 3278 break; 3279 case MO_32: 3280 if (have_isa_3_00) { 3281 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); 3282 break; 3283 } 3284 tcg_debug_assert((offset & 3) == 0); 3285 tcg_out_mem_long(s, 0, LVEWX, out, base, offset); 3286 elt = extract32(offset, 2, 2); 3287#if !HOST_BIG_ENDIAN 3288 elt ^= 3; 3289#endif 3290 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); 3291 break; 3292 case MO_64: 3293 if (have_vsx) { 3294 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); 3295 break; 3296 } 3297 tcg_debug_assert((offset & 7) == 0); 3298 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); 3299 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); 3300 elt = extract32(offset, 3, 1); 3301#if !HOST_BIG_ENDIAN 3302 elt = !elt; 3303#endif 3304 if (elt) { 3305 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); 3306 } else { 3307 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); 3308 } 3309 break; 3310 default: 3311 g_assert_not_reached(); 3312 } 3313 return true; 3314} 3315 3316static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3317 unsigned vecl, unsigned vece, 3318 const TCGArg args[TCG_MAX_OP_ARGS], 3319 const int const_args[TCG_MAX_OP_ARGS]) 3320{ 3321 static const uint32_t 3322 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, 3323 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, 3324 mul_op[4] = { 0, 0, VMULUWM, VMULLD }, 3325 neg_op[4] = { 0, 0, VNEGW, VNEGD }, 3326 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, 3327 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, 3328 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, 3329 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, 3330 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, 3331 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, 3332 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, 3333 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, 3334 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, 3335 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, 3336 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, 3337 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, 3338 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD }, 3339 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD }, 3340 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD }, 3341 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 }, 3342 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 }, 3343 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 }, 3344 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 }, 3345 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 }, 3346 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD }; 3347 3348 TCGType type = vecl + TCG_TYPE_V64; 3349 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3350 uint32_t insn; 3351 3352 switch (opc) { 3353 case INDEX_op_ld_vec: 3354 tcg_out_ld(s, type, a0, a1, a2); 3355 return; 3356 case INDEX_op_st_vec: 3357 tcg_out_st(s, type, a0, a1, a2); 3358 return; 3359 case INDEX_op_dupm_vec: 3360 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3361 return; 3362 3363 case INDEX_op_add_vec: 3364 insn = add_op[vece]; 3365 break; 3366 case INDEX_op_sub_vec: 3367 insn = sub_op[vece]; 3368 break; 3369 case INDEX_op_neg_vec: 3370 insn = neg_op[vece]; 3371 a2 = a1; 3372 a1 = 0; 3373 break; 3374 case INDEX_op_mul_vec: 3375 insn = mul_op[vece]; 3376 break; 3377 case INDEX_op_ssadd_vec: 3378 insn = ssadd_op[vece]; 3379 break; 3380 case INDEX_op_sssub_vec: 3381 insn = sssub_op[vece]; 3382 break; 3383 case INDEX_op_usadd_vec: 3384 insn = usadd_op[vece]; 3385 break; 3386 case INDEX_op_ussub_vec: 3387 insn = ussub_op[vece]; 3388 break; 3389 case INDEX_op_smin_vec: 3390 insn = smin_op[vece]; 3391 break; 3392 case INDEX_op_umin_vec: 3393 insn = umin_op[vece]; 3394 break; 3395 case INDEX_op_smax_vec: 3396 insn = smax_op[vece]; 3397 break; 3398 case INDEX_op_umax_vec: 3399 insn = umax_op[vece]; 3400 break; 3401 case INDEX_op_shlv_vec: 3402 insn = shlv_op[vece]; 3403 break; 3404 case INDEX_op_shrv_vec: 3405 insn = shrv_op[vece]; 3406 break; 3407 case INDEX_op_sarv_vec: 3408 insn = sarv_op[vece]; 3409 break; 3410 case INDEX_op_and_vec: 3411 insn = VAND; 3412 break; 3413 case INDEX_op_or_vec: 3414 insn = VOR; 3415 break; 3416 case INDEX_op_xor_vec: 3417 insn = VXOR; 3418 break; 3419 case INDEX_op_andc_vec: 3420 insn = VANDC; 3421 break; 3422 case INDEX_op_not_vec: 3423 insn = VNOR; 3424 a2 = a1; 3425 break; 3426 case INDEX_op_orc_vec: 3427 insn = VORC; 3428 break; 3429 case INDEX_op_nand_vec: 3430 insn = VNAND; 3431 break; 3432 case INDEX_op_nor_vec: 3433 insn = VNOR; 3434 break; 3435 case INDEX_op_eqv_vec: 3436 insn = VEQV; 3437 break; 3438 3439 case INDEX_op_cmp_vec: 3440 switch (args[3]) { 3441 case TCG_COND_EQ: 3442 insn = eq_op[vece]; 3443 break; 3444 case TCG_COND_NE: 3445 insn = ne_op[vece]; 3446 break; 3447 case TCG_COND_GT: 3448 insn = gts_op[vece]; 3449 break; 3450 case TCG_COND_GTU: 3451 insn = gtu_op[vece]; 3452 break; 3453 default: 3454 g_assert_not_reached(); 3455 } 3456 break; 3457 3458 case INDEX_op_bitsel_vec: 3459 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); 3460 return; 3461 3462 case INDEX_op_dup2_vec: 3463 assert(TCG_TARGET_REG_BITS == 32); 3464 /* With inputs a1 = xLxx, a2 = xHxx */ 3465 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ 3466 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ 3467 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ 3468 return; 3469 3470 case INDEX_op_ppc_mrgh_vec: 3471 insn = mrgh_op[vece]; 3472 break; 3473 case INDEX_op_ppc_mrgl_vec: 3474 insn = mrgl_op[vece]; 3475 break; 3476 case INDEX_op_ppc_muleu_vec: 3477 insn = muleu_op[vece]; 3478 break; 3479 case INDEX_op_ppc_mulou_vec: 3480 insn = mulou_op[vece]; 3481 break; 3482 case INDEX_op_ppc_pkum_vec: 3483 insn = pkum_op[vece]; 3484 break; 3485 case INDEX_op_rotlv_vec: 3486 insn = rotl_op[vece]; 3487 break; 3488 case INDEX_op_ppc_msum_vec: 3489 tcg_debug_assert(vece == MO_16); 3490 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])); 3491 return; 3492 3493 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3494 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3495 default: 3496 g_assert_not_reached(); 3497 } 3498 3499 tcg_debug_assert(insn != 0); 3500 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); 3501} 3502 3503static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, 3504 TCGv_vec v1, TCGArg imm, TCGOpcode opci) 3505{ 3506 TCGv_vec t1; 3507 3508 if (vece == MO_32) { 3509 /* 3510 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3511 * So using negative numbers gets us the 4th bit easily. 3512 */ 3513 imm = sextract32(imm, 0, 5); 3514 } else { 3515 imm &= (8 << vece) - 1; 3516 } 3517 3518 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ 3519 t1 = tcg_constant_vec(type, MO_8, imm); 3520 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), 3521 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3522} 3523 3524static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 3525 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 3526{ 3527 bool need_swap = false, need_inv = false; 3528 3529 tcg_debug_assert(vece <= MO_32 || have_isa_2_07); 3530 3531 switch (cond) { 3532 case TCG_COND_EQ: 3533 case TCG_COND_GT: 3534 case TCG_COND_GTU: 3535 break; 3536 case TCG_COND_NE: 3537 if (have_isa_3_00 && vece <= MO_32) { 3538 break; 3539 } 3540 /* fall through */ 3541 case TCG_COND_LE: 3542 case TCG_COND_LEU: 3543 need_inv = true; 3544 break; 3545 case TCG_COND_LT: 3546 case TCG_COND_LTU: 3547 need_swap = true; 3548 break; 3549 case TCG_COND_GE: 3550 case TCG_COND_GEU: 3551 need_swap = need_inv = true; 3552 break; 3553 default: 3554 g_assert_not_reached(); 3555 } 3556 3557 if (need_inv) { 3558 cond = tcg_invert_cond(cond); 3559 } 3560 if (need_swap) { 3561 TCGv_vec t1; 3562 t1 = v1, v1 = v2, v2 = t1; 3563 cond = tcg_swap_cond(cond); 3564 } 3565 3566 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), 3567 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 3568 3569 if (need_inv) { 3570 tcg_gen_not_vec(vece, v0, v0); 3571 } 3572} 3573 3574static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, 3575 TCGv_vec v1, TCGv_vec v2) 3576{ 3577 TCGv_vec t1 = tcg_temp_new_vec(type); 3578 TCGv_vec t2 = tcg_temp_new_vec(type); 3579 TCGv_vec c0, c16; 3580 3581 switch (vece) { 3582 case MO_8: 3583 case MO_16: 3584 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), 3585 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3586 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), 3587 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3588 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), 3589 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3590 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), 3591 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3592 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), 3593 tcgv_vec_arg(v0), tcgv_vec_arg(t1)); 3594 break; 3595 3596 case MO_32: 3597 tcg_debug_assert(!have_isa_2_07); 3598 /* 3599 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3600 * So using -16 is a quick way to represent 16. 3601 */ 3602 c16 = tcg_constant_vec(type, MO_8, -16); 3603 c0 = tcg_constant_vec(type, MO_8, 0); 3604 3605 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), 3606 tcgv_vec_arg(v2), tcgv_vec_arg(c16)); 3607 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), 3608 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3609 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), 3610 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); 3611 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), 3612 tcgv_vec_arg(t1), tcgv_vec_arg(c16)); 3613 tcg_gen_add_vec(MO_32, v0, t1, t2); 3614 break; 3615 3616 default: 3617 g_assert_not_reached(); 3618 } 3619 tcg_temp_free_vec(t1); 3620 tcg_temp_free_vec(t2); 3621} 3622 3623void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3624 TCGArg a0, ...) 3625{ 3626 va_list va; 3627 TCGv_vec v0, v1, v2, t0; 3628 TCGArg a2; 3629 3630 va_start(va, a0); 3631 v0 = temp_tcgv_vec(arg_temp(a0)); 3632 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3633 a2 = va_arg(va, TCGArg); 3634 3635 switch (opc) { 3636 case INDEX_op_shli_vec: 3637 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); 3638 break; 3639 case INDEX_op_shri_vec: 3640 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); 3641 break; 3642 case INDEX_op_sari_vec: 3643 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); 3644 break; 3645 case INDEX_op_rotli_vec: 3646 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); 3647 break; 3648 case INDEX_op_cmp_vec: 3649 v2 = temp_tcgv_vec(arg_temp(a2)); 3650 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 3651 break; 3652 case INDEX_op_mul_vec: 3653 v2 = temp_tcgv_vec(arg_temp(a2)); 3654 expand_vec_mul(type, vece, v0, v1, v2); 3655 break; 3656 case INDEX_op_rotlv_vec: 3657 v2 = temp_tcgv_vec(arg_temp(a2)); 3658 t0 = tcg_temp_new_vec(type); 3659 tcg_gen_neg_vec(vece, t0, v2); 3660 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3661 tcg_temp_free_vec(t0); 3662 break; 3663 default: 3664 g_assert_not_reached(); 3665 } 3666 va_end(va); 3667} 3668 3669static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3670{ 3671 switch (op) { 3672 case INDEX_op_goto_ptr: 3673 return C_O0_I1(r); 3674 3675 case INDEX_op_ld8u_i32: 3676 case INDEX_op_ld8s_i32: 3677 case INDEX_op_ld16u_i32: 3678 case INDEX_op_ld16s_i32: 3679 case INDEX_op_ld_i32: 3680 case INDEX_op_ctpop_i32: 3681 case INDEX_op_neg_i32: 3682 case INDEX_op_not_i32: 3683 case INDEX_op_ext8s_i32: 3684 case INDEX_op_ext16s_i32: 3685 case INDEX_op_bswap16_i32: 3686 case INDEX_op_bswap32_i32: 3687 case INDEX_op_extract_i32: 3688 case INDEX_op_ld8u_i64: 3689 case INDEX_op_ld8s_i64: 3690 case INDEX_op_ld16u_i64: 3691 case INDEX_op_ld16s_i64: 3692 case INDEX_op_ld32u_i64: 3693 case INDEX_op_ld32s_i64: 3694 case INDEX_op_ld_i64: 3695 case INDEX_op_ctpop_i64: 3696 case INDEX_op_neg_i64: 3697 case INDEX_op_not_i64: 3698 case INDEX_op_ext8s_i64: 3699 case INDEX_op_ext16s_i64: 3700 case INDEX_op_ext32s_i64: 3701 case INDEX_op_ext_i32_i64: 3702 case INDEX_op_extu_i32_i64: 3703 case INDEX_op_bswap16_i64: 3704 case INDEX_op_bswap32_i64: 3705 case INDEX_op_bswap64_i64: 3706 case INDEX_op_extract_i64: 3707 return C_O1_I1(r, r); 3708 3709 case INDEX_op_st8_i32: 3710 case INDEX_op_st16_i32: 3711 case INDEX_op_st_i32: 3712 case INDEX_op_st8_i64: 3713 case INDEX_op_st16_i64: 3714 case INDEX_op_st32_i64: 3715 case INDEX_op_st_i64: 3716 return C_O0_I2(r, r); 3717 3718 case INDEX_op_add_i32: 3719 case INDEX_op_and_i32: 3720 case INDEX_op_or_i32: 3721 case INDEX_op_xor_i32: 3722 case INDEX_op_andc_i32: 3723 case INDEX_op_orc_i32: 3724 case INDEX_op_eqv_i32: 3725 case INDEX_op_shl_i32: 3726 case INDEX_op_shr_i32: 3727 case INDEX_op_sar_i32: 3728 case INDEX_op_rotl_i32: 3729 case INDEX_op_rotr_i32: 3730 case INDEX_op_setcond_i32: 3731 case INDEX_op_and_i64: 3732 case INDEX_op_andc_i64: 3733 case INDEX_op_shl_i64: 3734 case INDEX_op_shr_i64: 3735 case INDEX_op_sar_i64: 3736 case INDEX_op_rotl_i64: 3737 case INDEX_op_rotr_i64: 3738 case INDEX_op_setcond_i64: 3739 return C_O1_I2(r, r, ri); 3740 3741 case INDEX_op_mul_i32: 3742 case INDEX_op_mul_i64: 3743 return C_O1_I2(r, r, rI); 3744 3745 case INDEX_op_div_i32: 3746 case INDEX_op_divu_i32: 3747 case INDEX_op_rem_i32: 3748 case INDEX_op_remu_i32: 3749 case INDEX_op_nand_i32: 3750 case INDEX_op_nor_i32: 3751 case INDEX_op_muluh_i32: 3752 case INDEX_op_mulsh_i32: 3753 case INDEX_op_orc_i64: 3754 case INDEX_op_eqv_i64: 3755 case INDEX_op_nand_i64: 3756 case INDEX_op_nor_i64: 3757 case INDEX_op_div_i64: 3758 case INDEX_op_divu_i64: 3759 case INDEX_op_rem_i64: 3760 case INDEX_op_remu_i64: 3761 case INDEX_op_mulsh_i64: 3762 case INDEX_op_muluh_i64: 3763 return C_O1_I2(r, r, r); 3764 3765 case INDEX_op_sub_i32: 3766 return C_O1_I2(r, rI, ri); 3767 case INDEX_op_add_i64: 3768 return C_O1_I2(r, r, rT); 3769 case INDEX_op_or_i64: 3770 case INDEX_op_xor_i64: 3771 return C_O1_I2(r, r, rU); 3772 case INDEX_op_sub_i64: 3773 return C_O1_I2(r, rI, rT); 3774 case INDEX_op_clz_i32: 3775 case INDEX_op_ctz_i32: 3776 case INDEX_op_clz_i64: 3777 case INDEX_op_ctz_i64: 3778 return C_O1_I2(r, r, rZW); 3779 3780 case INDEX_op_brcond_i32: 3781 case INDEX_op_brcond_i64: 3782 return C_O0_I2(r, ri); 3783 3784 case INDEX_op_movcond_i32: 3785 case INDEX_op_movcond_i64: 3786 return C_O1_I4(r, r, ri, rZ, rZ); 3787 case INDEX_op_deposit_i32: 3788 case INDEX_op_deposit_i64: 3789 return C_O1_I2(r, 0, rZ); 3790 case INDEX_op_brcond2_i32: 3791 return C_O0_I4(r, r, ri, ri); 3792 case INDEX_op_setcond2_i32: 3793 return C_O1_I4(r, r, r, ri, ri); 3794 case INDEX_op_add2_i64: 3795 case INDEX_op_add2_i32: 3796 return C_O2_I4(r, r, r, r, rI, rZM); 3797 case INDEX_op_sub2_i64: 3798 case INDEX_op_sub2_i32: 3799 return C_O2_I4(r, r, rI, rZM, r, r); 3800 3801 case INDEX_op_qemu_ld_i32: 3802 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 3803 ? C_O1_I1(r, L) 3804 : C_O1_I2(r, L, L)); 3805 3806 case INDEX_op_qemu_st_i32: 3807 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 3808 ? C_O0_I2(S, S) 3809 : C_O0_I3(S, S, S)); 3810 3811 case INDEX_op_qemu_ld_i64: 3812 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) 3813 : TARGET_LONG_BITS == 32 ? C_O2_I1(L, L, L) 3814 : C_O2_I2(L, L, L, L)); 3815 3816 case INDEX_op_qemu_st_i64: 3817 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(S, S) 3818 : TARGET_LONG_BITS == 32 ? C_O0_I3(S, S, S) 3819 : C_O0_I4(S, S, S, S)); 3820 3821 case INDEX_op_add_vec: 3822 case INDEX_op_sub_vec: 3823 case INDEX_op_mul_vec: 3824 case INDEX_op_and_vec: 3825 case INDEX_op_or_vec: 3826 case INDEX_op_xor_vec: 3827 case INDEX_op_andc_vec: 3828 case INDEX_op_orc_vec: 3829 case INDEX_op_nor_vec: 3830 case INDEX_op_eqv_vec: 3831 case INDEX_op_nand_vec: 3832 case INDEX_op_cmp_vec: 3833 case INDEX_op_ssadd_vec: 3834 case INDEX_op_sssub_vec: 3835 case INDEX_op_usadd_vec: 3836 case INDEX_op_ussub_vec: 3837 case INDEX_op_smax_vec: 3838 case INDEX_op_smin_vec: 3839 case INDEX_op_umax_vec: 3840 case INDEX_op_umin_vec: 3841 case INDEX_op_shlv_vec: 3842 case INDEX_op_shrv_vec: 3843 case INDEX_op_sarv_vec: 3844 case INDEX_op_rotlv_vec: 3845 case INDEX_op_rotrv_vec: 3846 case INDEX_op_ppc_mrgh_vec: 3847 case INDEX_op_ppc_mrgl_vec: 3848 case INDEX_op_ppc_muleu_vec: 3849 case INDEX_op_ppc_mulou_vec: 3850 case INDEX_op_ppc_pkum_vec: 3851 case INDEX_op_dup2_vec: 3852 return C_O1_I2(v, v, v); 3853 3854 case INDEX_op_not_vec: 3855 case INDEX_op_neg_vec: 3856 return C_O1_I1(v, v); 3857 3858 case INDEX_op_dup_vec: 3859 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); 3860 3861 case INDEX_op_ld_vec: 3862 case INDEX_op_dupm_vec: 3863 return C_O1_I1(v, r); 3864 3865 case INDEX_op_st_vec: 3866 return C_O0_I2(v, r); 3867 3868 case INDEX_op_bitsel_vec: 3869 case INDEX_op_ppc_msum_vec: 3870 return C_O1_I3(v, v, v, v); 3871 3872 default: 3873 g_assert_not_reached(); 3874 } 3875} 3876 3877static void tcg_target_init(TCGContext *s) 3878{ 3879 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 3880 unsigned long hwcap2 = qemu_getauxval(AT_HWCAP2); 3881 3882 have_isa = tcg_isa_base; 3883 if (hwcap & PPC_FEATURE_ARCH_2_06) { 3884 have_isa = tcg_isa_2_06; 3885 } 3886#ifdef PPC_FEATURE2_ARCH_2_07 3887 if (hwcap2 & PPC_FEATURE2_ARCH_2_07) { 3888 have_isa = tcg_isa_2_07; 3889 } 3890#endif 3891#ifdef PPC_FEATURE2_ARCH_3_00 3892 if (hwcap2 & PPC_FEATURE2_ARCH_3_00) { 3893 have_isa = tcg_isa_3_00; 3894 } 3895#endif 3896#ifdef PPC_FEATURE2_ARCH_3_10 3897 if (hwcap2 & PPC_FEATURE2_ARCH_3_10) { 3898 have_isa = tcg_isa_3_10; 3899 } 3900#endif 3901 3902#ifdef PPC_FEATURE2_HAS_ISEL 3903 /* Prefer explicit instruction from the kernel. */ 3904 have_isel = (hwcap2 & PPC_FEATURE2_HAS_ISEL) != 0; 3905#else 3906 /* Fall back to knowing Power7 (2.06) has ISEL. */ 3907 have_isel = have_isa_2_06; 3908#endif 3909 3910 if (hwcap & PPC_FEATURE_HAS_ALTIVEC) { 3911 have_altivec = true; 3912 /* We only care about the portion of VSX that overlaps Altivec. */ 3913 if (hwcap & PPC_FEATURE_HAS_VSX) { 3914 have_vsx = true; 3915 } 3916 } 3917 3918 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 3919 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 3920 if (have_altivec) { 3921 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3922 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3923 } 3924 3925 tcg_target_call_clobber_regs = 0; 3926 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3927 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3928 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3929 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3930 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3931 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3932 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); 3933 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 3934 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 3935 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 3936 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 3937 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 3938 3939 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3940 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3941 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3942 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3943 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3944 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3945 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3946 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3947 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); 3948 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); 3949 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); 3950 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); 3951 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); 3952 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); 3953 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); 3954 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); 3955 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3956 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3957 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3958 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3959 3960 s->reserved_regs = 0; 3961 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ 3962 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ 3963#if defined(_CALL_SYSV) 3964 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ 3965#endif 3966#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 3967 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ 3968#endif 3969 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); /* mem temp */ 3970 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); 3971 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); 3972 if (USE_REG_TB) { 3973 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ 3974 } 3975} 3976 3977#ifdef __ELF__ 3978typedef struct { 3979 DebugFrameCIE cie; 3980 DebugFrameFDEHeader fde; 3981 uint8_t fde_def_cfa[4]; 3982 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; 3983} DebugFrame; 3984 3985/* We're expecting a 2 byte uleb128 encoded value. */ 3986QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 3987 3988#if TCG_TARGET_REG_BITS == 64 3989# define ELF_HOST_MACHINE EM_PPC64 3990#else 3991# define ELF_HOST_MACHINE EM_PPC 3992#endif 3993 3994static DebugFrame debug_frame = { 3995 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 3996 .cie.id = -1, 3997 .cie.version = 1, 3998 .cie.code_align = 1, 3999 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ 4000 .cie.return_column = 65, 4001 4002 /* Total FDE size does not include the "len" member. */ 4003 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), 4004 4005 .fde_def_cfa = { 4006 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ 4007 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4008 (FRAME_SIZE >> 7) 4009 }, 4010 .fde_reg_ofs = { 4011 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ 4012 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, 4013 } 4014}; 4015 4016void tcg_register_jit(const void *buf, size_t buf_size) 4017{ 4018 uint8_t *p = &debug_frame.fde_reg_ofs[3]; 4019 int i; 4020 4021 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { 4022 p[0] = 0x80 + tcg_target_callee_save_regs[i]; 4023 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; 4024 } 4025 4026 debug_frame.fde.func_start = (uintptr_t)buf; 4027 debug_frame.fde.func_len = buf_size; 4028 4029 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4030} 4031#endif /* __ELF__ */ 4032#undef VMULEUB 4033#undef VMULEUH 4034#undef VMULEUW 4035#undef VMULOUB 4036#undef VMULOUH 4037#undef VMULOUW 4038#undef VMSUMUHM 4039