1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25#include "elf.h" 26#include "../tcg-pool.c.inc" 27#include "../tcg-ldst.c.inc" 28 29/* 30 * Standardize on the _CALL_FOO symbols used by GCC: 31 * Apple XCode does not define _CALL_DARWIN. 32 * Clang defines _CALL_ELF (64-bit) but not _CALL_SYSV or _CALL_AIX. 33 */ 34#if TCG_TARGET_REG_BITS == 64 35# ifdef _CALL_AIX 36 /* ok */ 37# elif defined(_CALL_ELF) && _CALL_ELF == 1 38# define _CALL_AIX 39# elif defined(_CALL_ELF) && _CALL_ELF == 2 40 /* ok */ 41# else 42# error "Unknown ABI" 43# endif 44#else 45# if defined(_CALL_SYSV) || defined(_CALL_DARWIN) 46 /* ok */ 47# elif defined(__APPLE__) 48# define _CALL_DARWIN 49# elif defined(__ELF__) 50# define _CALL_SYSV 51# else 52# error "Unknown ABI" 53# endif 54#endif 55 56#if TCG_TARGET_REG_BITS == 64 57# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_EXTEND 58# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 59#else 60# define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 61# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 62#endif 63#ifdef _CALL_SYSV 64# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 65# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_BY_REF 66#else 67# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 68# define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 69#endif 70 71/* For some memory operations, we need a scratch that isn't R0. For the AIX 72 calling convention, we can re-use the TOC register since we'll be reloading 73 it at every call. Otherwise R12 will do nicely as neither a call-saved 74 register nor a parameter register. */ 75#ifdef _CALL_AIX 76# define TCG_REG_TMP1 TCG_REG_R2 77#else 78# define TCG_REG_TMP1 TCG_REG_R12 79#endif 80#define TCG_REG_TMP2 TCG_REG_R11 81 82#define TCG_VEC_TMP1 TCG_REG_V0 83#define TCG_VEC_TMP2 TCG_REG_V1 84 85#define TCG_REG_TB TCG_REG_R31 86#define USE_REG_TB (TCG_TARGET_REG_BITS == 64) 87 88/* Shorthand for size of a pointer. Avoid promotion to unsigned. */ 89#define SZP ((int)sizeof(void *)) 90 91/* Shorthand for size of a register. */ 92#define SZR (TCG_TARGET_REG_BITS / 8) 93 94#define TCG_CT_CONST_S16 0x100 95#define TCG_CT_CONST_S32 0x400 96#define TCG_CT_CONST_U32 0x800 97#define TCG_CT_CONST_ZERO 0x1000 98#define TCG_CT_CONST_MONE 0x2000 99#define TCG_CT_CONST_WSZ 0x4000 100 101#define ALL_GENERAL_REGS 0xffffffffu 102#define ALL_VECTOR_REGS 0xffffffff00000000ull 103 104#define have_isel (cpuinfo & CPUINFO_ISEL) 105 106#ifndef CONFIG_SOFTMMU 107#define TCG_GUEST_BASE_REG 30 108#endif 109 110#ifdef CONFIG_DEBUG_TCG 111static const char tcg_target_reg_names[TCG_TARGET_NB_REGS][4] = { 112 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 113 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 114 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 115 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 116 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 117 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 118 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 119 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 120}; 121#endif 122 123static const int tcg_target_reg_alloc_order[] = { 124 TCG_REG_R14, /* call saved registers */ 125 TCG_REG_R15, 126 TCG_REG_R16, 127 TCG_REG_R17, 128 TCG_REG_R18, 129 TCG_REG_R19, 130 TCG_REG_R20, 131 TCG_REG_R21, 132 TCG_REG_R22, 133 TCG_REG_R23, 134 TCG_REG_R24, 135 TCG_REG_R25, 136 TCG_REG_R26, 137 TCG_REG_R27, 138 TCG_REG_R28, 139 TCG_REG_R29, 140 TCG_REG_R30, 141 TCG_REG_R31, 142 TCG_REG_R12, /* call clobbered, non-arguments */ 143 TCG_REG_R11, 144 TCG_REG_R2, 145 TCG_REG_R13, 146 TCG_REG_R10, /* call clobbered, arguments */ 147 TCG_REG_R9, 148 TCG_REG_R8, 149 TCG_REG_R7, 150 TCG_REG_R6, 151 TCG_REG_R5, 152 TCG_REG_R4, 153 TCG_REG_R3, 154 155 /* V0 and V1 reserved as temporaries; V20 - V31 are call-saved */ 156 TCG_REG_V2, /* call clobbered, vectors */ 157 TCG_REG_V3, 158 TCG_REG_V4, 159 TCG_REG_V5, 160 TCG_REG_V6, 161 TCG_REG_V7, 162 TCG_REG_V8, 163 TCG_REG_V9, 164 TCG_REG_V10, 165 TCG_REG_V11, 166 TCG_REG_V12, 167 TCG_REG_V13, 168 TCG_REG_V14, 169 TCG_REG_V15, 170 TCG_REG_V16, 171 TCG_REG_V17, 172 TCG_REG_V18, 173 TCG_REG_V19, 174}; 175 176static const int tcg_target_call_iarg_regs[] = { 177 TCG_REG_R3, 178 TCG_REG_R4, 179 TCG_REG_R5, 180 TCG_REG_R6, 181 TCG_REG_R7, 182 TCG_REG_R8, 183 TCG_REG_R9, 184 TCG_REG_R10 185}; 186 187static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 188{ 189 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 190 tcg_debug_assert(slot >= 0 && slot <= 1); 191 return TCG_REG_R3 + slot; 192} 193 194static const int tcg_target_callee_save_regs[] = { 195#ifdef _CALL_DARWIN 196 TCG_REG_R11, 197#endif 198 TCG_REG_R14, 199 TCG_REG_R15, 200 TCG_REG_R16, 201 TCG_REG_R17, 202 TCG_REG_R18, 203 TCG_REG_R19, 204 TCG_REG_R20, 205 TCG_REG_R21, 206 TCG_REG_R22, 207 TCG_REG_R23, 208 TCG_REG_R24, 209 TCG_REG_R25, 210 TCG_REG_R26, 211 TCG_REG_R27, /* currently used for the global env */ 212 TCG_REG_R28, 213 TCG_REG_R29, 214 TCG_REG_R30, 215 TCG_REG_R31 216}; 217 218static inline bool in_range_b(tcg_target_long target) 219{ 220 return target == sextract64(target, 0, 26); 221} 222 223static uint32_t reloc_pc24_val(const tcg_insn_unit *pc, 224 const tcg_insn_unit *target) 225{ 226 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 227 tcg_debug_assert(in_range_b(disp)); 228 return disp & 0x3fffffc; 229} 230 231static bool reloc_pc24(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 232{ 233 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 234 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 235 236 if (in_range_b(disp)) { 237 *src_rw = (*src_rw & ~0x3fffffc) | (disp & 0x3fffffc); 238 return true; 239 } 240 return false; 241} 242 243static uint16_t reloc_pc14_val(const tcg_insn_unit *pc, 244 const tcg_insn_unit *target) 245{ 246 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc); 247 tcg_debug_assert(disp == (int16_t) disp); 248 return disp & 0xfffc; 249} 250 251static bool reloc_pc14(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 252{ 253 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 254 ptrdiff_t disp = tcg_ptr_byte_diff(target, src_rx); 255 256 if (disp == (int16_t) disp) { 257 *src_rw = (*src_rw & ~0xfffc) | (disp & 0xfffc); 258 return true; 259 } 260 return false; 261} 262 263/* test if a constant matches the constraint */ 264static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece) 265{ 266 if (ct & TCG_CT_CONST) { 267 return 1; 268 } 269 270 /* The only 32-bit constraint we use aside from 271 TCG_CT_CONST is TCG_CT_CONST_S16. */ 272 if (type == TCG_TYPE_I32) { 273 val = (int32_t)val; 274 } 275 276 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 277 return 1; 278 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 279 return 1; 280 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) { 281 return 1; 282 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 283 return 1; 284 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) { 285 return 1; 286 } else if ((ct & TCG_CT_CONST_WSZ) 287 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 288 return 1; 289 } 290 return 0; 291} 292 293#define OPCD(opc) ((opc)<<26) 294#define XO19(opc) (OPCD(19)|((opc)<<1)) 295#define MD30(opc) (OPCD(30)|((opc)<<2)) 296#define MDS30(opc) (OPCD(30)|((opc)<<1)) 297#define XO31(opc) (OPCD(31)|((opc)<<1)) 298#define XO58(opc) (OPCD(58)|(opc)) 299#define XO62(opc) (OPCD(62)|(opc)) 300#define VX4(opc) (OPCD(4)|(opc)) 301 302#define B OPCD( 18) 303#define BC OPCD( 16) 304 305#define LBZ OPCD( 34) 306#define LHZ OPCD( 40) 307#define LHA OPCD( 42) 308#define LWZ OPCD( 32) 309#define LWZUX XO31( 55) 310#define LD XO58( 0) 311#define LDX XO31( 21) 312#define LDU XO58( 1) 313#define LDUX XO31( 53) 314#define LWA XO58( 2) 315#define LWAX XO31(341) 316#define LQ OPCD( 56) 317 318#define STB OPCD( 38) 319#define STH OPCD( 44) 320#define STW OPCD( 36) 321#define STD XO62( 0) 322#define STDU XO62( 1) 323#define STDX XO31(149) 324#define STQ XO62( 2) 325 326#define ADDIC OPCD( 12) 327#define ADDI OPCD( 14) 328#define ADDIS OPCD( 15) 329#define ORI OPCD( 24) 330#define ORIS OPCD( 25) 331#define XORI OPCD( 26) 332#define XORIS OPCD( 27) 333#define ANDI OPCD( 28) 334#define ANDIS OPCD( 29) 335#define MULLI OPCD( 7) 336#define CMPLI OPCD( 10) 337#define CMPI OPCD( 11) 338#define SUBFIC OPCD( 8) 339 340#define LWZU OPCD( 33) 341#define STWU OPCD( 37) 342 343#define RLWIMI OPCD( 20) 344#define RLWINM OPCD( 21) 345#define RLWNM OPCD( 23) 346 347#define RLDICL MD30( 0) 348#define RLDICR MD30( 1) 349#define RLDIMI MD30( 3) 350#define RLDCL MDS30( 8) 351 352#define BCLR XO19( 16) 353#define BCCTR XO19(528) 354#define CRAND XO19(257) 355#define CRANDC XO19(129) 356#define CRNAND XO19(225) 357#define CROR XO19(449) 358#define CRNOR XO19( 33) 359 360#define EXTSB XO31(954) 361#define EXTSH XO31(922) 362#define EXTSW XO31(986) 363#define ADD XO31(266) 364#define ADDE XO31(138) 365#define ADDME XO31(234) 366#define ADDZE XO31(202) 367#define ADDC XO31( 10) 368#define AND XO31( 28) 369#define SUBF XO31( 40) 370#define SUBFC XO31( 8) 371#define SUBFE XO31(136) 372#define SUBFME XO31(232) 373#define SUBFZE XO31(200) 374#define OR XO31(444) 375#define XOR XO31(316) 376#define MULLW XO31(235) 377#define MULHW XO31( 75) 378#define MULHWU XO31( 11) 379#define DIVW XO31(491) 380#define DIVWU XO31(459) 381#define MODSW XO31(779) 382#define MODUW XO31(267) 383#define CMP XO31( 0) 384#define CMPL XO31( 32) 385#define LHBRX XO31(790) 386#define LWBRX XO31(534) 387#define LDBRX XO31(532) 388#define STHBRX XO31(918) 389#define STWBRX XO31(662) 390#define STDBRX XO31(660) 391#define MFSPR XO31(339) 392#define MTSPR XO31(467) 393#define SRAWI XO31(824) 394#define NEG XO31(104) 395#define MFCR XO31( 19) 396#define MFOCRF (MFCR | (1u << 20)) 397#define NOR XO31(124) 398#define CNTLZW XO31( 26) 399#define CNTLZD XO31( 58) 400#define CNTTZW XO31(538) 401#define CNTTZD XO31(570) 402#define CNTPOPW XO31(378) 403#define CNTPOPD XO31(506) 404#define ANDC XO31( 60) 405#define ORC XO31(412) 406#define EQV XO31(284) 407#define NAND XO31(476) 408#define ISEL XO31( 15) 409 410#define MULLD XO31(233) 411#define MULHD XO31( 73) 412#define MULHDU XO31( 9) 413#define DIVD XO31(489) 414#define DIVDU XO31(457) 415#define MODSD XO31(777) 416#define MODUD XO31(265) 417 418#define LBZX XO31( 87) 419#define LHZX XO31(279) 420#define LHAX XO31(343) 421#define LWZX XO31( 23) 422#define STBX XO31(215) 423#define STHX XO31(407) 424#define STWX XO31(151) 425 426#define EIEIO XO31(854) 427#define HWSYNC XO31(598) 428#define LWSYNC (HWSYNC | (1u << 21)) 429 430#define SPR(a, b) ((((a)<<5)|(b))<<11) 431#define LR SPR(8, 0) 432#define CTR SPR(9, 0) 433 434#define SLW XO31( 24) 435#define SRW XO31(536) 436#define SRAW XO31(792) 437 438#define SLD XO31( 27) 439#define SRD XO31(539) 440#define SRAD XO31(794) 441#define SRADI XO31(413<<1) 442 443#define BRH XO31(219) 444#define BRW XO31(155) 445#define BRD XO31(187) 446 447#define TW XO31( 4) 448#define TRAP (TW | TO(31)) 449 450#define SETBC XO31(384) /* v3.10 */ 451#define SETBCR XO31(416) /* v3.10 */ 452#define SETNBC XO31(448) /* v3.10 */ 453#define SETNBCR XO31(480) /* v3.10 */ 454 455#define NOP ORI /* ori 0,0,0 */ 456 457#define LVX XO31(103) 458#define LVEBX XO31(7) 459#define LVEHX XO31(39) 460#define LVEWX XO31(71) 461#define LXSDX (XO31(588) | 1) /* v2.06, force tx=1 */ 462#define LXVDSX (XO31(332) | 1) /* v2.06, force tx=1 */ 463#define LXSIWZX (XO31(12) | 1) /* v2.07, force tx=1 */ 464#define LXV (OPCD(61) | 8 | 1) /* v3.00, force tx=1 */ 465#define LXSD (OPCD(57) | 2) /* v3.00 */ 466#define LXVWSX (XO31(364) | 1) /* v3.00, force tx=1 */ 467 468#define STVX XO31(231) 469#define STVEWX XO31(199) 470#define STXSDX (XO31(716) | 1) /* v2.06, force sx=1 */ 471#define STXSIWX (XO31(140) | 1) /* v2.07, force sx=1 */ 472#define STXV (OPCD(61) | 8 | 5) /* v3.00, force sx=1 */ 473#define STXSD (OPCD(61) | 2) /* v3.00 */ 474 475#define VADDSBS VX4(768) 476#define VADDUBS VX4(512) 477#define VADDUBM VX4(0) 478#define VADDSHS VX4(832) 479#define VADDUHS VX4(576) 480#define VADDUHM VX4(64) 481#define VADDSWS VX4(896) 482#define VADDUWS VX4(640) 483#define VADDUWM VX4(128) 484#define VADDUDM VX4(192) /* v2.07 */ 485 486#define VSUBSBS VX4(1792) 487#define VSUBUBS VX4(1536) 488#define VSUBUBM VX4(1024) 489#define VSUBSHS VX4(1856) 490#define VSUBUHS VX4(1600) 491#define VSUBUHM VX4(1088) 492#define VSUBSWS VX4(1920) 493#define VSUBUWS VX4(1664) 494#define VSUBUWM VX4(1152) 495#define VSUBUDM VX4(1216) /* v2.07 */ 496 497#define VNEGW (VX4(1538) | (6 << 16)) /* v3.00 */ 498#define VNEGD (VX4(1538) | (7 << 16)) /* v3.00 */ 499 500#define VMAXSB VX4(258) 501#define VMAXSH VX4(322) 502#define VMAXSW VX4(386) 503#define VMAXSD VX4(450) /* v2.07 */ 504#define VMAXUB VX4(2) 505#define VMAXUH VX4(66) 506#define VMAXUW VX4(130) 507#define VMAXUD VX4(194) /* v2.07 */ 508#define VMINSB VX4(770) 509#define VMINSH VX4(834) 510#define VMINSW VX4(898) 511#define VMINSD VX4(962) /* v2.07 */ 512#define VMINUB VX4(514) 513#define VMINUH VX4(578) 514#define VMINUW VX4(642) 515#define VMINUD VX4(706) /* v2.07 */ 516 517#define VCMPEQUB VX4(6) 518#define VCMPEQUH VX4(70) 519#define VCMPEQUW VX4(134) 520#define VCMPEQUD VX4(199) /* v2.07 */ 521#define VCMPGTSB VX4(774) 522#define VCMPGTSH VX4(838) 523#define VCMPGTSW VX4(902) 524#define VCMPGTSD VX4(967) /* v2.07 */ 525#define VCMPGTUB VX4(518) 526#define VCMPGTUH VX4(582) 527#define VCMPGTUW VX4(646) 528#define VCMPGTUD VX4(711) /* v2.07 */ 529#define VCMPNEB VX4(7) /* v3.00 */ 530#define VCMPNEH VX4(71) /* v3.00 */ 531#define VCMPNEW VX4(135) /* v3.00 */ 532 533#define VSLB VX4(260) 534#define VSLH VX4(324) 535#define VSLW VX4(388) 536#define VSLD VX4(1476) /* v2.07 */ 537#define VSRB VX4(516) 538#define VSRH VX4(580) 539#define VSRW VX4(644) 540#define VSRD VX4(1732) /* v2.07 */ 541#define VSRAB VX4(772) 542#define VSRAH VX4(836) 543#define VSRAW VX4(900) 544#define VSRAD VX4(964) /* v2.07 */ 545#define VRLB VX4(4) 546#define VRLH VX4(68) 547#define VRLW VX4(132) 548#define VRLD VX4(196) /* v2.07 */ 549 550#define VMULEUB VX4(520) 551#define VMULEUH VX4(584) 552#define VMULEUW VX4(648) /* v2.07 */ 553#define VMULOUB VX4(8) 554#define VMULOUH VX4(72) 555#define VMULOUW VX4(136) /* v2.07 */ 556#define VMULUWM VX4(137) /* v2.07 */ 557#define VMULLD VX4(457) /* v3.10 */ 558#define VMSUMUHM VX4(38) 559 560#define VMRGHB VX4(12) 561#define VMRGHH VX4(76) 562#define VMRGHW VX4(140) 563#define VMRGLB VX4(268) 564#define VMRGLH VX4(332) 565#define VMRGLW VX4(396) 566 567#define VPKUHUM VX4(14) 568#define VPKUWUM VX4(78) 569 570#define VAND VX4(1028) 571#define VANDC VX4(1092) 572#define VNOR VX4(1284) 573#define VOR VX4(1156) 574#define VXOR VX4(1220) 575#define VEQV VX4(1668) /* v2.07 */ 576#define VNAND VX4(1412) /* v2.07 */ 577#define VORC VX4(1348) /* v2.07 */ 578 579#define VSPLTB VX4(524) 580#define VSPLTH VX4(588) 581#define VSPLTW VX4(652) 582#define VSPLTISB VX4(780) 583#define VSPLTISH VX4(844) 584#define VSPLTISW VX4(908) 585 586#define VSLDOI VX4(44) 587 588#define XXPERMDI (OPCD(60) | (10 << 3) | 7) /* v2.06, force ax=bx=tx=1 */ 589#define XXSEL (OPCD(60) | (3 << 4) | 0xf) /* v2.06, force ax=bx=cx=tx=1 */ 590#define XXSPLTIB (OPCD(60) | (360 << 1) | 1) /* v3.00, force tx=1 */ 591 592#define MFVSRD (XO31(51) | 1) /* v2.07, force sx=1 */ 593#define MFVSRWZ (XO31(115) | 1) /* v2.07, force sx=1 */ 594#define MTVSRD (XO31(179) | 1) /* v2.07, force tx=1 */ 595#define MTVSRWZ (XO31(243) | 1) /* v2.07, force tx=1 */ 596#define MTVSRDD (XO31(435) | 1) /* v3.00, force tx=1 */ 597#define MTVSRWS (XO31(403) | 1) /* v3.00, force tx=1 */ 598 599#define RT(r) ((r)<<21) 600#define RS(r) ((r)<<21) 601#define RA(r) ((r)<<16) 602#define RB(r) ((r)<<11) 603#define TO(t) ((t)<<21) 604#define SH(s) ((s)<<11) 605#define MB(b) ((b)<<6) 606#define ME(e) ((e)<<1) 607#define BO(o) ((o)<<21) 608#define MB64(b) ((b)<<5) 609#define FXM(b) (1 << (19 - (b))) 610 611#define VRT(r) (((r) & 31) << 21) 612#define VRA(r) (((r) & 31) << 16) 613#define VRB(r) (((r) & 31) << 11) 614#define VRC(r) (((r) & 31) << 6) 615 616#define LK 1 617 618#define TAB(t, a, b) (RT(t) | RA(a) | RB(b)) 619#define SAB(s, a, b) (RS(s) | RA(a) | RB(b)) 620#define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff)) 621#define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff)) 622 623#define BF(n) ((n)<<23) 624#define BI(n, c) (((c)+((n)*4))<<16) 625#define BT(n, c) (((c)+((n)*4))<<21) 626#define BA(n, c) (((c)+((n)*4))<<16) 627#define BB(n, c) (((c)+((n)*4))<<11) 628#define BC_(n, c) (((c)+((n)*4))<<6) 629 630#define BO_COND_TRUE BO(12) 631#define BO_COND_FALSE BO( 4) 632#define BO_ALWAYS BO(20) 633 634enum { 635 CR_LT, 636 CR_GT, 637 CR_EQ, 638 CR_SO 639}; 640 641static const uint32_t tcg_to_bc[] = { 642 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE, 643 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE, 644 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE, 645 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE, 646 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE, 647 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE, 648 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE, 649 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE, 650 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE, 651 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE, 652}; 653 654/* The low bit here is set if the RA and RB fields must be inverted. */ 655static const uint32_t tcg_to_isel[] = { 656 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ), 657 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1, 658 [TCG_COND_LT] = ISEL | BC_(7, CR_LT), 659 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1, 660 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1, 661 [TCG_COND_GT] = ISEL | BC_(7, CR_GT), 662 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT), 663 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1, 664 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1, 665 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT), 666}; 667 668static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 669 intptr_t value, intptr_t addend) 670{ 671 const tcg_insn_unit *target; 672 int16_t lo; 673 int32_t hi; 674 675 value += addend; 676 target = (const tcg_insn_unit *)value; 677 678 switch (type) { 679 case R_PPC_REL14: 680 return reloc_pc14(code_ptr, target); 681 case R_PPC_REL24: 682 return reloc_pc24(code_ptr, target); 683 case R_PPC_ADDR16: 684 /* 685 * We are (slightly) abusing this relocation type. In particular, 686 * assert that the low 2 bits are zero, and do not modify them. 687 * That way we can use this with LD et al that have opcode bits 688 * in the low 2 bits of the insn. 689 */ 690 if ((value & 3) || value != (int16_t)value) { 691 return false; 692 } 693 *code_ptr = (*code_ptr & ~0xfffc) | (value & 0xfffc); 694 break; 695 case R_PPC_ADDR32: 696 /* 697 * We are abusing this relocation type. Again, this points to 698 * a pair of insns, lis + load. This is an absolute address 699 * relocation for PPC32 so the lis cannot be removed. 700 */ 701 lo = value; 702 hi = value - lo; 703 if (hi + lo != value) { 704 return false; 705 } 706 code_ptr[0] = deposit32(code_ptr[0], 0, 16, hi >> 16); 707 code_ptr[1] = deposit32(code_ptr[1], 0, 16, lo); 708 break; 709 default: 710 g_assert_not_reached(); 711 } 712 return true; 713} 714 715static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 716 TCGReg base, tcg_target_long offset); 717 718static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 719{ 720 if (ret == arg) { 721 return true; 722 } 723 switch (type) { 724 case TCG_TYPE_I64: 725 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 726 /* fallthru */ 727 case TCG_TYPE_I32: 728 if (ret < TCG_REG_V0) { 729 if (arg < TCG_REG_V0) { 730 tcg_out32(s, OR | SAB(arg, ret, arg)); 731 break; 732 } else if (have_isa_2_07) { 733 tcg_out32(s, (type == TCG_TYPE_I32 ? MFVSRWZ : MFVSRD) 734 | VRT(arg) | RA(ret)); 735 break; 736 } else { 737 /* Altivec does not support vector->integer moves. */ 738 return false; 739 } 740 } else if (arg < TCG_REG_V0) { 741 if (have_isa_2_07) { 742 tcg_out32(s, (type == TCG_TYPE_I32 ? MTVSRWZ : MTVSRD) 743 | VRT(ret) | RA(arg)); 744 break; 745 } else { 746 /* Altivec does not support integer->vector moves. */ 747 return false; 748 } 749 } 750 /* fallthru */ 751 case TCG_TYPE_V64: 752 case TCG_TYPE_V128: 753 tcg_debug_assert(ret >= TCG_REG_V0 && arg >= TCG_REG_V0); 754 tcg_out32(s, VOR | VRT(ret) | VRA(arg) | VRB(arg)); 755 break; 756 default: 757 g_assert_not_reached(); 758 } 759 return true; 760} 761 762static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs, 763 int sh, int mb) 764{ 765 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 766 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1); 767 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f)); 768 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb); 769} 770 771static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs, 772 int sh, int mb, int me) 773{ 774 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me)); 775} 776 777static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 778{ 779 tcg_out32(s, EXTSB | RA(dst) | RS(src)); 780} 781 782static void tcg_out_ext8u(TCGContext *s, TCGReg dst, TCGReg src) 783{ 784 tcg_out32(s, ANDI | SAI(src, dst, 0xff)); 785} 786 787static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg dst, TCGReg src) 788{ 789 tcg_out32(s, EXTSH | RA(dst) | RS(src)); 790} 791 792static void tcg_out_ext16u(TCGContext *s, TCGReg dst, TCGReg src) 793{ 794 tcg_out32(s, ANDI | SAI(src, dst, 0xffff)); 795} 796 797static void tcg_out_ext32s(TCGContext *s, TCGReg dst, TCGReg src) 798{ 799 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 800 tcg_out32(s, EXTSW | RA(dst) | RS(src)); 801} 802 803static void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src) 804{ 805 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 806 tcg_out_rld(s, RLDICL, dst, src, 0, 32); 807} 808 809static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 810{ 811 tcg_out_ext32s(s, dst, src); 812} 813 814static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg dst, TCGReg src) 815{ 816 tcg_out_ext32u(s, dst, src); 817} 818 819static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rn) 820{ 821 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 822 tcg_out_mov(s, TCG_TYPE_I32, rd, rn); 823} 824 825static inline void tcg_out_shli32(TCGContext *s, TCGReg dst, TCGReg src, int c) 826{ 827 tcg_out_rlw(s, RLWINM, dst, src, c, 0, 31 - c); 828} 829 830static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c) 831{ 832 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c); 833} 834 835static inline void tcg_out_sari32(TCGContext *s, TCGReg dst, TCGReg src, int c) 836{ 837 /* Limit immediate shift count lest we create an illegal insn. */ 838 tcg_out32(s, SRAWI | RA(dst) | RS(src) | SH(c & 31)); 839} 840 841static inline void tcg_out_shri32(TCGContext *s, TCGReg dst, TCGReg src, int c) 842{ 843 tcg_out_rlw(s, RLWINM, dst, src, 32 - c, c, 31); 844} 845 846static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c) 847{ 848 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c); 849} 850 851static inline void tcg_out_sari64(TCGContext *s, TCGReg dst, TCGReg src, int c) 852{ 853 tcg_out32(s, SRADI | RA(dst) | RS(src) | SH(c & 0x1f) | ((c >> 4) & 2)); 854} 855 856static void tcg_out_bswap16(TCGContext *s, TCGReg dst, TCGReg src, int flags) 857{ 858 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 859 860 if (have_isa_3_10) { 861 tcg_out32(s, BRH | RA(dst) | RS(src)); 862 if (flags & TCG_BSWAP_OS) { 863 tcg_out_ext16s(s, TCG_TYPE_REG, dst, dst); 864 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 865 tcg_out_ext16u(s, dst, dst); 866 } 867 return; 868 } 869 870 /* 871 * In the following, 872 * dep(a, b, m) -> (a & ~m) | (b & m) 873 * 874 * Begin with: src = xxxxabcd 875 */ 876 /* tmp = rol32(src, 24) & 0x000000ff = 0000000c */ 877 tcg_out_rlw(s, RLWINM, tmp, src, 24, 24, 31); 878 /* tmp = dep(tmp, rol32(src, 8), 0x0000ff00) = 000000dc */ 879 tcg_out_rlw(s, RLWIMI, tmp, src, 8, 16, 23); 880 881 if (flags & TCG_BSWAP_OS) { 882 tcg_out_ext16s(s, TCG_TYPE_REG, dst, tmp); 883 } else { 884 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 885 } 886} 887 888static void tcg_out_bswap32(TCGContext *s, TCGReg dst, TCGReg src, int flags) 889{ 890 TCGReg tmp = dst == src ? TCG_REG_R0 : dst; 891 892 if (have_isa_3_10) { 893 tcg_out32(s, BRW | RA(dst) | RS(src)); 894 if (flags & TCG_BSWAP_OS) { 895 tcg_out_ext32s(s, dst, dst); 896 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 897 tcg_out_ext32u(s, dst, dst); 898 } 899 return; 900 } 901 902 /* 903 * Stolen from gcc's builtin_bswap32. 904 * In the following, 905 * dep(a, b, m) -> (a & ~m) | (b & m) 906 * 907 * Begin with: src = xxxxabcd 908 */ 909 /* tmp = rol32(src, 8) & 0xffffffff = 0000bcda */ 910 tcg_out_rlw(s, RLWINM, tmp, src, 8, 0, 31); 911 /* tmp = dep(tmp, rol32(src, 24), 0xff000000) = 0000dcda */ 912 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 0, 7); 913 /* tmp = dep(tmp, rol32(src, 24), 0x0000ff00) = 0000dcba */ 914 tcg_out_rlw(s, RLWIMI, tmp, src, 24, 16, 23); 915 916 if (flags & TCG_BSWAP_OS) { 917 tcg_out_ext32s(s, dst, tmp); 918 } else { 919 tcg_out_mov(s, TCG_TYPE_REG, dst, tmp); 920 } 921} 922 923static void tcg_out_bswap64(TCGContext *s, TCGReg dst, TCGReg src) 924{ 925 TCGReg t0 = dst == src ? TCG_REG_R0 : dst; 926 TCGReg t1 = dst == src ? dst : TCG_REG_R0; 927 928 if (have_isa_3_10) { 929 tcg_out32(s, BRD | RA(dst) | RS(src)); 930 return; 931 } 932 933 /* 934 * In the following, 935 * dep(a, b, m) -> (a & ~m) | (b & m) 936 * 937 * Begin with: src = abcdefgh 938 */ 939 /* t0 = rol32(src, 8) & 0xffffffff = 0000fghe */ 940 tcg_out_rlw(s, RLWINM, t0, src, 8, 0, 31); 941 /* t0 = dep(t0, rol32(src, 24), 0xff000000) = 0000hghe */ 942 tcg_out_rlw(s, RLWIMI, t0, src, 24, 0, 7); 943 /* t0 = dep(t0, rol32(src, 24), 0x0000ff00) = 0000hgfe */ 944 tcg_out_rlw(s, RLWIMI, t0, src, 24, 16, 23); 945 946 /* t0 = rol64(t0, 32) = hgfe0000 */ 947 tcg_out_rld(s, RLDICL, t0, t0, 32, 0); 948 /* t1 = rol64(src, 32) = efghabcd */ 949 tcg_out_rld(s, RLDICL, t1, src, 32, 0); 950 951 /* t0 = dep(t0, rol32(t1, 24), 0xffffffff) = hgfebcda */ 952 tcg_out_rlw(s, RLWIMI, t0, t1, 8, 0, 31); 953 /* t0 = dep(t0, rol32(t1, 24), 0xff000000) = hgfedcda */ 954 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 0, 7); 955 /* t0 = dep(t0, rol32(t1, 24), 0x0000ff00) = hgfedcba */ 956 tcg_out_rlw(s, RLWIMI, t0, t1, 24, 16, 23); 957 958 tcg_out_mov(s, TCG_TYPE_REG, dst, t0); 959} 960 961/* Emit a move into ret of arg, if it can be done in one insn. */ 962static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 963{ 964 if (arg == (int16_t)arg) { 965 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 966 return true; 967 } 968 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 969 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 970 return true; 971 } 972 return false; 973} 974 975static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 976 tcg_target_long arg, bool in_prologue) 977{ 978 intptr_t tb_diff; 979 tcg_target_long tmp; 980 int shift; 981 982 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 983 984 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 985 arg = (int32_t)arg; 986 } 987 988 /* Load 16-bit immediates with one insn. */ 989 if (tcg_out_movi_one(s, ret, arg)) { 990 return; 991 } 992 993 /* Load addresses within the TB with one insn. */ 994 tb_diff = tcg_tbrel_diff(s, (void *)arg); 995 if (!in_prologue && USE_REG_TB && tb_diff == (int16_t)tb_diff) { 996 tcg_out32(s, ADDI | TAI(ret, TCG_REG_TB, tb_diff)); 997 return; 998 } 999 1000 /* Load 32-bit immediates with two insns. Note that we've already 1001 eliminated bare ADDIS, so we know both insns are required. */ 1002 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 1003 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16)); 1004 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1005 return; 1006 } 1007 if (arg == (uint32_t)arg && !(arg & 0x8000)) { 1008 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1009 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1010 return; 1011 } 1012 1013 /* Load masked 16-bit value. */ 1014 if (arg > 0 && (arg & 0x8000)) { 1015 tmp = arg | 0x7fff; 1016 if ((tmp & (tmp + 1)) == 0) { 1017 int mb = clz64(tmp + 1) + 1; 1018 tcg_out32(s, ADDI | TAI(ret, 0, arg)); 1019 tcg_out_rld(s, RLDICL, ret, ret, 0, mb); 1020 return; 1021 } 1022 } 1023 1024 /* Load common masks with 2 insns. */ 1025 shift = ctz64(arg); 1026 tmp = arg >> shift; 1027 if (tmp == (int16_t)tmp) { 1028 tcg_out32(s, ADDI | TAI(ret, 0, tmp)); 1029 tcg_out_shli64(s, ret, ret, shift); 1030 return; 1031 } 1032 shift = clz64(arg); 1033 if (tcg_out_movi_one(s, ret, arg << shift)) { 1034 tcg_out_shri64(s, ret, ret, shift); 1035 return; 1036 } 1037 1038 /* Load addresses within 2GB of TB with 2 (or rarely 3) insns. */ 1039 if (!in_prologue && USE_REG_TB && tb_diff == (int32_t)tb_diff) { 1040 tcg_out_mem_long(s, ADDI, ADD, ret, TCG_REG_TB, tb_diff); 1041 return; 1042 } 1043 1044 /* Use the constant pool, if possible. */ 1045 if (!in_prologue && USE_REG_TB) { 1046 new_pool_label(s, arg, R_PPC_ADDR16, s->code_ptr, 1047 tcg_tbrel_diff(s, NULL)); 1048 tcg_out32(s, LD | TAI(ret, TCG_REG_TB, 0)); 1049 return; 1050 } 1051 1052 tmp = arg >> 31 >> 1; 1053 tcg_out_movi(s, TCG_TYPE_I32, ret, tmp); 1054 if (tmp) { 1055 tcg_out_shli64(s, ret, ret, 32); 1056 } 1057 if (arg & 0xffff0000) { 1058 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16)); 1059 } 1060 if (arg & 0xffff) { 1061 tcg_out32(s, ORI | SAI(ret, ret, arg)); 1062 } 1063} 1064 1065static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1066 TCGReg ret, int64_t val) 1067{ 1068 uint32_t load_insn; 1069 int rel, low; 1070 intptr_t add; 1071 1072 switch (vece) { 1073 case MO_8: 1074 low = (int8_t)val; 1075 if (low >= -16 && low < 16) { 1076 tcg_out32(s, VSPLTISB | VRT(ret) | ((val & 31) << 16)); 1077 return; 1078 } 1079 if (have_isa_3_00) { 1080 tcg_out32(s, XXSPLTIB | VRT(ret) | ((val & 0xff) << 11)); 1081 return; 1082 } 1083 break; 1084 1085 case MO_16: 1086 low = (int16_t)val; 1087 if (low >= -16 && low < 16) { 1088 tcg_out32(s, VSPLTISH | VRT(ret) | ((val & 31) << 16)); 1089 return; 1090 } 1091 break; 1092 1093 case MO_32: 1094 low = (int32_t)val; 1095 if (low >= -16 && low < 16) { 1096 tcg_out32(s, VSPLTISW | VRT(ret) | ((val & 31) << 16)); 1097 return; 1098 } 1099 break; 1100 } 1101 1102 /* 1103 * Otherwise we must load the value from the constant pool. 1104 */ 1105 if (USE_REG_TB) { 1106 rel = R_PPC_ADDR16; 1107 add = tcg_tbrel_diff(s, NULL); 1108 } else { 1109 rel = R_PPC_ADDR32; 1110 add = 0; 1111 } 1112 1113 if (have_vsx) { 1114 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX; 1115 load_insn |= VRT(ret) | RB(TCG_REG_TMP1); 1116 if (TCG_TARGET_REG_BITS == 64) { 1117 new_pool_label(s, val, rel, s->code_ptr, add); 1118 } else { 1119 new_pool_l2(s, rel, s->code_ptr, add, val >> 32, val); 1120 } 1121 } else { 1122 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1); 1123 if (TCG_TARGET_REG_BITS == 64) { 1124 new_pool_l2(s, rel, s->code_ptr, add, val, val); 1125 } else { 1126 new_pool_l4(s, rel, s->code_ptr, add, 1127 val >> 32, val, val >> 32, val); 1128 } 1129 } 1130 1131 if (USE_REG_TB) { 1132 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, 0, 0)); 1133 load_insn |= RA(TCG_REG_TB); 1134 } else { 1135 tcg_out32(s, ADDIS | TAI(TCG_REG_TMP1, 0, 0)); 1136 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, TCG_REG_TMP1, 0)); 1137 } 1138 tcg_out32(s, load_insn); 1139} 1140 1141static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret, 1142 tcg_target_long arg) 1143{ 1144 switch (type) { 1145 case TCG_TYPE_I32: 1146 case TCG_TYPE_I64: 1147 tcg_debug_assert(ret < TCG_REG_V0); 1148 tcg_out_movi_int(s, type, ret, arg, false); 1149 break; 1150 1151 default: 1152 g_assert_not_reached(); 1153 } 1154} 1155 1156static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 1157{ 1158 return false; 1159} 1160 1161static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 1162 tcg_target_long imm) 1163{ 1164 /* This function is only used for passing structs by reference. */ 1165 g_assert_not_reached(); 1166} 1167 1168static bool mask_operand(uint32_t c, int *mb, int *me) 1169{ 1170 uint32_t lsb, test; 1171 1172 /* Accept a bit pattern like: 1173 0....01....1 1174 1....10....0 1175 0..01..10..0 1176 Keep track of the transitions. */ 1177 if (c == 0 || c == -1) { 1178 return false; 1179 } 1180 test = c; 1181 lsb = test & -test; 1182 test += lsb; 1183 if (test & (test - 1)) { 1184 return false; 1185 } 1186 1187 *me = clz32(lsb); 1188 *mb = test ? clz32(test & -test) + 1 : 0; 1189 return true; 1190} 1191 1192static bool mask64_operand(uint64_t c, int *mb, int *me) 1193{ 1194 uint64_t lsb; 1195 1196 if (c == 0) { 1197 return false; 1198 } 1199 1200 lsb = c & -c; 1201 /* Accept 1..10..0. */ 1202 if (c == -lsb) { 1203 *mb = 0; 1204 *me = clz64(lsb); 1205 return true; 1206 } 1207 /* Accept 0..01..1. */ 1208 if (lsb == 1 && (c & (c + 1)) == 0) { 1209 *mb = clz64(c + 1) + 1; 1210 *me = 63; 1211 return true; 1212 } 1213 return false; 1214} 1215 1216static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1217{ 1218 int mb, me; 1219 1220 if (mask_operand(c, &mb, &me)) { 1221 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me); 1222 } else if ((c & 0xffff) == c) { 1223 tcg_out32(s, ANDI | SAI(src, dst, c)); 1224 return; 1225 } else if ((c & 0xffff0000) == c) { 1226 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1227 return; 1228 } else { 1229 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c); 1230 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1231 } 1232} 1233 1234static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c) 1235{ 1236 int mb, me; 1237 1238 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1239 if (mask64_operand(c, &mb, &me)) { 1240 if (mb == 0) { 1241 tcg_out_rld(s, RLDICR, dst, src, 0, me); 1242 } else { 1243 tcg_out_rld(s, RLDICL, dst, src, 0, mb); 1244 } 1245 } else if ((c & 0xffff) == c) { 1246 tcg_out32(s, ANDI | SAI(src, dst, c)); 1247 return; 1248 } else if ((c & 0xffff0000) == c) { 1249 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16)); 1250 return; 1251 } else { 1252 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c); 1253 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0)); 1254 } 1255} 1256 1257static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c, 1258 int op_lo, int op_hi) 1259{ 1260 if (c >> 16) { 1261 tcg_out32(s, op_hi | SAI(src, dst, c >> 16)); 1262 src = dst; 1263 } 1264 if (c & 0xffff) { 1265 tcg_out32(s, op_lo | SAI(src, dst, c)); 1266 src = dst; 1267 } 1268} 1269 1270static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1271{ 1272 tcg_out_zori32(s, dst, src, c, ORI, ORIS); 1273} 1274 1275static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c) 1276{ 1277 tcg_out_zori32(s, dst, src, c, XORI, XORIS); 1278} 1279 1280static void tcg_out_b(TCGContext *s, int mask, const tcg_insn_unit *target) 1281{ 1282 ptrdiff_t disp = tcg_pcrel_diff(s, target); 1283 if (in_range_b(disp)) { 1284 tcg_out32(s, B | (disp & 0x3fffffc) | mask); 1285 } else { 1286 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target); 1287 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR); 1288 tcg_out32(s, BCCTR | BO_ALWAYS | mask); 1289 } 1290} 1291 1292static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt, 1293 TCGReg base, tcg_target_long offset) 1294{ 1295 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0; 1296 bool is_int_store = false; 1297 TCGReg rs = TCG_REG_TMP1; 1298 1299 switch (opi) { 1300 case LD: case LWA: 1301 align = 3; 1302 /* FALLTHRU */ 1303 default: 1304 if (rt > TCG_REG_R0 && rt < TCG_REG_V0) { 1305 rs = rt; 1306 break; 1307 } 1308 break; 1309 case LXSD: 1310 case STXSD: 1311 align = 3; 1312 break; 1313 case LXV: 1314 case STXV: 1315 align = 15; 1316 break; 1317 case STD: 1318 align = 3; 1319 /* FALLTHRU */ 1320 case STB: case STH: case STW: 1321 is_int_store = true; 1322 break; 1323 } 1324 1325 /* For unaligned, or very large offsets, use the indexed form. */ 1326 if (offset & align || offset != (int32_t)offset || opi == 0) { 1327 if (rs == base) { 1328 rs = TCG_REG_R0; 1329 } 1330 tcg_debug_assert(!is_int_store || rs != rt); 1331 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig); 1332 tcg_out32(s, opx | TAB(rt & 31, base, rs)); 1333 return; 1334 } 1335 1336 l0 = (int16_t)offset; 1337 offset = (offset - l0) >> 16; 1338 l1 = (int16_t)offset; 1339 1340 if (l1 < 0 && orig >= 0) { 1341 extra = 0x4000; 1342 l1 = (int16_t)(offset - 0x4000); 1343 } 1344 if (l1) { 1345 tcg_out32(s, ADDIS | TAI(rs, base, l1)); 1346 base = rs; 1347 } 1348 if (extra) { 1349 tcg_out32(s, ADDIS | TAI(rs, base, extra)); 1350 base = rs; 1351 } 1352 if (opi != ADDI || base != rt || l0 != 0) { 1353 tcg_out32(s, opi | TAI(rt & 31, base, l0)); 1354 } 1355} 1356 1357static void tcg_out_vsldoi(TCGContext *s, TCGReg ret, 1358 TCGReg va, TCGReg vb, int shb) 1359{ 1360 tcg_out32(s, VSLDOI | VRT(ret) | VRA(va) | VRB(vb) | (shb << 6)); 1361} 1362 1363static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, 1364 TCGReg base, intptr_t offset) 1365{ 1366 int shift; 1367 1368 switch (type) { 1369 case TCG_TYPE_I32: 1370 if (ret < TCG_REG_V0) { 1371 tcg_out_mem_long(s, LWZ, LWZX, ret, base, offset); 1372 break; 1373 } 1374 if (have_isa_2_07 && have_vsx) { 1375 tcg_out_mem_long(s, 0, LXSIWZX, ret, base, offset); 1376 break; 1377 } 1378 tcg_debug_assert((offset & 3) == 0); 1379 tcg_out_mem_long(s, 0, LVEWX, ret, base, offset); 1380 shift = (offset - 4) & 0xc; 1381 if (shift) { 1382 tcg_out_vsldoi(s, ret, ret, ret, shift); 1383 } 1384 break; 1385 case TCG_TYPE_I64: 1386 if (ret < TCG_REG_V0) { 1387 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1388 tcg_out_mem_long(s, LD, LDX, ret, base, offset); 1389 break; 1390 } 1391 /* fallthru */ 1392 case TCG_TYPE_V64: 1393 tcg_debug_assert(ret >= TCG_REG_V0); 1394 if (have_vsx) { 1395 tcg_out_mem_long(s, have_isa_3_00 ? LXSD : 0, LXSDX, 1396 ret, base, offset); 1397 break; 1398 } 1399 tcg_debug_assert((offset & 7) == 0); 1400 tcg_out_mem_long(s, 0, LVX, ret, base, offset & -16); 1401 if (offset & 8) { 1402 tcg_out_vsldoi(s, ret, ret, ret, 8); 1403 } 1404 break; 1405 case TCG_TYPE_V128: 1406 tcg_debug_assert(ret >= TCG_REG_V0); 1407 tcg_debug_assert((offset & 15) == 0); 1408 tcg_out_mem_long(s, have_isa_3_00 ? LXV : 0, 1409 LVX, ret, base, offset); 1410 break; 1411 default: 1412 g_assert_not_reached(); 1413 } 1414} 1415 1416static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 1417 TCGReg base, intptr_t offset) 1418{ 1419 int shift; 1420 1421 switch (type) { 1422 case TCG_TYPE_I32: 1423 if (arg < TCG_REG_V0) { 1424 tcg_out_mem_long(s, STW, STWX, arg, base, offset); 1425 break; 1426 } 1427 if (have_isa_2_07 && have_vsx) { 1428 tcg_out_mem_long(s, 0, STXSIWX, arg, base, offset); 1429 break; 1430 } 1431 assert((offset & 3) == 0); 1432 tcg_debug_assert((offset & 3) == 0); 1433 shift = (offset - 4) & 0xc; 1434 if (shift) { 1435 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, shift); 1436 arg = TCG_VEC_TMP1; 1437 } 1438 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1439 break; 1440 case TCG_TYPE_I64: 1441 if (arg < TCG_REG_V0) { 1442 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 1443 tcg_out_mem_long(s, STD, STDX, arg, base, offset); 1444 break; 1445 } 1446 /* fallthru */ 1447 case TCG_TYPE_V64: 1448 tcg_debug_assert(arg >= TCG_REG_V0); 1449 if (have_vsx) { 1450 tcg_out_mem_long(s, have_isa_3_00 ? STXSD : 0, 1451 STXSDX, arg, base, offset); 1452 break; 1453 } 1454 tcg_debug_assert((offset & 7) == 0); 1455 if (offset & 8) { 1456 tcg_out_vsldoi(s, TCG_VEC_TMP1, arg, arg, 8); 1457 arg = TCG_VEC_TMP1; 1458 } 1459 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset); 1460 tcg_out_mem_long(s, 0, STVEWX, arg, base, offset + 4); 1461 break; 1462 case TCG_TYPE_V128: 1463 tcg_debug_assert(arg >= TCG_REG_V0); 1464 tcg_out_mem_long(s, have_isa_3_00 ? STXV : 0, 1465 STVX, arg, base, offset); 1466 break; 1467 default: 1468 g_assert_not_reached(); 1469 } 1470} 1471 1472static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 1473 TCGReg base, intptr_t ofs) 1474{ 1475 return false; 1476} 1477 1478static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2, 1479 int const_arg2, int cr, TCGType type) 1480{ 1481 int imm; 1482 uint32_t op; 1483 1484 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1485 1486 /* Simplify the comparisons below wrt CMPI. */ 1487 if (type == TCG_TYPE_I32) { 1488 arg2 = (int32_t)arg2; 1489 } 1490 1491 switch (cond) { 1492 case TCG_COND_EQ: 1493 case TCG_COND_NE: 1494 if (const_arg2) { 1495 if ((int16_t) arg2 == arg2) { 1496 op = CMPI; 1497 imm = 1; 1498 break; 1499 } else if ((uint16_t) arg2 == arg2) { 1500 op = CMPLI; 1501 imm = 1; 1502 break; 1503 } 1504 } 1505 op = CMPL; 1506 imm = 0; 1507 break; 1508 1509 case TCG_COND_LT: 1510 case TCG_COND_GE: 1511 case TCG_COND_LE: 1512 case TCG_COND_GT: 1513 if (const_arg2) { 1514 if ((int16_t) arg2 == arg2) { 1515 op = CMPI; 1516 imm = 1; 1517 break; 1518 } 1519 } 1520 op = CMP; 1521 imm = 0; 1522 break; 1523 1524 case TCG_COND_LTU: 1525 case TCG_COND_GEU: 1526 case TCG_COND_LEU: 1527 case TCG_COND_GTU: 1528 if (const_arg2) { 1529 if ((uint16_t) arg2 == arg2) { 1530 op = CMPLI; 1531 imm = 1; 1532 break; 1533 } 1534 } 1535 op = CMPL; 1536 imm = 0; 1537 break; 1538 1539 default: 1540 g_assert_not_reached(); 1541 } 1542 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21); 1543 1544 if (imm) { 1545 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff)); 1546 } else { 1547 if (const_arg2) { 1548 tcg_out_movi(s, type, TCG_REG_R0, arg2); 1549 arg2 = TCG_REG_R0; 1550 } 1551 tcg_out32(s, op | RA(arg1) | RB(arg2)); 1552 } 1553} 1554 1555static void tcg_out_setcond_eq0(TCGContext *s, TCGType type, 1556 TCGReg dst, TCGReg src, bool neg) 1557{ 1558 if (neg && (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I64)) { 1559 /* 1560 * X != 0 implies X + -1 generates a carry. 1561 * RT = (~X + X) + CA 1562 * = -1 + CA 1563 * = CA ? 0 : -1 1564 */ 1565 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); 1566 tcg_out32(s, SUBFE | TAB(dst, src, src)); 1567 return; 1568 } 1569 1570 if (type == TCG_TYPE_I32) { 1571 tcg_out32(s, CNTLZW | RS(src) | RA(dst)); 1572 tcg_out_shri32(s, dst, dst, 5); 1573 } else { 1574 tcg_out32(s, CNTLZD | RS(src) | RA(dst)); 1575 tcg_out_shri64(s, dst, dst, 6); 1576 } 1577 if (neg) { 1578 tcg_out32(s, NEG | RT(dst) | RA(dst)); 1579 } 1580} 1581 1582static void tcg_out_setcond_ne0(TCGContext *s, TCGType type, 1583 TCGReg dst, TCGReg src, bool neg) 1584{ 1585 if (!neg && (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I64)) { 1586 /* 1587 * X != 0 implies X + -1 generates a carry. Extra addition 1588 * trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. 1589 */ 1590 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1)); 1591 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src)); 1592 return; 1593 } 1594 tcg_out_setcond_eq0(s, type, dst, src, false); 1595 if (neg) { 1596 tcg_out32(s, ADDI | TAI(dst, dst, -1)); 1597 } else { 1598 tcg_out_xori32(s, dst, dst, 1); 1599 } 1600} 1601 1602static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2, 1603 bool const_arg2) 1604{ 1605 if (const_arg2) { 1606 if ((uint32_t)arg2 == arg2) { 1607 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2); 1608 } else { 1609 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2); 1610 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0)); 1611 } 1612 } else { 1613 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2)); 1614 } 1615 return TCG_REG_R0; 1616} 1617 1618static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond, 1619 TCGArg arg0, TCGArg arg1, TCGArg arg2, 1620 int const_arg2, bool neg) 1621{ 1622 int sh; 1623 bool inv; 1624 1625 tcg_debug_assert(TCG_TARGET_REG_BITS == 64 || type == TCG_TYPE_I32); 1626 1627 /* Ignore high bits of a potential constant arg2. */ 1628 if (type == TCG_TYPE_I32) { 1629 arg2 = (uint32_t)arg2; 1630 } 1631 1632 /* With SETBC/SETBCR, we can always implement with 2 insns. */ 1633 if (have_isa_3_10) { 1634 tcg_insn_unit bi, opc; 1635 1636 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1637 1638 /* Re-use tcg_to_bc for BI and BO_COND_{TRUE,FALSE}. */ 1639 bi = tcg_to_bc[cond] & (0x1f << 16); 1640 if (tcg_to_bc[cond] & BO(8)) { 1641 opc = neg ? SETNBC : SETBC; 1642 } else { 1643 opc = neg ? SETNBCR : SETBCR; 1644 } 1645 tcg_out32(s, opc | RT(arg0) | bi); 1646 return; 1647 } 1648 1649 /* Handle common and trivial cases before handling anything else. */ 1650 if (arg2 == 0) { 1651 switch (cond) { 1652 case TCG_COND_EQ: 1653 tcg_out_setcond_eq0(s, type, arg0, arg1, neg); 1654 return; 1655 case TCG_COND_NE: 1656 tcg_out_setcond_ne0(s, type, arg0, arg1, neg); 1657 return; 1658 case TCG_COND_GE: 1659 tcg_out32(s, NOR | SAB(arg1, arg0, arg1)); 1660 arg1 = arg0; 1661 /* FALLTHRU */ 1662 case TCG_COND_LT: 1663 /* Extract the sign bit. */ 1664 if (type == TCG_TYPE_I32) { 1665 if (neg) { 1666 tcg_out_sari32(s, arg0, arg1, 31); 1667 } else { 1668 tcg_out_shri32(s, arg0, arg1, 31); 1669 } 1670 } else { 1671 if (neg) { 1672 tcg_out_sari64(s, arg0, arg1, 63); 1673 } else { 1674 tcg_out_shri64(s, arg0, arg1, 63); 1675 } 1676 } 1677 return; 1678 default: 1679 break; 1680 } 1681 } 1682 1683 /* If we have ISEL, we can implement everything with 3 or 4 insns. 1684 All other cases below are also at least 3 insns, so speed up the 1685 code generator by not considering them and always using ISEL. */ 1686 if (have_isel) { 1687 int isel, tab; 1688 1689 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1690 1691 isel = tcg_to_isel[cond]; 1692 1693 tcg_out_movi(s, type, arg0, neg ? -1 : 1); 1694 if (isel & 1) { 1695 /* arg0 = (bc ? 0 : 1) */ 1696 tab = TAB(arg0, 0, arg0); 1697 isel &= ~1; 1698 } else { 1699 /* arg0 = (bc ? 1 : 0) */ 1700 tcg_out_movi(s, type, TCG_REG_R0, 0); 1701 tab = TAB(arg0, arg0, TCG_REG_R0); 1702 } 1703 tcg_out32(s, isel | tab); 1704 return; 1705 } 1706 1707 inv = false; 1708 switch (cond) { 1709 case TCG_COND_EQ: 1710 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1711 tcg_out_setcond_eq0(s, type, arg0, arg1, neg); 1712 break; 1713 1714 case TCG_COND_NE: 1715 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2); 1716 tcg_out_setcond_ne0(s, type, arg0, arg1, neg); 1717 break; 1718 1719 case TCG_COND_LE: 1720 case TCG_COND_LEU: 1721 inv = true; 1722 /* fall through */ 1723 case TCG_COND_GT: 1724 case TCG_COND_GTU: 1725 sh = 30; /* CR7 CR_GT */ 1726 goto crtest; 1727 1728 case TCG_COND_GE: 1729 case TCG_COND_GEU: 1730 inv = true; 1731 /* fall through */ 1732 case TCG_COND_LT: 1733 case TCG_COND_LTU: 1734 sh = 29; /* CR7 CR_LT */ 1735 goto crtest; 1736 1737 crtest: 1738 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1739 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1740 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31); 1741 if (neg && inv) { 1742 tcg_out32(s, ADDI | TAI(arg0, arg0, -1)); 1743 } else if (neg) { 1744 tcg_out32(s, NEG | RT(arg0) | RA(arg0)); 1745 } else if (inv) { 1746 tcg_out_xori32(s, arg0, arg0, 1); 1747 } 1748 break; 1749 1750 default: 1751 g_assert_not_reached(); 1752 } 1753} 1754 1755static void tcg_out_bc(TCGContext *s, int bc, TCGLabel *l) 1756{ 1757 if (l->has_value) { 1758 bc |= reloc_pc14_val(tcg_splitwx_to_rx(s->code_ptr), l->u.value_ptr); 1759 } else { 1760 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, l, 0); 1761 } 1762 tcg_out32(s, bc); 1763} 1764 1765static void tcg_out_brcond(TCGContext *s, TCGCond cond, 1766 TCGArg arg1, TCGArg arg2, int const_arg2, 1767 TCGLabel *l, TCGType type) 1768{ 1769 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type); 1770 tcg_out_bc(s, tcg_to_bc[cond], l); 1771} 1772 1773static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond, 1774 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1, 1775 TCGArg v2, bool const_c2) 1776{ 1777 /* If for some reason both inputs are zero, don't produce bad code. */ 1778 if (v1 == 0 && v2 == 0) { 1779 tcg_out_movi(s, type, dest, 0); 1780 return; 1781 } 1782 1783 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type); 1784 1785 if (have_isel) { 1786 int isel = tcg_to_isel[cond]; 1787 1788 /* Swap the V operands if the operation indicates inversion. */ 1789 if (isel & 1) { 1790 int t = v1; 1791 v1 = v2; 1792 v2 = t; 1793 isel &= ~1; 1794 } 1795 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */ 1796 if (v2 == 0) { 1797 tcg_out_movi(s, type, TCG_REG_R0, 0); 1798 } 1799 tcg_out32(s, isel | TAB(dest, v1, v2)); 1800 } else { 1801 if (dest == v2) { 1802 cond = tcg_invert_cond(cond); 1803 v2 = v1; 1804 } else if (dest != v1) { 1805 if (v1 == 0) { 1806 tcg_out_movi(s, type, dest, 0); 1807 } else { 1808 tcg_out_mov(s, type, dest, v1); 1809 } 1810 } 1811 /* Branch forward over one insn */ 1812 tcg_out32(s, tcg_to_bc[cond] | 8); 1813 if (v2 == 0) { 1814 tcg_out_movi(s, type, dest, 0); 1815 } else { 1816 tcg_out_mov(s, type, dest, v2); 1817 } 1818 } 1819} 1820 1821static void tcg_out_cntxz(TCGContext *s, TCGType type, uint32_t opc, 1822 TCGArg a0, TCGArg a1, TCGArg a2, bool const_a2) 1823{ 1824 if (const_a2 && a2 == (type == TCG_TYPE_I32 ? 32 : 64)) { 1825 tcg_out32(s, opc | RA(a0) | RS(a1)); 1826 } else { 1827 tcg_out_cmp(s, TCG_COND_EQ, a1, 0, 1, 7, type); 1828 /* Note that the only other valid constant for a2 is 0. */ 1829 if (have_isel) { 1830 tcg_out32(s, opc | RA(TCG_REG_R0) | RS(a1)); 1831 tcg_out32(s, tcg_to_isel[TCG_COND_EQ] | TAB(a0, a2, TCG_REG_R0)); 1832 } else if (!const_a2 && a0 == a2) { 1833 tcg_out32(s, tcg_to_bc[TCG_COND_EQ] | 8); 1834 tcg_out32(s, opc | RA(a0) | RS(a1)); 1835 } else { 1836 tcg_out32(s, opc | RA(a0) | RS(a1)); 1837 tcg_out32(s, tcg_to_bc[TCG_COND_NE] | 8); 1838 if (const_a2) { 1839 tcg_out_movi(s, type, a0, 0); 1840 } else { 1841 tcg_out_mov(s, type, a0, a2); 1842 } 1843 } 1844 } 1845} 1846 1847static void tcg_out_cmp2(TCGContext *s, const TCGArg *args, 1848 const int *const_args) 1849{ 1850 static const struct { uint8_t bit1, bit2; } bits[] = { 1851 [TCG_COND_LT ] = { CR_LT, CR_LT }, 1852 [TCG_COND_LE ] = { CR_LT, CR_GT }, 1853 [TCG_COND_GT ] = { CR_GT, CR_GT }, 1854 [TCG_COND_GE ] = { CR_GT, CR_LT }, 1855 [TCG_COND_LTU] = { CR_LT, CR_LT }, 1856 [TCG_COND_LEU] = { CR_LT, CR_GT }, 1857 [TCG_COND_GTU] = { CR_GT, CR_GT }, 1858 [TCG_COND_GEU] = { CR_GT, CR_LT }, 1859 }; 1860 1861 TCGCond cond = args[4], cond2; 1862 TCGArg al, ah, bl, bh; 1863 int blconst, bhconst; 1864 int op, bit1, bit2; 1865 1866 al = args[0]; 1867 ah = args[1]; 1868 bl = args[2]; 1869 bh = args[3]; 1870 blconst = const_args[2]; 1871 bhconst = const_args[3]; 1872 1873 switch (cond) { 1874 case TCG_COND_EQ: 1875 op = CRAND; 1876 goto do_equality; 1877 case TCG_COND_NE: 1878 op = CRNAND; 1879 do_equality: 1880 tcg_out_cmp(s, cond, al, bl, blconst, 6, TCG_TYPE_I32); 1881 tcg_out_cmp(s, cond, ah, bh, bhconst, 7, TCG_TYPE_I32); 1882 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 1883 break; 1884 1885 case TCG_COND_LT: 1886 case TCG_COND_LE: 1887 case TCG_COND_GT: 1888 case TCG_COND_GE: 1889 case TCG_COND_LTU: 1890 case TCG_COND_LEU: 1891 case TCG_COND_GTU: 1892 case TCG_COND_GEU: 1893 bit1 = bits[cond].bit1; 1894 bit2 = bits[cond].bit2; 1895 op = (bit1 != bit2 ? CRANDC : CRAND); 1896 cond2 = tcg_unsigned_cond(cond); 1897 1898 tcg_out_cmp(s, cond, ah, bh, bhconst, 6, TCG_TYPE_I32); 1899 tcg_out_cmp(s, cond2, al, bl, blconst, 7, TCG_TYPE_I32); 1900 tcg_out32(s, op | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, bit2)); 1901 tcg_out32(s, CROR | BT(7, CR_EQ) | BA(6, bit1) | BB(7, CR_EQ)); 1902 break; 1903 1904 default: 1905 g_assert_not_reached(); 1906 } 1907} 1908 1909static void tcg_out_setcond2(TCGContext *s, const TCGArg *args, 1910 const int *const_args) 1911{ 1912 tcg_out_cmp2(s, args + 1, const_args + 1); 1913 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7)); 1914 tcg_out_rlw(s, RLWINM, args[0], TCG_REG_R0, 31, 31, 31); 1915} 1916 1917static void tcg_out_brcond2 (TCGContext *s, const TCGArg *args, 1918 const int *const_args) 1919{ 1920 tcg_out_cmp2(s, args, const_args); 1921 tcg_out_bc(s, BC | BI(7, CR_EQ) | BO_COND_TRUE, arg_label(args[5])); 1922} 1923 1924static void tcg_out_mb(TCGContext *s, TCGArg a0) 1925{ 1926 uint32_t insn; 1927 1928 if (a0 & TCG_MO_ST_LD) { 1929 insn = HWSYNC; 1930 } else { 1931 insn = LWSYNC; 1932 } 1933 1934 tcg_out32(s, insn); 1935} 1936 1937static void tcg_out_call_int(TCGContext *s, int lk, 1938 const tcg_insn_unit *target) 1939{ 1940#ifdef _CALL_AIX 1941 /* Look through the descriptor. If the branch is in range, and we 1942 don't have to spend too much effort on building the toc. */ 1943 const void *tgt = ((const void * const *)target)[0]; 1944 uintptr_t toc = ((const uintptr_t *)target)[1]; 1945 intptr_t diff = tcg_pcrel_diff(s, tgt); 1946 1947 if (in_range_b(diff) && toc == (uint32_t)toc) { 1948 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, toc); 1949 tcg_out_b(s, lk, tgt); 1950 } else { 1951 /* Fold the low bits of the constant into the addresses below. */ 1952 intptr_t arg = (intptr_t)target; 1953 int ofs = (int16_t)arg; 1954 1955 if (ofs + 8 < 0x8000) { 1956 arg -= ofs; 1957 } else { 1958 ofs = 0; 1959 } 1960 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, arg); 1961 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_TMP1, ofs); 1962 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR); 1963 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_TMP1, ofs + SZP); 1964 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1965 } 1966#elif defined(_CALL_ELF) && _CALL_ELF == 2 1967 intptr_t diff; 1968 1969 /* In the ELFv2 ABI, we have to set up r12 to contain the destination 1970 address, which the callee uses to compute its TOC address. */ 1971 /* FIXME: when the branch is in range, we could avoid r12 load if we 1972 knew that the destination uses the same TOC, and what its local 1973 entry point offset is. */ 1974 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target); 1975 1976 diff = tcg_pcrel_diff(s, target); 1977 if (in_range_b(diff)) { 1978 tcg_out_b(s, lk, target); 1979 } else { 1980 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR); 1981 tcg_out32(s, BCCTR | BO_ALWAYS | lk); 1982 } 1983#else 1984 tcg_out_b(s, lk, target); 1985#endif 1986} 1987 1988static void tcg_out_call(TCGContext *s, const tcg_insn_unit *target, 1989 const TCGHelperInfo *info) 1990{ 1991 tcg_out_call_int(s, LK, target); 1992} 1993 1994static const uint32_t qemu_ldx_opc[(MO_SSIZE + MO_BSWAP) + 1] = { 1995 [MO_UB] = LBZX, 1996 [MO_UW] = LHZX, 1997 [MO_UL] = LWZX, 1998 [MO_UQ] = LDX, 1999 [MO_SW] = LHAX, 2000 [MO_SL] = LWAX, 2001 [MO_BSWAP | MO_UB] = LBZX, 2002 [MO_BSWAP | MO_UW] = LHBRX, 2003 [MO_BSWAP | MO_UL] = LWBRX, 2004 [MO_BSWAP | MO_UQ] = LDBRX, 2005}; 2006 2007static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = { 2008 [MO_UB] = STBX, 2009 [MO_UW] = STHX, 2010 [MO_UL] = STWX, 2011 [MO_UQ] = STDX, 2012 [MO_BSWAP | MO_UB] = STBX, 2013 [MO_BSWAP | MO_UW] = STHBRX, 2014 [MO_BSWAP | MO_UL] = STWBRX, 2015 [MO_BSWAP | MO_UQ] = STDBRX, 2016}; 2017 2018static TCGReg ldst_ra_gen(TCGContext *s, const TCGLabelQemuLdst *l, int arg) 2019{ 2020 if (arg < 0) { 2021 arg = TCG_REG_TMP1; 2022 } 2023 tcg_out32(s, MFSPR | RT(arg) | LR); 2024 return arg; 2025} 2026 2027/* 2028 * For the purposes of ppc32 sorting 4 input registers into 4 argument 2029 * registers, there is an outside chance we would require 3 temps. 2030 */ 2031static const TCGLdstHelperParam ldst_helper_param = { 2032 .ra_gen = ldst_ra_gen, 2033 .ntmp = 3, 2034 .tmp = { TCG_REG_TMP1, TCG_REG_TMP2, TCG_REG_R0 } 2035}; 2036 2037static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2038{ 2039 MemOp opc = get_memop(lb->oi); 2040 2041 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2042 return false; 2043 } 2044 2045 tcg_out_ld_helper_args(s, lb, &ldst_helper_param); 2046 tcg_out_call_int(s, LK, qemu_ld_helpers[opc & MO_SIZE]); 2047 tcg_out_ld_helper_ret(s, lb, false, &ldst_helper_param); 2048 2049 tcg_out_b(s, 0, lb->raddr); 2050 return true; 2051} 2052 2053static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) 2054{ 2055 MemOp opc = get_memop(lb->oi); 2056 2057 if (!reloc_pc14(lb->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 2058 return false; 2059 } 2060 2061 tcg_out_st_helper_args(s, lb, &ldst_helper_param); 2062 tcg_out_call_int(s, LK, qemu_st_helpers[opc & MO_SIZE]); 2063 2064 tcg_out_b(s, 0, lb->raddr); 2065 return true; 2066} 2067 2068typedef struct { 2069 TCGReg base; 2070 TCGReg index; 2071 TCGAtomAlign aa; 2072} HostAddress; 2073 2074bool tcg_target_has_memory_bswap(MemOp memop) 2075{ 2076 TCGAtomAlign aa; 2077 2078 if ((memop & MO_SIZE) <= MO_64) { 2079 return true; 2080 } 2081 2082 /* 2083 * Reject 16-byte memop with 16-byte atomicity, 2084 * but do allow a pair of 64-bit operations. 2085 */ 2086 aa = atom_and_align_for_opc(tcg_ctx, memop, MO_ATOM_IFALIGN, true); 2087 return aa.atom <= MO_64; 2088} 2089 2090/* We expect to use a 16-bit negative offset from ENV. */ 2091#define MIN_TLB_MASK_TABLE_OFS -32768 2092 2093/* 2094 * For softmmu, perform the TLB load and compare. 2095 * For useronly, perform any required alignment tests. 2096 * In both cases, return a TCGLabelQemuLdst structure if the slow path 2097 * is required and fill in @h with the host address for the fast path. 2098 */ 2099static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 2100 TCGReg addrlo, TCGReg addrhi, 2101 MemOpIdx oi, bool is_ld) 2102{ 2103 TCGType addr_type = s->addr_type; 2104 TCGLabelQemuLdst *ldst = NULL; 2105 MemOp opc = get_memop(oi); 2106 MemOp a_bits, s_bits; 2107 2108 /* 2109 * Book II, Section 1.4, Single-Copy Atomicity, specifies: 2110 * 2111 * Before 3.0, "An access that is not atomic is performed as a set of 2112 * smaller disjoint atomic accesses. In general, the number and alignment 2113 * of these accesses are implementation-dependent." Thus MO_ATOM_IFALIGN. 2114 * 2115 * As of 3.0, "the non-atomic access is performed as described in 2116 * the corresponding list", which matches MO_ATOM_SUBALIGN. 2117 */ 2118 s_bits = opc & MO_SIZE; 2119 h->aa = atom_and_align_for_opc(s, opc, 2120 have_isa_3_00 ? MO_ATOM_SUBALIGN 2121 : MO_ATOM_IFALIGN, 2122 s_bits == MO_128); 2123 a_bits = h->aa.align; 2124 2125#ifdef CONFIG_SOFTMMU 2126 int mem_index = get_mmuidx(oi); 2127 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 2128 : offsetof(CPUTLBEntry, addr_write); 2129 int fast_off = tlb_mask_table_ofs(s, mem_index); 2130 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 2131 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 2132 2133 ldst = new_ldst_label(s); 2134 ldst->is_ld = is_ld; 2135 ldst->oi = oi; 2136 ldst->addrlo_reg = addrlo; 2137 ldst->addrhi_reg = addrhi; 2138 2139 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 2140 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); 2141 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); 2142 2143 /* Extract the page index, shifted into place for tlb index. */ 2144 if (TCG_TARGET_REG_BITS == 32) { 2145 tcg_out_shri32(s, TCG_REG_R0, addrlo, 2146 s->page_bits - CPU_TLB_ENTRY_BITS); 2147 } else { 2148 tcg_out_shri64(s, TCG_REG_R0, addrlo, 2149 s->page_bits - CPU_TLB_ENTRY_BITS); 2150 } 2151 tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); 2152 2153 /* 2154 * Load the (low part) TLB comparator into TMP2. 2155 * For 64-bit host, always load the entire 64-bit slot for simplicity. 2156 * We will ignore the high bits with tcg_out_cmp(..., addr_type). 2157 */ 2158 if (TCG_TARGET_REG_BITS == 64) { 2159 if (cmp_off == 0) { 2160 tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); 2161 } else { 2162 tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); 2163 tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); 2164 } 2165 } else if (cmp_off == 0 && !HOST_BIG_ENDIAN) { 2166 tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); 2167 } else { 2168 tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); 2169 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, 2170 cmp_off + 4 * HOST_BIG_ENDIAN); 2171 } 2172 2173 /* 2174 * Load the TLB addend for use on the fast path. 2175 * Do this asap to minimize any load use delay. 2176 */ 2177 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { 2178 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, 2179 offsetof(CPUTLBEntry, addend)); 2180 } 2181 2182 /* Clear the non-page, non-alignment bits from the address in R0. */ 2183 if (TCG_TARGET_REG_BITS == 32) { 2184 /* 2185 * We don't support unaligned accesses on 32-bits. 2186 * Preserve the bottom bits and thus trigger a comparison 2187 * failure on unaligned accesses. 2188 */ 2189 if (a_bits < s_bits) { 2190 a_bits = s_bits; 2191 } 2192 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addrlo, 0, 2193 (32 - a_bits) & 31, 31 - s->page_bits); 2194 } else { 2195 TCGReg t = addrlo; 2196 2197 /* 2198 * If the access is unaligned, we need to make sure we fail if we 2199 * cross a page boundary. The trick is to add the access size-1 2200 * to the address before masking the low bits. That will make the 2201 * address overflow to the next page if we cross a page boundary, 2202 * which will then force a mismatch of the TLB compare. 2203 */ 2204 if (a_bits < s_bits) { 2205 unsigned a_mask = (1 << a_bits) - 1; 2206 unsigned s_mask = (1 << s_bits) - 1; 2207 tcg_out32(s, ADDI | TAI(TCG_REG_R0, t, s_mask - a_mask)); 2208 t = TCG_REG_R0; 2209 } 2210 2211 /* Mask the address for the requested alignment. */ 2212 if (addr_type == TCG_TYPE_I32) { 2213 tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, 2214 (32 - a_bits) & 31, 31 - s->page_bits); 2215 } else if (a_bits == 0) { 2216 tcg_out_rld(s, RLDICR, TCG_REG_R0, t, 0, 63 - s->page_bits); 2217 } else { 2218 tcg_out_rld(s, RLDICL, TCG_REG_R0, t, 2219 64 - s->page_bits, s->page_bits - a_bits); 2220 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, s->page_bits, 0); 2221 } 2222 } 2223 2224 if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { 2225 /* Low part comparison into cr7. */ 2226 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 2227 0, 7, TCG_TYPE_I32); 2228 2229 /* Load the high part TLB comparator into TMP2. */ 2230 tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, 2231 cmp_off + 4 * !HOST_BIG_ENDIAN); 2232 2233 /* Load addend, deferred for this case. */ 2234 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, 2235 offsetof(CPUTLBEntry, addend)); 2236 2237 /* High part comparison into cr6. */ 2238 tcg_out_cmp(s, TCG_COND_EQ, addrhi, TCG_REG_TMP2, 0, 6, TCG_TYPE_I32); 2239 2240 /* Combine comparisons into cr7. */ 2241 tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); 2242 } else { 2243 /* Full comparison into cr7. */ 2244 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, addr_type); 2245 } 2246 2247 /* Load a pointer into the current opcode w/conditional branch-link. */ 2248 ldst->label_ptr[0] = s->code_ptr; 2249 tcg_out32(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK); 2250 2251 h->base = TCG_REG_TMP1; 2252#else 2253 if (a_bits) { 2254 ldst = new_ldst_label(s); 2255 ldst->is_ld = is_ld; 2256 ldst->oi = oi; 2257 ldst->addrlo_reg = addrlo; 2258 ldst->addrhi_reg = addrhi; 2259 2260 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 2261 tcg_debug_assert(a_bits < 16); 2262 tcg_out32(s, ANDI | SAI(addrlo, TCG_REG_R0, (1 << a_bits) - 1)); 2263 2264 ldst->label_ptr[0] = s->code_ptr; 2265 tcg_out32(s, BC | BI(0, CR_EQ) | BO_COND_FALSE | LK); 2266 } 2267 2268 h->base = guest_base ? TCG_GUEST_BASE_REG : 0; 2269#endif 2270 2271 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 2272 /* Zero-extend the guest address for use in the host address. */ 2273 tcg_out_ext32u(s, TCG_REG_R0, addrlo); 2274 h->index = TCG_REG_R0; 2275 } else { 2276 h->index = addrlo; 2277 } 2278 2279 return ldst; 2280} 2281 2282static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 2283 TCGReg addrlo, TCGReg addrhi, 2284 MemOpIdx oi, TCGType data_type) 2285{ 2286 MemOp opc = get_memop(oi); 2287 TCGLabelQemuLdst *ldst; 2288 HostAddress h; 2289 2290 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 2291 2292 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2293 if (opc & MO_BSWAP) { 2294 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2295 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2296 tcg_out32(s, LWBRX | TAB(datahi, h.base, TCG_REG_R0)); 2297 } else if (h.base != 0) { 2298 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2299 tcg_out32(s, LWZX | TAB(datahi, h.base, h.index)); 2300 tcg_out32(s, LWZX | TAB(datalo, h.base, TCG_REG_R0)); 2301 } else if (h.index == datahi) { 2302 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2303 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2304 } else { 2305 tcg_out32(s, LWZ | TAI(datahi, h.index, 0)); 2306 tcg_out32(s, LWZ | TAI(datalo, h.index, 4)); 2307 } 2308 } else { 2309 uint32_t insn = qemu_ldx_opc[opc & (MO_BSWAP | MO_SSIZE)]; 2310 if (!have_isa_2_06 && insn == LDBRX) { 2311 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2312 tcg_out32(s, LWBRX | TAB(datalo, h.base, h.index)); 2313 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, h.base, TCG_REG_R0)); 2314 tcg_out_rld(s, RLDIMI, datalo, TCG_REG_R0, 32, 0); 2315 } else if (insn) { 2316 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2317 } else { 2318 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)]; 2319 tcg_out32(s, insn | TAB(datalo, h.base, h.index)); 2320 tcg_out_movext(s, TCG_TYPE_REG, datalo, 2321 TCG_TYPE_REG, opc & MO_SSIZE, datalo); 2322 } 2323 } 2324 2325 if (ldst) { 2326 ldst->type = data_type; 2327 ldst->datalo_reg = datalo; 2328 ldst->datahi_reg = datahi; 2329 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2330 } 2331} 2332 2333static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 2334 TCGReg addrlo, TCGReg addrhi, 2335 MemOpIdx oi, TCGType data_type) 2336{ 2337 MemOp opc = get_memop(oi); 2338 TCGLabelQemuLdst *ldst; 2339 HostAddress h; 2340 2341 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 2342 2343 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 2344 if (opc & MO_BSWAP) { 2345 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2346 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2347 tcg_out32(s, STWBRX | SAB(datahi, h.base, TCG_REG_R0)); 2348 } else if (h.base != 0) { 2349 tcg_out32(s, ADDI | TAI(TCG_REG_R0, h.index, 4)); 2350 tcg_out32(s, STWX | SAB(datahi, h.base, h.index)); 2351 tcg_out32(s, STWX | SAB(datalo, h.base, TCG_REG_R0)); 2352 } else { 2353 tcg_out32(s, STW | TAI(datahi, h.index, 0)); 2354 tcg_out32(s, STW | TAI(datalo, h.index, 4)); 2355 } 2356 } else { 2357 uint32_t insn = qemu_stx_opc[opc & (MO_BSWAP | MO_SIZE)]; 2358 if (!have_isa_2_06 && insn == STDBRX) { 2359 tcg_out32(s, STWBRX | SAB(datalo, h.base, h.index)); 2360 tcg_out32(s, ADDI | TAI(TCG_REG_TMP1, h.index, 4)); 2361 tcg_out_shri64(s, TCG_REG_R0, datalo, 32); 2362 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, h.base, TCG_REG_TMP1)); 2363 } else { 2364 tcg_out32(s, insn | SAB(datalo, h.base, h.index)); 2365 } 2366 } 2367 2368 if (ldst) { 2369 ldst->type = data_type; 2370 ldst->datalo_reg = datalo; 2371 ldst->datahi_reg = datahi; 2372 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2373 } 2374} 2375 2376static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg datalo, TCGReg datahi, 2377 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 2378{ 2379 TCGLabelQemuLdst *ldst; 2380 HostAddress h; 2381 bool need_bswap; 2382 uint32_t insn; 2383 TCGReg index; 2384 2385 ldst = prepare_host_addr(s, &h, addr_reg, -1, oi, is_ld); 2386 2387 /* Compose the final address, as LQ/STQ have no indexing. */ 2388 index = h.index; 2389 if (h.base != 0) { 2390 index = TCG_REG_TMP1; 2391 tcg_out32(s, ADD | TAB(index, h.base, h.index)); 2392 } 2393 need_bswap = get_memop(oi) & MO_BSWAP; 2394 2395 if (h.aa.atom == MO_128) { 2396 tcg_debug_assert(!need_bswap); 2397 tcg_debug_assert(datalo & 1); 2398 tcg_debug_assert(datahi == datalo - 1); 2399 insn = is_ld ? LQ : STQ; 2400 tcg_out32(s, insn | TAI(datahi, index, 0)); 2401 } else { 2402 TCGReg d1, d2; 2403 2404 if (HOST_BIG_ENDIAN ^ need_bswap) { 2405 d1 = datahi, d2 = datalo; 2406 } else { 2407 d1 = datalo, d2 = datahi; 2408 } 2409 2410 if (need_bswap) { 2411 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, 8); 2412 insn = is_ld ? LDBRX : STDBRX; 2413 tcg_out32(s, insn | TAB(d1, 0, index)); 2414 tcg_out32(s, insn | TAB(d2, index, TCG_REG_R0)); 2415 } else { 2416 insn = is_ld ? LD : STD; 2417 tcg_out32(s, insn | TAI(d1, index, 0)); 2418 tcg_out32(s, insn | TAI(d2, index, 8)); 2419 } 2420 } 2421 2422 if (ldst) { 2423 ldst->type = TCG_TYPE_I128; 2424 ldst->datalo_reg = datalo; 2425 ldst->datahi_reg = datahi; 2426 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 2427 } 2428} 2429 2430static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2431{ 2432 int i; 2433 for (i = 0; i < count; ++i) { 2434 p[i] = NOP; 2435 } 2436} 2437 2438/* Parameters for function call generation, used in tcg.c. */ 2439#define TCG_TARGET_STACK_ALIGN 16 2440 2441#ifdef _CALL_AIX 2442# define LINK_AREA_SIZE (6 * SZR) 2443# define LR_OFFSET (1 * SZR) 2444# define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR) 2445#elif defined(_CALL_DARWIN) 2446# define LINK_AREA_SIZE (6 * SZR) 2447# define LR_OFFSET (2 * SZR) 2448#elif TCG_TARGET_REG_BITS == 64 2449# if defined(_CALL_ELF) && _CALL_ELF == 2 2450# define LINK_AREA_SIZE (4 * SZR) 2451# define LR_OFFSET (1 * SZR) 2452# endif 2453#else /* TCG_TARGET_REG_BITS == 32 */ 2454# if defined(_CALL_SYSV) 2455# define LINK_AREA_SIZE (2 * SZR) 2456# define LR_OFFSET (1 * SZR) 2457# endif 2458#endif 2459#ifndef LR_OFFSET 2460# error "Unhandled abi" 2461#endif 2462#ifndef TCG_TARGET_CALL_STACK_OFFSET 2463# define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE 2464#endif 2465 2466#define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2467#define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR) 2468 2469#define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \ 2470 + TCG_STATIC_CALL_ARGS_SIZE \ 2471 + CPU_TEMP_BUF_SIZE \ 2472 + REG_SAVE_SIZE \ 2473 + TCG_TARGET_STACK_ALIGN - 1) \ 2474 & -TCG_TARGET_STACK_ALIGN) 2475 2476#define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE) 2477 2478static void tcg_target_qemu_prologue(TCGContext *s) 2479{ 2480 int i; 2481 2482#ifdef _CALL_AIX 2483 const void **desc = (const void **)s->code_ptr; 2484 desc[0] = tcg_splitwx_to_rx(desc + 2); /* entry point */ 2485 desc[1] = 0; /* environment pointer */ 2486 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */ 2487#endif 2488 2489 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE, 2490 CPU_TEMP_BUF_SIZE); 2491 2492 /* Prologue */ 2493 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR); 2494 tcg_out32(s, (SZR == 8 ? STDU : STWU) 2495 | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE)); 2496 2497 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2498 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2499 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2500 } 2501 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2502 2503#ifndef CONFIG_SOFTMMU 2504 if (guest_base) { 2505 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, true); 2506 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2507 } 2508#endif 2509 2510 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2511 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR); 2512 if (USE_REG_TB) { 2513 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2514 } 2515 tcg_out32(s, BCCTR | BO_ALWAYS); 2516 2517 /* Epilogue */ 2518 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2519 2520 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET); 2521 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) { 2522 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2523 TCG_REG_R1, REG_SAVE_BOT + i * SZR); 2524 } 2525 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR); 2526 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE)); 2527 tcg_out32(s, BCLR | BO_ALWAYS); 2528} 2529 2530static void tcg_out_tb_start(TCGContext *s) 2531{ 2532 /* nothing to do */ 2533} 2534 2535static void tcg_out_exit_tb(TCGContext *s, uintptr_t arg) 2536{ 2537 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, arg); 2538 tcg_out_b(s, 0, tcg_code_gen_epilogue); 2539} 2540 2541static void tcg_out_goto_tb(TCGContext *s, int which) 2542{ 2543 uintptr_t ptr = get_jmp_target_addr(s, which); 2544 2545 if (USE_REG_TB) { 2546 ptrdiff_t offset = tcg_tbrel_diff(s, (void *)ptr); 2547 tcg_out_mem_long(s, LD, LDX, TCG_REG_TB, TCG_REG_TB, offset); 2548 2549 /* TODO: Use direct branches when possible. */ 2550 set_jmp_insn_offset(s, which); 2551 tcg_out32(s, MTSPR | RS(TCG_REG_TB) | CTR); 2552 2553 tcg_out32(s, BCCTR | BO_ALWAYS); 2554 2555 /* For the unlinked case, need to reset TCG_REG_TB. */ 2556 set_jmp_reset_offset(s, which); 2557 tcg_out_mem_long(s, ADDI, ADD, TCG_REG_TB, TCG_REG_TB, 2558 -tcg_current_code_size(s)); 2559 } else { 2560 /* Direct branch will be patched by tb_target_set_jmp_target. */ 2561 set_jmp_insn_offset(s, which); 2562 tcg_out32(s, NOP); 2563 2564 /* When branch is out of range, fall through to indirect. */ 2565 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP1, ptr - (int16_t)ptr); 2566 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, (int16_t)ptr); 2567 tcg_out32(s, MTSPR | RS(TCG_REG_TMP1) | CTR); 2568 tcg_out32(s, BCCTR | BO_ALWAYS); 2569 set_jmp_reset_offset(s, which); 2570 } 2571} 2572 2573void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2574 uintptr_t jmp_rx, uintptr_t jmp_rw) 2575{ 2576 uintptr_t addr = tb->jmp_target_addr[n]; 2577 intptr_t diff = addr - jmp_rx; 2578 tcg_insn_unit insn; 2579 2580 if (USE_REG_TB) { 2581 return; 2582 } 2583 2584 if (in_range_b(diff)) { 2585 insn = B | (diff & 0x3fffffc); 2586 } else { 2587 insn = NOP; 2588 } 2589 2590 qatomic_set((uint32_t *)jmp_rw, insn); 2591 flush_idcache_range(jmp_rx, jmp_rw, 4); 2592} 2593 2594static void tcg_out_op(TCGContext *s, TCGOpcode opc, 2595 const TCGArg args[TCG_MAX_OP_ARGS], 2596 const int const_args[TCG_MAX_OP_ARGS]) 2597{ 2598 TCGArg a0, a1, a2; 2599 2600 switch (opc) { 2601 case INDEX_op_goto_ptr: 2602 tcg_out32(s, MTSPR | RS(args[0]) | CTR); 2603 if (USE_REG_TB) { 2604 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, args[0]); 2605 } 2606 tcg_out32(s, ADDI | TAI(TCG_REG_R3, 0, 0)); 2607 tcg_out32(s, BCCTR | BO_ALWAYS); 2608 break; 2609 case INDEX_op_br: 2610 { 2611 TCGLabel *l = arg_label(args[0]); 2612 uint32_t insn = B; 2613 2614 if (l->has_value) { 2615 insn |= reloc_pc24_val(tcg_splitwx_to_rx(s->code_ptr), 2616 l->u.value_ptr); 2617 } else { 2618 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, l, 0); 2619 } 2620 tcg_out32(s, insn); 2621 } 2622 break; 2623 case INDEX_op_ld8u_i32: 2624 case INDEX_op_ld8u_i64: 2625 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2626 break; 2627 case INDEX_op_ld8s_i32: 2628 case INDEX_op_ld8s_i64: 2629 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]); 2630 tcg_out_ext8s(s, TCG_TYPE_REG, args[0], args[0]); 2631 break; 2632 case INDEX_op_ld16u_i32: 2633 case INDEX_op_ld16u_i64: 2634 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]); 2635 break; 2636 case INDEX_op_ld16s_i32: 2637 case INDEX_op_ld16s_i64: 2638 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]); 2639 break; 2640 case INDEX_op_ld_i32: 2641 case INDEX_op_ld32u_i64: 2642 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]); 2643 break; 2644 case INDEX_op_ld32s_i64: 2645 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]); 2646 break; 2647 case INDEX_op_ld_i64: 2648 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]); 2649 break; 2650 case INDEX_op_st8_i32: 2651 case INDEX_op_st8_i64: 2652 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]); 2653 break; 2654 case INDEX_op_st16_i32: 2655 case INDEX_op_st16_i64: 2656 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]); 2657 break; 2658 case INDEX_op_st_i32: 2659 case INDEX_op_st32_i64: 2660 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]); 2661 break; 2662 case INDEX_op_st_i64: 2663 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]); 2664 break; 2665 2666 case INDEX_op_add_i32: 2667 a0 = args[0], a1 = args[1], a2 = args[2]; 2668 if (const_args[2]) { 2669 do_addi_32: 2670 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2); 2671 } else { 2672 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2673 } 2674 break; 2675 case INDEX_op_sub_i32: 2676 a0 = args[0], a1 = args[1], a2 = args[2]; 2677 if (const_args[1]) { 2678 if (const_args[2]) { 2679 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2); 2680 } else { 2681 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2682 } 2683 } else if (const_args[2]) { 2684 a2 = -a2; 2685 goto do_addi_32; 2686 } else { 2687 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2688 } 2689 break; 2690 2691 case INDEX_op_and_i32: 2692 a0 = args[0], a1 = args[1], a2 = args[2]; 2693 if (const_args[2]) { 2694 tcg_out_andi32(s, a0, a1, a2); 2695 } else { 2696 tcg_out32(s, AND | SAB(a1, a0, a2)); 2697 } 2698 break; 2699 case INDEX_op_and_i64: 2700 a0 = args[0], a1 = args[1], a2 = args[2]; 2701 if (const_args[2]) { 2702 tcg_out_andi64(s, a0, a1, a2); 2703 } else { 2704 tcg_out32(s, AND | SAB(a1, a0, a2)); 2705 } 2706 break; 2707 case INDEX_op_or_i64: 2708 case INDEX_op_or_i32: 2709 a0 = args[0], a1 = args[1], a2 = args[2]; 2710 if (const_args[2]) { 2711 tcg_out_ori32(s, a0, a1, a2); 2712 } else { 2713 tcg_out32(s, OR | SAB(a1, a0, a2)); 2714 } 2715 break; 2716 case INDEX_op_xor_i64: 2717 case INDEX_op_xor_i32: 2718 a0 = args[0], a1 = args[1], a2 = args[2]; 2719 if (const_args[2]) { 2720 tcg_out_xori32(s, a0, a1, a2); 2721 } else { 2722 tcg_out32(s, XOR | SAB(a1, a0, a2)); 2723 } 2724 break; 2725 case INDEX_op_andc_i32: 2726 a0 = args[0], a1 = args[1], a2 = args[2]; 2727 if (const_args[2]) { 2728 tcg_out_andi32(s, a0, a1, ~a2); 2729 } else { 2730 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2731 } 2732 break; 2733 case INDEX_op_andc_i64: 2734 a0 = args[0], a1 = args[1], a2 = args[2]; 2735 if (const_args[2]) { 2736 tcg_out_andi64(s, a0, a1, ~a2); 2737 } else { 2738 tcg_out32(s, ANDC | SAB(a1, a0, a2)); 2739 } 2740 break; 2741 case INDEX_op_orc_i32: 2742 if (const_args[2]) { 2743 tcg_out_ori32(s, args[0], args[1], ~args[2]); 2744 break; 2745 } 2746 /* FALLTHRU */ 2747 case INDEX_op_orc_i64: 2748 tcg_out32(s, ORC | SAB(args[1], args[0], args[2])); 2749 break; 2750 case INDEX_op_eqv_i32: 2751 if (const_args[2]) { 2752 tcg_out_xori32(s, args[0], args[1], ~args[2]); 2753 break; 2754 } 2755 /* FALLTHRU */ 2756 case INDEX_op_eqv_i64: 2757 tcg_out32(s, EQV | SAB(args[1], args[0], args[2])); 2758 break; 2759 case INDEX_op_nand_i32: 2760 case INDEX_op_nand_i64: 2761 tcg_out32(s, NAND | SAB(args[1], args[0], args[2])); 2762 break; 2763 case INDEX_op_nor_i32: 2764 case INDEX_op_nor_i64: 2765 tcg_out32(s, NOR | SAB(args[1], args[0], args[2])); 2766 break; 2767 2768 case INDEX_op_clz_i32: 2769 tcg_out_cntxz(s, TCG_TYPE_I32, CNTLZW, args[0], args[1], 2770 args[2], const_args[2]); 2771 break; 2772 case INDEX_op_ctz_i32: 2773 tcg_out_cntxz(s, TCG_TYPE_I32, CNTTZW, args[0], args[1], 2774 args[2], const_args[2]); 2775 break; 2776 case INDEX_op_ctpop_i32: 2777 tcg_out32(s, CNTPOPW | SAB(args[1], args[0], 0)); 2778 break; 2779 2780 case INDEX_op_clz_i64: 2781 tcg_out_cntxz(s, TCG_TYPE_I64, CNTLZD, args[0], args[1], 2782 args[2], const_args[2]); 2783 break; 2784 case INDEX_op_ctz_i64: 2785 tcg_out_cntxz(s, TCG_TYPE_I64, CNTTZD, args[0], args[1], 2786 args[2], const_args[2]); 2787 break; 2788 case INDEX_op_ctpop_i64: 2789 tcg_out32(s, CNTPOPD | SAB(args[1], args[0], 0)); 2790 break; 2791 2792 case INDEX_op_mul_i32: 2793 a0 = args[0], a1 = args[1], a2 = args[2]; 2794 if (const_args[2]) { 2795 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2796 } else { 2797 tcg_out32(s, MULLW | TAB(a0, a1, a2)); 2798 } 2799 break; 2800 2801 case INDEX_op_div_i32: 2802 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2])); 2803 break; 2804 2805 case INDEX_op_divu_i32: 2806 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2])); 2807 break; 2808 2809 case INDEX_op_rem_i32: 2810 tcg_out32(s, MODSW | TAB(args[0], args[1], args[2])); 2811 break; 2812 2813 case INDEX_op_remu_i32: 2814 tcg_out32(s, MODUW | TAB(args[0], args[1], args[2])); 2815 break; 2816 2817 case INDEX_op_shl_i32: 2818 if (const_args[2]) { 2819 /* Limit immediate shift count lest we create an illegal insn. */ 2820 tcg_out_shli32(s, args[0], args[1], args[2] & 31); 2821 } else { 2822 tcg_out32(s, SLW | SAB(args[1], args[0], args[2])); 2823 } 2824 break; 2825 case INDEX_op_shr_i32: 2826 if (const_args[2]) { 2827 /* Limit immediate shift count lest we create an illegal insn. */ 2828 tcg_out_shri32(s, args[0], args[1], args[2] & 31); 2829 } else { 2830 tcg_out32(s, SRW | SAB(args[1], args[0], args[2])); 2831 } 2832 break; 2833 case INDEX_op_sar_i32: 2834 if (const_args[2]) { 2835 tcg_out_sari32(s, args[0], args[1], args[2]); 2836 } else { 2837 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2])); 2838 } 2839 break; 2840 case INDEX_op_rotl_i32: 2841 if (const_args[2]) { 2842 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31); 2843 } else { 2844 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2]) 2845 | MB(0) | ME(31)); 2846 } 2847 break; 2848 case INDEX_op_rotr_i32: 2849 if (const_args[2]) { 2850 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31); 2851 } else { 2852 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32)); 2853 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0) 2854 | MB(0) | ME(31)); 2855 } 2856 break; 2857 2858 case INDEX_op_brcond_i32: 2859 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2860 arg_label(args[3]), TCG_TYPE_I32); 2861 break; 2862 case INDEX_op_brcond_i64: 2863 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1], 2864 arg_label(args[3]), TCG_TYPE_I64); 2865 break; 2866 case INDEX_op_brcond2_i32: 2867 tcg_out_brcond2(s, args, const_args); 2868 break; 2869 2870 case INDEX_op_neg_i32: 2871 case INDEX_op_neg_i64: 2872 tcg_out32(s, NEG | RT(args[0]) | RA(args[1])); 2873 break; 2874 2875 case INDEX_op_not_i32: 2876 case INDEX_op_not_i64: 2877 tcg_out32(s, NOR | SAB(args[1], args[0], args[1])); 2878 break; 2879 2880 case INDEX_op_add_i64: 2881 a0 = args[0], a1 = args[1], a2 = args[2]; 2882 if (const_args[2]) { 2883 do_addi_64: 2884 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2); 2885 } else { 2886 tcg_out32(s, ADD | TAB(a0, a1, a2)); 2887 } 2888 break; 2889 case INDEX_op_sub_i64: 2890 a0 = args[0], a1 = args[1], a2 = args[2]; 2891 if (const_args[1]) { 2892 if (const_args[2]) { 2893 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2); 2894 } else { 2895 tcg_out32(s, SUBFIC | TAI(a0, a2, a1)); 2896 } 2897 } else if (const_args[2]) { 2898 a2 = -a2; 2899 goto do_addi_64; 2900 } else { 2901 tcg_out32(s, SUBF | TAB(a0, a2, a1)); 2902 } 2903 break; 2904 2905 case INDEX_op_shl_i64: 2906 if (const_args[2]) { 2907 /* Limit immediate shift count lest we create an illegal insn. */ 2908 tcg_out_shli64(s, args[0], args[1], args[2] & 63); 2909 } else { 2910 tcg_out32(s, SLD | SAB(args[1], args[0], args[2])); 2911 } 2912 break; 2913 case INDEX_op_shr_i64: 2914 if (const_args[2]) { 2915 /* Limit immediate shift count lest we create an illegal insn. */ 2916 tcg_out_shri64(s, args[0], args[1], args[2] & 63); 2917 } else { 2918 tcg_out32(s, SRD | SAB(args[1], args[0], args[2])); 2919 } 2920 break; 2921 case INDEX_op_sar_i64: 2922 if (const_args[2]) { 2923 tcg_out_sari64(s, args[0], args[1], args[2]); 2924 } else { 2925 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2])); 2926 } 2927 break; 2928 case INDEX_op_rotl_i64: 2929 if (const_args[2]) { 2930 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0); 2931 } else { 2932 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0)); 2933 } 2934 break; 2935 case INDEX_op_rotr_i64: 2936 if (const_args[2]) { 2937 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0); 2938 } else { 2939 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64)); 2940 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0)); 2941 } 2942 break; 2943 2944 case INDEX_op_mul_i64: 2945 a0 = args[0], a1 = args[1], a2 = args[2]; 2946 if (const_args[2]) { 2947 tcg_out32(s, MULLI | TAI(a0, a1, a2)); 2948 } else { 2949 tcg_out32(s, MULLD | TAB(a0, a1, a2)); 2950 } 2951 break; 2952 case INDEX_op_div_i64: 2953 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2])); 2954 break; 2955 case INDEX_op_divu_i64: 2956 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2])); 2957 break; 2958 case INDEX_op_rem_i64: 2959 tcg_out32(s, MODSD | TAB(args[0], args[1], args[2])); 2960 break; 2961 case INDEX_op_remu_i64: 2962 tcg_out32(s, MODUD | TAB(args[0], args[1], args[2])); 2963 break; 2964 2965 case INDEX_op_qemu_ld_a64_i32: 2966 if (TCG_TARGET_REG_BITS == 32) { 2967 tcg_out_qemu_ld(s, args[0], -1, args[1], args[2], 2968 args[3], TCG_TYPE_I32); 2969 break; 2970 } 2971 /* fall through */ 2972 case INDEX_op_qemu_ld_a32_i32: 2973 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32); 2974 break; 2975 case INDEX_op_qemu_ld_a32_i64: 2976 if (TCG_TARGET_REG_BITS == 64) { 2977 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2978 args[2], TCG_TYPE_I64); 2979 } else { 2980 tcg_out_qemu_ld(s, args[0], args[1], args[2], -1, 2981 args[3], TCG_TYPE_I64); 2982 } 2983 break; 2984 case INDEX_op_qemu_ld_a64_i64: 2985 if (TCG_TARGET_REG_BITS == 64) { 2986 tcg_out_qemu_ld(s, args[0], -1, args[1], -1, 2987 args[2], TCG_TYPE_I64); 2988 } else { 2989 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3], 2990 args[4], TCG_TYPE_I64); 2991 } 2992 break; 2993 case INDEX_op_qemu_ld_a32_i128: 2994 case INDEX_op_qemu_ld_a64_i128: 2995 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 2996 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], true); 2997 break; 2998 2999 case INDEX_op_qemu_st_a64_i32: 3000 if (TCG_TARGET_REG_BITS == 32) { 3001 tcg_out_qemu_st(s, args[0], -1, args[1], args[2], 3002 args[3], TCG_TYPE_I32); 3003 break; 3004 } 3005 /* fall through */ 3006 case INDEX_op_qemu_st_a32_i32: 3007 tcg_out_qemu_st(s, args[0], -1, args[1], -1, args[2], TCG_TYPE_I32); 3008 break; 3009 case INDEX_op_qemu_st_a32_i64: 3010 if (TCG_TARGET_REG_BITS == 64) { 3011 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 3012 args[2], TCG_TYPE_I64); 3013 } else { 3014 tcg_out_qemu_st(s, args[0], args[1], args[2], -1, 3015 args[3], TCG_TYPE_I64); 3016 } 3017 break; 3018 case INDEX_op_qemu_st_a64_i64: 3019 if (TCG_TARGET_REG_BITS == 64) { 3020 tcg_out_qemu_st(s, args[0], -1, args[1], -1, 3021 args[2], TCG_TYPE_I64); 3022 } else { 3023 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3], 3024 args[4], TCG_TYPE_I64); 3025 } 3026 break; 3027 case INDEX_op_qemu_st_a32_i128: 3028 case INDEX_op_qemu_st_a64_i128: 3029 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 3030 tcg_out_qemu_ldst_i128(s, args[0], args[1], args[2], args[3], false); 3031 break; 3032 3033 case INDEX_op_setcond_i32: 3034 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], 3035 const_args[2], false); 3036 break; 3037 case INDEX_op_setcond_i64: 3038 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], 3039 const_args[2], false); 3040 break; 3041 case INDEX_op_negsetcond_i32: 3042 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2], 3043 const_args[2], true); 3044 break; 3045 case INDEX_op_negsetcond_i64: 3046 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2], 3047 const_args[2], true); 3048 break; 3049 case INDEX_op_setcond2_i32: 3050 tcg_out_setcond2(s, args, const_args); 3051 break; 3052 3053 case INDEX_op_bswap16_i32: 3054 case INDEX_op_bswap16_i64: 3055 tcg_out_bswap16(s, args[0], args[1], args[2]); 3056 break; 3057 case INDEX_op_bswap32_i32: 3058 tcg_out_bswap32(s, args[0], args[1], 0); 3059 break; 3060 case INDEX_op_bswap32_i64: 3061 tcg_out_bswap32(s, args[0], args[1], args[2]); 3062 break; 3063 case INDEX_op_bswap64_i64: 3064 tcg_out_bswap64(s, args[0], args[1]); 3065 break; 3066 3067 case INDEX_op_deposit_i32: 3068 if (const_args[2]) { 3069 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3]; 3070 tcg_out_andi32(s, args[0], args[0], ~mask); 3071 } else { 3072 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3], 3073 32 - args[3] - args[4], 31 - args[3]); 3074 } 3075 break; 3076 case INDEX_op_deposit_i64: 3077 if (const_args[2]) { 3078 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3]; 3079 tcg_out_andi64(s, args[0], args[0], ~mask); 3080 } else { 3081 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3], 3082 64 - args[3] - args[4]); 3083 } 3084 break; 3085 3086 case INDEX_op_extract_i32: 3087 tcg_out_rlw(s, RLWINM, args[0], args[1], 3088 32 - args[2], 32 - args[3], 31); 3089 break; 3090 case INDEX_op_extract_i64: 3091 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 64 - args[3]); 3092 break; 3093 3094 case INDEX_op_movcond_i32: 3095 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2], 3096 args[3], args[4], const_args[2]); 3097 break; 3098 case INDEX_op_movcond_i64: 3099 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2], 3100 args[3], args[4], const_args[2]); 3101 break; 3102 3103#if TCG_TARGET_REG_BITS == 64 3104 case INDEX_op_add2_i64: 3105#else 3106 case INDEX_op_add2_i32: 3107#endif 3108 /* Note that the CA bit is defined based on the word size of the 3109 environment. So in 64-bit mode it's always carry-out of bit 63. 3110 The fallback code using deposit works just as well for 32-bit. */ 3111 a0 = args[0], a1 = args[1]; 3112 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) { 3113 a0 = TCG_REG_R0; 3114 } 3115 if (const_args[4]) { 3116 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4])); 3117 } else { 3118 tcg_out32(s, ADDC | TAB(a0, args[2], args[4])); 3119 } 3120 if (const_args[5]) { 3121 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3])); 3122 } else { 3123 tcg_out32(s, ADDE | TAB(a1, args[3], args[5])); 3124 } 3125 if (a0 != args[0]) { 3126 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3127 } 3128 break; 3129 3130#if TCG_TARGET_REG_BITS == 64 3131 case INDEX_op_sub2_i64: 3132#else 3133 case INDEX_op_sub2_i32: 3134#endif 3135 a0 = args[0], a1 = args[1]; 3136 if (a0 == args[5] || (!const_args[3] && a0 == args[3])) { 3137 a0 = TCG_REG_R0; 3138 } 3139 if (const_args[2]) { 3140 tcg_out32(s, SUBFIC | TAI(a0, args[4], args[2])); 3141 } else { 3142 tcg_out32(s, SUBFC | TAB(a0, args[4], args[2])); 3143 } 3144 if (const_args[3]) { 3145 tcg_out32(s, (args[3] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5])); 3146 } else { 3147 tcg_out32(s, SUBFE | TAB(a1, args[5], args[3])); 3148 } 3149 if (a0 != args[0]) { 3150 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0); 3151 } 3152 break; 3153 3154 case INDEX_op_muluh_i32: 3155 tcg_out32(s, MULHWU | TAB(args[0], args[1], args[2])); 3156 break; 3157 case INDEX_op_mulsh_i32: 3158 tcg_out32(s, MULHW | TAB(args[0], args[1], args[2])); 3159 break; 3160 case INDEX_op_muluh_i64: 3161 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2])); 3162 break; 3163 case INDEX_op_mulsh_i64: 3164 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2])); 3165 break; 3166 3167 case INDEX_op_mb: 3168 tcg_out_mb(s, args[0]); 3169 break; 3170 3171 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 3172 case INDEX_op_mov_i64: 3173 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 3174 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 3175 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 3176 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 3177 case INDEX_op_ext8s_i64: 3178 case INDEX_op_ext8u_i32: 3179 case INDEX_op_ext8u_i64: 3180 case INDEX_op_ext16s_i32: 3181 case INDEX_op_ext16s_i64: 3182 case INDEX_op_ext16u_i32: 3183 case INDEX_op_ext16u_i64: 3184 case INDEX_op_ext32s_i64: 3185 case INDEX_op_ext32u_i64: 3186 case INDEX_op_ext_i32_i64: 3187 case INDEX_op_extu_i32_i64: 3188 case INDEX_op_extrl_i64_i32: 3189 default: 3190 g_assert_not_reached(); 3191 } 3192} 3193 3194int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 3195{ 3196 switch (opc) { 3197 case INDEX_op_and_vec: 3198 case INDEX_op_or_vec: 3199 case INDEX_op_xor_vec: 3200 case INDEX_op_andc_vec: 3201 case INDEX_op_not_vec: 3202 case INDEX_op_nor_vec: 3203 case INDEX_op_eqv_vec: 3204 case INDEX_op_nand_vec: 3205 return 1; 3206 case INDEX_op_orc_vec: 3207 return have_isa_2_07; 3208 case INDEX_op_add_vec: 3209 case INDEX_op_sub_vec: 3210 case INDEX_op_smax_vec: 3211 case INDEX_op_smin_vec: 3212 case INDEX_op_umax_vec: 3213 case INDEX_op_umin_vec: 3214 case INDEX_op_shlv_vec: 3215 case INDEX_op_shrv_vec: 3216 case INDEX_op_sarv_vec: 3217 case INDEX_op_rotlv_vec: 3218 return vece <= MO_32 || have_isa_2_07; 3219 case INDEX_op_ssadd_vec: 3220 case INDEX_op_sssub_vec: 3221 case INDEX_op_usadd_vec: 3222 case INDEX_op_ussub_vec: 3223 return vece <= MO_32; 3224 case INDEX_op_cmp_vec: 3225 case INDEX_op_shli_vec: 3226 case INDEX_op_shri_vec: 3227 case INDEX_op_sari_vec: 3228 case INDEX_op_rotli_vec: 3229 return vece <= MO_32 || have_isa_2_07 ? -1 : 0; 3230 case INDEX_op_neg_vec: 3231 return vece >= MO_32 && have_isa_3_00; 3232 case INDEX_op_mul_vec: 3233 switch (vece) { 3234 case MO_8: 3235 case MO_16: 3236 return -1; 3237 case MO_32: 3238 return have_isa_2_07 ? 1 : -1; 3239 case MO_64: 3240 return have_isa_3_10; 3241 } 3242 return 0; 3243 case INDEX_op_bitsel_vec: 3244 return have_vsx; 3245 case INDEX_op_rotrv_vec: 3246 return -1; 3247 default: 3248 return 0; 3249 } 3250} 3251 3252static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 3253 TCGReg dst, TCGReg src) 3254{ 3255 tcg_debug_assert(dst >= TCG_REG_V0); 3256 3257 /* Splat from integer reg allowed via constraints for v3.00. */ 3258 if (src < TCG_REG_V0) { 3259 tcg_debug_assert(have_isa_3_00); 3260 switch (vece) { 3261 case MO_64: 3262 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src)); 3263 return true; 3264 case MO_32: 3265 tcg_out32(s, MTVSRWS | VRT(dst) | RA(src)); 3266 return true; 3267 default: 3268 /* Fail, so that we fall back on either dupm or mov+dup. */ 3269 return false; 3270 } 3271 } 3272 3273 /* 3274 * Recall we use (or emulate) VSX integer loads, so the integer is 3275 * right justified within the left (zero-index) double-word. 3276 */ 3277 switch (vece) { 3278 case MO_8: 3279 tcg_out32(s, VSPLTB | VRT(dst) | VRB(src) | (7 << 16)); 3280 break; 3281 case MO_16: 3282 tcg_out32(s, VSPLTH | VRT(dst) | VRB(src) | (3 << 16)); 3283 break; 3284 case MO_32: 3285 tcg_out32(s, VSPLTW | VRT(dst) | VRB(src) | (1 << 16)); 3286 break; 3287 case MO_64: 3288 if (have_vsx) { 3289 tcg_out32(s, XXPERMDI | VRT(dst) | VRA(src) | VRB(src)); 3290 break; 3291 } 3292 tcg_out_vsldoi(s, TCG_VEC_TMP1, src, src, 8); 3293 tcg_out_vsldoi(s, dst, TCG_VEC_TMP1, src, 8); 3294 break; 3295 default: 3296 g_assert_not_reached(); 3297 } 3298 return true; 3299} 3300 3301static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 3302 TCGReg out, TCGReg base, intptr_t offset) 3303{ 3304 int elt; 3305 3306 tcg_debug_assert(out >= TCG_REG_V0); 3307 switch (vece) { 3308 case MO_8: 3309 if (have_isa_3_00) { 3310 tcg_out_mem_long(s, LXV, LVX, out, base, offset & -16); 3311 } else { 3312 tcg_out_mem_long(s, 0, LVEBX, out, base, offset); 3313 } 3314 elt = extract32(offset, 0, 4); 3315#if !HOST_BIG_ENDIAN 3316 elt ^= 15; 3317#endif 3318 tcg_out32(s, VSPLTB | VRT(out) | VRB(out) | (elt << 16)); 3319 break; 3320 case MO_16: 3321 tcg_debug_assert((offset & 1) == 0); 3322 if (have_isa_3_00) { 3323 tcg_out_mem_long(s, LXV | 8, LVX, out, base, offset & -16); 3324 } else { 3325 tcg_out_mem_long(s, 0, LVEHX, out, base, offset); 3326 } 3327 elt = extract32(offset, 1, 3); 3328#if !HOST_BIG_ENDIAN 3329 elt ^= 7; 3330#endif 3331 tcg_out32(s, VSPLTH | VRT(out) | VRB(out) | (elt << 16)); 3332 break; 3333 case MO_32: 3334 if (have_isa_3_00) { 3335 tcg_out_mem_long(s, 0, LXVWSX, out, base, offset); 3336 break; 3337 } 3338 tcg_debug_assert((offset & 3) == 0); 3339 tcg_out_mem_long(s, 0, LVEWX, out, base, offset); 3340 elt = extract32(offset, 2, 2); 3341#if !HOST_BIG_ENDIAN 3342 elt ^= 3; 3343#endif 3344 tcg_out32(s, VSPLTW | VRT(out) | VRB(out) | (elt << 16)); 3345 break; 3346 case MO_64: 3347 if (have_vsx) { 3348 tcg_out_mem_long(s, 0, LXVDSX, out, base, offset); 3349 break; 3350 } 3351 tcg_debug_assert((offset & 7) == 0); 3352 tcg_out_mem_long(s, 0, LVX, out, base, offset & -16); 3353 tcg_out_vsldoi(s, TCG_VEC_TMP1, out, out, 8); 3354 elt = extract32(offset, 3, 1); 3355#if !HOST_BIG_ENDIAN 3356 elt = !elt; 3357#endif 3358 if (elt) { 3359 tcg_out_vsldoi(s, out, out, TCG_VEC_TMP1, 8); 3360 } else { 3361 tcg_out_vsldoi(s, out, TCG_VEC_TMP1, out, 8); 3362 } 3363 break; 3364 default: 3365 g_assert_not_reached(); 3366 } 3367 return true; 3368} 3369 3370static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 3371 unsigned vecl, unsigned vece, 3372 const TCGArg args[TCG_MAX_OP_ARGS], 3373 const int const_args[TCG_MAX_OP_ARGS]) 3374{ 3375 static const uint32_t 3376 add_op[4] = { VADDUBM, VADDUHM, VADDUWM, VADDUDM }, 3377 sub_op[4] = { VSUBUBM, VSUBUHM, VSUBUWM, VSUBUDM }, 3378 mul_op[4] = { 0, 0, VMULUWM, VMULLD }, 3379 neg_op[4] = { 0, 0, VNEGW, VNEGD }, 3380 eq_op[4] = { VCMPEQUB, VCMPEQUH, VCMPEQUW, VCMPEQUD }, 3381 ne_op[4] = { VCMPNEB, VCMPNEH, VCMPNEW, 0 }, 3382 gts_op[4] = { VCMPGTSB, VCMPGTSH, VCMPGTSW, VCMPGTSD }, 3383 gtu_op[4] = { VCMPGTUB, VCMPGTUH, VCMPGTUW, VCMPGTUD }, 3384 ssadd_op[4] = { VADDSBS, VADDSHS, VADDSWS, 0 }, 3385 usadd_op[4] = { VADDUBS, VADDUHS, VADDUWS, 0 }, 3386 sssub_op[4] = { VSUBSBS, VSUBSHS, VSUBSWS, 0 }, 3387 ussub_op[4] = { VSUBUBS, VSUBUHS, VSUBUWS, 0 }, 3388 umin_op[4] = { VMINUB, VMINUH, VMINUW, VMINUD }, 3389 smin_op[4] = { VMINSB, VMINSH, VMINSW, VMINSD }, 3390 umax_op[4] = { VMAXUB, VMAXUH, VMAXUW, VMAXUD }, 3391 smax_op[4] = { VMAXSB, VMAXSH, VMAXSW, VMAXSD }, 3392 shlv_op[4] = { VSLB, VSLH, VSLW, VSLD }, 3393 shrv_op[4] = { VSRB, VSRH, VSRW, VSRD }, 3394 sarv_op[4] = { VSRAB, VSRAH, VSRAW, VSRAD }, 3395 mrgh_op[4] = { VMRGHB, VMRGHH, VMRGHW, 0 }, 3396 mrgl_op[4] = { VMRGLB, VMRGLH, VMRGLW, 0 }, 3397 muleu_op[4] = { VMULEUB, VMULEUH, VMULEUW, 0 }, 3398 mulou_op[4] = { VMULOUB, VMULOUH, VMULOUW, 0 }, 3399 pkum_op[4] = { VPKUHUM, VPKUWUM, 0, 0 }, 3400 rotl_op[4] = { VRLB, VRLH, VRLW, VRLD }; 3401 3402 TCGType type = vecl + TCG_TYPE_V64; 3403 TCGArg a0 = args[0], a1 = args[1], a2 = args[2]; 3404 uint32_t insn; 3405 3406 switch (opc) { 3407 case INDEX_op_ld_vec: 3408 tcg_out_ld(s, type, a0, a1, a2); 3409 return; 3410 case INDEX_op_st_vec: 3411 tcg_out_st(s, type, a0, a1, a2); 3412 return; 3413 case INDEX_op_dupm_vec: 3414 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 3415 return; 3416 3417 case INDEX_op_add_vec: 3418 insn = add_op[vece]; 3419 break; 3420 case INDEX_op_sub_vec: 3421 insn = sub_op[vece]; 3422 break; 3423 case INDEX_op_neg_vec: 3424 insn = neg_op[vece]; 3425 a2 = a1; 3426 a1 = 0; 3427 break; 3428 case INDEX_op_mul_vec: 3429 insn = mul_op[vece]; 3430 break; 3431 case INDEX_op_ssadd_vec: 3432 insn = ssadd_op[vece]; 3433 break; 3434 case INDEX_op_sssub_vec: 3435 insn = sssub_op[vece]; 3436 break; 3437 case INDEX_op_usadd_vec: 3438 insn = usadd_op[vece]; 3439 break; 3440 case INDEX_op_ussub_vec: 3441 insn = ussub_op[vece]; 3442 break; 3443 case INDEX_op_smin_vec: 3444 insn = smin_op[vece]; 3445 break; 3446 case INDEX_op_umin_vec: 3447 insn = umin_op[vece]; 3448 break; 3449 case INDEX_op_smax_vec: 3450 insn = smax_op[vece]; 3451 break; 3452 case INDEX_op_umax_vec: 3453 insn = umax_op[vece]; 3454 break; 3455 case INDEX_op_shlv_vec: 3456 insn = shlv_op[vece]; 3457 break; 3458 case INDEX_op_shrv_vec: 3459 insn = shrv_op[vece]; 3460 break; 3461 case INDEX_op_sarv_vec: 3462 insn = sarv_op[vece]; 3463 break; 3464 case INDEX_op_and_vec: 3465 insn = VAND; 3466 break; 3467 case INDEX_op_or_vec: 3468 insn = VOR; 3469 break; 3470 case INDEX_op_xor_vec: 3471 insn = VXOR; 3472 break; 3473 case INDEX_op_andc_vec: 3474 insn = VANDC; 3475 break; 3476 case INDEX_op_not_vec: 3477 insn = VNOR; 3478 a2 = a1; 3479 break; 3480 case INDEX_op_orc_vec: 3481 insn = VORC; 3482 break; 3483 case INDEX_op_nand_vec: 3484 insn = VNAND; 3485 break; 3486 case INDEX_op_nor_vec: 3487 insn = VNOR; 3488 break; 3489 case INDEX_op_eqv_vec: 3490 insn = VEQV; 3491 break; 3492 3493 case INDEX_op_cmp_vec: 3494 switch (args[3]) { 3495 case TCG_COND_EQ: 3496 insn = eq_op[vece]; 3497 break; 3498 case TCG_COND_NE: 3499 insn = ne_op[vece]; 3500 break; 3501 case TCG_COND_GT: 3502 insn = gts_op[vece]; 3503 break; 3504 case TCG_COND_GTU: 3505 insn = gtu_op[vece]; 3506 break; 3507 default: 3508 g_assert_not_reached(); 3509 } 3510 break; 3511 3512 case INDEX_op_bitsel_vec: 3513 tcg_out32(s, XXSEL | VRT(a0) | VRC(a1) | VRB(a2) | VRA(args[3])); 3514 return; 3515 3516 case INDEX_op_dup2_vec: 3517 assert(TCG_TARGET_REG_BITS == 32); 3518 /* With inputs a1 = xLxx, a2 = xHxx */ 3519 tcg_out32(s, VMRGHW | VRT(a0) | VRA(a2) | VRB(a1)); /* a0 = xxHL */ 3520 tcg_out_vsldoi(s, TCG_VEC_TMP1, a0, a0, 8); /* tmp = HLxx */ 3521 tcg_out_vsldoi(s, a0, a0, TCG_VEC_TMP1, 8); /* a0 = HLHL */ 3522 return; 3523 3524 case INDEX_op_ppc_mrgh_vec: 3525 insn = mrgh_op[vece]; 3526 break; 3527 case INDEX_op_ppc_mrgl_vec: 3528 insn = mrgl_op[vece]; 3529 break; 3530 case INDEX_op_ppc_muleu_vec: 3531 insn = muleu_op[vece]; 3532 break; 3533 case INDEX_op_ppc_mulou_vec: 3534 insn = mulou_op[vece]; 3535 break; 3536 case INDEX_op_ppc_pkum_vec: 3537 insn = pkum_op[vece]; 3538 break; 3539 case INDEX_op_rotlv_vec: 3540 insn = rotl_op[vece]; 3541 break; 3542 case INDEX_op_ppc_msum_vec: 3543 tcg_debug_assert(vece == MO_16); 3544 tcg_out32(s, VMSUMUHM | VRT(a0) | VRA(a1) | VRB(a2) | VRC(args[3])); 3545 return; 3546 3547 case INDEX_op_mov_vec: /* Always emitted via tcg_out_mov. */ 3548 case INDEX_op_dup_vec: /* Always emitted via tcg_out_dup_vec. */ 3549 default: 3550 g_assert_not_reached(); 3551 } 3552 3553 tcg_debug_assert(insn != 0); 3554 tcg_out32(s, insn | VRT(a0) | VRA(a1) | VRB(a2)); 3555} 3556 3557static void expand_vec_shi(TCGType type, unsigned vece, TCGv_vec v0, 3558 TCGv_vec v1, TCGArg imm, TCGOpcode opci) 3559{ 3560 TCGv_vec t1; 3561 3562 if (vece == MO_32) { 3563 /* 3564 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3565 * So using negative numbers gets us the 4th bit easily. 3566 */ 3567 imm = sextract32(imm, 0, 5); 3568 } else { 3569 imm &= (8 << vece) - 1; 3570 } 3571 3572 /* Splat w/bytes for xxspltib when 2.07 allows MO_64. */ 3573 t1 = tcg_constant_vec(type, MO_8, imm); 3574 vec_gen_3(opci, type, vece, tcgv_vec_arg(v0), 3575 tcgv_vec_arg(v1), tcgv_vec_arg(t1)); 3576} 3577 3578static void expand_vec_cmp(TCGType type, unsigned vece, TCGv_vec v0, 3579 TCGv_vec v1, TCGv_vec v2, TCGCond cond) 3580{ 3581 bool need_swap = false, need_inv = false; 3582 3583 tcg_debug_assert(vece <= MO_32 || have_isa_2_07); 3584 3585 switch (cond) { 3586 case TCG_COND_EQ: 3587 case TCG_COND_GT: 3588 case TCG_COND_GTU: 3589 break; 3590 case TCG_COND_NE: 3591 if (have_isa_3_00 && vece <= MO_32) { 3592 break; 3593 } 3594 /* fall through */ 3595 case TCG_COND_LE: 3596 case TCG_COND_LEU: 3597 need_inv = true; 3598 break; 3599 case TCG_COND_LT: 3600 case TCG_COND_LTU: 3601 need_swap = true; 3602 break; 3603 case TCG_COND_GE: 3604 case TCG_COND_GEU: 3605 need_swap = need_inv = true; 3606 break; 3607 default: 3608 g_assert_not_reached(); 3609 } 3610 3611 if (need_inv) { 3612 cond = tcg_invert_cond(cond); 3613 } 3614 if (need_swap) { 3615 TCGv_vec t1; 3616 t1 = v1, v1 = v2, v2 = t1; 3617 cond = tcg_swap_cond(cond); 3618 } 3619 3620 vec_gen_4(INDEX_op_cmp_vec, type, vece, tcgv_vec_arg(v0), 3621 tcgv_vec_arg(v1), tcgv_vec_arg(v2), cond); 3622 3623 if (need_inv) { 3624 tcg_gen_not_vec(vece, v0, v0); 3625 } 3626} 3627 3628static void expand_vec_mul(TCGType type, unsigned vece, TCGv_vec v0, 3629 TCGv_vec v1, TCGv_vec v2) 3630{ 3631 TCGv_vec t1 = tcg_temp_new_vec(type); 3632 TCGv_vec t2 = tcg_temp_new_vec(type); 3633 TCGv_vec c0, c16; 3634 3635 switch (vece) { 3636 case MO_8: 3637 case MO_16: 3638 vec_gen_3(INDEX_op_ppc_muleu_vec, type, vece, tcgv_vec_arg(t1), 3639 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3640 vec_gen_3(INDEX_op_ppc_mulou_vec, type, vece, tcgv_vec_arg(t2), 3641 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3642 vec_gen_3(INDEX_op_ppc_mrgh_vec, type, vece + 1, tcgv_vec_arg(v0), 3643 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3644 vec_gen_3(INDEX_op_ppc_mrgl_vec, type, vece + 1, tcgv_vec_arg(t1), 3645 tcgv_vec_arg(t1), tcgv_vec_arg(t2)); 3646 vec_gen_3(INDEX_op_ppc_pkum_vec, type, vece, tcgv_vec_arg(v0), 3647 tcgv_vec_arg(v0), tcgv_vec_arg(t1)); 3648 break; 3649 3650 case MO_32: 3651 tcg_debug_assert(!have_isa_2_07); 3652 /* 3653 * Only 5 bits are significant, and VSPLTISB can represent -16..15. 3654 * So using -16 is a quick way to represent 16. 3655 */ 3656 c16 = tcg_constant_vec(type, MO_8, -16); 3657 c0 = tcg_constant_vec(type, MO_8, 0); 3658 3659 vec_gen_3(INDEX_op_rotlv_vec, type, MO_32, tcgv_vec_arg(t1), 3660 tcgv_vec_arg(v2), tcgv_vec_arg(c16)); 3661 vec_gen_3(INDEX_op_ppc_mulou_vec, type, MO_16, tcgv_vec_arg(t2), 3662 tcgv_vec_arg(v1), tcgv_vec_arg(v2)); 3663 vec_gen_4(INDEX_op_ppc_msum_vec, type, MO_16, tcgv_vec_arg(t1), 3664 tcgv_vec_arg(v1), tcgv_vec_arg(t1), tcgv_vec_arg(c0)); 3665 vec_gen_3(INDEX_op_shlv_vec, type, MO_32, tcgv_vec_arg(t1), 3666 tcgv_vec_arg(t1), tcgv_vec_arg(c16)); 3667 tcg_gen_add_vec(MO_32, v0, t1, t2); 3668 break; 3669 3670 default: 3671 g_assert_not_reached(); 3672 } 3673 tcg_temp_free_vec(t1); 3674 tcg_temp_free_vec(t2); 3675} 3676 3677void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 3678 TCGArg a0, ...) 3679{ 3680 va_list va; 3681 TCGv_vec v0, v1, v2, t0; 3682 TCGArg a2; 3683 3684 va_start(va, a0); 3685 v0 = temp_tcgv_vec(arg_temp(a0)); 3686 v1 = temp_tcgv_vec(arg_temp(va_arg(va, TCGArg))); 3687 a2 = va_arg(va, TCGArg); 3688 3689 switch (opc) { 3690 case INDEX_op_shli_vec: 3691 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shlv_vec); 3692 break; 3693 case INDEX_op_shri_vec: 3694 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_shrv_vec); 3695 break; 3696 case INDEX_op_sari_vec: 3697 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_sarv_vec); 3698 break; 3699 case INDEX_op_rotli_vec: 3700 expand_vec_shi(type, vece, v0, v1, a2, INDEX_op_rotlv_vec); 3701 break; 3702 case INDEX_op_cmp_vec: 3703 v2 = temp_tcgv_vec(arg_temp(a2)); 3704 expand_vec_cmp(type, vece, v0, v1, v2, va_arg(va, TCGArg)); 3705 break; 3706 case INDEX_op_mul_vec: 3707 v2 = temp_tcgv_vec(arg_temp(a2)); 3708 expand_vec_mul(type, vece, v0, v1, v2); 3709 break; 3710 case INDEX_op_rotlv_vec: 3711 v2 = temp_tcgv_vec(arg_temp(a2)); 3712 t0 = tcg_temp_new_vec(type); 3713 tcg_gen_neg_vec(vece, t0, v2); 3714 tcg_gen_rotlv_vec(vece, v0, v1, t0); 3715 tcg_temp_free_vec(t0); 3716 break; 3717 default: 3718 g_assert_not_reached(); 3719 } 3720 va_end(va); 3721} 3722 3723static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 3724{ 3725 switch (op) { 3726 case INDEX_op_goto_ptr: 3727 return C_O0_I1(r); 3728 3729 case INDEX_op_ld8u_i32: 3730 case INDEX_op_ld8s_i32: 3731 case INDEX_op_ld16u_i32: 3732 case INDEX_op_ld16s_i32: 3733 case INDEX_op_ld_i32: 3734 case INDEX_op_ctpop_i32: 3735 case INDEX_op_neg_i32: 3736 case INDEX_op_not_i32: 3737 case INDEX_op_ext8s_i32: 3738 case INDEX_op_ext16s_i32: 3739 case INDEX_op_bswap16_i32: 3740 case INDEX_op_bswap32_i32: 3741 case INDEX_op_extract_i32: 3742 case INDEX_op_ld8u_i64: 3743 case INDEX_op_ld8s_i64: 3744 case INDEX_op_ld16u_i64: 3745 case INDEX_op_ld16s_i64: 3746 case INDEX_op_ld32u_i64: 3747 case INDEX_op_ld32s_i64: 3748 case INDEX_op_ld_i64: 3749 case INDEX_op_ctpop_i64: 3750 case INDEX_op_neg_i64: 3751 case INDEX_op_not_i64: 3752 case INDEX_op_ext8s_i64: 3753 case INDEX_op_ext16s_i64: 3754 case INDEX_op_ext32s_i64: 3755 case INDEX_op_ext_i32_i64: 3756 case INDEX_op_extu_i32_i64: 3757 case INDEX_op_bswap16_i64: 3758 case INDEX_op_bswap32_i64: 3759 case INDEX_op_bswap64_i64: 3760 case INDEX_op_extract_i64: 3761 return C_O1_I1(r, r); 3762 3763 case INDEX_op_st8_i32: 3764 case INDEX_op_st16_i32: 3765 case INDEX_op_st_i32: 3766 case INDEX_op_st8_i64: 3767 case INDEX_op_st16_i64: 3768 case INDEX_op_st32_i64: 3769 case INDEX_op_st_i64: 3770 return C_O0_I2(r, r); 3771 3772 case INDEX_op_add_i32: 3773 case INDEX_op_and_i32: 3774 case INDEX_op_or_i32: 3775 case INDEX_op_xor_i32: 3776 case INDEX_op_andc_i32: 3777 case INDEX_op_orc_i32: 3778 case INDEX_op_eqv_i32: 3779 case INDEX_op_shl_i32: 3780 case INDEX_op_shr_i32: 3781 case INDEX_op_sar_i32: 3782 case INDEX_op_rotl_i32: 3783 case INDEX_op_rotr_i32: 3784 case INDEX_op_setcond_i32: 3785 case INDEX_op_negsetcond_i32: 3786 case INDEX_op_and_i64: 3787 case INDEX_op_andc_i64: 3788 case INDEX_op_shl_i64: 3789 case INDEX_op_shr_i64: 3790 case INDEX_op_sar_i64: 3791 case INDEX_op_rotl_i64: 3792 case INDEX_op_rotr_i64: 3793 case INDEX_op_setcond_i64: 3794 case INDEX_op_negsetcond_i64: 3795 return C_O1_I2(r, r, ri); 3796 3797 case INDEX_op_mul_i32: 3798 case INDEX_op_mul_i64: 3799 return C_O1_I2(r, r, rI); 3800 3801 case INDEX_op_div_i32: 3802 case INDEX_op_divu_i32: 3803 case INDEX_op_rem_i32: 3804 case INDEX_op_remu_i32: 3805 case INDEX_op_nand_i32: 3806 case INDEX_op_nor_i32: 3807 case INDEX_op_muluh_i32: 3808 case INDEX_op_mulsh_i32: 3809 case INDEX_op_orc_i64: 3810 case INDEX_op_eqv_i64: 3811 case INDEX_op_nand_i64: 3812 case INDEX_op_nor_i64: 3813 case INDEX_op_div_i64: 3814 case INDEX_op_divu_i64: 3815 case INDEX_op_rem_i64: 3816 case INDEX_op_remu_i64: 3817 case INDEX_op_mulsh_i64: 3818 case INDEX_op_muluh_i64: 3819 return C_O1_I2(r, r, r); 3820 3821 case INDEX_op_sub_i32: 3822 return C_O1_I2(r, rI, ri); 3823 case INDEX_op_add_i64: 3824 return C_O1_I2(r, r, rT); 3825 case INDEX_op_or_i64: 3826 case INDEX_op_xor_i64: 3827 return C_O1_I2(r, r, rU); 3828 case INDEX_op_sub_i64: 3829 return C_O1_I2(r, rI, rT); 3830 case INDEX_op_clz_i32: 3831 case INDEX_op_ctz_i32: 3832 case INDEX_op_clz_i64: 3833 case INDEX_op_ctz_i64: 3834 return C_O1_I2(r, r, rZW); 3835 3836 case INDEX_op_brcond_i32: 3837 case INDEX_op_brcond_i64: 3838 return C_O0_I2(r, ri); 3839 3840 case INDEX_op_movcond_i32: 3841 case INDEX_op_movcond_i64: 3842 return C_O1_I4(r, r, ri, rZ, rZ); 3843 case INDEX_op_deposit_i32: 3844 case INDEX_op_deposit_i64: 3845 return C_O1_I2(r, 0, rZ); 3846 case INDEX_op_brcond2_i32: 3847 return C_O0_I4(r, r, ri, ri); 3848 case INDEX_op_setcond2_i32: 3849 return C_O1_I4(r, r, r, ri, ri); 3850 case INDEX_op_add2_i64: 3851 case INDEX_op_add2_i32: 3852 return C_O2_I4(r, r, r, r, rI, rZM); 3853 case INDEX_op_sub2_i64: 3854 case INDEX_op_sub2_i32: 3855 return C_O2_I4(r, r, rI, rZM, r, r); 3856 3857 case INDEX_op_qemu_ld_a32_i32: 3858 return C_O1_I1(r, r); 3859 case INDEX_op_qemu_ld_a64_i32: 3860 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r); 3861 case INDEX_op_qemu_ld_a32_i64: 3862 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 3863 case INDEX_op_qemu_ld_a64_i64: 3864 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r); 3865 3866 case INDEX_op_qemu_st_a32_i32: 3867 return C_O0_I2(r, r); 3868 case INDEX_op_qemu_st_a64_i32: 3869 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r); 3870 case INDEX_op_qemu_st_a32_i64: 3871 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I3(r, r, r); 3872 case INDEX_op_qemu_st_a64_i64: 3873 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(r, r) : C_O0_I4(r, r, r, r); 3874 3875 case INDEX_op_qemu_ld_a32_i128: 3876 case INDEX_op_qemu_ld_a64_i128: 3877 return C_O2_I1(o, m, r); 3878 case INDEX_op_qemu_st_a32_i128: 3879 case INDEX_op_qemu_st_a64_i128: 3880 return C_O0_I3(o, m, r); 3881 3882 case INDEX_op_add_vec: 3883 case INDEX_op_sub_vec: 3884 case INDEX_op_mul_vec: 3885 case INDEX_op_and_vec: 3886 case INDEX_op_or_vec: 3887 case INDEX_op_xor_vec: 3888 case INDEX_op_andc_vec: 3889 case INDEX_op_orc_vec: 3890 case INDEX_op_nor_vec: 3891 case INDEX_op_eqv_vec: 3892 case INDEX_op_nand_vec: 3893 case INDEX_op_cmp_vec: 3894 case INDEX_op_ssadd_vec: 3895 case INDEX_op_sssub_vec: 3896 case INDEX_op_usadd_vec: 3897 case INDEX_op_ussub_vec: 3898 case INDEX_op_smax_vec: 3899 case INDEX_op_smin_vec: 3900 case INDEX_op_umax_vec: 3901 case INDEX_op_umin_vec: 3902 case INDEX_op_shlv_vec: 3903 case INDEX_op_shrv_vec: 3904 case INDEX_op_sarv_vec: 3905 case INDEX_op_rotlv_vec: 3906 case INDEX_op_rotrv_vec: 3907 case INDEX_op_ppc_mrgh_vec: 3908 case INDEX_op_ppc_mrgl_vec: 3909 case INDEX_op_ppc_muleu_vec: 3910 case INDEX_op_ppc_mulou_vec: 3911 case INDEX_op_ppc_pkum_vec: 3912 case INDEX_op_dup2_vec: 3913 return C_O1_I2(v, v, v); 3914 3915 case INDEX_op_not_vec: 3916 case INDEX_op_neg_vec: 3917 return C_O1_I1(v, v); 3918 3919 case INDEX_op_dup_vec: 3920 return have_isa_3_00 ? C_O1_I1(v, vr) : C_O1_I1(v, v); 3921 3922 case INDEX_op_ld_vec: 3923 case INDEX_op_dupm_vec: 3924 return C_O1_I1(v, r); 3925 3926 case INDEX_op_st_vec: 3927 return C_O0_I2(v, r); 3928 3929 case INDEX_op_bitsel_vec: 3930 case INDEX_op_ppc_msum_vec: 3931 return C_O1_I3(v, v, v, v); 3932 3933 default: 3934 g_assert_not_reached(); 3935 } 3936} 3937 3938static void tcg_target_init(TCGContext *s) 3939{ 3940 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 3941 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 3942 if (have_altivec) { 3943 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull; 3944 tcg_target_available_regs[TCG_TYPE_V128] = 0xffffffff00000000ull; 3945 } 3946 3947 tcg_target_call_clobber_regs = 0; 3948 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R0); 3949 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R2); 3950 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R3); 3951 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R4); 3952 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R5); 3953 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R6); 3954 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R7); 3955 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R8); 3956 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R9); 3957 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R10); 3958 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R11); 3959 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_R12); 3960 3961 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 3962 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 3963 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V2); 3964 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V3); 3965 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V4); 3966 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V5); 3967 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V6); 3968 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V7); 3969 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V8); 3970 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V9); 3971 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V10); 3972 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V11); 3973 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V12); 3974 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V13); 3975 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V14); 3976 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V15); 3977 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V16); 3978 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V17); 3979 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V18); 3980 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V19); 3981 3982 s->reserved_regs = 0; 3983 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */ 3984 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */ 3985#if defined(_CALL_SYSV) 3986 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* toc pointer */ 3987#endif 3988#if defined(_CALL_SYSV) || TCG_TARGET_REG_BITS == 64 3989 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */ 3990#endif 3991 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 3992 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 3993 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP1); 3994 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP2); 3995 if (USE_REG_TB) { 3996 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tb->tc_ptr */ 3997 } 3998} 3999 4000#ifdef __ELF__ 4001typedef struct { 4002 DebugFrameCIE cie; 4003 DebugFrameFDEHeader fde; 4004 uint8_t fde_def_cfa[4]; 4005 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3]; 4006} DebugFrame; 4007 4008/* We're expecting a 2 byte uleb128 encoded value. */ 4009QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14)); 4010 4011#if TCG_TARGET_REG_BITS == 64 4012# define ELF_HOST_MACHINE EM_PPC64 4013#else 4014# define ELF_HOST_MACHINE EM_PPC 4015#endif 4016 4017static DebugFrame debug_frame = { 4018 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */ 4019 .cie.id = -1, 4020 .cie.version = 1, 4021 .cie.code_align = 1, 4022 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */ 4023 .cie.return_column = 65, 4024 4025 /* Total FDE size does not include the "len" member. */ 4026 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset), 4027 4028 .fde_def_cfa = { 4029 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */ 4030 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 4031 (FRAME_SIZE >> 7) 4032 }, 4033 .fde_reg_ofs = { 4034 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */ 4035 0x11, 65, (LR_OFFSET / -SZR) & 0x7f, 4036 } 4037}; 4038 4039void tcg_register_jit(const void *buf, size_t buf_size) 4040{ 4041 uint8_t *p = &debug_frame.fde_reg_ofs[3]; 4042 int i; 4043 4044 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) { 4045 p[0] = 0x80 + tcg_target_callee_save_regs[i]; 4046 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR; 4047 } 4048 4049 debug_frame.fde.func_start = (uintptr_t)buf; 4050 debug_frame.fde.func_len = buf_size; 4051 4052 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 4053} 4054#endif /* __ELF__ */ 4055#undef VMULEUB 4056#undef VMULEUH 4057#undef VMULEUW 4058#undef VMULOUB 4059#undef VMULOUH 4060#undef VMULOUW 4061#undef VMSUMUHM 4062