1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_isa_2_06 (cpuinfo & CPUINFO_V2_06) 13 #define have_isa_2_07 (cpuinfo & CPUINFO_V2_07) 14 #define have_isa_3_00 (cpuinfo & CPUINFO_V3_0) 15 #define have_isa_3_10 (cpuinfo & CPUINFO_V3_1) 16 #define have_altivec (cpuinfo & CPUINFO_ALTIVEC) 17 #define have_vsx (cpuinfo & CPUINFO_VSX) 18 19 /* optional instructions */ 20 #define TCG_TARGET_HAS_bswap16_i32 1 21 #define TCG_TARGET_HAS_bswap32_i32 1 22 #define TCG_TARGET_HAS_extract2_i32 0 23 #define TCG_TARGET_HAS_negsetcond_i32 1 24 #define TCG_TARGET_HAS_qemu_st8_i32 0 25 26 #if TCG_TARGET_REG_BITS == 64 27 #define TCG_TARGET_HAS_add2_i32 0 28 #define TCG_TARGET_HAS_sub2_i32 0 29 #define TCG_TARGET_HAS_extr_i64_i32 0 30 #define TCG_TARGET_HAS_bswap16_i64 1 31 #define TCG_TARGET_HAS_bswap32_i64 1 32 #define TCG_TARGET_HAS_bswap64_i64 1 33 #define TCG_TARGET_HAS_extract2_i64 0 34 #define TCG_TARGET_HAS_negsetcond_i64 1 35 #define TCG_TARGET_HAS_add2_i64 1 36 #define TCG_TARGET_HAS_sub2_i64 1 37 #endif 38 39 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 40 (TCG_TARGET_REG_BITS == 64 && have_isa_2_07) 41 42 #define TCG_TARGET_HAS_tst 1 43 44 /* 45 * While technically Altivec could support V64, it has no 64-bit store 46 * instruction and substituting two 32-bit stores makes the generated 47 * code quite large. 48 */ 49 #define TCG_TARGET_HAS_v64 have_vsx 50 #define TCG_TARGET_HAS_v128 have_altivec 51 #define TCG_TARGET_HAS_v256 0 52 53 #define TCG_TARGET_HAS_andc_vec 1 54 #define TCG_TARGET_HAS_orc_vec have_isa_2_07 55 #define TCG_TARGET_HAS_nand_vec have_isa_2_07 56 #define TCG_TARGET_HAS_nor_vec 1 57 #define TCG_TARGET_HAS_eqv_vec have_isa_2_07 58 #define TCG_TARGET_HAS_not_vec 1 59 #define TCG_TARGET_HAS_neg_vec have_isa_3_00 60 #define TCG_TARGET_HAS_abs_vec 0 61 #define TCG_TARGET_HAS_roti_vec 0 62 #define TCG_TARGET_HAS_rots_vec 0 63 #define TCG_TARGET_HAS_rotv_vec 1 64 #define TCG_TARGET_HAS_shi_vec 0 65 #define TCG_TARGET_HAS_shs_vec 0 66 #define TCG_TARGET_HAS_shv_vec 1 67 #define TCG_TARGET_HAS_mul_vec 1 68 #define TCG_TARGET_HAS_sat_vec 1 69 #define TCG_TARGET_HAS_minmax_vec 1 70 #define TCG_TARGET_HAS_bitsel_vec have_vsx 71 #define TCG_TARGET_HAS_cmpsel_vec 1 72 #define TCG_TARGET_HAS_tst_vec 0 73 74 #define TCG_TARGET_extract_valid(type, ofs, len) 1 75 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 76 77 static inline bool 78 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 79 { 80 if (type == TCG_TYPE_I64 && ofs + len == 32) { 81 return true; 82 } 83 return ofs == 0 && (len == 8 || len == 16); 84 } 85 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 86 87 #endif 88