1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_isa_2_06 (cpuinfo & CPUINFO_V2_06) 13 #define have_isa_2_07 (cpuinfo & CPUINFO_V2_07) 14 #define have_isa_3_00 (cpuinfo & CPUINFO_V3_0) 15 #define have_isa_3_10 (cpuinfo & CPUINFO_V3_1) 16 #define have_altivec (cpuinfo & CPUINFO_ALTIVEC) 17 #define have_vsx (cpuinfo & CPUINFO_VSX) 18 19 /* optional instructions */ 20 #define TCG_TARGET_HAS_div_i32 1 21 #define TCG_TARGET_HAS_rem_i32 have_isa_3_00 22 #define TCG_TARGET_HAS_rot_i32 1 23 #define TCG_TARGET_HAS_bswap16_i32 1 24 #define TCG_TARGET_HAS_bswap32_i32 1 25 #define TCG_TARGET_HAS_not_i32 1 26 #define TCG_TARGET_HAS_orc_i32 1 27 #define TCG_TARGET_HAS_eqv_i32 1 28 #define TCG_TARGET_HAS_nand_i32 1 29 #define TCG_TARGET_HAS_nor_i32 1 30 #define TCG_TARGET_HAS_clz_i32 1 31 #define TCG_TARGET_HAS_ctz_i32 have_isa_3_00 32 #define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06 33 #define TCG_TARGET_HAS_extract2_i32 0 34 #define TCG_TARGET_HAS_negsetcond_i32 1 35 #define TCG_TARGET_HAS_mulu2_i32 0 36 #define TCG_TARGET_HAS_muls2_i32 0 37 #define TCG_TARGET_HAS_muluh_i32 1 38 #define TCG_TARGET_HAS_mulsh_i32 1 39 #define TCG_TARGET_HAS_qemu_st8_i32 0 40 41 #if TCG_TARGET_REG_BITS == 64 42 #define TCG_TARGET_HAS_add2_i32 0 43 #define TCG_TARGET_HAS_sub2_i32 0 44 #define TCG_TARGET_HAS_extr_i64_i32 0 45 #define TCG_TARGET_HAS_div_i64 1 46 #define TCG_TARGET_HAS_rem_i64 have_isa_3_00 47 #define TCG_TARGET_HAS_rot_i64 1 48 #define TCG_TARGET_HAS_bswap16_i64 1 49 #define TCG_TARGET_HAS_bswap32_i64 1 50 #define TCG_TARGET_HAS_bswap64_i64 1 51 #define TCG_TARGET_HAS_not_i64 1 52 #define TCG_TARGET_HAS_orc_i64 1 53 #define TCG_TARGET_HAS_eqv_i64 1 54 #define TCG_TARGET_HAS_nand_i64 1 55 #define TCG_TARGET_HAS_nor_i64 1 56 #define TCG_TARGET_HAS_clz_i64 1 57 #define TCG_TARGET_HAS_ctz_i64 have_isa_3_00 58 #define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06 59 #define TCG_TARGET_HAS_extract2_i64 0 60 #define TCG_TARGET_HAS_negsetcond_i64 1 61 #define TCG_TARGET_HAS_add2_i64 1 62 #define TCG_TARGET_HAS_sub2_i64 1 63 #define TCG_TARGET_HAS_mulu2_i64 0 64 #define TCG_TARGET_HAS_muls2_i64 0 65 #define TCG_TARGET_HAS_muluh_i64 1 66 #define TCG_TARGET_HAS_mulsh_i64 1 67 #endif 68 69 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 70 (TCG_TARGET_REG_BITS == 64 && have_isa_2_07) 71 72 #define TCG_TARGET_HAS_tst 1 73 74 /* 75 * While technically Altivec could support V64, it has no 64-bit store 76 * instruction and substituting two 32-bit stores makes the generated 77 * code quite large. 78 */ 79 #define TCG_TARGET_HAS_v64 have_vsx 80 #define TCG_TARGET_HAS_v128 have_altivec 81 #define TCG_TARGET_HAS_v256 0 82 83 #define TCG_TARGET_HAS_andc_vec 1 84 #define TCG_TARGET_HAS_orc_vec have_isa_2_07 85 #define TCG_TARGET_HAS_nand_vec have_isa_2_07 86 #define TCG_TARGET_HAS_nor_vec 1 87 #define TCG_TARGET_HAS_eqv_vec have_isa_2_07 88 #define TCG_TARGET_HAS_not_vec 1 89 #define TCG_TARGET_HAS_neg_vec have_isa_3_00 90 #define TCG_TARGET_HAS_abs_vec 0 91 #define TCG_TARGET_HAS_roti_vec 0 92 #define TCG_TARGET_HAS_rots_vec 0 93 #define TCG_TARGET_HAS_rotv_vec 1 94 #define TCG_TARGET_HAS_shi_vec 0 95 #define TCG_TARGET_HAS_shs_vec 0 96 #define TCG_TARGET_HAS_shv_vec 1 97 #define TCG_TARGET_HAS_mul_vec 1 98 #define TCG_TARGET_HAS_sat_vec 1 99 #define TCG_TARGET_HAS_minmax_vec 1 100 #define TCG_TARGET_HAS_bitsel_vec have_vsx 101 #define TCG_TARGET_HAS_cmpsel_vec 1 102 #define TCG_TARGET_HAS_tst_vec 0 103 104 #define TCG_TARGET_extract_valid(type, ofs, len) 1 105 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 106 107 static inline bool 108 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 109 { 110 if (type == TCG_TYPE_I64 && ofs + len == 32) { 111 return true; 112 } 113 return ofs == 0 && (len == 8 || len == 16); 114 } 115 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 116 117 #endif 118