1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008 Fabrice Bellard 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 #define have_isa_2_06 (cpuinfo & CPUINFO_V2_06) 13 #define have_isa_2_07 (cpuinfo & CPUINFO_V2_07) 14 #define have_isa_3_00 (cpuinfo & CPUINFO_V3_0) 15 #define have_isa_3_10 (cpuinfo & CPUINFO_V3_1) 16 #define have_altivec (cpuinfo & CPUINFO_ALTIVEC) 17 #define have_vsx (cpuinfo & CPUINFO_VSX) 18 19 /* optional instructions */ 20 #define TCG_TARGET_HAS_div_i32 1 21 #define TCG_TARGET_HAS_rem_i32 have_isa_3_00 22 #define TCG_TARGET_HAS_rot_i32 1 23 #define TCG_TARGET_HAS_bswap16_i32 1 24 #define TCG_TARGET_HAS_bswap32_i32 1 25 #define TCG_TARGET_HAS_not_i32 1 26 #define TCG_TARGET_HAS_clz_i32 1 27 #define TCG_TARGET_HAS_ctz_i32 have_isa_3_00 28 #define TCG_TARGET_HAS_ctpop_i32 have_isa_2_06 29 #define TCG_TARGET_HAS_extract2_i32 0 30 #define TCG_TARGET_HAS_negsetcond_i32 1 31 #define TCG_TARGET_HAS_mulu2_i32 0 32 #define TCG_TARGET_HAS_muls2_i32 0 33 #define TCG_TARGET_HAS_muluh_i32 1 34 #define TCG_TARGET_HAS_mulsh_i32 1 35 #define TCG_TARGET_HAS_qemu_st8_i32 0 36 37 #if TCG_TARGET_REG_BITS == 64 38 #define TCG_TARGET_HAS_add2_i32 0 39 #define TCG_TARGET_HAS_sub2_i32 0 40 #define TCG_TARGET_HAS_extr_i64_i32 0 41 #define TCG_TARGET_HAS_div_i64 1 42 #define TCG_TARGET_HAS_rem_i64 have_isa_3_00 43 #define TCG_TARGET_HAS_rot_i64 1 44 #define TCG_TARGET_HAS_bswap16_i64 1 45 #define TCG_TARGET_HAS_bswap32_i64 1 46 #define TCG_TARGET_HAS_bswap64_i64 1 47 #define TCG_TARGET_HAS_not_i64 1 48 #define TCG_TARGET_HAS_clz_i64 1 49 #define TCG_TARGET_HAS_ctz_i64 have_isa_3_00 50 #define TCG_TARGET_HAS_ctpop_i64 have_isa_2_06 51 #define TCG_TARGET_HAS_extract2_i64 0 52 #define TCG_TARGET_HAS_negsetcond_i64 1 53 #define TCG_TARGET_HAS_add2_i64 1 54 #define TCG_TARGET_HAS_sub2_i64 1 55 #define TCG_TARGET_HAS_mulu2_i64 0 56 #define TCG_TARGET_HAS_muls2_i64 0 57 #define TCG_TARGET_HAS_muluh_i64 1 58 #define TCG_TARGET_HAS_mulsh_i64 1 59 #endif 60 61 #define TCG_TARGET_HAS_qemu_ldst_i128 \ 62 (TCG_TARGET_REG_BITS == 64 && have_isa_2_07) 63 64 #define TCG_TARGET_HAS_tst 1 65 66 /* 67 * While technically Altivec could support V64, it has no 64-bit store 68 * instruction and substituting two 32-bit stores makes the generated 69 * code quite large. 70 */ 71 #define TCG_TARGET_HAS_v64 have_vsx 72 #define TCG_TARGET_HAS_v128 have_altivec 73 #define TCG_TARGET_HAS_v256 0 74 75 #define TCG_TARGET_HAS_andc_vec 1 76 #define TCG_TARGET_HAS_orc_vec have_isa_2_07 77 #define TCG_TARGET_HAS_nand_vec have_isa_2_07 78 #define TCG_TARGET_HAS_nor_vec 1 79 #define TCG_TARGET_HAS_eqv_vec have_isa_2_07 80 #define TCG_TARGET_HAS_not_vec 1 81 #define TCG_TARGET_HAS_neg_vec have_isa_3_00 82 #define TCG_TARGET_HAS_abs_vec 0 83 #define TCG_TARGET_HAS_roti_vec 0 84 #define TCG_TARGET_HAS_rots_vec 0 85 #define TCG_TARGET_HAS_rotv_vec 1 86 #define TCG_TARGET_HAS_shi_vec 0 87 #define TCG_TARGET_HAS_shs_vec 0 88 #define TCG_TARGET_HAS_shv_vec 1 89 #define TCG_TARGET_HAS_mul_vec 1 90 #define TCG_TARGET_HAS_sat_vec 1 91 #define TCG_TARGET_HAS_minmax_vec 1 92 #define TCG_TARGET_HAS_bitsel_vec have_vsx 93 #define TCG_TARGET_HAS_cmpsel_vec 1 94 #define TCG_TARGET_HAS_tst_vec 0 95 96 #define TCG_TARGET_extract_valid(type, ofs, len) 1 97 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 98 99 static inline bool 100 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 101 { 102 if (type == TCG_TYPE_I64 && ofs + len == 32) { 103 return true; 104 } 105 return ofs == 0 && (len == 8 || len == 16); 106 } 107 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 108 109 #endif 110