185d251d7SRichard Henderson /* SPDX-License-Identifier: MIT */ 285d251d7SRichard Henderson /* 385d251d7SRichard Henderson * Define PowerPC target-specific operand constraints. 485d251d7SRichard Henderson * Copyright (c) 2021 Linaro 585d251d7SRichard Henderson */ 685d251d7SRichard Henderson 785d251d7SRichard Henderson /* 885d251d7SRichard Henderson * Define constraint letters for register sets: 985d251d7SRichard Henderson * REGS(letter, register_mask) 1085d251d7SRichard Henderson */ 1185d251d7SRichard Henderson REGS('r', ALL_GENERAL_REGS) 12*526cd4ecSRichard Henderson REGS('o', ALL_GENERAL_REGS & 0xAAAAAAAAu) /* odd registers */ 1385d251d7SRichard Henderson REGS('v', ALL_VECTOR_REGS) 1485d251d7SRichard Henderson 1585d251d7SRichard Henderson /* 1685d251d7SRichard Henderson * Define constraint letters for constants: 1785d251d7SRichard Henderson * CONST(letter, TCG_CT_CONST_* bit set) 1885d251d7SRichard Henderson */ 1985d251d7SRichard Henderson CONST('I', TCG_CT_CONST_S16) 2085d251d7SRichard Henderson CONST('M', TCG_CT_CONST_MONE) 2185d251d7SRichard Henderson CONST('T', TCG_CT_CONST_S32) 2285d251d7SRichard Henderson CONST('U', TCG_CT_CONST_U32) 2385d251d7SRichard Henderson CONST('W', TCG_CT_CONST_WSZ) 2485d251d7SRichard Henderson CONST('Z', TCG_CT_CONST_ZERO) 25