1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #ifndef MIPS_TCG_TARGET_H 28 #define MIPS_TCG_TARGET_H 29 30 #if _MIPS_SIM == _ABIO32 31 # define TCG_TARGET_REG_BITS 32 32 #elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 33 # define TCG_TARGET_REG_BITS 64 34 #else 35 # error "Unknown ABI" 36 #endif 37 38 #define TCG_TARGET_INSN_UNIT_SIZE 4 39 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16 40 #define TCG_TARGET_NB_REGS 32 41 42 typedef enum { 43 TCG_REG_ZERO = 0, 44 TCG_REG_AT, 45 TCG_REG_V0, 46 TCG_REG_V1, 47 TCG_REG_A0, 48 TCG_REG_A1, 49 TCG_REG_A2, 50 TCG_REG_A3, 51 TCG_REG_T0, 52 TCG_REG_T1, 53 TCG_REG_T2, 54 TCG_REG_T3, 55 TCG_REG_T4, 56 TCG_REG_T5, 57 TCG_REG_T6, 58 TCG_REG_T7, 59 TCG_REG_S0, 60 TCG_REG_S1, 61 TCG_REG_S2, 62 TCG_REG_S3, 63 TCG_REG_S4, 64 TCG_REG_S5, 65 TCG_REG_S6, 66 TCG_REG_S7, 67 TCG_REG_T8, 68 TCG_REG_T9, 69 TCG_REG_K0, 70 TCG_REG_K1, 71 TCG_REG_GP, 72 TCG_REG_SP, 73 TCG_REG_S8, 74 TCG_REG_RA, 75 76 TCG_REG_CALL_STACK = TCG_REG_SP, 77 TCG_AREG0 = TCG_REG_S0, 78 } TCGReg; 79 80 /* used for function call generation */ 81 #define TCG_TARGET_STACK_ALIGN 16 82 #if _MIPS_SIM == _ABIO32 83 # define TCG_TARGET_CALL_STACK_OFFSET 16 84 #else 85 # define TCG_TARGET_CALL_STACK_OFFSET 0 86 #endif 87 #define TCG_TARGET_CALL_ALIGN_ARGS 1 88 89 /* MOVN/MOVZ instructions detection */ 90 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ 91 defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \ 92 defined(_MIPS_ARCH_MIPS4) 93 #define use_movnz_instructions 1 94 #else 95 extern bool use_movnz_instructions; 96 #endif 97 98 /* MIPS32 instruction set detection */ 99 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1) 100 #define use_mips32_instructions 1 101 #else 102 extern bool use_mips32_instructions; 103 #endif 104 105 /* MIPS32R2 instruction set detection */ 106 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 107 #define use_mips32r2_instructions 1 108 #else 109 extern bool use_mips32r2_instructions; 110 #endif 111 112 /* MIPS32R6 instruction set detection */ 113 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 6) 114 #define use_mips32r6_instructions 1 115 #else 116 #define use_mips32r6_instructions 0 117 #endif 118 119 /* optional instructions */ 120 #define TCG_TARGET_HAS_div_i32 1 121 #define TCG_TARGET_HAS_rem_i32 1 122 #define TCG_TARGET_HAS_not_i32 1 123 #define TCG_TARGET_HAS_nor_i32 1 124 #define TCG_TARGET_HAS_andc_i32 0 125 #define TCG_TARGET_HAS_orc_i32 0 126 #define TCG_TARGET_HAS_eqv_i32 0 127 #define TCG_TARGET_HAS_nand_i32 0 128 #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions) 129 #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions) 130 #define TCG_TARGET_HAS_muluh_i32 1 131 #define TCG_TARGET_HAS_mulsh_i32 1 132 #define TCG_TARGET_HAS_bswap32_i32 1 133 #define TCG_TARGET_HAS_goto_ptr 1 134 135 #if TCG_TARGET_REG_BITS == 64 136 #define TCG_TARGET_HAS_add2_i32 0 137 #define TCG_TARGET_HAS_sub2_i32 0 138 #define TCG_TARGET_HAS_extrl_i64_i32 1 139 #define TCG_TARGET_HAS_extrh_i64_i32 1 140 #define TCG_TARGET_HAS_div_i64 1 141 #define TCG_TARGET_HAS_rem_i64 1 142 #define TCG_TARGET_HAS_not_i64 1 143 #define TCG_TARGET_HAS_nor_i64 1 144 #define TCG_TARGET_HAS_andc_i64 0 145 #define TCG_TARGET_HAS_orc_i64 0 146 #define TCG_TARGET_HAS_eqv_i64 0 147 #define TCG_TARGET_HAS_nand_i64 0 148 #define TCG_TARGET_HAS_add2_i64 0 149 #define TCG_TARGET_HAS_sub2_i64 0 150 #define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions) 151 #define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions) 152 #define TCG_TARGET_HAS_muluh_i64 1 153 #define TCG_TARGET_HAS_mulsh_i64 1 154 #define TCG_TARGET_HAS_ext32s_i64 1 155 #define TCG_TARGET_HAS_ext32u_i64 1 156 #endif 157 158 /* optional instructions detected at runtime */ 159 #define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions 160 #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions 161 #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions 162 #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions 163 #define TCG_TARGET_HAS_sextract_i32 0 164 #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions 165 #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions 166 #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions 167 #define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions 168 #define TCG_TARGET_HAS_ctz_i32 0 169 #define TCG_TARGET_HAS_ctpop_i32 0 170 171 #if TCG_TARGET_REG_BITS == 64 172 #define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions 173 #define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions 174 #define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions 175 #define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions 176 #define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions 177 #define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions 178 #define TCG_TARGET_HAS_sextract_i64 0 179 #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions 180 #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions 181 #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions 182 #define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions 183 #define TCG_TARGET_HAS_ctz_i64 0 184 #define TCG_TARGET_HAS_ctpop_i64 0 185 #endif 186 187 /* optional instructions automatically implemented */ 188 #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */ 189 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */ 190 #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */ 191 192 #if TCG_TARGET_REG_BITS == 64 193 #define TCG_TARGET_HAS_neg_i64 0 /* sub rd, zero, rt */ 194 #define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */ 195 #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */ 196 #endif 197 198 #ifdef __OpenBSD__ 199 #include <machine/sysarch.h> 200 #else 201 #include <sys/cachectl.h> 202 #endif 203 204 static inline void flush_icache_range(uintptr_t start, uintptr_t stop) 205 { 206 cacheflush ((void *)start, stop-start, ICACHE); 207 } 208 209 #endif 210