1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_WSZ 0x800 /* word size */ 191 192#define ALL_GENERAL_REGS 0xffffffffu 193 194static bool is_p2m1(tcg_target_long val) 195{ 196 return val && ((val + 1) & val) == 0; 197} 198 199/* test if a constant matches the constraint */ 200static bool tcg_target_const_match(int64_t val, int ct, 201 TCGType type, TCGCond cond, int vece) 202{ 203 if (ct & TCG_CT_CONST) { 204 return 1; 205 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 206 return 1; 207 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 208 return 1; 209 } else if ((ct & TCG_CT_CONST_P2M1) 210 && use_mips32r2_instructions && is_p2m1(val)) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_WSZ) 213 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 214 return 1; 215 } 216 return 0; 217} 218 219/* instruction opcodes */ 220typedef enum { 221 OPC_J = 002 << 26, 222 OPC_JAL = 003 << 26, 223 OPC_BEQ = 004 << 26, 224 OPC_BNE = 005 << 26, 225 OPC_BLEZ = 006 << 26, 226 OPC_BGTZ = 007 << 26, 227 OPC_ADDIU = 011 << 26, 228 OPC_SLTI = 012 << 26, 229 OPC_SLTIU = 013 << 26, 230 OPC_ANDI = 014 << 26, 231 OPC_ORI = 015 << 26, 232 OPC_XORI = 016 << 26, 233 OPC_LUI = 017 << 26, 234 OPC_BNEL = 025 << 26, 235 OPC_BNEZALC_R6 = 030 << 26, 236 OPC_DADDIU = 031 << 26, 237 OPC_LDL = 032 << 26, 238 OPC_LDR = 033 << 26, 239 OPC_LB = 040 << 26, 240 OPC_LH = 041 << 26, 241 OPC_LWL = 042 << 26, 242 OPC_LW = 043 << 26, 243 OPC_LBU = 044 << 26, 244 OPC_LHU = 045 << 26, 245 OPC_LWR = 046 << 26, 246 OPC_LWU = 047 << 26, 247 OPC_SB = 050 << 26, 248 OPC_SH = 051 << 26, 249 OPC_SWL = 052 << 26, 250 OPC_SW = 053 << 26, 251 OPC_SDL = 054 << 26, 252 OPC_SDR = 055 << 26, 253 OPC_SWR = 056 << 26, 254 OPC_LD = 067 << 26, 255 OPC_SD = 077 << 26, 256 257 OPC_SPECIAL = 000 << 26, 258 OPC_SLL = OPC_SPECIAL | 000, 259 OPC_SRL = OPC_SPECIAL | 002, 260 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 261 OPC_SRA = OPC_SPECIAL | 003, 262 OPC_SLLV = OPC_SPECIAL | 004, 263 OPC_SRLV = OPC_SPECIAL | 006, 264 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 265 OPC_SRAV = OPC_SPECIAL | 007, 266 OPC_JR_R5 = OPC_SPECIAL | 010, 267 OPC_JALR = OPC_SPECIAL | 011, 268 OPC_MOVZ = OPC_SPECIAL | 012, 269 OPC_MOVN = OPC_SPECIAL | 013, 270 OPC_SYNC = OPC_SPECIAL | 017, 271 OPC_MFHI = OPC_SPECIAL | 020, 272 OPC_MFLO = OPC_SPECIAL | 022, 273 OPC_DSLLV = OPC_SPECIAL | 024, 274 OPC_DSRLV = OPC_SPECIAL | 026, 275 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 276 OPC_DSRAV = OPC_SPECIAL | 027, 277 OPC_MULT = OPC_SPECIAL | 030, 278 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 279 OPC_MUH = OPC_SPECIAL | 030 | 0300, 280 OPC_MULTU = OPC_SPECIAL | 031, 281 OPC_MULU = OPC_SPECIAL | 031 | 0200, 282 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 283 OPC_DIV = OPC_SPECIAL | 032, 284 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 285 OPC_MOD = OPC_SPECIAL | 032 | 0300, 286 OPC_DIVU = OPC_SPECIAL | 033, 287 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 288 OPC_MODU = OPC_SPECIAL | 033 | 0300, 289 OPC_DMULT = OPC_SPECIAL | 034, 290 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 291 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 292 OPC_DMULTU = OPC_SPECIAL | 035, 293 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 294 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 295 OPC_DDIV = OPC_SPECIAL | 036, 296 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 297 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 298 OPC_DDIVU = OPC_SPECIAL | 037, 299 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 300 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 301 OPC_ADDU = OPC_SPECIAL | 041, 302 OPC_SUBU = OPC_SPECIAL | 043, 303 OPC_AND = OPC_SPECIAL | 044, 304 OPC_OR = OPC_SPECIAL | 045, 305 OPC_XOR = OPC_SPECIAL | 046, 306 OPC_NOR = OPC_SPECIAL | 047, 307 OPC_SLT = OPC_SPECIAL | 052, 308 OPC_SLTU = OPC_SPECIAL | 053, 309 OPC_DADDU = OPC_SPECIAL | 055, 310 OPC_DSUBU = OPC_SPECIAL | 057, 311 OPC_SELEQZ = OPC_SPECIAL | 065, 312 OPC_SELNEZ = OPC_SPECIAL | 067, 313 OPC_DSLL = OPC_SPECIAL | 070, 314 OPC_DSRL = OPC_SPECIAL | 072, 315 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 316 OPC_DSRA = OPC_SPECIAL | 073, 317 OPC_DSLL32 = OPC_SPECIAL | 074, 318 OPC_DSRL32 = OPC_SPECIAL | 076, 319 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 320 OPC_DSRA32 = OPC_SPECIAL | 077, 321 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 322 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 323 324 OPC_REGIMM = 001 << 26, 325 OPC_BLTZ = OPC_REGIMM | (000 << 16), 326 OPC_BGEZ = OPC_REGIMM | (001 << 16), 327 328 OPC_SPECIAL2 = 034 << 26, 329 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 330 OPC_CLZ = OPC_SPECIAL2 | 040, 331 OPC_DCLZ = OPC_SPECIAL2 | 044, 332 333 OPC_SPECIAL3 = 037 << 26, 334 OPC_EXT = OPC_SPECIAL3 | 000, 335 OPC_DEXTM = OPC_SPECIAL3 | 001, 336 OPC_DEXTU = OPC_SPECIAL3 | 002, 337 OPC_DEXT = OPC_SPECIAL3 | 003, 338 OPC_INS = OPC_SPECIAL3 | 004, 339 OPC_DINSM = OPC_SPECIAL3 | 005, 340 OPC_DINSU = OPC_SPECIAL3 | 006, 341 OPC_DINS = OPC_SPECIAL3 | 007, 342 OPC_WSBH = OPC_SPECIAL3 | 00240, 343 OPC_DSBH = OPC_SPECIAL3 | 00244, 344 OPC_DSHD = OPC_SPECIAL3 | 00544, 345 OPC_SEB = OPC_SPECIAL3 | 02040, 346 OPC_SEH = OPC_SPECIAL3 | 03040, 347 348 /* MIPS r6 doesn't have JR, JALR should be used instead */ 349 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 350 351 /* 352 * MIPS r6 replaces MUL with an alternative encoding which is 353 * backwards-compatible at the assembly level. 354 */ 355 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 356 357 /* MIPS r6 introduced names for weaker variants of SYNC. These are 358 backward compatible to previous architecture revisions. */ 359 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 360 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 361 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 362 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 363 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 364 365 /* Aliases for convenience. */ 366 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 367 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 368} MIPSInsn; 369 370/* 371 * Type reg 372 */ 373static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 374 TCGReg rd, TCGReg rs, TCGReg rt) 375{ 376 int32_t inst; 377 378 inst = opc; 379 inst |= (rs & 0x1F) << 21; 380 inst |= (rt & 0x1F) << 16; 381 inst |= (rd & 0x1F) << 11; 382 tcg_out32(s, inst); 383} 384 385/* 386 * Type immediate 387 */ 388static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 389 TCGReg rt, TCGReg rs, TCGArg imm) 390{ 391 int32_t inst; 392 393 inst = opc; 394 inst |= (rs & 0x1F) << 21; 395 inst |= (rt & 0x1F) << 16; 396 inst |= (imm & 0xffff); 397 tcg_out32(s, inst); 398} 399 400/* 401 * Type bitfield 402 */ 403static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 404 TCGReg rs, int msb, int lsb) 405{ 406 int32_t inst; 407 408 inst = opc; 409 inst |= (rs & 0x1F) << 21; 410 inst |= (rt & 0x1F) << 16; 411 inst |= (msb & 0x1F) << 11; 412 inst |= (lsb & 0x1F) << 6; 413 tcg_out32(s, inst); 414} 415 416static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 417 MIPSInsn oph, TCGReg rt, TCGReg rs, 418 int msb, int lsb) 419{ 420 if (lsb >= 32) { 421 opc = oph; 422 msb -= 32; 423 lsb -= 32; 424 } else if (msb >= 32) { 425 opc = opm; 426 msb -= 32; 427 } 428 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 429} 430 431/* 432 * Type branch 433 */ 434static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 435{ 436 tcg_out_opc_imm(s, opc, rt, rs, 0); 437} 438 439/* 440 * Type sa 441 */ 442static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 443 TCGReg rd, TCGReg rt, TCGArg sa) 444{ 445 int32_t inst; 446 447 inst = opc; 448 inst |= (rt & 0x1F) << 16; 449 inst |= (rd & 0x1F) << 11; 450 inst |= (sa & 0x1F) << 6; 451 tcg_out32(s, inst); 452 453} 454 455static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 456 TCGReg rd, TCGReg rt, TCGArg sa) 457{ 458 int32_t inst; 459 460 inst = (sa & 32 ? opc2 : opc1); 461 inst |= (rt & 0x1F) << 16; 462 inst |= (rd & 0x1F) << 11; 463 inst |= (sa & 0x1F) << 6; 464 tcg_out32(s, inst); 465} 466 467/* 468 * Type jump. 469 * Returns true if the branch was in range and the insn was emitted. 470 */ 471static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 472{ 473 uintptr_t dest = (uintptr_t)target; 474 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 475 int32_t inst; 476 477 /* The pc-region branch happens within the 256MB region of 478 the delay slot (thus the +4). */ 479 if ((from ^ dest) & -(1 << 28)) { 480 return false; 481 } 482 tcg_debug_assert((dest & 3) == 0); 483 484 inst = opc; 485 inst |= (dest >> 2) & 0x3ffffff; 486 tcg_out32(s, inst); 487 return true; 488} 489 490static void tcg_out_nop(TCGContext *s) 491{ 492 tcg_out32(s, 0); 493} 494 495static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 496{ 497 memset(p, 0, count * sizeof(tcg_insn_unit)); 498} 499 500static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 501{ 502 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 503} 504 505static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 506{ 507 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 508} 509 510static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 511{ 512 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 513} 514 515static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 516{ 517 /* Simple reg-reg move, optimising out the 'do nothing' case */ 518 if (ret != arg) { 519 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 520 } 521 return true; 522} 523 524static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 525{ 526 if (arg == (int16_t)arg) { 527 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 528 return true; 529 } 530 if (arg == (uint16_t)arg) { 531 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 532 return true; 533 } 534 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 535 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 536 return true; 537 } 538 return false; 539} 540 541static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 542{ 543 /* 544 * All signed 32-bit constants are loadable with two immediates, 545 * and everything else requires more work. 546 */ 547 if (arg == (int32_t)arg) { 548 if (!tcg_out_movi_one(s, ret, arg)) { 549 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 550 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 551 } 552 return true; 553 } 554 return false; 555} 556 557static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 558 tcg_target_long arg, TCGReg tbreg) 559{ 560 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 561 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 562} 563 564static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 565 tcg_target_long arg, TCGReg tbreg) 566{ 567 tcg_target_long tmp; 568 int sh, lo; 569 570 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 571 arg = (int32_t)arg; 572 } 573 574 /* Load all 32-bit constants. */ 575 if (tcg_out_movi_two(s, ret, arg)) { 576 return; 577 } 578 assert(TCG_TARGET_REG_BITS == 64); 579 580 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 581 tmp = tcg_tbrel_diff(s, (void *)arg); 582 if (tmp == (int16_t)tmp) { 583 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 584 return; 585 } 586 if (tcg_out_movi_two(s, ret, tmp)) { 587 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 588 return; 589 } 590 591 /* 592 * Load bitmasks with a right-shift. This is good for things 593 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 594 * or similarly using LUI. For this to work, bit 31 must be set. 595 */ 596 if (arg > 0 && (int32_t)arg < 0) { 597 sh = clz64(arg); 598 if (tcg_out_movi_one(s, ret, arg << sh)) { 599 tcg_out_dsrl(s, ret, ret, sh); 600 return; 601 } 602 } 603 604 /* 605 * Load slightly larger constants using left-shift. 606 * Limit this sequence to 3 insns to avoid too much expansion. 607 */ 608 sh = ctz64(arg); 609 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 610 tcg_out_dsll(s, ret, ret, sh); 611 return; 612 } 613 614 /* 615 * Load slightly larger constants using left-shift and add/or. 616 * Prefer addi with a negative immediate when that would produce 617 * a larger shift. For this to work, bits 15 and 16 must be set. 618 */ 619 lo = arg & 0xffff; 620 if (lo) { 621 if ((arg & 0x18000) == 0x18000) { 622 lo = (int16_t)arg; 623 } 624 tmp = arg - lo; 625 sh = ctz64(tmp); 626 tmp >>= sh; 627 if (tcg_out_movi_one(s, ret, tmp)) { 628 tcg_out_dsll(s, ret, ret, sh); 629 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 630 return; 631 } 632 } 633 634 /* Otherwise, put 64-bit constants into the constant pool. */ 635 tcg_out_movi_pool(s, ret, arg, tbreg); 636} 637 638static void tcg_out_movi(TCGContext *s, TCGType type, 639 TCGReg ret, tcg_target_long arg) 640{ 641 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 642 tcg_out_movi_int(s, type, ret, arg, tbreg); 643} 644 645static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 646{ 647 tcg_debug_assert(use_mips32r2_instructions); 648 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 649} 650 651static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 652{ 653 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 654} 655 656static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 657{ 658 tcg_debug_assert(use_mips32r2_instructions); 659 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 660} 661 662static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 663{ 664 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 665} 666 667static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 668{ 669 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 670 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 671} 672 673static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 674{ 675 if (rd != rs) { 676 tcg_out_ext32s(s, rd, rs); 677 } 678} 679 680static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 681{ 682 tcg_out_ext32u(s, rd, rs); 683} 684 685static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 686{ 687 tcg_out_ext32s(s, rd, rs); 688} 689 690static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 691{ 692 return false; 693} 694 695static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 696 tcg_target_long imm) 697{ 698 /* This function is only used for passing structs by reference. */ 699 g_assert_not_reached(); 700} 701 702static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 703{ 704 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 705 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 706 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 707 } 708} 709 710static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 711{ 712 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 713 if (use_mips32r2_instructions) { 714 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 715 } else { 716 tcg_out_dsll(s, ret, arg, 32); 717 tcg_out_dsrl(s, ret, ret, 32); 718 } 719} 720 721static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 722 TCGReg addr, intptr_t ofs) 723{ 724 int16_t lo = ofs; 725 if (ofs != lo) { 726 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 727 if (addr != TCG_REG_ZERO) { 728 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 729 } 730 addr = TCG_TMP0; 731 } 732 tcg_out_opc_imm(s, opc, data, addr, lo); 733} 734 735static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 736 TCGReg arg1, intptr_t arg2) 737{ 738 MIPSInsn opc = OPC_LD; 739 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 740 opc = OPC_LW; 741 } 742 tcg_out_ldst(s, opc, arg, arg1, arg2); 743} 744 745static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 746 TCGReg arg1, intptr_t arg2) 747{ 748 MIPSInsn opc = OPC_SD; 749 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 750 opc = OPC_SW; 751 } 752 tcg_out_ldst(s, opc, arg, arg1, arg2); 753} 754 755static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 756 TCGReg base, intptr_t ofs) 757{ 758 if (val == 0) { 759 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 760 return true; 761 } 762 return false; 763} 764 765#define SETCOND_INV TCG_TARGET_NB_REGS 766#define SETCOND_NEZ (SETCOND_INV << 1) 767#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 768 769static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 770 TCGReg arg1, TCGReg arg2) 771{ 772 int flags = 0; 773 774 switch (cond) { 775 case TCG_COND_EQ: /* -> NE */ 776 case TCG_COND_GE: /* -> LT */ 777 case TCG_COND_GEU: /* -> LTU */ 778 case TCG_COND_LE: /* -> GT */ 779 case TCG_COND_LEU: /* -> GTU */ 780 cond = tcg_invert_cond(cond); 781 flags ^= SETCOND_INV; 782 break; 783 default: 784 break; 785 } 786 787 switch (cond) { 788 case TCG_COND_NE: 789 flags |= SETCOND_NEZ; 790 if (arg2 == 0) { 791 return arg1 | flags; 792 } 793 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 794 break; 795 case TCG_COND_LT: 796 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 797 break; 798 case TCG_COND_LTU: 799 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 800 break; 801 case TCG_COND_GT: 802 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 803 break; 804 case TCG_COND_GTU: 805 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 806 break; 807 default: 808 g_assert_not_reached(); 809 } 810 return ret | flags; 811} 812 813static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 814{ 815 if (tmpflags != ret) { 816 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 817 818 switch (tmpflags & SETCOND_FLAGS) { 819 case SETCOND_INV: 820 /* Intermediate result is boolean: simply invert. */ 821 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 822 break; 823 case SETCOND_NEZ: 824 /* Intermediate result is zero/non-zero: test != 0. */ 825 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 826 break; 827 case SETCOND_NEZ | SETCOND_INV: 828 /* Intermediate result is zero/non-zero: test == 0. */ 829 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 830 break; 831 default: 832 g_assert_not_reached(); 833 } 834 } 835} 836 837static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 838 TCGReg ret, TCGReg arg1, TCGReg arg2) 839{ 840 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 841 tcg_out_setcond_end(s, ret, tmpflags); 842} 843 844static const TCGOutOpSetcond outop_setcond = { 845 .base.static_constraint = C_O1_I2(r, r, rz), 846 .out_rrr = tgen_setcond, 847}; 848 849static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 850 TCGReg ret, TCGReg arg1, TCGReg arg2) 851{ 852 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 853 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 854 855 /* If intermediate result is zero/non-zero: test != 0. */ 856 if (tmpflags & SETCOND_NEZ) { 857 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 858 tmp = ret; 859 } 860 /* Produce the 0/-1 result. */ 861 if (tmpflags & SETCOND_INV) { 862 tcg_out_opc_imm(s, OPC_ADDIU, ret, tmp, -1); 863 } else { 864 tcg_out_opc_reg(s, OPC_SUBU, ret, TCG_REG_ZERO, tmp); 865 } 866} 867 868static const TCGOutOpSetcond outop_negsetcond = { 869 .base.static_constraint = C_O1_I2(r, r, rz), 870 .out_rrr = tgen_negsetcond, 871}; 872 873static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 874 TCGReg arg1, TCGReg arg2, TCGLabel *l) 875{ 876 static const MIPSInsn b_zero[16] = { 877 [TCG_COND_LT] = OPC_BLTZ, 878 [TCG_COND_GT] = OPC_BGTZ, 879 [TCG_COND_LE] = OPC_BLEZ, 880 [TCG_COND_GE] = OPC_BGEZ, 881 }; 882 883 MIPSInsn b_opc = 0; 884 885 switch (cond) { 886 case TCG_COND_EQ: 887 b_opc = OPC_BEQ; 888 break; 889 case TCG_COND_NE: 890 b_opc = OPC_BNE; 891 break; 892 case TCG_COND_LT: 893 case TCG_COND_GT: 894 case TCG_COND_LE: 895 case TCG_COND_GE: 896 if (arg2 == 0) { 897 b_opc = b_zero[cond]; 898 arg2 = arg1; 899 arg1 = 0; 900 } 901 break; 902 default: 903 break; 904 } 905 906 if (b_opc == 0) { 907 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 908 909 arg2 = TCG_REG_ZERO; 910 arg1 = tmpflags & ~SETCOND_FLAGS; 911 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 912 } 913 914 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 915 tcg_out_opc_br(s, b_opc, arg1, arg2); 916 tcg_out_nop(s); 917} 918 919static const TCGOutOpBrcond outop_brcond = { 920 .base.static_constraint = C_O0_I2(r, rz), 921 .out_rr = tgen_brcond, 922}; 923 924static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 925 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 926{ 927 int flags = 0; 928 929 switch (cond) { 930 case TCG_COND_EQ: 931 flags |= SETCOND_INV; 932 /* fall through */ 933 case TCG_COND_NE: 934 flags |= SETCOND_NEZ; 935 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 936 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 937 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 938 break; 939 940 default: 941 tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); 942 tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), 943 TCG_TMP1, al, bl); 944 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 945 tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); 946 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 947 break; 948 } 949 return ret | flags; 950} 951 952static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 953 TCGReg al, TCGReg ah, 954 TCGArg bl, bool const_bl, 955 TCGArg bh, bool const_bh) 956{ 957 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 958 tcg_out_setcond_end(s, ret, tmpflags); 959} 960 961#if TCG_TARGET_REG_BITS != 32 962__attribute__((unused)) 963#endif 964static const TCGOutOpSetcond2 outop_setcond2 = { 965 .base.static_constraint = C_O1_I4(r, r, r, rz, rz), 966 .out = tgen_setcond2, 967}; 968 969static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 970 TCGArg bl, bool const_bl, 971 TCGArg bh, bool const_bh, TCGLabel *l) 972{ 973 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 974 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 975 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 976 977 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 978 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 979 tcg_out_nop(s); 980} 981 982#if TCG_TARGET_REG_BITS != 32 983__attribute__((unused)) 984#endif 985static const TCGOutOpBrcond2 outop_brcond2 = { 986 .base.static_constraint = C_O0_I4(r, r, rz, rz), 987 .out = tgen_brcond2, 988}; 989 990static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 991 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 992 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 993{ 994 int tmpflags; 995 bool eqz; 996 997 /* If one of the values is zero, put it last to match SEL*Z instructions */ 998 if (use_mips32r6_instructions && v1 == 0) { 999 v1 = v2; 1000 v2 = 0; 1001 cond = tcg_invert_cond(cond); 1002 } 1003 1004 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1005 c1 = tmpflags & ~SETCOND_FLAGS; 1006 eqz = tmpflags & SETCOND_INV; 1007 1008 if (use_mips32r6_instructions) { 1009 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1010 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1011 1012 if (v2 != 0) { 1013 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1014 } 1015 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1016 if (v2 != 0) { 1017 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1018 } 1019 return; 1020 } 1021 1022 /* This should be guaranteed via constraints */ 1023 tcg_debug_assert(v2 == ret); 1024 1025 if (use_movnz_instructions) { 1026 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1027 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1028 } else { 1029 /* Invert the condition in order to branch over the move. */ 1030 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1031 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1032 tcg_out_nop(s); 1033 /* Open-code tcg_out_mov, without the nop-move check. */ 1034 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1035 } 1036} 1037 1038static const TCGOutOpMovcond outop_movcond = { 1039 .base.static_constraint = (use_mips32r6_instructions 1040 ? C_O1_I4(r, r, rz, rz, rz) 1041 : C_O1_I4(r, r, rz, rz, 0)), 1042 .out = tgen_movcond, 1043}; 1044 1045static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1046{ 1047 /* 1048 * Note that __mips_abicalls requires the called function's address 1049 * to be loaded into $25 (t9), even if a direct branch is in range. 1050 * 1051 * For n64, always drop the pointer into the constant pool. 1052 * We can re-use helper addresses often and do not want any 1053 * of the longer sequences tcg_out_movi may try. 1054 */ 1055 if (sizeof(uintptr_t) == 8) { 1056 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1057 } else { 1058 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1059 } 1060 1061 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1062 if (tail) { 1063 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1064 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1065 } 1066 } else { 1067 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1068 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1069 } 1070 } 1071} 1072 1073static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1074 const TCGHelperInfo *info) 1075{ 1076 tcg_out_call_int(s, arg, false); 1077 tcg_out_nop(s); 1078} 1079 1080/* We have four temps, we might as well expose three of them. */ 1081static const TCGLdstHelperParam ldst_helper_param = { 1082 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1083}; 1084 1085static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1086{ 1087 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1088 MemOp opc = get_memop(l->oi); 1089 1090 /* resolve label address */ 1091 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1092 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1093 return false; 1094 } 1095 1096 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1097 1098 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1099 /* delay slot */ 1100 tcg_out_nop(s); 1101 1102 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1103 1104 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1105 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1106 return false; 1107 } 1108 1109 /* delay slot */ 1110 tcg_out_nop(s); 1111 return true; 1112} 1113 1114static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1115{ 1116 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1117 MemOp opc = get_memop(l->oi); 1118 1119 /* resolve label address */ 1120 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1121 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1122 return false; 1123 } 1124 1125 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1126 1127 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1128 /* delay slot */ 1129 tcg_out_nop(s); 1130 1131 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1132 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1133 return false; 1134 } 1135 1136 /* delay slot */ 1137 tcg_out_nop(s); 1138 return true; 1139} 1140 1141typedef struct { 1142 TCGReg base; 1143 TCGAtomAlign aa; 1144} HostAddress; 1145 1146bool tcg_target_has_memory_bswap(MemOp memop) 1147{ 1148 return false; 1149} 1150 1151/* We expect to use a 16-bit negative offset from ENV. */ 1152#define MIN_TLB_MASK_TABLE_OFS -32768 1153 1154/* 1155 * For system-mode, perform the TLB load and compare. 1156 * For user-mode, perform any required alignment tests. 1157 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1158 * is required and fill in @h with the host address for the fast path. 1159 */ 1160static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1161 TCGReg addr, MemOpIdx oi, bool is_ld) 1162{ 1163 TCGType addr_type = s->addr_type; 1164 TCGLabelQemuLdst *ldst = NULL; 1165 MemOp opc = get_memop(oi); 1166 MemOp a_bits; 1167 unsigned s_bits = opc & MO_SIZE; 1168 unsigned a_mask; 1169 TCGReg base; 1170 1171 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1172 a_bits = h->aa.align; 1173 a_mask = (1 << a_bits) - 1; 1174 1175 if (tcg_use_softmmu) { 1176 unsigned s_mask = (1 << s_bits) - 1; 1177 int mem_index = get_mmuidx(oi); 1178 int fast_off = tlb_mask_table_ofs(s, mem_index); 1179 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1180 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1181 int add_off = offsetof(CPUTLBEntry, addend); 1182 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1183 : offsetof(CPUTLBEntry, addr_write); 1184 1185 ldst = new_ldst_label(s); 1186 ldst->is_ld = is_ld; 1187 ldst->oi = oi; 1188 ldst->addr_reg = addr; 1189 1190 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1191 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1192 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1193 1194 /* Extract the TLB index from the address into TMP3. */ 1195 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1196 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1197 s->page_bits - CPU_TLB_ENTRY_BITS); 1198 } else { 1199 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1200 } 1201 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1202 1203 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1204 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1205 1206 /* Load the tlb comparator. */ 1207 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1208 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1209 cmp_off + HOST_BIG_ENDIAN * 4); 1210 } else { 1211 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1212 } 1213 1214 /* Load the tlb addend for the fast path. */ 1215 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1216 1217 /* 1218 * Mask the page bits, keeping the alignment bits to compare against. 1219 * For unaligned accesses, compare against the end of the access to 1220 * verify that it does not cross a page boundary. 1221 */ 1222 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1223 if (a_mask < s_mask) { 1224 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1225 || addr_type == TCG_TYPE_I32 1226 ? OPC_ADDIU : OPC_DADDIU), 1227 TCG_TMP2, addr, s_mask - a_mask); 1228 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1229 } else { 1230 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1231 } 1232 1233 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1234 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1235 tcg_out_ext32u(s, TCG_TMP2, addr); 1236 addr = TCG_TMP2; 1237 } 1238 1239 ldst->label_ptr[0] = s->code_ptr; 1240 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1241 1242 /* delay slot */ 1243 base = TCG_TMP3; 1244 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1245 } else { 1246 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1247 ldst = new_ldst_label(s); 1248 1249 ldst->is_ld = is_ld; 1250 ldst->oi = oi; 1251 ldst->addr_reg = addr; 1252 1253 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1254 tcg_debug_assert(a_bits < 16); 1255 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1256 1257 ldst->label_ptr[0] = s->code_ptr; 1258 if (use_mips32r6_instructions) { 1259 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1260 } else { 1261 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1262 tcg_out_nop(s); 1263 } 1264 } 1265 1266 base = addr; 1267 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1268 tcg_out_ext32u(s, TCG_REG_A0, base); 1269 base = TCG_REG_A0; 1270 } 1271 if (guest_base) { 1272 if (guest_base == (int16_t)guest_base) { 1273 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1274 } else { 1275 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1276 TCG_GUEST_BASE_REG); 1277 } 1278 base = TCG_REG_A0; 1279 } 1280 } 1281 1282 h->base = base; 1283 return ldst; 1284} 1285 1286static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1287 TCGReg base, MemOp opc, TCGType type) 1288{ 1289 switch (opc & MO_SSIZE) { 1290 case MO_UB: 1291 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1292 break; 1293 case MO_SB: 1294 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1295 break; 1296 case MO_UW: 1297 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1298 break; 1299 case MO_SW: 1300 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1301 break; 1302 case MO_UL: 1303 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1304 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1305 break; 1306 } 1307 /* FALLTHRU */ 1308 case MO_SL: 1309 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1310 break; 1311 case MO_UQ: 1312 /* Prefer to load from offset 0 first, but allow for overlap. */ 1313 if (TCG_TARGET_REG_BITS == 64) { 1314 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1315 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1316 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1317 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1318 } else { 1319 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1320 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1321 } 1322 break; 1323 default: 1324 g_assert_not_reached(); 1325 } 1326} 1327 1328static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1329 TCGReg base, MemOp opc, TCGType type) 1330{ 1331 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1332 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1333 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1334 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1335 bool sgn = opc & MO_SIGN; 1336 1337 switch (opc & MO_SIZE) { 1338 case MO_16: 1339 if (HOST_BIG_ENDIAN) { 1340 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1341 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1342 if (use_mips32r2_instructions) { 1343 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1344 } else { 1345 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1346 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1347 } 1348 } else if (use_mips32r2_instructions && lo != base) { 1349 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1350 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1351 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1352 } else { 1353 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1354 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1355 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1356 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1357 } 1358 break; 1359 1360 case MO_32: 1361 tcg_out_opc_imm(s, lw1, lo, base, 0); 1362 tcg_out_opc_imm(s, lw2, lo, base, 3); 1363 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1364 tcg_out_ext32u(s, lo, lo); 1365 } 1366 break; 1367 1368 case MO_64: 1369 if (TCG_TARGET_REG_BITS == 64) { 1370 tcg_out_opc_imm(s, ld1, lo, base, 0); 1371 tcg_out_opc_imm(s, ld2, lo, base, 7); 1372 } else { 1373 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1374 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1375 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1376 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1377 } 1378 break; 1379 1380 default: 1381 g_assert_not_reached(); 1382 } 1383} 1384 1385static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1386 TCGReg addr, MemOpIdx oi, TCGType data_type) 1387{ 1388 MemOp opc = get_memop(oi); 1389 TCGLabelQemuLdst *ldst; 1390 HostAddress h; 1391 1392 ldst = prepare_host_addr(s, &h, addr, oi, true); 1393 1394 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1395 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1396 } else { 1397 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1398 } 1399 1400 if (ldst) { 1401 ldst->type = data_type; 1402 ldst->datalo_reg = datalo; 1403 ldst->datahi_reg = datahi; 1404 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1405 } 1406} 1407 1408static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1409 TCGReg base, MemOp opc) 1410{ 1411 switch (opc & MO_SIZE) { 1412 case MO_8: 1413 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1414 break; 1415 case MO_16: 1416 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1417 break; 1418 case MO_32: 1419 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1420 break; 1421 case MO_64: 1422 if (TCG_TARGET_REG_BITS == 64) { 1423 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1424 } else { 1425 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1426 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1427 } 1428 break; 1429 default: 1430 g_assert_not_reached(); 1431 } 1432} 1433 1434static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1435 TCGReg base, MemOp opc) 1436{ 1437 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1438 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1439 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1440 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1441 1442 switch (opc & MO_SIZE) { 1443 case MO_16: 1444 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1445 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1446 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1447 break; 1448 1449 case MO_32: 1450 tcg_out_opc_imm(s, sw1, lo, base, 0); 1451 tcg_out_opc_imm(s, sw2, lo, base, 3); 1452 break; 1453 1454 case MO_64: 1455 if (TCG_TARGET_REG_BITS == 64) { 1456 tcg_out_opc_imm(s, sd1, lo, base, 0); 1457 tcg_out_opc_imm(s, sd2, lo, base, 7); 1458 } else { 1459 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1460 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1461 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1462 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1463 } 1464 break; 1465 1466 default: 1467 g_assert_not_reached(); 1468 } 1469} 1470 1471static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1472 TCGReg addr, MemOpIdx oi, TCGType data_type) 1473{ 1474 MemOp opc = get_memop(oi); 1475 TCGLabelQemuLdst *ldst; 1476 HostAddress h; 1477 1478 ldst = prepare_host_addr(s, &h, addr, oi, false); 1479 1480 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1481 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1482 } else { 1483 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1484 } 1485 1486 if (ldst) { 1487 ldst->type = data_type; 1488 ldst->datalo_reg = datalo; 1489 ldst->datahi_reg = datahi; 1490 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1491 } 1492} 1493 1494static void tcg_out_mb(TCGContext *s, TCGArg a0) 1495{ 1496 static const MIPSInsn sync[] = { 1497 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1498 as the former is an ordering barrier and the latter 1499 is a completion barrier. */ 1500 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1501 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1502 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1503 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1504 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1505 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1506 }; 1507 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1508} 1509 1510static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1511{ 1512 TCGReg base = TCG_REG_ZERO; 1513 int16_t lo = 0; 1514 1515 if (a0) { 1516 intptr_t ofs; 1517 if (TCG_TARGET_REG_BITS == 64) { 1518 ofs = tcg_tbrel_diff(s, (void *)a0); 1519 lo = ofs; 1520 if (ofs == lo) { 1521 base = TCG_REG_TB; 1522 } else { 1523 base = TCG_REG_V0; 1524 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1525 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1526 } 1527 } else { 1528 ofs = a0; 1529 lo = ofs; 1530 base = TCG_REG_V0; 1531 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1532 } 1533 } 1534 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1535 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1536 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1537 } 1538 /* delay slot */ 1539 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1540} 1541 1542static void tcg_out_goto_tb(TCGContext *s, int which) 1543{ 1544 intptr_t ofs = get_jmp_target_addr(s, which); 1545 TCGReg base, dest; 1546 1547 /* indirect jump method */ 1548 if (TCG_TARGET_REG_BITS == 64) { 1549 dest = TCG_REG_TB; 1550 base = TCG_REG_TB; 1551 ofs = tcg_tbrel_diff(s, (void *)ofs); 1552 } else { 1553 dest = TCG_TMP0; 1554 base = TCG_REG_ZERO; 1555 } 1556 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1557 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1558 /* delay slot */ 1559 tcg_out_nop(s); 1560 1561 set_jmp_reset_offset(s, which); 1562 if (TCG_TARGET_REG_BITS == 64) { 1563 /* For the unlinked case, need to reset TCG_REG_TB. */ 1564 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1565 -tcg_current_code_size(s)); 1566 } 1567} 1568 1569void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1570 uintptr_t jmp_rx, uintptr_t jmp_rw) 1571{ 1572 /* Always indirect, nothing to do */ 1573} 1574 1575 1576static void tgen_add(TCGContext *s, TCGType type, 1577 TCGReg a0, TCGReg a1, TCGReg a2) 1578{ 1579 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1580 tcg_out_opc_reg(s, insn, a0, a1, a2); 1581} 1582 1583static void tgen_addi(TCGContext *s, TCGType type, 1584 TCGReg a0, TCGReg a1, tcg_target_long a2) 1585{ 1586 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1587 tcg_out_opc_imm(s, insn, a0, a1, a2); 1588} 1589 1590static const TCGOutOpBinary outop_add = { 1591 .base.static_constraint = C_O1_I2(r, r, rJ), 1592 .out_rrr = tgen_add, 1593 .out_rri = tgen_addi, 1594}; 1595 1596static const TCGOutOpBinary outop_addco = { 1597 .base.static_constraint = C_NotImplemented, 1598}; 1599 1600static const TCGOutOpAddSubCarry outop_addci = { 1601 .base.static_constraint = C_NotImplemented, 1602}; 1603 1604static const TCGOutOpBinary outop_addcio = { 1605 .base.static_constraint = C_NotImplemented, 1606}; 1607 1608static void tcg_out_set_carry(TCGContext *s) 1609{ 1610 g_assert_not_reached(); 1611} 1612 1613static void tgen_and(TCGContext *s, TCGType type, 1614 TCGReg a0, TCGReg a1, TCGReg a2) 1615{ 1616 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1617} 1618 1619static void tgen_andi(TCGContext *s, TCGType type, 1620 TCGReg a0, TCGReg a1, tcg_target_long a2) 1621{ 1622 int msb; 1623 1624 if (a2 == (uint16_t)a2) { 1625 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1626 return; 1627 } 1628 1629 tcg_debug_assert(use_mips32r2_instructions); 1630 tcg_debug_assert(is_p2m1(a2)); 1631 msb = ctz64(~a2) - 1; 1632 if (type == TCG_TYPE_I32) { 1633 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1634 } else { 1635 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1636 } 1637} 1638 1639static const TCGOutOpBinary outop_and = { 1640 .base.static_constraint = C_O1_I2(r, r, rIK), 1641 .out_rrr = tgen_and, 1642 .out_rri = tgen_andi, 1643}; 1644 1645static const TCGOutOpBinary outop_andc = { 1646 .base.static_constraint = C_NotImplemented, 1647}; 1648 1649static void tgen_clz(TCGContext *s, TCGType type, 1650 TCGReg a0, TCGReg a1, TCGReg a2) 1651{ 1652 if (use_mips32r6_instructions) { 1653 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1654 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1655 tgen_movcond(s, TCG_TYPE_REG, TCG_COND_EQ, a0, a1, a2, false, 1656 TCG_TMP0, false, TCG_REG_ZERO, false); 1657 } else { 1658 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1659 if (a0 == a2) { 1660 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1661 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1662 } else if (a0 != a1) { 1663 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1664 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1665 } else { 1666 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1667 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1668 tcg_out_mov(s, type, a0, TCG_TMP0); 1669 } 1670 } 1671} 1672 1673static void tgen_clzi(TCGContext *s, TCGType type, 1674 TCGReg a0, TCGReg a1, tcg_target_long a2) 1675{ 1676 if (a2 == 0) { 1677 tgen_clz(s, type, a0, a1, TCG_REG_ZERO); 1678 } else if (use_mips32r6_instructions) { 1679 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1680 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1681 } else { 1682 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1683 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1684 } 1685} 1686 1687static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 1688{ 1689 return use_mips32r2_instructions ? C_O1_I2(r, r, rzW) : C_NotImplemented; 1690} 1691 1692static const TCGOutOpBinary outop_clz = { 1693 .base.static_constraint = C_Dynamic, 1694 .base.dynamic_constraint = cset_clz, 1695 .out_rrr = tgen_clz, 1696 .out_rri = tgen_clzi, 1697}; 1698 1699static const TCGOutOpUnary outop_ctpop = { 1700 .base.static_constraint = C_NotImplemented, 1701}; 1702 1703static const TCGOutOpBinary outop_ctz = { 1704 .base.static_constraint = C_NotImplemented, 1705}; 1706 1707static void tgen_divs(TCGContext *s, TCGType type, 1708 TCGReg a0, TCGReg a1, TCGReg a2) 1709{ 1710 if (use_mips32r6_instructions) { 1711 if (type == TCG_TYPE_I32) { 1712 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1713 } else { 1714 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1715 } 1716 } else { 1717 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1718 tcg_out_opc_reg(s, insn, 0, a1, a2); 1719 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1720 } 1721} 1722 1723static const TCGOutOpBinary outop_divs = { 1724 .base.static_constraint = C_O1_I2(r, r, r), 1725 .out_rrr = tgen_divs, 1726}; 1727 1728static const TCGOutOpDivRem outop_divs2 = { 1729 .base.static_constraint = C_NotImplemented, 1730}; 1731 1732static void tgen_divu(TCGContext *s, TCGType type, 1733 TCGReg a0, TCGReg a1, TCGReg a2) 1734{ 1735 if (use_mips32r6_instructions) { 1736 if (type == TCG_TYPE_I32) { 1737 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1738 } else { 1739 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1740 } 1741 } else { 1742 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1743 tcg_out_opc_reg(s, insn, 0, a1, a2); 1744 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1745 } 1746} 1747 1748static const TCGOutOpBinary outop_divu = { 1749 .base.static_constraint = C_O1_I2(r, r, r), 1750 .out_rrr = tgen_divu, 1751}; 1752 1753static const TCGOutOpDivRem outop_divu2 = { 1754 .base.static_constraint = C_NotImplemented, 1755}; 1756 1757static const TCGOutOpBinary outop_eqv = { 1758 .base.static_constraint = C_NotImplemented, 1759}; 1760 1761#if TCG_TARGET_REG_BITS == 64 1762static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 1763{ 1764 tcg_out_dsra(s, a0, a1, 32); 1765} 1766 1767static const TCGOutOpUnary outop_extrh_i64_i32 = { 1768 .base.static_constraint = C_O1_I1(r, r), 1769 .out_rr = tgen_extrh_i64_i32, 1770}; 1771#endif 1772 1773static void tgen_mul(TCGContext *s, TCGType type, 1774 TCGReg a0, TCGReg a1, TCGReg a2) 1775{ 1776 MIPSInsn insn; 1777 1778 if (type == TCG_TYPE_I32) { 1779 if (use_mips32_instructions) { 1780 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1781 return; 1782 } 1783 insn = OPC_MULT; 1784 } else { 1785 if (use_mips32r6_instructions) { 1786 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1787 return; 1788 } 1789 insn = OPC_DMULT; 1790 } 1791 tcg_out_opc_reg(s, insn, 0, a1, a2); 1792 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1793} 1794 1795static const TCGOutOpBinary outop_mul = { 1796 .base.static_constraint = C_O1_I2(r, r, r), 1797 .out_rrr = tgen_mul, 1798}; 1799 1800static void tgen_muls2(TCGContext *s, TCGType type, 1801 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1802{ 1803 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1804 tcg_out_opc_reg(s, insn, 0, a2, a3); 1805 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1806 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1807} 1808 1809static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1810{ 1811 return use_mips32r6_instructions ? C_NotImplemented : C_O2_I2(r, r, r, r); 1812} 1813 1814static const TCGOutOpMul2 outop_muls2 = { 1815 .base.static_constraint = C_Dynamic, 1816 .base.dynamic_constraint = cset_mul2, 1817 .out_rrrr = tgen_muls2, 1818}; 1819 1820static void tgen_mulsh(TCGContext *s, TCGType type, 1821 TCGReg a0, TCGReg a1, TCGReg a2) 1822{ 1823 if (use_mips32r6_instructions) { 1824 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH; 1825 tcg_out_opc_reg(s, insn, a0, a1, a2); 1826 } else { 1827 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1828 tcg_out_opc_reg(s, insn, 0, a1, a2); 1829 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1830 } 1831} 1832 1833static const TCGOutOpBinary outop_mulsh = { 1834 .base.static_constraint = C_O1_I2(r, r, r), 1835 .out_rrr = tgen_mulsh, 1836}; 1837 1838static void tgen_mulu2(TCGContext *s, TCGType type, 1839 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1840{ 1841 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1842 tcg_out_opc_reg(s, insn, 0, a2, a3); 1843 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1844 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1845} 1846 1847static const TCGOutOpMul2 outop_mulu2 = { 1848 .base.static_constraint = C_Dynamic, 1849 .base.dynamic_constraint = cset_mul2, 1850 .out_rrrr = tgen_mulu2, 1851}; 1852 1853static void tgen_muluh(TCGContext *s, TCGType type, 1854 TCGReg a0, TCGReg a1, TCGReg a2) 1855{ 1856 if (use_mips32r6_instructions) { 1857 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; 1858 tcg_out_opc_reg(s, insn, a0, a1, a2); 1859 } else { 1860 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1861 tcg_out_opc_reg(s, insn, 0, a1, a2); 1862 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1863 } 1864} 1865 1866static const TCGOutOpBinary outop_muluh = { 1867 .base.static_constraint = C_O1_I2(r, r, r), 1868 .out_rrr = tgen_muluh, 1869}; 1870 1871static const TCGOutOpBinary outop_nand = { 1872 .base.static_constraint = C_NotImplemented, 1873}; 1874 1875static void tgen_nor(TCGContext *s, TCGType type, 1876 TCGReg a0, TCGReg a1, TCGReg a2) 1877{ 1878 tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); 1879} 1880 1881static const TCGOutOpBinary outop_nor = { 1882 .base.static_constraint = C_O1_I2(r, r, r), 1883 .out_rrr = tgen_nor, 1884}; 1885 1886static void tgen_or(TCGContext *s, TCGType type, 1887 TCGReg a0, TCGReg a1, TCGReg a2) 1888{ 1889 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1890} 1891 1892static void tgen_ori(TCGContext *s, TCGType type, 1893 TCGReg a0, TCGReg a1, tcg_target_long a2) 1894{ 1895 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1896} 1897 1898static const TCGOutOpBinary outop_or = { 1899 .base.static_constraint = C_O1_I2(r, r, rI), 1900 .out_rrr = tgen_or, 1901 .out_rri = tgen_ori, 1902}; 1903 1904static const TCGOutOpBinary outop_orc = { 1905 .base.static_constraint = C_NotImplemented, 1906}; 1907 1908static void tgen_rems(TCGContext *s, TCGType type, 1909 TCGReg a0, TCGReg a1, TCGReg a2) 1910{ 1911 if (use_mips32r6_instructions) { 1912 if (type == TCG_TYPE_I32) { 1913 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1914 } else { 1915 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1916 } 1917 } else { 1918 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1919 tcg_out_opc_reg(s, insn, 0, a1, a2); 1920 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1921 } 1922} 1923 1924static const TCGOutOpBinary outop_rems = { 1925 .base.static_constraint = C_O1_I2(r, r, r), 1926 .out_rrr = tgen_rems, 1927}; 1928 1929static void tgen_remu(TCGContext *s, TCGType type, 1930 TCGReg a0, TCGReg a1, TCGReg a2) 1931{ 1932 if (use_mips32r6_instructions) { 1933 if (type == TCG_TYPE_I32) { 1934 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1935 } else { 1936 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1937 } 1938 } else { 1939 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1940 tcg_out_opc_reg(s, insn, 0, a1, a2); 1941 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1942 } 1943} 1944 1945static const TCGOutOpBinary outop_remu = { 1946 .base.static_constraint = C_O1_I2(r, r, r), 1947 .out_rrr = tgen_remu, 1948}; 1949 1950static const TCGOutOpBinary outop_rotl = { 1951 .base.static_constraint = C_NotImplemented, 1952}; 1953 1954static TCGConstraintSetIndex cset_rotr(TCGType type, unsigned flags) 1955{ 1956 return use_mips32r2_instructions ? C_O1_I2(r, r, ri) : C_NotImplemented; 1957} 1958 1959static void tgen_rotr(TCGContext *s, TCGType type, 1960 TCGReg a0, TCGReg a1, TCGReg a2) 1961{ 1962 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; 1963 tcg_out_opc_reg(s, insn, a0, a1, a2); 1964} 1965 1966static void tgen_rotri(TCGContext *s, TCGType type, 1967 TCGReg a0, TCGReg a1, tcg_target_long a2) 1968{ 1969 if (type == TCG_TYPE_I32) { 1970 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); 1971 } else { 1972 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 1973 } 1974} 1975 1976static const TCGOutOpBinary outop_rotr = { 1977 .base.static_constraint = C_Dynamic, 1978 .base.dynamic_constraint = cset_rotr, 1979 .out_rrr = tgen_rotr, 1980 .out_rri = tgen_rotri, 1981}; 1982 1983static void tgen_sar(TCGContext *s, TCGType type, 1984 TCGReg a0, TCGReg a1, TCGReg a2) 1985{ 1986 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; 1987 tcg_out_opc_reg(s, insn, a0, a1, a2); 1988} 1989 1990static void tgen_sari(TCGContext *s, TCGType type, 1991 TCGReg a0, TCGReg a1, tcg_target_long a2) 1992{ 1993 if (type == TCG_TYPE_I32) { 1994 tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); 1995 } else { 1996 tcg_out_dsra(s, a0, a1, a2); 1997 } 1998} 1999 2000static const TCGOutOpBinary outop_sar = { 2001 .base.static_constraint = C_O1_I2(r, r, ri), 2002 .out_rrr = tgen_sar, 2003 .out_rri = tgen_sari, 2004}; 2005 2006static void tgen_shl(TCGContext *s, TCGType type, 2007 TCGReg a0, TCGReg a1, TCGReg a2) 2008{ 2009 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; 2010 tcg_out_opc_reg(s, insn, a0, a1, a2); 2011} 2012 2013static void tgen_shli(TCGContext *s, TCGType type, 2014 TCGReg a0, TCGReg a1, tcg_target_long a2) 2015{ 2016 if (type == TCG_TYPE_I32) { 2017 tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); 2018 } else { 2019 tcg_out_dsll(s, a0, a1, a2); 2020 } 2021} 2022 2023static const TCGOutOpBinary outop_shl = { 2024 .base.static_constraint = C_O1_I2(r, r, ri), 2025 .out_rrr = tgen_shl, 2026 .out_rri = tgen_shli, 2027}; 2028 2029static void tgen_shr(TCGContext *s, TCGType type, 2030 TCGReg a0, TCGReg a1, TCGReg a2) 2031{ 2032 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; 2033 tcg_out_opc_reg(s, insn, a0, a1, a2); 2034} 2035 2036static void tgen_shri(TCGContext *s, TCGType type, 2037 TCGReg a0, TCGReg a1, tcg_target_long a2) 2038{ 2039 if (type == TCG_TYPE_I32) { 2040 tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); 2041 } else { 2042 tcg_out_dsrl(s, a0, a1, a2); 2043 } 2044} 2045 2046static const TCGOutOpBinary outop_shr = { 2047 .base.static_constraint = C_O1_I2(r, r, ri), 2048 .out_rrr = tgen_shr, 2049 .out_rri = tgen_shri, 2050}; 2051 2052static void tgen_sub(TCGContext *s, TCGType type, 2053 TCGReg a0, TCGReg a1, TCGReg a2) 2054{ 2055 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU; 2056 tcg_out_opc_reg(s, insn, a0, a1, a2); 2057} 2058 2059static const TCGOutOpSubtract outop_sub = { 2060 .base.static_constraint = C_O1_I2(r, r, r), 2061 .out_rrr = tgen_sub, 2062}; 2063 2064static const TCGOutOpAddSubCarry outop_subbo = { 2065 .base.static_constraint = C_NotImplemented, 2066}; 2067 2068static const TCGOutOpAddSubCarry outop_subbi = { 2069 .base.static_constraint = C_NotImplemented, 2070}; 2071 2072static const TCGOutOpAddSubCarry outop_subbio = { 2073 .base.static_constraint = C_NotImplemented, 2074}; 2075 2076static void tcg_out_set_borrow(TCGContext *s) 2077{ 2078 g_assert_not_reached(); 2079} 2080 2081static void tgen_xor(TCGContext *s, TCGType type, 2082 TCGReg a0, TCGReg a1, TCGReg a2) 2083{ 2084 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2085} 2086 2087static void tgen_xori(TCGContext *s, TCGType type, 2088 TCGReg a0, TCGReg a1, tcg_target_long a2) 2089{ 2090 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2091} 2092 2093static const TCGOutOpBinary outop_xor = { 2094 .base.static_constraint = C_O1_I2(r, r, rI), 2095 .out_rrr = tgen_xor, 2096 .out_rri = tgen_xori, 2097}; 2098 2099static void tgen_bswap16(TCGContext *s, TCGType type, 2100 TCGReg ret, TCGReg arg, unsigned flags) 2101{ 2102 /* With arg = abcd: */ 2103 if (use_mips32r2_instructions) { 2104 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 2105 if (flags & TCG_BSWAP_OS) { 2106 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 2107 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2108 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 2109 } 2110 return; 2111 } 2112 2113 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 2114 if (!(flags & TCG_BSWAP_IZ)) { 2115 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 2116 } 2117 if (flags & TCG_BSWAP_OS) { 2118 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 2119 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 2120 } else { 2121 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 2122 if (flags & TCG_BSWAP_OZ) { 2123 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 2124 } 2125 } 2126 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 2127} 2128 2129static const TCGOutOpBswap outop_bswap16 = { 2130 .base.static_constraint = C_O1_I1(r, r), 2131 .out_rr = tgen_bswap16, 2132}; 2133 2134static void tgen_bswap32(TCGContext *s, TCGType type, 2135 TCGReg ret, TCGReg arg, unsigned flags) 2136{ 2137 if (use_mips32r2_instructions) { 2138 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 2139 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 2140 if (flags & TCG_BSWAP_OZ) { 2141 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 2142 } 2143 } else { 2144 if (flags & TCG_BSWAP_OZ) { 2145 tcg_out_bswap_subr(s, bswap32u_addr); 2146 } else { 2147 tcg_out_bswap_subr(s, bswap32_addr); 2148 } 2149 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2150 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2151 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2152 } 2153} 2154 2155static const TCGOutOpBswap outop_bswap32 = { 2156 .base.static_constraint = C_O1_I1(r, r), 2157 .out_rr = tgen_bswap32, 2158}; 2159 2160#if TCG_TARGET_REG_BITS == 64 2161static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2162{ 2163 if (use_mips32r2_instructions) { 2164 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 2165 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 2166 } else { 2167 tcg_out_bswap_subr(s, bswap64_addr); 2168 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2169 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2170 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2171 } 2172} 2173 2174static const TCGOutOpUnary outop_bswap64 = { 2175 .base.static_constraint = C_O1_I1(r, r), 2176 .out_rr = tgen_bswap64, 2177}; 2178#endif /* TCG_TARGET_REG_BITS == 64 */ 2179 2180static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2181{ 2182 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2183} 2184 2185static const TCGOutOpUnary outop_neg = { 2186 .base.static_constraint = C_O1_I1(r, r), 2187 .out_rr = tgen_neg, 2188}; 2189 2190static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2191{ 2192 tgen_nor(s, type, a0, TCG_REG_ZERO, a1); 2193} 2194 2195static const TCGOutOpUnary outop_not = { 2196 .base.static_constraint = C_O1_I1(r, r), 2197 .out_rr = tgen_not, 2198}; 2199 2200static void tgen_deposit(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2201 TCGReg a2, unsigned ofs, unsigned len) 2202{ 2203 if (type == TCG_TYPE_I32) { 2204 tcg_out_opc_bf(s, OPC_INS, a0, a2, ofs + len - 1, ofs); 2205 } else { 2206 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2207 ofs + len - 1, ofs); 2208 } 2209} 2210 2211static const TCGOutOpDeposit outop_deposit = { 2212 .base.static_constraint = C_O1_I2(r, 0, rz), 2213 .out_rrr = tgen_deposit, 2214}; 2215 2216static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2217 unsigned ofs, unsigned len) 2218{ 2219 if (ofs == 0 && len <= 16) { 2220 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << len) - 1); 2221 } else if (type == TCG_TYPE_I32) { 2222 tcg_out_opc_bf(s, OPC_EXT, a0, a1, len - 1, ofs); 2223 } else { 2224 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2225 a0, a1, len - 1, ofs); 2226 } 2227} 2228 2229static const TCGOutOpExtract outop_extract = { 2230 .base.static_constraint = C_O1_I1(r, r), 2231 .out_rr = tgen_extract, 2232}; 2233 2234static void tgen_sextract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2235 unsigned ofs, unsigned len) 2236{ 2237 if (ofs == 0) { 2238 switch (len) { 2239 case 8: 2240 tcg_out_ext8s(s, type, a0, a1); 2241 return; 2242 case 16: 2243 tcg_out_ext16s(s, type, a0, a1); 2244 return; 2245 case 32: 2246 tcg_out_ext32s(s, a0, a1); 2247 return; 2248 } 2249 } 2250 g_assert_not_reached(); 2251} 2252 2253static const TCGOutOpExtract outop_sextract = { 2254 .base.static_constraint = C_O1_I1(r, r), 2255 .out_rr = tgen_sextract, 2256}; 2257 2258static const TCGOutOpExtract2 outop_extract2 = { 2259 .base.static_constraint = C_NotImplemented, 2260}; 2261 2262 2263static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2264 const TCGArg args[TCG_MAX_OP_ARGS], 2265 const int const_args[TCG_MAX_OP_ARGS]) 2266{ 2267 MIPSInsn i1; 2268 TCGArg a0, a1, a2; 2269 2270 a0 = args[0]; 2271 a1 = args[1]; 2272 a2 = args[2]; 2273 2274 switch (opc) { 2275 case INDEX_op_goto_ptr: 2276 /* jmp to the given host address (could be epilogue) */ 2277 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2278 if (TCG_TARGET_REG_BITS == 64) { 2279 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 2280 } else { 2281 tcg_out_nop(s); 2282 } 2283 break; 2284 case INDEX_op_br: 2285 tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, 2286 TCG_REG_ZERO, TCG_REG_ZERO, arg_label(a0)); 2287 break; 2288 2289 case INDEX_op_ld8u_i32: 2290 case INDEX_op_ld8u_i64: 2291 i1 = OPC_LBU; 2292 goto do_ldst; 2293 case INDEX_op_ld8s_i32: 2294 case INDEX_op_ld8s_i64: 2295 i1 = OPC_LB; 2296 goto do_ldst; 2297 case INDEX_op_ld16u_i32: 2298 case INDEX_op_ld16u_i64: 2299 i1 = OPC_LHU; 2300 goto do_ldst; 2301 case INDEX_op_ld16s_i32: 2302 case INDEX_op_ld16s_i64: 2303 i1 = OPC_LH; 2304 goto do_ldst; 2305 case INDEX_op_ld_i32: 2306 case INDEX_op_ld32s_i64: 2307 i1 = OPC_LW; 2308 goto do_ldst; 2309 case INDEX_op_ld32u_i64: 2310 i1 = OPC_LWU; 2311 goto do_ldst; 2312 case INDEX_op_ld_i64: 2313 i1 = OPC_LD; 2314 goto do_ldst; 2315 case INDEX_op_st8_i32: 2316 case INDEX_op_st8_i64: 2317 i1 = OPC_SB; 2318 goto do_ldst; 2319 case INDEX_op_st16_i32: 2320 case INDEX_op_st16_i64: 2321 i1 = OPC_SH; 2322 goto do_ldst; 2323 case INDEX_op_st_i32: 2324 case INDEX_op_st32_i64: 2325 i1 = OPC_SW; 2326 goto do_ldst; 2327 case INDEX_op_st_i64: 2328 i1 = OPC_SD; 2329 do_ldst: 2330 tcg_out_ldst(s, i1, a0, a1, a2); 2331 break; 2332 2333 case INDEX_op_qemu_ld_i32: 2334 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2335 break; 2336 case INDEX_op_qemu_ld_i64: 2337 if (TCG_TARGET_REG_BITS == 64) { 2338 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2339 } else { 2340 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2341 } 2342 break; 2343 2344 case INDEX_op_qemu_st_i32: 2345 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2346 break; 2347 case INDEX_op_qemu_st_i64: 2348 if (TCG_TARGET_REG_BITS == 64) { 2349 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2350 } else { 2351 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2352 } 2353 break; 2354 2355 case INDEX_op_mb: 2356 tcg_out_mb(s, a0); 2357 break; 2358 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2359 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2360 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2361 default: 2362 g_assert_not_reached(); 2363 } 2364} 2365 2366static TCGConstraintSetIndex 2367tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2368{ 2369 switch (op) { 2370 case INDEX_op_goto_ptr: 2371 return C_O0_I1(r); 2372 2373 case INDEX_op_ld8u_i32: 2374 case INDEX_op_ld8s_i32: 2375 case INDEX_op_ld16u_i32: 2376 case INDEX_op_ld16s_i32: 2377 case INDEX_op_ld_i32: 2378 case INDEX_op_ld8u_i64: 2379 case INDEX_op_ld8s_i64: 2380 case INDEX_op_ld16u_i64: 2381 case INDEX_op_ld16s_i64: 2382 case INDEX_op_ld32s_i64: 2383 case INDEX_op_ld32u_i64: 2384 case INDEX_op_ld_i64: 2385 return C_O1_I1(r, r); 2386 2387 case INDEX_op_st8_i32: 2388 case INDEX_op_st16_i32: 2389 case INDEX_op_st_i32: 2390 case INDEX_op_st8_i64: 2391 case INDEX_op_st16_i64: 2392 case INDEX_op_st32_i64: 2393 case INDEX_op_st_i64: 2394 return C_O0_I2(rz, r); 2395 2396 case INDEX_op_qemu_ld_i32: 2397 return C_O1_I1(r, r); 2398 case INDEX_op_qemu_st_i32: 2399 return C_O0_I2(rz, r); 2400 case INDEX_op_qemu_ld_i64: 2401 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2402 case INDEX_op_qemu_st_i64: 2403 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2404 2405 default: 2406 return C_NotImplemented; 2407 } 2408} 2409 2410static const int tcg_target_callee_save_regs[] = { 2411 TCG_REG_S0, 2412 TCG_REG_S1, 2413 TCG_REG_S2, 2414 TCG_REG_S3, 2415 TCG_REG_S4, 2416 TCG_REG_S5, 2417 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2418 TCG_REG_S7, /* used for guest_base */ 2419 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2420 TCG_REG_RA, /* should be last for ABI compliance */ 2421}; 2422 2423/* The Linux kernel doesn't provide any information about the available 2424 instruction set. Probe it using a signal handler. */ 2425 2426 2427#ifndef use_movnz_instructions 2428bool use_movnz_instructions = false; 2429#endif 2430 2431#ifndef use_mips32_instructions 2432bool use_mips32_instructions = false; 2433#endif 2434 2435#ifndef use_mips32r2_instructions 2436bool use_mips32r2_instructions = false; 2437#endif 2438 2439static volatile sig_atomic_t got_sigill; 2440 2441static void sigill_handler(int signo, siginfo_t *si, void *data) 2442{ 2443 /* Skip the faulty instruction */ 2444 ucontext_t *uc = (ucontext_t *)data; 2445 uc->uc_mcontext.pc += 4; 2446 2447 got_sigill = 1; 2448} 2449 2450static void tcg_target_detect_isa(void) 2451{ 2452 struct sigaction sa_old, sa_new; 2453 2454 memset(&sa_new, 0, sizeof(sa_new)); 2455 sa_new.sa_flags = SA_SIGINFO; 2456 sa_new.sa_sigaction = sigill_handler; 2457 sigaction(SIGILL, &sa_new, &sa_old); 2458 2459 /* Probe for movn/movz, necessary to implement movcond. */ 2460#ifndef use_movnz_instructions 2461 got_sigill = 0; 2462 asm volatile(".set push\n" 2463 ".set mips32\n" 2464 "movn $zero, $zero, $zero\n" 2465 "movz $zero, $zero, $zero\n" 2466 ".set pop\n" 2467 : : : ); 2468 use_movnz_instructions = !got_sigill; 2469#endif 2470 2471 /* Probe for MIPS32 instructions. As no subsetting is allowed 2472 by the specification, it is only necessary to probe for one 2473 of the instructions. */ 2474#ifndef use_mips32_instructions 2475 got_sigill = 0; 2476 asm volatile(".set push\n" 2477 ".set mips32\n" 2478 "mul $zero, $zero\n" 2479 ".set pop\n" 2480 : : : ); 2481 use_mips32_instructions = !got_sigill; 2482#endif 2483 2484 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2485 available. As no subsetting is allowed by the specification, 2486 it is only necessary to probe for one of the instructions. */ 2487#ifndef use_mips32r2_instructions 2488 if (use_mips32_instructions) { 2489 got_sigill = 0; 2490 asm volatile(".set push\n" 2491 ".set mips32r2\n" 2492 "seb $zero, $zero\n" 2493 ".set pop\n" 2494 : : : ); 2495 use_mips32r2_instructions = !got_sigill; 2496 } 2497#endif 2498 2499 sigaction(SIGILL, &sa_old, NULL); 2500} 2501 2502static tcg_insn_unit *align_code_ptr(TCGContext *s) 2503{ 2504 uintptr_t p = (uintptr_t)s->code_ptr; 2505 if (p & 15) { 2506 p = (p + 15) & -16; 2507 s->code_ptr = (void *)p; 2508 } 2509 return s->code_ptr; 2510} 2511 2512/* Stack frame parameters. */ 2513#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2514#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2515#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2516 2517#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2518 + TCG_TARGET_STACK_ALIGN - 1) \ 2519 & -TCG_TARGET_STACK_ALIGN) 2520#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2521 2522/* We're expecting to be able to use an immediate for frame allocation. */ 2523QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2524 2525/* Generate global QEMU prologue and epilogue code */ 2526static void tcg_target_qemu_prologue(TCGContext *s) 2527{ 2528 int i; 2529 2530 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2531 2532 /* TB prologue */ 2533 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2534 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2535 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2536 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2537 } 2538 2539 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2540 /* 2541 * The function call abi for n32 and n64 will have loaded $25 (t9) 2542 * with the address of the prologue, so we can use that instead 2543 * of TCG_REG_TB. 2544 */ 2545#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2546# error "Unknown mips abi" 2547#endif 2548 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2549 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2550 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2551 } 2552 2553 if (TCG_TARGET_REG_BITS == 64) { 2554 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2555 } 2556 2557 /* Call generated code */ 2558 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2559 /* delay slot */ 2560 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2561 2562 /* 2563 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2564 * and fall through to the rest of the epilogue. 2565 */ 2566 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2567 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2568 2569 /* TB epilogue */ 2570 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2571 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2572 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2573 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2574 } 2575 2576 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2577 /* delay slot */ 2578 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2579 2580 if (use_mips32r2_instructions) { 2581 return; 2582 } 2583 2584 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2585 clobbers TCG_TMP1, TCG_TMP2. */ 2586 2587 /* 2588 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2589 */ 2590 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2591 /* t3 = (ssss)d000 */ 2592 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2593 /* t1 = 000a */ 2594 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2595 /* t2 = 00c0 */ 2596 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2597 /* t3 = d00a */ 2598 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2599 /* t1 = 0abc */ 2600 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2601 /* t2 = 0c00 */ 2602 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2603 /* t1 = 00b0 */ 2604 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2605 /* t3 = dc0a */ 2606 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2607 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2608 /* t3 = dcba -- delay slot */ 2609 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2610 2611 if (TCG_TARGET_REG_BITS == 32) { 2612 return; 2613 } 2614 2615 /* 2616 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2617 */ 2618 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2619 /* t1 = (0000)000d */ 2620 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2621 /* t3 = 000a */ 2622 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2623 /* t1 = (0000)d000 */ 2624 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2625 /* t2 = 00c0 */ 2626 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2627 /* t3 = d00a */ 2628 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2629 /* t1 = 0abc */ 2630 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2631 /* t2 = 0c00 */ 2632 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2633 /* t1 = 00b0 */ 2634 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2635 /* t3 = dc0a */ 2636 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2637 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2638 /* t3 = dcba -- delay slot */ 2639 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2640 2641 /* 2642 * bswap64 -- 64-bit swap. a0 = abcdefgh 2643 */ 2644 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2645 /* t3 = h0000000 */ 2646 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2647 /* t1 = 0000000a */ 2648 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2649 2650 /* t2 = 000000g0 */ 2651 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2652 /* t3 = h000000a */ 2653 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2654 /* t1 = 00000abc */ 2655 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2656 /* t2 = 0g000000 */ 2657 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2658 /* t1 = 000000b0 */ 2659 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2660 2661 /* t3 = hg00000a */ 2662 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2663 /* t2 = 0000abcd */ 2664 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2665 /* t3 = hg0000ba */ 2666 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2667 2668 /* t1 = 000000c0 */ 2669 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2670 /* t2 = 0000000d */ 2671 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2672 /* t1 = 00000c00 */ 2673 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2674 /* t2 = 0000d000 */ 2675 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2676 2677 /* t3 = hg000cba */ 2678 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2679 /* t1 = 00abcdef */ 2680 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2681 /* t3 = hg00dcba */ 2682 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2683 2684 /* t2 = 0000000f */ 2685 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2686 /* t1 = 000000e0 */ 2687 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2688 /* t2 = 00f00000 */ 2689 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2690 /* t1 = 000e0000 */ 2691 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2692 2693 /* t3 = hgf0dcba */ 2694 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2695 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2696 /* t3 = hgfedcba -- delay slot */ 2697 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2698} 2699 2700static void tcg_out_tb_start(TCGContext *s) 2701{ 2702 /* nothing to do */ 2703} 2704 2705static void tcg_target_init(TCGContext *s) 2706{ 2707 tcg_target_detect_isa(); 2708 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2709 if (TCG_TARGET_REG_BITS == 64) { 2710 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2711 } 2712 2713 tcg_target_call_clobber_regs = 0; 2714 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2715 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2716 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2717 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2718 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2719 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2720 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2721 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2722 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2723 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2724 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2725 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2726 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2727 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2728 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2729 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2730 2731 s->reserved_regs = 0; 2732 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2733 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2734 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2735 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2736 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2737 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2738 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2739 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2740 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2741 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2742 if (TCG_TARGET_REG_BITS == 64) { 2743 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2744 } 2745} 2746 2747typedef struct { 2748 DebugFrameHeader h; 2749 uint8_t fde_def_cfa[4]; 2750 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2751} DebugFrame; 2752 2753#define ELF_HOST_MACHINE EM_MIPS 2754/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2755 which is good because they're really quite complicated for MIPS. */ 2756 2757static const DebugFrame debug_frame = { 2758 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2759 .h.cie.id = -1, 2760 .h.cie.version = 1, 2761 .h.cie.code_align = 1, 2762 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2763 .h.cie.return_column = TCG_REG_RA, 2764 2765 /* Total FDE size does not include the "len" member. */ 2766 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2767 2768 .fde_def_cfa = { 2769 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2770 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2771 (FRAME_SIZE >> 7) 2772 }, 2773 .fde_reg_ofs = { 2774 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2775 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2776 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2777 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2778 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2779 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2780 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2781 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2782 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2783 } 2784}; 2785 2786void tcg_register_jit(const void *buf, size_t buf_size) 2787{ 2788 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2789} 2790