1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */ 191#define TCG_CT_CONST_WSZ 0x1000 /* word size */ 192 193#define ALL_GENERAL_REGS 0xffffffffu 194 195static bool is_p2m1(tcg_target_long val) 196{ 197 return val && ((val + 1) & val) == 0; 198} 199 200/* test if a constant matches the constraint */ 201static bool tcg_target_const_match(int64_t val, int ct, 202 TCGType type, TCGCond cond, int vece) 203{ 204 if (ct & TCG_CT_CONST) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_P2M1) 213 && use_mips32r2_instructions && is_p2m1(val)) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_WSZ) 216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 217 return 1; 218 } 219 return 0; 220} 221 222/* instruction opcodes */ 223typedef enum { 224 OPC_J = 002 << 26, 225 OPC_JAL = 003 << 26, 226 OPC_BEQ = 004 << 26, 227 OPC_BNE = 005 << 26, 228 OPC_BLEZ = 006 << 26, 229 OPC_BGTZ = 007 << 26, 230 OPC_ADDIU = 011 << 26, 231 OPC_SLTI = 012 << 26, 232 OPC_SLTIU = 013 << 26, 233 OPC_ANDI = 014 << 26, 234 OPC_ORI = 015 << 26, 235 OPC_XORI = 016 << 26, 236 OPC_LUI = 017 << 26, 237 OPC_BNEL = 025 << 26, 238 OPC_BNEZALC_R6 = 030 << 26, 239 OPC_DADDIU = 031 << 26, 240 OPC_LDL = 032 << 26, 241 OPC_LDR = 033 << 26, 242 OPC_LB = 040 << 26, 243 OPC_LH = 041 << 26, 244 OPC_LWL = 042 << 26, 245 OPC_LW = 043 << 26, 246 OPC_LBU = 044 << 26, 247 OPC_LHU = 045 << 26, 248 OPC_LWR = 046 << 26, 249 OPC_LWU = 047 << 26, 250 OPC_SB = 050 << 26, 251 OPC_SH = 051 << 26, 252 OPC_SWL = 052 << 26, 253 OPC_SW = 053 << 26, 254 OPC_SDL = 054 << 26, 255 OPC_SDR = 055 << 26, 256 OPC_SWR = 056 << 26, 257 OPC_LD = 067 << 26, 258 OPC_SD = 077 << 26, 259 260 OPC_SPECIAL = 000 << 26, 261 OPC_SLL = OPC_SPECIAL | 000, 262 OPC_SRL = OPC_SPECIAL | 002, 263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 264 OPC_SRA = OPC_SPECIAL | 003, 265 OPC_SLLV = OPC_SPECIAL | 004, 266 OPC_SRLV = OPC_SPECIAL | 006, 267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 268 OPC_SRAV = OPC_SPECIAL | 007, 269 OPC_JR_R5 = OPC_SPECIAL | 010, 270 OPC_JALR = OPC_SPECIAL | 011, 271 OPC_MOVZ = OPC_SPECIAL | 012, 272 OPC_MOVN = OPC_SPECIAL | 013, 273 OPC_SYNC = OPC_SPECIAL | 017, 274 OPC_MFHI = OPC_SPECIAL | 020, 275 OPC_MFLO = OPC_SPECIAL | 022, 276 OPC_DSLLV = OPC_SPECIAL | 024, 277 OPC_DSRLV = OPC_SPECIAL | 026, 278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 279 OPC_DSRAV = OPC_SPECIAL | 027, 280 OPC_MULT = OPC_SPECIAL | 030, 281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 282 OPC_MUH = OPC_SPECIAL | 030 | 0300, 283 OPC_MULTU = OPC_SPECIAL | 031, 284 OPC_MULU = OPC_SPECIAL | 031 | 0200, 285 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 286 OPC_DIV = OPC_SPECIAL | 032, 287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 288 OPC_MOD = OPC_SPECIAL | 032 | 0300, 289 OPC_DIVU = OPC_SPECIAL | 033, 290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 291 OPC_MODU = OPC_SPECIAL | 033 | 0300, 292 OPC_DMULT = OPC_SPECIAL | 034, 293 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 294 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 295 OPC_DMULTU = OPC_SPECIAL | 035, 296 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 298 OPC_DDIV = OPC_SPECIAL | 036, 299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 300 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 301 OPC_DDIVU = OPC_SPECIAL | 037, 302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 303 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 304 OPC_ADDU = OPC_SPECIAL | 041, 305 OPC_SUBU = OPC_SPECIAL | 043, 306 OPC_AND = OPC_SPECIAL | 044, 307 OPC_OR = OPC_SPECIAL | 045, 308 OPC_XOR = OPC_SPECIAL | 046, 309 OPC_NOR = OPC_SPECIAL | 047, 310 OPC_SLT = OPC_SPECIAL | 052, 311 OPC_SLTU = OPC_SPECIAL | 053, 312 OPC_DADDU = OPC_SPECIAL | 055, 313 OPC_DSUBU = OPC_SPECIAL | 057, 314 OPC_SELEQZ = OPC_SPECIAL | 065, 315 OPC_SELNEZ = OPC_SPECIAL | 067, 316 OPC_DSLL = OPC_SPECIAL | 070, 317 OPC_DSRL = OPC_SPECIAL | 072, 318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 319 OPC_DSRA = OPC_SPECIAL | 073, 320 OPC_DSLL32 = OPC_SPECIAL | 074, 321 OPC_DSRL32 = OPC_SPECIAL | 076, 322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 323 OPC_DSRA32 = OPC_SPECIAL | 077, 324 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 326 327 OPC_REGIMM = 001 << 26, 328 OPC_BLTZ = OPC_REGIMM | (000 << 16), 329 OPC_BGEZ = OPC_REGIMM | (001 << 16), 330 331 OPC_SPECIAL2 = 034 << 26, 332 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 333 OPC_CLZ = OPC_SPECIAL2 | 040, 334 OPC_DCLZ = OPC_SPECIAL2 | 044, 335 336 OPC_SPECIAL3 = 037 << 26, 337 OPC_EXT = OPC_SPECIAL3 | 000, 338 OPC_DEXTM = OPC_SPECIAL3 | 001, 339 OPC_DEXTU = OPC_SPECIAL3 | 002, 340 OPC_DEXT = OPC_SPECIAL3 | 003, 341 OPC_INS = OPC_SPECIAL3 | 004, 342 OPC_DINSM = OPC_SPECIAL3 | 005, 343 OPC_DINSU = OPC_SPECIAL3 | 006, 344 OPC_DINS = OPC_SPECIAL3 | 007, 345 OPC_WSBH = OPC_SPECIAL3 | 00240, 346 OPC_DSBH = OPC_SPECIAL3 | 00244, 347 OPC_DSHD = OPC_SPECIAL3 | 00544, 348 OPC_SEB = OPC_SPECIAL3 | 02040, 349 OPC_SEH = OPC_SPECIAL3 | 03040, 350 351 /* MIPS r6 doesn't have JR, JALR should be used instead */ 352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 353 354 /* 355 * MIPS r6 replaces MUL with an alternative encoding which is 356 * backwards-compatible at the assembly level. 357 */ 358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 359 360 /* MIPS r6 introduced names for weaker variants of SYNC. These are 361 backward compatible to previous architecture revisions. */ 362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 367 368 /* Aliases for convenience. */ 369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 371} MIPSInsn; 372 373/* 374 * Type reg 375 */ 376static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 377 TCGReg rd, TCGReg rs, TCGReg rt) 378{ 379 int32_t inst; 380 381 inst = opc; 382 inst |= (rs & 0x1F) << 21; 383 inst |= (rt & 0x1F) << 16; 384 inst |= (rd & 0x1F) << 11; 385 tcg_out32(s, inst); 386} 387 388/* 389 * Type immediate 390 */ 391static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 392 TCGReg rt, TCGReg rs, TCGArg imm) 393{ 394 int32_t inst; 395 396 inst = opc; 397 inst |= (rs & 0x1F) << 21; 398 inst |= (rt & 0x1F) << 16; 399 inst |= (imm & 0xffff); 400 tcg_out32(s, inst); 401} 402 403/* 404 * Type bitfield 405 */ 406static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 407 TCGReg rs, int msb, int lsb) 408{ 409 int32_t inst; 410 411 inst = opc; 412 inst |= (rs & 0x1F) << 21; 413 inst |= (rt & 0x1F) << 16; 414 inst |= (msb & 0x1F) << 11; 415 inst |= (lsb & 0x1F) << 6; 416 tcg_out32(s, inst); 417} 418 419static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 420 MIPSInsn oph, TCGReg rt, TCGReg rs, 421 int msb, int lsb) 422{ 423 if (lsb >= 32) { 424 opc = oph; 425 msb -= 32; 426 lsb -= 32; 427 } else if (msb >= 32) { 428 opc = opm; 429 msb -= 32; 430 } 431 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 432} 433 434/* 435 * Type branch 436 */ 437static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 438{ 439 tcg_out_opc_imm(s, opc, rt, rs, 0); 440} 441 442/* 443 * Type sa 444 */ 445static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 446 TCGReg rd, TCGReg rt, TCGArg sa) 447{ 448 int32_t inst; 449 450 inst = opc; 451 inst |= (rt & 0x1F) << 16; 452 inst |= (rd & 0x1F) << 11; 453 inst |= (sa & 0x1F) << 6; 454 tcg_out32(s, inst); 455 456} 457 458static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 459 TCGReg rd, TCGReg rt, TCGArg sa) 460{ 461 int32_t inst; 462 463 inst = (sa & 32 ? opc2 : opc1); 464 inst |= (rt & 0x1F) << 16; 465 inst |= (rd & 0x1F) << 11; 466 inst |= (sa & 0x1F) << 6; 467 tcg_out32(s, inst); 468} 469 470/* 471 * Type jump. 472 * Returns true if the branch was in range and the insn was emitted. 473 */ 474static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 475{ 476 uintptr_t dest = (uintptr_t)target; 477 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 478 int32_t inst; 479 480 /* The pc-region branch happens within the 256MB region of 481 the delay slot (thus the +4). */ 482 if ((from ^ dest) & -(1 << 28)) { 483 return false; 484 } 485 tcg_debug_assert((dest & 3) == 0); 486 487 inst = opc; 488 inst |= (dest >> 2) & 0x3ffffff; 489 tcg_out32(s, inst); 490 return true; 491} 492 493static void tcg_out_nop(TCGContext *s) 494{ 495 tcg_out32(s, 0); 496} 497 498static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 499{ 500 memset(p, 0, count * sizeof(tcg_insn_unit)); 501} 502 503static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 504{ 505 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 506} 507 508static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 509{ 510 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 511} 512 513static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 514{ 515 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 516} 517 518static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 519{ 520 /* Simple reg-reg move, optimising out the 'do nothing' case */ 521 if (ret != arg) { 522 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 523 } 524 return true; 525} 526 527static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 528{ 529 if (arg == (int16_t)arg) { 530 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 531 return true; 532 } 533 if (arg == (uint16_t)arg) { 534 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 535 return true; 536 } 537 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 538 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 539 return true; 540 } 541 return false; 542} 543 544static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 545{ 546 /* 547 * All signed 32-bit constants are loadable with two immediates, 548 * and everything else requires more work. 549 */ 550 if (arg == (int32_t)arg) { 551 if (!tcg_out_movi_one(s, ret, arg)) { 552 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 553 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 554 } 555 return true; 556 } 557 return false; 558} 559 560static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 561 tcg_target_long arg, TCGReg tbreg) 562{ 563 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 564 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 565} 566 567static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 568 tcg_target_long arg, TCGReg tbreg) 569{ 570 tcg_target_long tmp; 571 int sh, lo; 572 573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 574 arg = (int32_t)arg; 575 } 576 577 /* Load all 32-bit constants. */ 578 if (tcg_out_movi_two(s, ret, arg)) { 579 return; 580 } 581 assert(TCG_TARGET_REG_BITS == 64); 582 583 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 584 tmp = tcg_tbrel_diff(s, (void *)arg); 585 if (tmp == (int16_t)tmp) { 586 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 587 return; 588 } 589 if (tcg_out_movi_two(s, ret, tmp)) { 590 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 591 return; 592 } 593 594 /* 595 * Load bitmasks with a right-shift. This is good for things 596 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 597 * or similarly using LUI. For this to work, bit 31 must be set. 598 */ 599 if (arg > 0 && (int32_t)arg < 0) { 600 sh = clz64(arg); 601 if (tcg_out_movi_one(s, ret, arg << sh)) { 602 tcg_out_dsrl(s, ret, ret, sh); 603 return; 604 } 605 } 606 607 /* 608 * Load slightly larger constants using left-shift. 609 * Limit this sequence to 3 insns to avoid too much expansion. 610 */ 611 sh = ctz64(arg); 612 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 613 tcg_out_dsll(s, ret, ret, sh); 614 return; 615 } 616 617 /* 618 * Load slightly larger constants using left-shift and add/or. 619 * Prefer addi with a negative immediate when that would produce 620 * a larger shift. For this to work, bits 15 and 16 must be set. 621 */ 622 lo = arg & 0xffff; 623 if (lo) { 624 if ((arg & 0x18000) == 0x18000) { 625 lo = (int16_t)arg; 626 } 627 tmp = arg - lo; 628 sh = ctz64(tmp); 629 tmp >>= sh; 630 if (tcg_out_movi_one(s, ret, tmp)) { 631 tcg_out_dsll(s, ret, ret, sh); 632 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 633 return; 634 } 635 } 636 637 /* Otherwise, put 64-bit constants into the constant pool. */ 638 tcg_out_movi_pool(s, ret, arg, tbreg); 639} 640 641static void tcg_out_movi(TCGContext *s, TCGType type, 642 TCGReg ret, tcg_target_long arg) 643{ 644 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 645 tcg_out_movi_int(s, type, ret, arg, tbreg); 646} 647 648static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 649{ 650 tcg_debug_assert(use_mips32r2_instructions); 651 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 652} 653 654static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 655{ 656 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 657} 658 659static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 660{ 661 tcg_debug_assert(use_mips32r2_instructions); 662 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 663} 664 665static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 666{ 667 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 668} 669 670static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 671{ 672 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 673 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 674} 675 676static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 if (rd != rs) { 679 tcg_out_ext32s(s, rd, rs); 680 } 681} 682 683static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 684{ 685 tcg_out_ext32u(s, rd, rs); 686} 687 688static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 689{ 690 tcg_out_ext32s(s, rd, rs); 691} 692 693static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 694{ 695 return false; 696} 697 698static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 699 tcg_target_long imm) 700{ 701 /* This function is only used for passing structs by reference. */ 702 g_assert_not_reached(); 703} 704 705static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 706{ 707 /* ret and arg can't be register tmp0 */ 708 tcg_debug_assert(ret != TCG_TMP0); 709 tcg_debug_assert(arg != TCG_TMP0); 710 711 /* With arg = abcd: */ 712 if (use_mips32r2_instructions) { 713 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 714 if (flags & TCG_BSWAP_OS) { 715 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 716 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 717 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 718 } 719 return; 720 } 721 722 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 723 if (!(flags & TCG_BSWAP_IZ)) { 724 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 725 } 726 if (flags & TCG_BSWAP_OS) { 727 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 728 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 729 } else { 730 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 731 if (flags & TCG_BSWAP_OZ) { 732 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 733 } 734 } 735 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 736} 737 738static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 739{ 740 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 741 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 742 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 743 } 744} 745 746static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 747{ 748 if (use_mips32r2_instructions) { 749 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 750 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 751 if (flags & TCG_BSWAP_OZ) { 752 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 753 } 754 } else { 755 if (flags & TCG_BSWAP_OZ) { 756 tcg_out_bswap_subr(s, bswap32u_addr); 757 } else { 758 tcg_out_bswap_subr(s, bswap32_addr); 759 } 760 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 761 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 762 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 763 } 764} 765 766static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 767{ 768 if (use_mips32r2_instructions) { 769 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 770 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 771 } else { 772 tcg_out_bswap_subr(s, bswap64_addr); 773 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 774 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 775 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 776 } 777} 778 779static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 780{ 781 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 782 if (use_mips32r2_instructions) { 783 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 784 } else { 785 tcg_out_dsll(s, ret, arg, 32); 786 tcg_out_dsrl(s, ret, ret, 32); 787 } 788} 789 790static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 791 TCGReg addr, intptr_t ofs) 792{ 793 int16_t lo = ofs; 794 if (ofs != lo) { 795 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 796 if (addr != TCG_REG_ZERO) { 797 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 798 } 799 addr = TCG_TMP0; 800 } 801 tcg_out_opc_imm(s, opc, data, addr, lo); 802} 803 804static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 805 TCGReg arg1, intptr_t arg2) 806{ 807 MIPSInsn opc = OPC_LD; 808 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 809 opc = OPC_LW; 810 } 811 tcg_out_ldst(s, opc, arg, arg1, arg2); 812} 813 814static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 815 TCGReg arg1, intptr_t arg2) 816{ 817 MIPSInsn opc = OPC_SD; 818 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 819 opc = OPC_SW; 820 } 821 tcg_out_ldst(s, opc, arg, arg1, arg2); 822} 823 824static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 825 TCGReg base, intptr_t ofs) 826{ 827 if (val == 0) { 828 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 829 return true; 830 } 831 return false; 832} 833 834static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 835 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 836 bool cbh, bool is_sub) 837{ 838 TCGReg th = TCG_TMP1; 839 840 /* If we have a negative constant such that negating it would 841 make the high part zero, we can (usually) eliminate one insn. */ 842 if (cbl && cbh && bh == -1 && bl != 0) { 843 bl = -bl; 844 bh = 0; 845 is_sub = !is_sub; 846 } 847 848 /* By operating on the high part first, we get to use the final 849 carry operation to move back from the temporary. */ 850 if (!cbh) { 851 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 852 } else if (bh != 0 || ah == rl) { 853 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 854 } else { 855 th = ah; 856 } 857 858 /* Note that tcg optimization should eliminate the bl == 0 case. */ 859 if (is_sub) { 860 if (cbl) { 861 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 862 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 863 } else { 864 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 865 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 866 } 867 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 868 } else { 869 if (cbl) { 870 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 871 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 872 } else if (rl == al && rl == bl) { 873 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 874 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 875 } else { 876 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 877 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 878 } 879 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 880 } 881} 882 883#define SETCOND_INV TCG_TARGET_NB_REGS 884#define SETCOND_NEZ (SETCOND_INV << 1) 885#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 886 887static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 888 TCGReg arg1, TCGReg arg2) 889{ 890 int flags = 0; 891 892 switch (cond) { 893 case TCG_COND_EQ: /* -> NE */ 894 case TCG_COND_GE: /* -> LT */ 895 case TCG_COND_GEU: /* -> LTU */ 896 case TCG_COND_LE: /* -> GT */ 897 case TCG_COND_LEU: /* -> GTU */ 898 cond = tcg_invert_cond(cond); 899 flags ^= SETCOND_INV; 900 break; 901 default: 902 break; 903 } 904 905 switch (cond) { 906 case TCG_COND_NE: 907 flags |= SETCOND_NEZ; 908 if (arg2 == 0) { 909 return arg1 | flags; 910 } 911 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 912 break; 913 case TCG_COND_LT: 914 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 915 break; 916 case TCG_COND_LTU: 917 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 918 break; 919 case TCG_COND_GT: 920 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 921 break; 922 case TCG_COND_GTU: 923 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 924 break; 925 default: 926 g_assert_not_reached(); 927 } 928 return ret | flags; 929} 930 931static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 932{ 933 if (tmpflags != ret) { 934 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 935 936 switch (tmpflags & SETCOND_FLAGS) { 937 case SETCOND_INV: 938 /* Intermediate result is boolean: simply invert. */ 939 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 940 break; 941 case SETCOND_NEZ: 942 /* Intermediate result is zero/non-zero: test != 0. */ 943 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 944 break; 945 case SETCOND_NEZ | SETCOND_INV: 946 /* Intermediate result is zero/non-zero: test == 0. */ 947 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 948 break; 949 default: 950 g_assert_not_reached(); 951 } 952 } 953} 954 955static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 956 TCGReg ret, TCGReg arg1, TCGReg arg2) 957{ 958 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 959 tcg_out_setcond_end(s, ret, tmpflags); 960} 961 962static const TCGOutOpSetcond outop_setcond = { 963 .base.static_constraint = C_O1_I2(r, r, rz), 964 .out_rrr = tgen_setcond, 965}; 966 967static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 968 TCGReg ret, TCGReg arg1, TCGReg arg2) 969{ 970 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 971 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 972 973 /* If intermediate result is zero/non-zero: test != 0. */ 974 if (tmpflags & SETCOND_NEZ) { 975 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 976 tmp = ret; 977 } 978 /* Produce the 0/-1 result. */ 979 if (tmpflags & SETCOND_INV) { 980 tcg_out_opc_imm(s, OPC_ADDIU, ret, tmp, -1); 981 } else { 982 tcg_out_opc_reg(s, OPC_SUBU, ret, TCG_REG_ZERO, tmp); 983 } 984} 985 986static const TCGOutOpSetcond outop_negsetcond = { 987 .base.static_constraint = C_O1_I2(r, r, rz), 988 .out_rrr = tgen_negsetcond, 989}; 990 991static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 992 TCGReg arg1, TCGReg arg2, TCGLabel *l) 993{ 994 static const MIPSInsn b_zero[16] = { 995 [TCG_COND_LT] = OPC_BLTZ, 996 [TCG_COND_GT] = OPC_BGTZ, 997 [TCG_COND_LE] = OPC_BLEZ, 998 [TCG_COND_GE] = OPC_BGEZ, 999 }; 1000 1001 MIPSInsn b_opc = 0; 1002 1003 switch (cond) { 1004 case TCG_COND_EQ: 1005 b_opc = OPC_BEQ; 1006 break; 1007 case TCG_COND_NE: 1008 b_opc = OPC_BNE; 1009 break; 1010 case TCG_COND_LT: 1011 case TCG_COND_GT: 1012 case TCG_COND_LE: 1013 case TCG_COND_GE: 1014 if (arg2 == 0) { 1015 b_opc = b_zero[cond]; 1016 arg2 = arg1; 1017 arg1 = 0; 1018 } 1019 break; 1020 default: 1021 break; 1022 } 1023 1024 if (b_opc == 0) { 1025 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 1026 1027 arg2 = TCG_REG_ZERO; 1028 arg1 = tmpflags & ~SETCOND_FLAGS; 1029 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1030 } 1031 1032 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1033 tcg_out_opc_br(s, b_opc, arg1, arg2); 1034 tcg_out_nop(s); 1035} 1036 1037static const TCGOutOpBrcond outop_brcond = { 1038 .base.static_constraint = C_O0_I2(r, rz), 1039 .out_rr = tgen_brcond, 1040}; 1041 1042static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 1043 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1044{ 1045 int flags = 0; 1046 1047 switch (cond) { 1048 case TCG_COND_EQ: 1049 flags |= SETCOND_INV; 1050 /* fall through */ 1051 case TCG_COND_NE: 1052 flags |= SETCOND_NEZ; 1053 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 1054 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 1055 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1056 break; 1057 1058 default: 1059 tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); 1060 tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), 1061 TCG_TMP1, al, bl); 1062 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 1063 tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); 1064 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1065 break; 1066 } 1067 return ret | flags; 1068} 1069 1070static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1071 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1072{ 1073 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1074 tcg_out_setcond_end(s, ret, tmpflags); 1075} 1076 1077static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1078 TCGReg bl, TCGReg bh, TCGLabel *l) 1079{ 1080 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1081 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1082 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1083 1084 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1085 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1086 tcg_out_nop(s); 1087} 1088 1089static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 1090 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 1091 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 1092{ 1093 int tmpflags; 1094 bool eqz; 1095 1096 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1097 if (use_mips32r6_instructions && v1 == 0) { 1098 v1 = v2; 1099 v2 = 0; 1100 cond = tcg_invert_cond(cond); 1101 } 1102 1103 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1104 c1 = tmpflags & ~SETCOND_FLAGS; 1105 eqz = tmpflags & SETCOND_INV; 1106 1107 if (use_mips32r6_instructions) { 1108 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1109 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1110 1111 if (v2 != 0) { 1112 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1113 } 1114 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1115 if (v2 != 0) { 1116 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1117 } 1118 return; 1119 } 1120 1121 /* This should be guaranteed via constraints */ 1122 tcg_debug_assert(v2 == ret); 1123 1124 if (use_movnz_instructions) { 1125 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1126 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1127 } else { 1128 /* Invert the condition in order to branch over the move. */ 1129 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1130 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1131 tcg_out_nop(s); 1132 /* Open-code tcg_out_mov, without the nop-move check. */ 1133 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1134 } 1135} 1136 1137static const TCGOutOpMovcond outop_movcond = { 1138 .base.static_constraint = (use_mips32r6_instructions 1139 ? C_O1_I4(r, r, rz, rz, rz) 1140 : C_O1_I4(r, r, rz, rz, 0)), 1141 .out = tgen_movcond, 1142}; 1143 1144static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1145{ 1146 /* 1147 * Note that __mips_abicalls requires the called function's address 1148 * to be loaded into $25 (t9), even if a direct branch is in range. 1149 * 1150 * For n64, always drop the pointer into the constant pool. 1151 * We can re-use helper addresses often and do not want any 1152 * of the longer sequences tcg_out_movi may try. 1153 */ 1154 if (sizeof(uintptr_t) == 8) { 1155 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1156 } else { 1157 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1158 } 1159 1160 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1161 if (tail) { 1162 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1163 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1164 } 1165 } else { 1166 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1167 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1168 } 1169 } 1170} 1171 1172static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1173 const TCGHelperInfo *info) 1174{ 1175 tcg_out_call_int(s, arg, false); 1176 tcg_out_nop(s); 1177} 1178 1179/* We have four temps, we might as well expose three of them. */ 1180static const TCGLdstHelperParam ldst_helper_param = { 1181 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1182}; 1183 1184static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1185{ 1186 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1187 MemOp opc = get_memop(l->oi); 1188 1189 /* resolve label address */ 1190 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1191 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1192 return false; 1193 } 1194 1195 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1196 1197 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1198 /* delay slot */ 1199 tcg_out_nop(s); 1200 1201 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1202 1203 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1204 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1205 return false; 1206 } 1207 1208 /* delay slot */ 1209 tcg_out_nop(s); 1210 return true; 1211} 1212 1213static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1214{ 1215 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1216 MemOp opc = get_memop(l->oi); 1217 1218 /* resolve label address */ 1219 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1220 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1221 return false; 1222 } 1223 1224 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1225 1226 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1227 /* delay slot */ 1228 tcg_out_nop(s); 1229 1230 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1231 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1232 return false; 1233 } 1234 1235 /* delay slot */ 1236 tcg_out_nop(s); 1237 return true; 1238} 1239 1240typedef struct { 1241 TCGReg base; 1242 TCGAtomAlign aa; 1243} HostAddress; 1244 1245bool tcg_target_has_memory_bswap(MemOp memop) 1246{ 1247 return false; 1248} 1249 1250/* We expect to use a 16-bit negative offset from ENV. */ 1251#define MIN_TLB_MASK_TABLE_OFS -32768 1252 1253/* 1254 * For system-mode, perform the TLB load and compare. 1255 * For user-mode, perform any required alignment tests. 1256 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1257 * is required and fill in @h with the host address for the fast path. 1258 */ 1259static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1260 TCGReg addr, MemOpIdx oi, bool is_ld) 1261{ 1262 TCGType addr_type = s->addr_type; 1263 TCGLabelQemuLdst *ldst = NULL; 1264 MemOp opc = get_memop(oi); 1265 MemOp a_bits; 1266 unsigned s_bits = opc & MO_SIZE; 1267 unsigned a_mask; 1268 TCGReg base; 1269 1270 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1271 a_bits = h->aa.align; 1272 a_mask = (1 << a_bits) - 1; 1273 1274 if (tcg_use_softmmu) { 1275 unsigned s_mask = (1 << s_bits) - 1; 1276 int mem_index = get_mmuidx(oi); 1277 int fast_off = tlb_mask_table_ofs(s, mem_index); 1278 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1279 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1280 int add_off = offsetof(CPUTLBEntry, addend); 1281 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1282 : offsetof(CPUTLBEntry, addr_write); 1283 1284 ldst = new_ldst_label(s); 1285 ldst->is_ld = is_ld; 1286 ldst->oi = oi; 1287 ldst->addr_reg = addr; 1288 1289 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1290 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1291 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1292 1293 /* Extract the TLB index from the address into TMP3. */ 1294 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1295 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1296 s->page_bits - CPU_TLB_ENTRY_BITS); 1297 } else { 1298 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1299 } 1300 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1301 1302 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1303 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1304 1305 /* Load the tlb comparator. */ 1306 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1307 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1308 cmp_off + HOST_BIG_ENDIAN * 4); 1309 } else { 1310 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1311 } 1312 1313 /* Load the tlb addend for the fast path. */ 1314 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1315 1316 /* 1317 * Mask the page bits, keeping the alignment bits to compare against. 1318 * For unaligned accesses, compare against the end of the access to 1319 * verify that it does not cross a page boundary. 1320 */ 1321 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1322 if (a_mask < s_mask) { 1323 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1324 || addr_type == TCG_TYPE_I32 1325 ? OPC_ADDIU : OPC_DADDIU), 1326 TCG_TMP2, addr, s_mask - a_mask); 1327 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1328 } else { 1329 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1330 } 1331 1332 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1333 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1334 tcg_out_ext32u(s, TCG_TMP2, addr); 1335 addr = TCG_TMP2; 1336 } 1337 1338 ldst->label_ptr[0] = s->code_ptr; 1339 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1340 1341 /* delay slot */ 1342 base = TCG_TMP3; 1343 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1344 } else { 1345 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1346 ldst = new_ldst_label(s); 1347 1348 ldst->is_ld = is_ld; 1349 ldst->oi = oi; 1350 ldst->addr_reg = addr; 1351 1352 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1353 tcg_debug_assert(a_bits < 16); 1354 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1355 1356 ldst->label_ptr[0] = s->code_ptr; 1357 if (use_mips32r6_instructions) { 1358 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1359 } else { 1360 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1361 tcg_out_nop(s); 1362 } 1363 } 1364 1365 base = addr; 1366 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1367 tcg_out_ext32u(s, TCG_REG_A0, base); 1368 base = TCG_REG_A0; 1369 } 1370 if (guest_base) { 1371 if (guest_base == (int16_t)guest_base) { 1372 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1373 } else { 1374 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1375 TCG_GUEST_BASE_REG); 1376 } 1377 base = TCG_REG_A0; 1378 } 1379 } 1380 1381 h->base = base; 1382 return ldst; 1383} 1384 1385static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1386 TCGReg base, MemOp opc, TCGType type) 1387{ 1388 switch (opc & MO_SSIZE) { 1389 case MO_UB: 1390 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1391 break; 1392 case MO_SB: 1393 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1394 break; 1395 case MO_UW: 1396 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1397 break; 1398 case MO_SW: 1399 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1400 break; 1401 case MO_UL: 1402 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1403 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1404 break; 1405 } 1406 /* FALLTHRU */ 1407 case MO_SL: 1408 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1409 break; 1410 case MO_UQ: 1411 /* Prefer to load from offset 0 first, but allow for overlap. */ 1412 if (TCG_TARGET_REG_BITS == 64) { 1413 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1414 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1415 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1416 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1417 } else { 1418 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1419 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1420 } 1421 break; 1422 default: 1423 g_assert_not_reached(); 1424 } 1425} 1426 1427static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1428 TCGReg base, MemOp opc, TCGType type) 1429{ 1430 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1431 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1432 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1433 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1434 bool sgn = opc & MO_SIGN; 1435 1436 switch (opc & MO_SIZE) { 1437 case MO_16: 1438 if (HOST_BIG_ENDIAN) { 1439 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1440 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1441 if (use_mips32r2_instructions) { 1442 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1443 } else { 1444 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1445 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1446 } 1447 } else if (use_mips32r2_instructions && lo != base) { 1448 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1449 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1450 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1451 } else { 1452 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1453 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1454 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1455 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1456 } 1457 break; 1458 1459 case MO_32: 1460 tcg_out_opc_imm(s, lw1, lo, base, 0); 1461 tcg_out_opc_imm(s, lw2, lo, base, 3); 1462 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1463 tcg_out_ext32u(s, lo, lo); 1464 } 1465 break; 1466 1467 case MO_64: 1468 if (TCG_TARGET_REG_BITS == 64) { 1469 tcg_out_opc_imm(s, ld1, lo, base, 0); 1470 tcg_out_opc_imm(s, ld2, lo, base, 7); 1471 } else { 1472 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1473 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1474 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1475 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1476 } 1477 break; 1478 1479 default: 1480 g_assert_not_reached(); 1481 } 1482} 1483 1484static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1485 TCGReg addr, MemOpIdx oi, TCGType data_type) 1486{ 1487 MemOp opc = get_memop(oi); 1488 TCGLabelQemuLdst *ldst; 1489 HostAddress h; 1490 1491 ldst = prepare_host_addr(s, &h, addr, oi, true); 1492 1493 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1494 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1495 } else { 1496 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1497 } 1498 1499 if (ldst) { 1500 ldst->type = data_type; 1501 ldst->datalo_reg = datalo; 1502 ldst->datahi_reg = datahi; 1503 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1504 } 1505} 1506 1507static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1508 TCGReg base, MemOp opc) 1509{ 1510 switch (opc & MO_SIZE) { 1511 case MO_8: 1512 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1513 break; 1514 case MO_16: 1515 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1516 break; 1517 case MO_32: 1518 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1519 break; 1520 case MO_64: 1521 if (TCG_TARGET_REG_BITS == 64) { 1522 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1523 } else { 1524 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1525 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1526 } 1527 break; 1528 default: 1529 g_assert_not_reached(); 1530 } 1531} 1532 1533static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1534 TCGReg base, MemOp opc) 1535{ 1536 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1537 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1538 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1539 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1540 1541 switch (opc & MO_SIZE) { 1542 case MO_16: 1543 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1544 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1545 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1546 break; 1547 1548 case MO_32: 1549 tcg_out_opc_imm(s, sw1, lo, base, 0); 1550 tcg_out_opc_imm(s, sw2, lo, base, 3); 1551 break; 1552 1553 case MO_64: 1554 if (TCG_TARGET_REG_BITS == 64) { 1555 tcg_out_opc_imm(s, sd1, lo, base, 0); 1556 tcg_out_opc_imm(s, sd2, lo, base, 7); 1557 } else { 1558 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1559 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1560 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1561 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1562 } 1563 break; 1564 1565 default: 1566 g_assert_not_reached(); 1567 } 1568} 1569 1570static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1571 TCGReg addr, MemOpIdx oi, TCGType data_type) 1572{ 1573 MemOp opc = get_memop(oi); 1574 TCGLabelQemuLdst *ldst; 1575 HostAddress h; 1576 1577 ldst = prepare_host_addr(s, &h, addr, oi, false); 1578 1579 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1580 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1581 } else { 1582 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1583 } 1584 1585 if (ldst) { 1586 ldst->type = data_type; 1587 ldst->datalo_reg = datalo; 1588 ldst->datahi_reg = datahi; 1589 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1590 } 1591} 1592 1593static void tcg_out_mb(TCGContext *s, TCGArg a0) 1594{ 1595 static const MIPSInsn sync[] = { 1596 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1597 as the former is an ordering barrier and the latter 1598 is a completion barrier. */ 1599 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1600 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1601 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1602 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1603 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1604 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1605 }; 1606 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1607} 1608 1609static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1610{ 1611 TCGReg base = TCG_REG_ZERO; 1612 int16_t lo = 0; 1613 1614 if (a0) { 1615 intptr_t ofs; 1616 if (TCG_TARGET_REG_BITS == 64) { 1617 ofs = tcg_tbrel_diff(s, (void *)a0); 1618 lo = ofs; 1619 if (ofs == lo) { 1620 base = TCG_REG_TB; 1621 } else { 1622 base = TCG_REG_V0; 1623 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1624 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1625 } 1626 } else { 1627 ofs = a0; 1628 lo = ofs; 1629 base = TCG_REG_V0; 1630 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1631 } 1632 } 1633 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1634 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1635 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1636 } 1637 /* delay slot */ 1638 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1639} 1640 1641static void tcg_out_goto_tb(TCGContext *s, int which) 1642{ 1643 intptr_t ofs = get_jmp_target_addr(s, which); 1644 TCGReg base, dest; 1645 1646 /* indirect jump method */ 1647 if (TCG_TARGET_REG_BITS == 64) { 1648 dest = TCG_REG_TB; 1649 base = TCG_REG_TB; 1650 ofs = tcg_tbrel_diff(s, (void *)ofs); 1651 } else { 1652 dest = TCG_TMP0; 1653 base = TCG_REG_ZERO; 1654 } 1655 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1656 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1657 /* delay slot */ 1658 tcg_out_nop(s); 1659 1660 set_jmp_reset_offset(s, which); 1661 if (TCG_TARGET_REG_BITS == 64) { 1662 /* For the unlinked case, need to reset TCG_REG_TB. */ 1663 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1664 -tcg_current_code_size(s)); 1665 } 1666} 1667 1668void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1669 uintptr_t jmp_rx, uintptr_t jmp_rw) 1670{ 1671 /* Always indirect, nothing to do */ 1672} 1673 1674 1675static void tgen_add(TCGContext *s, TCGType type, 1676 TCGReg a0, TCGReg a1, TCGReg a2) 1677{ 1678 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1679 tcg_out_opc_reg(s, insn, a0, a1, a2); 1680} 1681 1682static void tgen_addi(TCGContext *s, TCGType type, 1683 TCGReg a0, TCGReg a1, tcg_target_long a2) 1684{ 1685 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1686 tcg_out_opc_imm(s, insn, a0, a1, a2); 1687} 1688 1689static const TCGOutOpBinary outop_add = { 1690 .base.static_constraint = C_O1_I2(r, r, rJ), 1691 .out_rrr = tgen_add, 1692 .out_rri = tgen_addi, 1693}; 1694 1695static void tgen_and(TCGContext *s, TCGType type, 1696 TCGReg a0, TCGReg a1, TCGReg a2) 1697{ 1698 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1699} 1700 1701static void tgen_andi(TCGContext *s, TCGType type, 1702 TCGReg a0, TCGReg a1, tcg_target_long a2) 1703{ 1704 int msb; 1705 1706 if (a2 == (uint16_t)a2) { 1707 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1708 return; 1709 } 1710 1711 tcg_debug_assert(use_mips32r2_instructions); 1712 tcg_debug_assert(is_p2m1(a2)); 1713 msb = ctz64(~a2) - 1; 1714 if (type == TCG_TYPE_I32) { 1715 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1716 } else { 1717 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1718 } 1719} 1720 1721static const TCGOutOpBinary outop_and = { 1722 .base.static_constraint = C_O1_I2(r, r, rIK), 1723 .out_rrr = tgen_and, 1724 .out_rri = tgen_andi, 1725}; 1726 1727static const TCGOutOpBinary outop_andc = { 1728 .base.static_constraint = C_NotImplemented, 1729}; 1730 1731static void tgen_clz(TCGContext *s, TCGType type, 1732 TCGReg a0, TCGReg a1, TCGReg a2) 1733{ 1734 if (use_mips32r6_instructions) { 1735 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1736 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1737 tgen_movcond(s, TCG_TYPE_REG, TCG_COND_EQ, a0, a1, a2, false, 1738 TCG_TMP0, false, TCG_REG_ZERO, false); 1739 } else { 1740 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1741 if (a0 == a2) { 1742 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1743 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1744 } else if (a0 != a1) { 1745 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1746 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1747 } else { 1748 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1749 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1750 tcg_out_mov(s, type, a0, TCG_TMP0); 1751 } 1752 } 1753} 1754 1755static void tgen_clzi(TCGContext *s, TCGType type, 1756 TCGReg a0, TCGReg a1, tcg_target_long a2) 1757{ 1758 if (a2 == 0) { 1759 tgen_clz(s, type, a0, a1, TCG_REG_ZERO); 1760 } else if (use_mips32r6_instructions) { 1761 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1762 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1763 } else { 1764 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1765 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1766 } 1767} 1768 1769static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 1770{ 1771 return use_mips32r2_instructions ? C_O1_I2(r, r, rzW) : C_NotImplemented; 1772} 1773 1774static const TCGOutOpBinary outop_clz = { 1775 .base.static_constraint = C_Dynamic, 1776 .base.dynamic_constraint = cset_clz, 1777 .out_rrr = tgen_clz, 1778 .out_rri = tgen_clzi, 1779}; 1780 1781static const TCGOutOpUnary outop_ctpop = { 1782 .base.static_constraint = C_NotImplemented, 1783}; 1784 1785static const TCGOutOpBinary outop_ctz = { 1786 .base.static_constraint = C_NotImplemented, 1787}; 1788 1789static void tgen_divs(TCGContext *s, TCGType type, 1790 TCGReg a0, TCGReg a1, TCGReg a2) 1791{ 1792 if (use_mips32r6_instructions) { 1793 if (type == TCG_TYPE_I32) { 1794 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1795 } else { 1796 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1797 } 1798 } else { 1799 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1800 tcg_out_opc_reg(s, insn, 0, a1, a2); 1801 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1802 } 1803} 1804 1805static const TCGOutOpBinary outop_divs = { 1806 .base.static_constraint = C_O1_I2(r, r, r), 1807 .out_rrr = tgen_divs, 1808}; 1809 1810static const TCGOutOpDivRem outop_divs2 = { 1811 .base.static_constraint = C_NotImplemented, 1812}; 1813 1814static void tgen_divu(TCGContext *s, TCGType type, 1815 TCGReg a0, TCGReg a1, TCGReg a2) 1816{ 1817 if (use_mips32r6_instructions) { 1818 if (type == TCG_TYPE_I32) { 1819 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1820 } else { 1821 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1822 } 1823 } else { 1824 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1825 tcg_out_opc_reg(s, insn, 0, a1, a2); 1826 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1827 } 1828} 1829 1830static const TCGOutOpBinary outop_divu = { 1831 .base.static_constraint = C_O1_I2(r, r, r), 1832 .out_rrr = tgen_divu, 1833}; 1834 1835static const TCGOutOpDivRem outop_divu2 = { 1836 .base.static_constraint = C_NotImplemented, 1837}; 1838 1839static const TCGOutOpBinary outop_eqv = { 1840 .base.static_constraint = C_NotImplemented, 1841}; 1842 1843static void tgen_mul(TCGContext *s, TCGType type, 1844 TCGReg a0, TCGReg a1, TCGReg a2) 1845{ 1846 MIPSInsn insn; 1847 1848 if (type == TCG_TYPE_I32) { 1849 if (use_mips32_instructions) { 1850 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1851 return; 1852 } 1853 insn = OPC_MULT; 1854 } else { 1855 if (use_mips32r6_instructions) { 1856 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1857 return; 1858 } 1859 insn = OPC_DMULT; 1860 } 1861 tcg_out_opc_reg(s, insn, 0, a1, a2); 1862 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1863} 1864 1865static const TCGOutOpBinary outop_mul = { 1866 .base.static_constraint = C_O1_I2(r, r, r), 1867 .out_rrr = tgen_mul, 1868}; 1869 1870static void tgen_muls2(TCGContext *s, TCGType type, 1871 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1872{ 1873 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1874 tcg_out_opc_reg(s, insn, 0, a2, a3); 1875 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1876 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1877} 1878 1879static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1880{ 1881 return use_mips32r6_instructions ? C_NotImplemented : C_O2_I2(r, r, r, r); 1882} 1883 1884static const TCGOutOpMul2 outop_muls2 = { 1885 .base.static_constraint = C_Dynamic, 1886 .base.dynamic_constraint = cset_mul2, 1887 .out_rrrr = tgen_muls2, 1888}; 1889 1890static void tgen_mulsh(TCGContext *s, TCGType type, 1891 TCGReg a0, TCGReg a1, TCGReg a2) 1892{ 1893 if (use_mips32r6_instructions) { 1894 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH; 1895 tcg_out_opc_reg(s, insn, a0, a1, a2); 1896 } else { 1897 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1898 tcg_out_opc_reg(s, insn, 0, a1, a2); 1899 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1900 } 1901} 1902 1903static const TCGOutOpBinary outop_mulsh = { 1904 .base.static_constraint = C_O1_I2(r, r, r), 1905 .out_rrr = tgen_mulsh, 1906}; 1907 1908static void tgen_mulu2(TCGContext *s, TCGType type, 1909 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1910{ 1911 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1912 tcg_out_opc_reg(s, insn, 0, a2, a3); 1913 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1914 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1915} 1916 1917static const TCGOutOpMul2 outop_mulu2 = { 1918 .base.static_constraint = C_Dynamic, 1919 .base.dynamic_constraint = cset_mul2, 1920 .out_rrrr = tgen_mulu2, 1921}; 1922 1923static void tgen_muluh(TCGContext *s, TCGType type, 1924 TCGReg a0, TCGReg a1, TCGReg a2) 1925{ 1926 if (use_mips32r6_instructions) { 1927 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; 1928 tcg_out_opc_reg(s, insn, a0, a1, a2); 1929 } else { 1930 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1931 tcg_out_opc_reg(s, insn, 0, a1, a2); 1932 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1933 } 1934} 1935 1936static const TCGOutOpBinary outop_muluh = { 1937 .base.static_constraint = C_O1_I2(r, r, r), 1938 .out_rrr = tgen_muluh, 1939}; 1940 1941static const TCGOutOpBinary outop_nand = { 1942 .base.static_constraint = C_NotImplemented, 1943}; 1944 1945static void tgen_nor(TCGContext *s, TCGType type, 1946 TCGReg a0, TCGReg a1, TCGReg a2) 1947{ 1948 tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); 1949} 1950 1951static const TCGOutOpBinary outop_nor = { 1952 .base.static_constraint = C_O1_I2(r, r, r), 1953 .out_rrr = tgen_nor, 1954}; 1955 1956static void tgen_or(TCGContext *s, TCGType type, 1957 TCGReg a0, TCGReg a1, TCGReg a2) 1958{ 1959 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1960} 1961 1962static void tgen_ori(TCGContext *s, TCGType type, 1963 TCGReg a0, TCGReg a1, tcg_target_long a2) 1964{ 1965 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1966} 1967 1968static const TCGOutOpBinary outop_or = { 1969 .base.static_constraint = C_O1_I2(r, r, rI), 1970 .out_rrr = tgen_or, 1971 .out_rri = tgen_ori, 1972}; 1973 1974static const TCGOutOpBinary outop_orc = { 1975 .base.static_constraint = C_NotImplemented, 1976}; 1977 1978static void tgen_rems(TCGContext *s, TCGType type, 1979 TCGReg a0, TCGReg a1, TCGReg a2) 1980{ 1981 if (use_mips32r6_instructions) { 1982 if (type == TCG_TYPE_I32) { 1983 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1984 } else { 1985 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1986 } 1987 } else { 1988 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1989 tcg_out_opc_reg(s, insn, 0, a1, a2); 1990 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1991 } 1992} 1993 1994static const TCGOutOpBinary outop_rems = { 1995 .base.static_constraint = C_O1_I2(r, r, r), 1996 .out_rrr = tgen_rems, 1997}; 1998 1999static void tgen_remu(TCGContext *s, TCGType type, 2000 TCGReg a0, TCGReg a1, TCGReg a2) 2001{ 2002 if (use_mips32r6_instructions) { 2003 if (type == TCG_TYPE_I32) { 2004 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 2005 } else { 2006 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 2007 } 2008 } else { 2009 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 2010 tcg_out_opc_reg(s, insn, 0, a1, a2); 2011 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 2012 } 2013} 2014 2015static const TCGOutOpBinary outop_remu = { 2016 .base.static_constraint = C_O1_I2(r, r, r), 2017 .out_rrr = tgen_remu, 2018}; 2019 2020static const TCGOutOpBinary outop_rotl = { 2021 .base.static_constraint = C_NotImplemented, 2022}; 2023 2024static TCGConstraintSetIndex cset_rotr(TCGType type, unsigned flags) 2025{ 2026 return use_mips32r2_instructions ? C_O1_I2(r, r, ri) : C_NotImplemented; 2027} 2028 2029static void tgen_rotr(TCGContext *s, TCGType type, 2030 TCGReg a0, TCGReg a1, TCGReg a2) 2031{ 2032 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; 2033 tcg_out_opc_reg(s, insn, a0, a1, a2); 2034} 2035 2036static void tgen_rotri(TCGContext *s, TCGType type, 2037 TCGReg a0, TCGReg a1, tcg_target_long a2) 2038{ 2039 if (type == TCG_TYPE_I32) { 2040 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); 2041 } else { 2042 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2043 } 2044} 2045 2046static const TCGOutOpBinary outop_rotr = { 2047 .base.static_constraint = C_Dynamic, 2048 .base.dynamic_constraint = cset_rotr, 2049 .out_rrr = tgen_rotr, 2050 .out_rri = tgen_rotri, 2051}; 2052 2053static void tgen_sar(TCGContext *s, TCGType type, 2054 TCGReg a0, TCGReg a1, TCGReg a2) 2055{ 2056 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; 2057 tcg_out_opc_reg(s, insn, a0, a1, a2); 2058} 2059 2060static void tgen_sari(TCGContext *s, TCGType type, 2061 TCGReg a0, TCGReg a1, tcg_target_long a2) 2062{ 2063 if (type == TCG_TYPE_I32) { 2064 tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); 2065 } else { 2066 tcg_out_dsra(s, a0, a1, a2); 2067 } 2068} 2069 2070static const TCGOutOpBinary outop_sar = { 2071 .base.static_constraint = C_O1_I2(r, r, ri), 2072 .out_rrr = tgen_sar, 2073 .out_rri = tgen_sari, 2074}; 2075 2076static void tgen_shl(TCGContext *s, TCGType type, 2077 TCGReg a0, TCGReg a1, TCGReg a2) 2078{ 2079 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; 2080 tcg_out_opc_reg(s, insn, a0, a1, a2); 2081} 2082 2083static void tgen_shli(TCGContext *s, TCGType type, 2084 TCGReg a0, TCGReg a1, tcg_target_long a2) 2085{ 2086 if (type == TCG_TYPE_I32) { 2087 tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); 2088 } else { 2089 tcg_out_dsll(s, a0, a1, a2); 2090 } 2091} 2092 2093static const TCGOutOpBinary outop_shl = { 2094 .base.static_constraint = C_O1_I2(r, r, ri), 2095 .out_rrr = tgen_shl, 2096 .out_rri = tgen_shli, 2097}; 2098 2099static void tgen_shr(TCGContext *s, TCGType type, 2100 TCGReg a0, TCGReg a1, TCGReg a2) 2101{ 2102 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; 2103 tcg_out_opc_reg(s, insn, a0, a1, a2); 2104} 2105 2106static void tgen_shri(TCGContext *s, TCGType type, 2107 TCGReg a0, TCGReg a1, tcg_target_long a2) 2108{ 2109 if (type == TCG_TYPE_I32) { 2110 tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); 2111 } else { 2112 tcg_out_dsrl(s, a0, a1, a2); 2113 } 2114} 2115 2116static const TCGOutOpBinary outop_shr = { 2117 .base.static_constraint = C_O1_I2(r, r, ri), 2118 .out_rrr = tgen_shr, 2119 .out_rri = tgen_shri, 2120}; 2121 2122static void tgen_sub(TCGContext *s, TCGType type, 2123 TCGReg a0, TCGReg a1, TCGReg a2) 2124{ 2125 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU; 2126 tcg_out_opc_reg(s, insn, a0, a1, a2); 2127} 2128 2129static const TCGOutOpSubtract outop_sub = { 2130 .base.static_constraint = C_O1_I2(r, r, r), 2131 .out_rrr = tgen_sub, 2132}; 2133 2134static void tgen_xor(TCGContext *s, TCGType type, 2135 TCGReg a0, TCGReg a1, TCGReg a2) 2136{ 2137 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2138} 2139 2140static void tgen_xori(TCGContext *s, TCGType type, 2141 TCGReg a0, TCGReg a1, tcg_target_long a2) 2142{ 2143 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2144} 2145 2146static const TCGOutOpBinary outop_xor = { 2147 .base.static_constraint = C_O1_I2(r, r, rI), 2148 .out_rrr = tgen_xor, 2149 .out_rri = tgen_xori, 2150}; 2151 2152static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2153{ 2154 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2155} 2156 2157static const TCGOutOpUnary outop_neg = { 2158 .base.static_constraint = C_O1_I1(r, r), 2159 .out_rr = tgen_neg, 2160}; 2161 2162static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2163{ 2164 tgen_nor(s, type, a0, TCG_REG_ZERO, a1); 2165} 2166 2167static const TCGOutOpUnary outop_not = { 2168 .base.static_constraint = C_O1_I1(r, r), 2169 .out_rr = tgen_not, 2170}; 2171 2172 2173static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2174 const TCGArg args[TCG_MAX_OP_ARGS], 2175 const int const_args[TCG_MAX_OP_ARGS]) 2176{ 2177 MIPSInsn i1; 2178 TCGArg a0, a1, a2; 2179 2180 a0 = args[0]; 2181 a1 = args[1]; 2182 a2 = args[2]; 2183 2184 switch (opc) { 2185 case INDEX_op_goto_ptr: 2186 /* jmp to the given host address (could be epilogue) */ 2187 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2188 if (TCG_TARGET_REG_BITS == 64) { 2189 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 2190 } else { 2191 tcg_out_nop(s); 2192 } 2193 break; 2194 case INDEX_op_br: 2195 tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, 2196 TCG_REG_ZERO, TCG_REG_ZERO, arg_label(a0)); 2197 break; 2198 2199 case INDEX_op_ld8u_i32: 2200 case INDEX_op_ld8u_i64: 2201 i1 = OPC_LBU; 2202 goto do_ldst; 2203 case INDEX_op_ld8s_i32: 2204 case INDEX_op_ld8s_i64: 2205 i1 = OPC_LB; 2206 goto do_ldst; 2207 case INDEX_op_ld16u_i32: 2208 case INDEX_op_ld16u_i64: 2209 i1 = OPC_LHU; 2210 goto do_ldst; 2211 case INDEX_op_ld16s_i32: 2212 case INDEX_op_ld16s_i64: 2213 i1 = OPC_LH; 2214 goto do_ldst; 2215 case INDEX_op_ld_i32: 2216 case INDEX_op_ld32s_i64: 2217 i1 = OPC_LW; 2218 goto do_ldst; 2219 case INDEX_op_ld32u_i64: 2220 i1 = OPC_LWU; 2221 goto do_ldst; 2222 case INDEX_op_ld_i64: 2223 i1 = OPC_LD; 2224 goto do_ldst; 2225 case INDEX_op_st8_i32: 2226 case INDEX_op_st8_i64: 2227 i1 = OPC_SB; 2228 goto do_ldst; 2229 case INDEX_op_st16_i32: 2230 case INDEX_op_st16_i64: 2231 i1 = OPC_SH; 2232 goto do_ldst; 2233 case INDEX_op_st_i32: 2234 case INDEX_op_st32_i64: 2235 i1 = OPC_SW; 2236 goto do_ldst; 2237 case INDEX_op_st_i64: 2238 i1 = OPC_SD; 2239 do_ldst: 2240 tcg_out_ldst(s, i1, a0, a1, a2); 2241 break; 2242 2243 case INDEX_op_bswap16_i32: 2244 case INDEX_op_bswap16_i64: 2245 tcg_out_bswap16(s, a0, a1, a2); 2246 break; 2247 case INDEX_op_bswap32_i32: 2248 tcg_out_bswap32(s, a0, a1, 0); 2249 break; 2250 case INDEX_op_bswap32_i64: 2251 tcg_out_bswap32(s, a0, a1, a2); 2252 break; 2253 case INDEX_op_bswap64_i64: 2254 tcg_out_bswap64(s, a0, a1); 2255 break; 2256 case INDEX_op_extrh_i64_i32: 2257 tcg_out_dsra(s, a0, a1, 32); 2258 break; 2259 2260 case INDEX_op_deposit_i32: 2261 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2262 break; 2263 case INDEX_op_deposit_i64: 2264 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2265 args[3] + args[4] - 1, args[3]); 2266 break; 2267 2268 case INDEX_op_extract_i32: 2269 if (a2 == 0 && args[3] <= 16) { 2270 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2271 } else { 2272 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2273 } 2274 break; 2275 case INDEX_op_extract_i64: 2276 if (a2 == 0 && args[3] <= 16) { 2277 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2278 } else { 2279 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2280 a0, a1, args[3] - 1, a2); 2281 } 2282 break; 2283 2284 case INDEX_op_sextract_i64: 2285 if (a2 == 0 && args[3] == 32) { 2286 tcg_out_ext32s(s, a0, a1); 2287 break; 2288 } 2289 /* FALLTHRU */ 2290 case INDEX_op_sextract_i32: 2291 if (a2 == 0 && args[3] == 8) { 2292 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 2293 } else if (a2 == 0 && args[3] == 16) { 2294 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 2295 } else { 2296 g_assert_not_reached(); 2297 } 2298 break; 2299 2300 case INDEX_op_brcond2_i32: 2301 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2302 break; 2303 2304 case INDEX_op_setcond2_i32: 2305 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2306 break; 2307 2308 case INDEX_op_qemu_ld_i32: 2309 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2310 break; 2311 case INDEX_op_qemu_ld_i64: 2312 if (TCG_TARGET_REG_BITS == 64) { 2313 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2314 } else { 2315 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2316 } 2317 break; 2318 2319 case INDEX_op_qemu_st_i32: 2320 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2321 break; 2322 case INDEX_op_qemu_st_i64: 2323 if (TCG_TARGET_REG_BITS == 64) { 2324 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2325 } else { 2326 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2327 } 2328 break; 2329 2330 case INDEX_op_add2_i32: 2331 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2332 const_args[4], const_args[5], false); 2333 break; 2334 case INDEX_op_sub2_i32: 2335 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2336 const_args[4], const_args[5], true); 2337 break; 2338 2339 case INDEX_op_mb: 2340 tcg_out_mb(s, a0); 2341 break; 2342 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2343 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2344 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2345 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2346 case INDEX_op_extu_i32_i64: 2347 case INDEX_op_extrl_i64_i32: 2348 default: 2349 g_assert_not_reached(); 2350 } 2351} 2352 2353static TCGConstraintSetIndex 2354tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2355{ 2356 switch (op) { 2357 case INDEX_op_goto_ptr: 2358 return C_O0_I1(r); 2359 2360 case INDEX_op_ld8u_i32: 2361 case INDEX_op_ld8s_i32: 2362 case INDEX_op_ld16u_i32: 2363 case INDEX_op_ld16s_i32: 2364 case INDEX_op_ld_i32: 2365 case INDEX_op_bswap16_i32: 2366 case INDEX_op_bswap32_i32: 2367 case INDEX_op_extract_i32: 2368 case INDEX_op_sextract_i32: 2369 case INDEX_op_ld8u_i64: 2370 case INDEX_op_ld8s_i64: 2371 case INDEX_op_ld16u_i64: 2372 case INDEX_op_ld16s_i64: 2373 case INDEX_op_ld32s_i64: 2374 case INDEX_op_ld32u_i64: 2375 case INDEX_op_ld_i64: 2376 case INDEX_op_bswap16_i64: 2377 case INDEX_op_bswap32_i64: 2378 case INDEX_op_bswap64_i64: 2379 case INDEX_op_ext_i32_i64: 2380 case INDEX_op_extu_i32_i64: 2381 case INDEX_op_extrl_i64_i32: 2382 case INDEX_op_extrh_i64_i32: 2383 case INDEX_op_extract_i64: 2384 case INDEX_op_sextract_i64: 2385 return C_O1_I1(r, r); 2386 2387 case INDEX_op_st8_i32: 2388 case INDEX_op_st16_i32: 2389 case INDEX_op_st_i32: 2390 case INDEX_op_st8_i64: 2391 case INDEX_op_st16_i64: 2392 case INDEX_op_st32_i64: 2393 case INDEX_op_st_i64: 2394 return C_O0_I2(rz, r); 2395 2396 case INDEX_op_deposit_i32: 2397 case INDEX_op_deposit_i64: 2398 return C_O1_I2(r, 0, rz); 2399 case INDEX_op_add2_i32: 2400 case INDEX_op_sub2_i32: 2401 return C_O2_I4(r, r, rz, rz, rN, rN); 2402 case INDEX_op_setcond2_i32: 2403 return C_O1_I4(r, rz, rz, rz, rz); 2404 case INDEX_op_brcond2_i32: 2405 return C_O0_I4(rz, rz, rz, rz); 2406 2407 case INDEX_op_qemu_ld_i32: 2408 return C_O1_I1(r, r); 2409 case INDEX_op_qemu_st_i32: 2410 return C_O0_I2(rz, r); 2411 case INDEX_op_qemu_ld_i64: 2412 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2413 case INDEX_op_qemu_st_i64: 2414 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2415 2416 default: 2417 return C_NotImplemented; 2418 } 2419} 2420 2421static const int tcg_target_callee_save_regs[] = { 2422 TCG_REG_S0, 2423 TCG_REG_S1, 2424 TCG_REG_S2, 2425 TCG_REG_S3, 2426 TCG_REG_S4, 2427 TCG_REG_S5, 2428 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2429 TCG_REG_S7, /* used for guest_base */ 2430 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2431 TCG_REG_RA, /* should be last for ABI compliance */ 2432}; 2433 2434/* The Linux kernel doesn't provide any information about the available 2435 instruction set. Probe it using a signal handler. */ 2436 2437 2438#ifndef use_movnz_instructions 2439bool use_movnz_instructions = false; 2440#endif 2441 2442#ifndef use_mips32_instructions 2443bool use_mips32_instructions = false; 2444#endif 2445 2446#ifndef use_mips32r2_instructions 2447bool use_mips32r2_instructions = false; 2448#endif 2449 2450static volatile sig_atomic_t got_sigill; 2451 2452static void sigill_handler(int signo, siginfo_t *si, void *data) 2453{ 2454 /* Skip the faulty instruction */ 2455 ucontext_t *uc = (ucontext_t *)data; 2456 uc->uc_mcontext.pc += 4; 2457 2458 got_sigill = 1; 2459} 2460 2461static void tcg_target_detect_isa(void) 2462{ 2463 struct sigaction sa_old, sa_new; 2464 2465 memset(&sa_new, 0, sizeof(sa_new)); 2466 sa_new.sa_flags = SA_SIGINFO; 2467 sa_new.sa_sigaction = sigill_handler; 2468 sigaction(SIGILL, &sa_new, &sa_old); 2469 2470 /* Probe for movn/movz, necessary to implement movcond. */ 2471#ifndef use_movnz_instructions 2472 got_sigill = 0; 2473 asm volatile(".set push\n" 2474 ".set mips32\n" 2475 "movn $zero, $zero, $zero\n" 2476 "movz $zero, $zero, $zero\n" 2477 ".set pop\n" 2478 : : : ); 2479 use_movnz_instructions = !got_sigill; 2480#endif 2481 2482 /* Probe for MIPS32 instructions. As no subsetting is allowed 2483 by the specification, it is only necessary to probe for one 2484 of the instructions. */ 2485#ifndef use_mips32_instructions 2486 got_sigill = 0; 2487 asm volatile(".set push\n" 2488 ".set mips32\n" 2489 "mul $zero, $zero\n" 2490 ".set pop\n" 2491 : : : ); 2492 use_mips32_instructions = !got_sigill; 2493#endif 2494 2495 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2496 available. As no subsetting is allowed by the specification, 2497 it is only necessary to probe for one of the instructions. */ 2498#ifndef use_mips32r2_instructions 2499 if (use_mips32_instructions) { 2500 got_sigill = 0; 2501 asm volatile(".set push\n" 2502 ".set mips32r2\n" 2503 "seb $zero, $zero\n" 2504 ".set pop\n" 2505 : : : ); 2506 use_mips32r2_instructions = !got_sigill; 2507 } 2508#endif 2509 2510 sigaction(SIGILL, &sa_old, NULL); 2511} 2512 2513static tcg_insn_unit *align_code_ptr(TCGContext *s) 2514{ 2515 uintptr_t p = (uintptr_t)s->code_ptr; 2516 if (p & 15) { 2517 p = (p + 15) & -16; 2518 s->code_ptr = (void *)p; 2519 } 2520 return s->code_ptr; 2521} 2522 2523/* Stack frame parameters. */ 2524#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2525#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2526#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2527 2528#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2529 + TCG_TARGET_STACK_ALIGN - 1) \ 2530 & -TCG_TARGET_STACK_ALIGN) 2531#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2532 2533/* We're expecting to be able to use an immediate for frame allocation. */ 2534QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2535 2536/* Generate global QEMU prologue and epilogue code */ 2537static void tcg_target_qemu_prologue(TCGContext *s) 2538{ 2539 int i; 2540 2541 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2542 2543 /* TB prologue */ 2544 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2545 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2546 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2547 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2548 } 2549 2550 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2551 /* 2552 * The function call abi for n32 and n64 will have loaded $25 (t9) 2553 * with the address of the prologue, so we can use that instead 2554 * of TCG_REG_TB. 2555 */ 2556#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2557# error "Unknown mips abi" 2558#endif 2559 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2560 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2561 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2562 } 2563 2564 if (TCG_TARGET_REG_BITS == 64) { 2565 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2566 } 2567 2568 /* Call generated code */ 2569 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2570 /* delay slot */ 2571 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2572 2573 /* 2574 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2575 * and fall through to the rest of the epilogue. 2576 */ 2577 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2578 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2579 2580 /* TB epilogue */ 2581 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2582 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2583 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2584 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2585 } 2586 2587 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2588 /* delay slot */ 2589 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2590 2591 if (use_mips32r2_instructions) { 2592 return; 2593 } 2594 2595 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2596 clobbers TCG_TMP1, TCG_TMP2. */ 2597 2598 /* 2599 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2600 */ 2601 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2602 /* t3 = (ssss)d000 */ 2603 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2604 /* t1 = 000a */ 2605 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2606 /* t2 = 00c0 */ 2607 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2608 /* t3 = d00a */ 2609 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2610 /* t1 = 0abc */ 2611 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2612 /* t2 = 0c00 */ 2613 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2614 /* t1 = 00b0 */ 2615 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2616 /* t3 = dc0a */ 2617 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2618 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2619 /* t3 = dcba -- delay slot */ 2620 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2621 2622 if (TCG_TARGET_REG_BITS == 32) { 2623 return; 2624 } 2625 2626 /* 2627 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2628 */ 2629 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2630 /* t1 = (0000)000d */ 2631 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2632 /* t3 = 000a */ 2633 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2634 /* t1 = (0000)d000 */ 2635 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2636 /* t2 = 00c0 */ 2637 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2638 /* t3 = d00a */ 2639 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2640 /* t1 = 0abc */ 2641 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2642 /* t2 = 0c00 */ 2643 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2644 /* t1 = 00b0 */ 2645 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2646 /* t3 = dc0a */ 2647 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2648 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2649 /* t3 = dcba -- delay slot */ 2650 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2651 2652 /* 2653 * bswap64 -- 64-bit swap. a0 = abcdefgh 2654 */ 2655 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2656 /* t3 = h0000000 */ 2657 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2658 /* t1 = 0000000a */ 2659 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2660 2661 /* t2 = 000000g0 */ 2662 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2663 /* t3 = h000000a */ 2664 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2665 /* t1 = 00000abc */ 2666 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2667 /* t2 = 0g000000 */ 2668 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2669 /* t1 = 000000b0 */ 2670 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2671 2672 /* t3 = hg00000a */ 2673 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2674 /* t2 = 0000abcd */ 2675 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2676 /* t3 = hg0000ba */ 2677 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2678 2679 /* t1 = 000000c0 */ 2680 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2681 /* t2 = 0000000d */ 2682 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2683 /* t1 = 00000c00 */ 2684 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2685 /* t2 = 0000d000 */ 2686 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2687 2688 /* t3 = hg000cba */ 2689 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2690 /* t1 = 00abcdef */ 2691 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2692 /* t3 = hg00dcba */ 2693 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2694 2695 /* t2 = 0000000f */ 2696 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2697 /* t1 = 000000e0 */ 2698 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2699 /* t2 = 00f00000 */ 2700 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2701 /* t1 = 000e0000 */ 2702 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2703 2704 /* t3 = hgf0dcba */ 2705 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2706 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2707 /* t3 = hgfedcba -- delay slot */ 2708 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2709} 2710 2711static void tcg_out_tb_start(TCGContext *s) 2712{ 2713 /* nothing to do */ 2714} 2715 2716static void tcg_target_init(TCGContext *s) 2717{ 2718 tcg_target_detect_isa(); 2719 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2720 if (TCG_TARGET_REG_BITS == 64) { 2721 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2722 } 2723 2724 tcg_target_call_clobber_regs = 0; 2725 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2726 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2727 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2728 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2729 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2730 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2731 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2732 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2733 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2734 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2735 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2736 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2737 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2738 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2741 2742 s->reserved_regs = 0; 2743 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2744 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2745 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2746 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2747 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2748 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2749 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2750 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2751 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2752 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2753 if (TCG_TARGET_REG_BITS == 64) { 2754 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2755 } 2756} 2757 2758typedef struct { 2759 DebugFrameHeader h; 2760 uint8_t fde_def_cfa[4]; 2761 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2762} DebugFrame; 2763 2764#define ELF_HOST_MACHINE EM_MIPS 2765/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2766 which is good because they're really quite complicated for MIPS. */ 2767 2768static const DebugFrame debug_frame = { 2769 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2770 .h.cie.id = -1, 2771 .h.cie.version = 1, 2772 .h.cie.code_align = 1, 2773 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2774 .h.cie.return_column = TCG_REG_RA, 2775 2776 /* Total FDE size does not include the "len" member. */ 2777 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2778 2779 .fde_def_cfa = { 2780 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2781 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2782 (FRAME_SIZE >> 7) 2783 }, 2784 .fde_reg_ofs = { 2785 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2786 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2787 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2788 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2789 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2790 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2791 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2792 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2793 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2794 } 2795}; 2796 2797void tcg_register_jit(const void *buf, size_t buf_size) 2798{ 2799 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2800} 2801