1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#ifdef HOST_WORDS_BIGENDIAN 28# define MIPS_BE 1 29#else 30# define MIPS_BE 0 31#endif 32 33#if TCG_TARGET_REG_BITS == 32 34# define LO_OFF (MIPS_BE * 4) 35# define HI_OFF (4 - LO_OFF) 36#else 37/* To assert at compile-time that these values are never used 38 for TCG_TARGET_REG_BITS == 64. */ 39int link_error(void); 40# define LO_OFF link_error() 41# define HI_OFF link_error() 42#endif 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "zero", 47 "at", 48 "v0", 49 "v1", 50 "a0", 51 "a1", 52 "a2", 53 "a3", 54 "t0", 55 "t1", 56 "t2", 57 "t3", 58 "t4", 59 "t5", 60 "t6", 61 "t7", 62 "s0", 63 "s1", 64 "s2", 65 "s3", 66 "s4", 67 "s5", 68 "s6", 69 "s7", 70 "t8", 71 "t9", 72 "k0", 73 "k1", 74 "gp", 75 "sp", 76 "s8", 77 "ra", 78}; 79#endif 80 81#define TCG_TMP0 TCG_REG_AT 82#define TCG_TMP1 TCG_REG_T9 83#define TCG_TMP2 TCG_REG_T8 84#define TCG_TMP3 TCG_REG_T7 85 86#ifndef CONFIG_SOFTMMU 87#define TCG_GUEST_BASE_REG TCG_REG_S1 88#endif 89 90/* check if we really need so many registers :P */ 91static const int tcg_target_reg_alloc_order[] = { 92 /* Call saved registers. */ 93 TCG_REG_S0, 94 TCG_REG_S1, 95 TCG_REG_S2, 96 TCG_REG_S3, 97 TCG_REG_S4, 98 TCG_REG_S5, 99 TCG_REG_S6, 100 TCG_REG_S7, 101 TCG_REG_S8, 102 103 /* Call clobbered registers. */ 104 TCG_REG_T4, 105 TCG_REG_T5, 106 TCG_REG_T6, 107 TCG_REG_T7, 108 TCG_REG_T8, 109 TCG_REG_T9, 110 TCG_REG_V1, 111 TCG_REG_V0, 112 113 /* Argument registers, opposite order of allocation. */ 114 TCG_REG_T3, 115 TCG_REG_T2, 116 TCG_REG_T1, 117 TCG_REG_T0, 118 TCG_REG_A3, 119 TCG_REG_A2, 120 TCG_REG_A1, 121 TCG_REG_A0, 122}; 123 124static const TCGReg tcg_target_call_iarg_regs[] = { 125 TCG_REG_A0, 126 TCG_REG_A1, 127 TCG_REG_A2, 128 TCG_REG_A3, 129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 130 TCG_REG_T0, 131 TCG_REG_T1, 132 TCG_REG_T2, 133 TCG_REG_T3, 134#endif 135}; 136 137static const TCGReg tcg_target_call_oarg_regs[2] = { 138 TCG_REG_V0, 139 TCG_REG_V1 140}; 141 142static const tcg_insn_unit *tb_ret_addr; 143static const tcg_insn_unit *bswap32_addr; 144static const tcg_insn_unit *bswap32u_addr; 145static const tcg_insn_unit *bswap64_addr; 146 147static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 148{ 149 /* Let the compiler perform the right-shift as part of the arithmetic. */ 150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 151 ptrdiff_t disp = target - (src_rx + 1); 152 if (disp == (int16_t)disp) { 153 *src_rw = deposit32(*src_rw, 0, 16, disp); 154 return true; 155 } 156 return false; 157} 158 159static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 160 intptr_t value, intptr_t addend) 161{ 162 tcg_debug_assert(type == R_MIPS_PC16); 163 tcg_debug_assert(addend == 0); 164 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 165} 166 167#define TCG_CT_CONST_ZERO 0x100 168#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 169#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 170#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 171#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 172#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 173 174#define ALL_GENERAL_REGS 0xffffffffu 175#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) 176 177#ifdef CONFIG_SOFTMMU 178#define ALL_QLOAD_REGS \ 179 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) 180#define ALL_QSTORE_REGS \ 181 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ 182 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ 183 : (1 << TCG_REG_A1))) 184#else 185#define ALL_QLOAD_REGS NOA0_REGS 186#define ALL_QSTORE_REGS NOA0_REGS 187#endif 188 189 190static inline bool is_p2m1(tcg_target_long val) 191{ 192 return val && ((val + 1) & val) == 0; 193} 194 195/* test if a constant matches the constraint */ 196static inline int tcg_target_const_match(tcg_target_long val, TCGType type, 197 const TCGArgConstraint *arg_ct) 198{ 199 int ct; 200 ct = arg_ct->ct; 201 if (ct & TCG_CT_CONST) { 202 return 1; 203 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 204 return 1; 205 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 206 return 1; 207 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 208 return 1; 209 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 210 return 1; 211 } else if ((ct & TCG_CT_CONST_P2M1) 212 && use_mips32r2_instructions && is_p2m1(val)) { 213 return 1; 214 } else if ((ct & TCG_CT_CONST_WSZ) 215 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 216 return 1; 217 } 218 return 0; 219} 220 221/* instruction opcodes */ 222typedef enum { 223 OPC_J = 002 << 26, 224 OPC_JAL = 003 << 26, 225 OPC_BEQ = 004 << 26, 226 OPC_BNE = 005 << 26, 227 OPC_BLEZ = 006 << 26, 228 OPC_BGTZ = 007 << 26, 229 OPC_ADDIU = 011 << 26, 230 OPC_SLTI = 012 << 26, 231 OPC_SLTIU = 013 << 26, 232 OPC_ANDI = 014 << 26, 233 OPC_ORI = 015 << 26, 234 OPC_XORI = 016 << 26, 235 OPC_LUI = 017 << 26, 236 OPC_DADDIU = 031 << 26, 237 OPC_LB = 040 << 26, 238 OPC_LH = 041 << 26, 239 OPC_LW = 043 << 26, 240 OPC_LBU = 044 << 26, 241 OPC_LHU = 045 << 26, 242 OPC_LWU = 047 << 26, 243 OPC_SB = 050 << 26, 244 OPC_SH = 051 << 26, 245 OPC_SW = 053 << 26, 246 OPC_LD = 067 << 26, 247 OPC_SD = 077 << 26, 248 249 OPC_SPECIAL = 000 << 26, 250 OPC_SLL = OPC_SPECIAL | 000, 251 OPC_SRL = OPC_SPECIAL | 002, 252 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 253 OPC_SRA = OPC_SPECIAL | 003, 254 OPC_SLLV = OPC_SPECIAL | 004, 255 OPC_SRLV = OPC_SPECIAL | 006, 256 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 257 OPC_SRAV = OPC_SPECIAL | 007, 258 OPC_JR_R5 = OPC_SPECIAL | 010, 259 OPC_JALR = OPC_SPECIAL | 011, 260 OPC_MOVZ = OPC_SPECIAL | 012, 261 OPC_MOVN = OPC_SPECIAL | 013, 262 OPC_SYNC = OPC_SPECIAL | 017, 263 OPC_MFHI = OPC_SPECIAL | 020, 264 OPC_MFLO = OPC_SPECIAL | 022, 265 OPC_DSLLV = OPC_SPECIAL | 024, 266 OPC_DSRLV = OPC_SPECIAL | 026, 267 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 268 OPC_DSRAV = OPC_SPECIAL | 027, 269 OPC_MULT = OPC_SPECIAL | 030, 270 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 271 OPC_MUH = OPC_SPECIAL | 030 | 0300, 272 OPC_MULTU = OPC_SPECIAL | 031, 273 OPC_MULU = OPC_SPECIAL | 031 | 0200, 274 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 275 OPC_DIV = OPC_SPECIAL | 032, 276 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 277 OPC_MOD = OPC_SPECIAL | 032 | 0300, 278 OPC_DIVU = OPC_SPECIAL | 033, 279 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 280 OPC_MODU = OPC_SPECIAL | 033 | 0300, 281 OPC_DMULT = OPC_SPECIAL | 034, 282 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 283 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 284 OPC_DMULTU = OPC_SPECIAL | 035, 285 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 286 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 287 OPC_DDIV = OPC_SPECIAL | 036, 288 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 289 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 290 OPC_DDIVU = OPC_SPECIAL | 037, 291 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 292 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 293 OPC_ADDU = OPC_SPECIAL | 041, 294 OPC_SUBU = OPC_SPECIAL | 043, 295 OPC_AND = OPC_SPECIAL | 044, 296 OPC_OR = OPC_SPECIAL | 045, 297 OPC_XOR = OPC_SPECIAL | 046, 298 OPC_NOR = OPC_SPECIAL | 047, 299 OPC_SLT = OPC_SPECIAL | 052, 300 OPC_SLTU = OPC_SPECIAL | 053, 301 OPC_DADDU = OPC_SPECIAL | 055, 302 OPC_DSUBU = OPC_SPECIAL | 057, 303 OPC_SELEQZ = OPC_SPECIAL | 065, 304 OPC_SELNEZ = OPC_SPECIAL | 067, 305 OPC_DSLL = OPC_SPECIAL | 070, 306 OPC_DSRL = OPC_SPECIAL | 072, 307 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 308 OPC_DSRA = OPC_SPECIAL | 073, 309 OPC_DSLL32 = OPC_SPECIAL | 074, 310 OPC_DSRL32 = OPC_SPECIAL | 076, 311 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 312 OPC_DSRA32 = OPC_SPECIAL | 077, 313 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 314 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 315 316 OPC_REGIMM = 001 << 26, 317 OPC_BLTZ = OPC_REGIMM | (000 << 16), 318 OPC_BGEZ = OPC_REGIMM | (001 << 16), 319 320 OPC_SPECIAL2 = 034 << 26, 321 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 322 OPC_CLZ = OPC_SPECIAL2 | 040, 323 OPC_DCLZ = OPC_SPECIAL2 | 044, 324 325 OPC_SPECIAL3 = 037 << 26, 326 OPC_EXT = OPC_SPECIAL3 | 000, 327 OPC_DEXTM = OPC_SPECIAL3 | 001, 328 OPC_DEXTU = OPC_SPECIAL3 | 002, 329 OPC_DEXT = OPC_SPECIAL3 | 003, 330 OPC_INS = OPC_SPECIAL3 | 004, 331 OPC_DINSM = OPC_SPECIAL3 | 005, 332 OPC_DINSU = OPC_SPECIAL3 | 006, 333 OPC_DINS = OPC_SPECIAL3 | 007, 334 OPC_WSBH = OPC_SPECIAL3 | 00240, 335 OPC_DSBH = OPC_SPECIAL3 | 00244, 336 OPC_DSHD = OPC_SPECIAL3 | 00544, 337 OPC_SEB = OPC_SPECIAL3 | 02040, 338 OPC_SEH = OPC_SPECIAL3 | 03040, 339 340 /* MIPS r6 doesn't have JR, JALR should be used instead */ 341 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 342 343 /* 344 * MIPS r6 replaces MUL with an alternative encoding which is 345 * backwards-compatible at the assembly level. 346 */ 347 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 348 349 /* MIPS r6 introduced names for weaker variants of SYNC. These are 350 backward compatible to previous architecture revisions. */ 351 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 352 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 353 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 354 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 355 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 356 357 /* Aliases for convenience. */ 358 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 359 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 360 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 361 ? OPC_SRL : OPC_DSRL, 362} MIPSInsn; 363 364/* 365 * Type reg 366 */ 367static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 368 TCGReg rd, TCGReg rs, TCGReg rt) 369{ 370 int32_t inst; 371 372 inst = opc; 373 inst |= (rs & 0x1F) << 21; 374 inst |= (rt & 0x1F) << 16; 375 inst |= (rd & 0x1F) << 11; 376 tcg_out32(s, inst); 377} 378 379/* 380 * Type immediate 381 */ 382static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 383 TCGReg rt, TCGReg rs, TCGArg imm) 384{ 385 int32_t inst; 386 387 inst = opc; 388 inst |= (rs & 0x1F) << 21; 389 inst |= (rt & 0x1F) << 16; 390 inst |= (imm & 0xffff); 391 tcg_out32(s, inst); 392} 393 394/* 395 * Type bitfield 396 */ 397static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 398 TCGReg rs, int msb, int lsb) 399{ 400 int32_t inst; 401 402 inst = opc; 403 inst |= (rs & 0x1F) << 21; 404 inst |= (rt & 0x1F) << 16; 405 inst |= (msb & 0x1F) << 11; 406 inst |= (lsb & 0x1F) << 6; 407 tcg_out32(s, inst); 408} 409 410static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 411 MIPSInsn oph, TCGReg rt, TCGReg rs, 412 int msb, int lsb) 413{ 414 if (lsb >= 32) { 415 opc = oph; 416 msb -= 32; 417 lsb -= 32; 418 } else if (msb >= 32) { 419 opc = opm; 420 msb -= 32; 421 } 422 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 423} 424 425/* 426 * Type branch 427 */ 428static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, 429 TCGReg rt, TCGReg rs) 430{ 431 tcg_out_opc_imm(s, opc, rt, rs, 0); 432} 433 434/* 435 * Type sa 436 */ 437static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 438 TCGReg rd, TCGReg rt, TCGArg sa) 439{ 440 int32_t inst; 441 442 inst = opc; 443 inst |= (rt & 0x1F) << 16; 444 inst |= (rd & 0x1F) << 11; 445 inst |= (sa & 0x1F) << 6; 446 tcg_out32(s, inst); 447 448} 449 450static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 451 TCGReg rd, TCGReg rt, TCGArg sa) 452{ 453 int32_t inst; 454 455 inst = (sa & 32 ? opc2 : opc1); 456 inst |= (rt & 0x1F) << 16; 457 inst |= (rd & 0x1F) << 11; 458 inst |= (sa & 0x1F) << 6; 459 tcg_out32(s, inst); 460} 461 462/* 463 * Type jump. 464 * Returns true if the branch was in range and the insn was emitted. 465 */ 466static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 467{ 468 uintptr_t dest = (uintptr_t)target; 469 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 470 int32_t inst; 471 472 /* The pc-region branch happens within the 256MB region of 473 the delay slot (thus the +4). */ 474 if ((from ^ dest) & -(1 << 28)) { 475 return false; 476 } 477 tcg_debug_assert((dest & 3) == 0); 478 479 inst = opc; 480 inst |= (dest >> 2) & 0x3ffffff; 481 tcg_out32(s, inst); 482 return true; 483} 484 485static inline void tcg_out_nop(TCGContext *s) 486{ 487 tcg_out32(s, 0); 488} 489 490static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 491{ 492 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 493} 494 495static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 496{ 497 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 498} 499 500static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 501{ 502 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 503} 504 505static inline bool tcg_out_mov(TCGContext *s, TCGType type, 506 TCGReg ret, TCGReg arg) 507{ 508 /* Simple reg-reg move, optimising out the 'do nothing' case */ 509 if (ret != arg) { 510 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 511 } 512 return true; 513} 514 515static void tcg_out_movi(TCGContext *s, TCGType type, 516 TCGReg ret, tcg_target_long arg) 517{ 518 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 519 arg = (int32_t)arg; 520 } 521 if (arg == (int16_t)arg) { 522 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 523 return; 524 } 525 if (arg == (uint16_t)arg) { 526 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 527 return; 528 } 529 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 530 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 531 } else { 532 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 533 if (arg & 0xffff0000ull) { 534 tcg_out_dsll(s, ret, ret, 16); 535 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 536 tcg_out_dsll(s, ret, ret, 16); 537 } else { 538 tcg_out_dsll(s, ret, ret, 32); 539 } 540 } 541 if (arg & 0xffff) { 542 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 543 } 544} 545 546static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) 547{ 548 if (use_mips32r2_instructions) { 549 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 550 } else { 551 /* ret and arg can't be register at */ 552 if (ret == TCG_TMP0 || arg == TCG_TMP0) { 553 tcg_abort(); 554 } 555 556 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); 557 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); 558 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); 559 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); 560 } 561} 562 563static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) 564{ 565 if (use_mips32r2_instructions) { 566 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 567 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); 568 } else { 569 /* ret and arg can't be register at */ 570 if (ret == TCG_TMP0 || arg == TCG_TMP0) { 571 tcg_abort(); 572 } 573 574 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); 575 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 576 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 577 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); 578 } 579} 580 581static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 582{ 583 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); 584 tcg_debug_assert(ok); 585} 586 587static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) 588{ 589 if (use_mips32r2_instructions) { 590 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 591 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 592 } else { 593 tcg_out_bswap_subr(s, bswap32_addr); 594 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 595 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 596 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 597 } 598} 599 600static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) 601{ 602 if (use_mips32r2_instructions) { 603 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 604 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 605 tcg_out_dsrl(s, ret, ret, 32); 606 } else { 607 tcg_out_bswap_subr(s, bswap32u_addr); 608 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 609 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 610 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 611 } 612} 613 614static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 615{ 616 if (use_mips32r2_instructions) { 617 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 618 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 619 } else { 620 tcg_out_bswap_subr(s, bswap64_addr); 621 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 622 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 623 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 624 } 625} 626 627static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) 628{ 629 if (use_mips32r2_instructions) { 630 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); 631 } else { 632 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 633 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); 634 } 635} 636 637static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) 638{ 639 if (use_mips32r2_instructions) { 640 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); 641 } else { 642 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); 643 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 644 } 645} 646 647static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 648{ 649 if (use_mips32r2_instructions) { 650 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 651 } else { 652 tcg_out_dsll(s, ret, arg, 32); 653 tcg_out_dsrl(s, ret, ret, 32); 654 } 655} 656 657static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 658 TCGReg addr, intptr_t ofs) 659{ 660 int16_t lo = ofs; 661 if (ofs != lo) { 662 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 663 if (addr != TCG_REG_ZERO) { 664 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 665 } 666 addr = TCG_TMP0; 667 } 668 tcg_out_opc_imm(s, opc, data, addr, lo); 669} 670 671static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 672 TCGReg arg1, intptr_t arg2) 673{ 674 MIPSInsn opc = OPC_LD; 675 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 676 opc = OPC_LW; 677 } 678 tcg_out_ldst(s, opc, arg, arg1, arg2); 679} 680 681static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 682 TCGReg arg1, intptr_t arg2) 683{ 684 MIPSInsn opc = OPC_SD; 685 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 686 opc = OPC_SW; 687 } 688 tcg_out_ldst(s, opc, arg, arg1, arg2); 689} 690 691static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 692 TCGReg base, intptr_t ofs) 693{ 694 if (val == 0) { 695 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 696 return true; 697 } 698 return false; 699} 700 701static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 702 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 703 bool cbh, bool is_sub) 704{ 705 TCGReg th = TCG_TMP1; 706 707 /* If we have a negative constant such that negating it would 708 make the high part zero, we can (usually) eliminate one insn. */ 709 if (cbl && cbh && bh == -1 && bl != 0) { 710 bl = -bl; 711 bh = 0; 712 is_sub = !is_sub; 713 } 714 715 /* By operating on the high part first, we get to use the final 716 carry operation to move back from the temporary. */ 717 if (!cbh) { 718 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 719 } else if (bh != 0 || ah == rl) { 720 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 721 } else { 722 th = ah; 723 } 724 725 /* Note that tcg optimization should eliminate the bl == 0 case. */ 726 if (is_sub) { 727 if (cbl) { 728 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 729 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 730 } else { 731 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 732 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 733 } 734 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 735 } else { 736 if (cbl) { 737 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 738 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 739 } else if (rl == al && rl == bl) { 740 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 741 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 742 } else { 743 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 744 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 745 } 746 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 747 } 748} 749 750/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 751#define MIPS_CMP_INV 1 752#define MIPS_CMP_SWAP 2 753 754static const uint8_t mips_cmp_map[16] = { 755 [TCG_COND_LT] = 0, 756 [TCG_COND_LTU] = 0, 757 [TCG_COND_GE] = MIPS_CMP_INV, 758 [TCG_COND_GEU] = MIPS_CMP_INV, 759 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 760 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 761 [TCG_COND_GT] = MIPS_CMP_SWAP, 762 [TCG_COND_GTU] = MIPS_CMP_SWAP, 763}; 764 765static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 766 TCGReg arg1, TCGReg arg2) 767{ 768 MIPSInsn s_opc = OPC_SLTU; 769 int cmp_map; 770 771 switch (cond) { 772 case TCG_COND_EQ: 773 if (arg2 != 0) { 774 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 775 arg1 = ret; 776 } 777 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 778 break; 779 780 case TCG_COND_NE: 781 if (arg2 != 0) { 782 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 783 arg1 = ret; 784 } 785 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 786 break; 787 788 case TCG_COND_LT: 789 case TCG_COND_GE: 790 case TCG_COND_LE: 791 case TCG_COND_GT: 792 s_opc = OPC_SLT; 793 /* FALLTHRU */ 794 795 case TCG_COND_LTU: 796 case TCG_COND_GEU: 797 case TCG_COND_LEU: 798 case TCG_COND_GTU: 799 cmp_map = mips_cmp_map[cond]; 800 if (cmp_map & MIPS_CMP_SWAP) { 801 TCGReg t = arg1; 802 arg1 = arg2; 803 arg2 = t; 804 } 805 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 806 if (cmp_map & MIPS_CMP_INV) { 807 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 808 } 809 break; 810 811 default: 812 tcg_abort(); 813 break; 814 } 815} 816 817static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 818 TCGReg arg2, TCGLabel *l) 819{ 820 static const MIPSInsn b_zero[16] = { 821 [TCG_COND_LT] = OPC_BLTZ, 822 [TCG_COND_GT] = OPC_BGTZ, 823 [TCG_COND_LE] = OPC_BLEZ, 824 [TCG_COND_GE] = OPC_BGEZ, 825 }; 826 827 MIPSInsn s_opc = OPC_SLTU; 828 MIPSInsn b_opc; 829 int cmp_map; 830 831 switch (cond) { 832 case TCG_COND_EQ: 833 b_opc = OPC_BEQ; 834 break; 835 case TCG_COND_NE: 836 b_opc = OPC_BNE; 837 break; 838 839 case TCG_COND_LT: 840 case TCG_COND_GT: 841 case TCG_COND_LE: 842 case TCG_COND_GE: 843 if (arg2 == 0) { 844 b_opc = b_zero[cond]; 845 arg2 = arg1; 846 arg1 = 0; 847 break; 848 } 849 s_opc = OPC_SLT; 850 /* FALLTHRU */ 851 852 case TCG_COND_LTU: 853 case TCG_COND_GTU: 854 case TCG_COND_LEU: 855 case TCG_COND_GEU: 856 cmp_map = mips_cmp_map[cond]; 857 if (cmp_map & MIPS_CMP_SWAP) { 858 TCGReg t = arg1; 859 arg1 = arg2; 860 arg2 = t; 861 } 862 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 863 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 864 arg1 = TCG_TMP0; 865 arg2 = TCG_REG_ZERO; 866 break; 867 868 default: 869 tcg_abort(); 870 break; 871 } 872 873 tcg_out_opc_br(s, b_opc, arg1, arg2); 874 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 875 tcg_out_nop(s); 876} 877 878static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 879 TCGReg al, TCGReg ah, 880 TCGReg bl, TCGReg bh) 881{ 882 /* Merge highpart comparison into AH. */ 883 if (bh != 0) { 884 if (ah != 0) { 885 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 886 ah = tmp0; 887 } else { 888 ah = bh; 889 } 890 } 891 /* Merge lowpart comparison into AL. */ 892 if (bl != 0) { 893 if (al != 0) { 894 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 895 al = tmp1; 896 } else { 897 al = bl; 898 } 899 } 900 /* Merge high and low part comparisons into AL. */ 901 if (ah != 0) { 902 if (al != 0) { 903 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 904 al = tmp0; 905 } else { 906 al = ah; 907 } 908 } 909 return al; 910} 911 912static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 913 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 914{ 915 TCGReg tmp0 = TCG_TMP0; 916 TCGReg tmp1 = ret; 917 918 tcg_debug_assert(ret != TCG_TMP0); 919 if (ret == ah || ret == bh) { 920 tcg_debug_assert(ret != TCG_TMP1); 921 tmp1 = TCG_TMP1; 922 } 923 924 switch (cond) { 925 case TCG_COND_EQ: 926 case TCG_COND_NE: 927 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 928 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 929 break; 930 931 default: 932 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 933 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 934 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 935 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 936 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 937 break; 938 } 939} 940 941static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 942 TCGReg bl, TCGReg bh, TCGLabel *l) 943{ 944 TCGCond b_cond = TCG_COND_NE; 945 TCGReg tmp = TCG_TMP1; 946 947 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 948 With setcond, we emit between 3 and 10 insns and only 1 branch, 949 which ought to get better branch prediction. */ 950 switch (cond) { 951 case TCG_COND_EQ: 952 case TCG_COND_NE: 953 b_cond = cond; 954 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 955 break; 956 957 default: 958 /* Minimize code size by preferring a compare not requiring INV. */ 959 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 960 cond = tcg_invert_cond(cond); 961 b_cond = TCG_COND_EQ; 962 } 963 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 964 break; 965 } 966 967 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 968} 969 970static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 971 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 972{ 973 bool eqz = false; 974 975 /* If one of the values is zero, put it last to match SEL*Z instructions */ 976 if (use_mips32r6_instructions && v1 == 0) { 977 v1 = v2; 978 v2 = 0; 979 cond = tcg_invert_cond(cond); 980 } 981 982 switch (cond) { 983 case TCG_COND_EQ: 984 eqz = true; 985 /* FALLTHRU */ 986 case TCG_COND_NE: 987 if (c2 != 0) { 988 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 989 c1 = TCG_TMP0; 990 } 991 break; 992 993 default: 994 /* Minimize code size by preferring a compare not requiring INV. */ 995 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 996 cond = tcg_invert_cond(cond); 997 eqz = true; 998 } 999 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 1000 c1 = TCG_TMP0; 1001 break; 1002 } 1003 1004 if (use_mips32r6_instructions) { 1005 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1006 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1007 1008 if (v2 != 0) { 1009 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1010 } 1011 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1012 if (v2 != 0) { 1013 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1014 } 1015 } else { 1016 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1017 1018 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1019 1020 /* This should be guaranteed via constraints */ 1021 tcg_debug_assert(v2 == ret); 1022 } 1023} 1024 1025static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1026{ 1027 /* Note that the ABI requires the called function's address to be 1028 loaded into T9, even if a direct branch is in range. */ 1029 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1030 1031 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1032 if (tail) { 1033 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1034 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1035 } 1036 } else { 1037 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1038 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1039 } 1040 } 1041} 1042 1043static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) 1044{ 1045 tcg_out_call_int(s, arg, false); 1046 tcg_out_nop(s); 1047} 1048 1049#if defined(CONFIG_SOFTMMU) 1050#include "../tcg-ldst.c.inc" 1051 1052static void * const qemu_ld_helpers[16] = { 1053 [MO_UB] = helper_ret_ldub_mmu, 1054 [MO_SB] = helper_ret_ldsb_mmu, 1055 [MO_LEUW] = helper_le_lduw_mmu, 1056 [MO_LESW] = helper_le_ldsw_mmu, 1057 [MO_LEUL] = helper_le_ldul_mmu, 1058 [MO_LEQ] = helper_le_ldq_mmu, 1059 [MO_BEUW] = helper_be_lduw_mmu, 1060 [MO_BESW] = helper_be_ldsw_mmu, 1061 [MO_BEUL] = helper_be_ldul_mmu, 1062 [MO_BEQ] = helper_be_ldq_mmu, 1063#if TCG_TARGET_REG_BITS == 64 1064 [MO_LESL] = helper_le_ldsl_mmu, 1065 [MO_BESL] = helper_be_ldsl_mmu, 1066#endif 1067}; 1068 1069static void * const qemu_st_helpers[16] = { 1070 [MO_UB] = helper_ret_stb_mmu, 1071 [MO_LEUW] = helper_le_stw_mmu, 1072 [MO_LEUL] = helper_le_stl_mmu, 1073 [MO_LEQ] = helper_le_stq_mmu, 1074 [MO_BEUW] = helper_be_stw_mmu, 1075 [MO_BEUL] = helper_be_stl_mmu, 1076 [MO_BEQ] = helper_be_stq_mmu, 1077}; 1078 1079/* Helper routines for marshalling helper function arguments into 1080 * the correct registers and stack. 1081 * I is where we want to put this argument, and is updated and returned 1082 * for the next call. ARG is the argument itself. 1083 * 1084 * We provide routines for arguments which are: immediate, 32 bit 1085 * value in register, 16 and 8 bit values in register (which must be zero 1086 * extended before use) and 64 bit value in a lo:hi register pair. 1087 */ 1088 1089static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) 1090{ 1091 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1092 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); 1093 } else { 1094 /* For N32 and N64, the initial offset is different. But there 1095 we also have 8 argument register so we don't run out here. */ 1096 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1097 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); 1098 } 1099 return i + 1; 1100} 1101 1102static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) 1103{ 1104 TCGReg tmp = TCG_TMP0; 1105 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1106 tmp = tcg_target_call_iarg_regs[i]; 1107 } 1108 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); 1109 return tcg_out_call_iarg_reg(s, i, tmp); 1110} 1111 1112static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) 1113{ 1114 TCGReg tmp = TCG_TMP0; 1115 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1116 tmp = tcg_target_call_iarg_regs[i]; 1117 } 1118 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); 1119 return tcg_out_call_iarg_reg(s, i, tmp); 1120} 1121 1122static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) 1123{ 1124 TCGReg tmp = TCG_TMP0; 1125 if (arg == 0) { 1126 tmp = TCG_REG_ZERO; 1127 } else { 1128 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1129 tmp = tcg_target_call_iarg_regs[i]; 1130 } 1131 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); 1132 } 1133 return tcg_out_call_iarg_reg(s, i, tmp); 1134} 1135 1136static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) 1137{ 1138 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1139 i = (i + 1) & ~1; 1140 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); 1141 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); 1142 return i; 1143} 1144 1145/* We expect to use a 16-bit negative offset from ENV. */ 1146QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1147QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1148 1149/* 1150 * Perform the tlb comparison operation. 1151 * The complete host address is placed in BASE. 1152 * Clobbers TMP0, TMP1, TMP2, TMP3. 1153 */ 1154static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, 1155 TCGReg addrh, TCGMemOpIdx oi, 1156 tcg_insn_unit *label_ptr[2], bool is_load) 1157{ 1158 MemOp opc = get_memop(oi); 1159 unsigned s_bits = opc & MO_SIZE; 1160 unsigned a_bits = get_alignment_bits(opc); 1161 int mem_index = get_mmuidx(oi); 1162 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1163 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1164 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1165 int add_off = offsetof(CPUTLBEntry, addend); 1166 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) 1167 : offsetof(CPUTLBEntry, addr_write)); 1168 target_ulong mask; 1169 1170 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1171 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1172 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1173 1174 /* Extract the TLB index from the address into TMP3. */ 1175 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, 1176 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1177 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1178 1179 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1180 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1181 1182 /* We don't currently support unaligned accesses. 1183 We could do so with mips32r6. */ 1184 if (a_bits < s_bits) { 1185 a_bits = s_bits; 1186 } 1187 1188 /* Mask the page bits, keeping the alignment bits to compare against. */ 1189 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 1190 1191 /* Load the (low-half) tlb comparator. */ 1192 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1193 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1194 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); 1195 } else { 1196 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD 1197 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), 1198 TCG_TMP0, TCG_TMP3, cmp_off); 1199 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); 1200 /* No second compare is required here; 1201 load the tlb addend for the fast path. */ 1202 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1203 } 1204 1205 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1206 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1207 tcg_out_ext32u(s, base, addrl); 1208 addrl = base; 1209 } 1210 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); 1211 1212 label_ptr[0] = s->code_ptr; 1213 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1214 1215 /* Load and test the high half tlb comparator. */ 1216 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1217 /* delay slot */ 1218 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1219 1220 /* Load the tlb addend for the fast path. */ 1221 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1222 1223 label_ptr[1] = s->code_ptr; 1224 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); 1225 } 1226 1227 /* delay slot */ 1228 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); 1229} 1230 1231static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, 1232 TCGType ext, 1233 TCGReg datalo, TCGReg datahi, 1234 TCGReg addrlo, TCGReg addrhi, 1235 void *raddr, tcg_insn_unit *label_ptr[2]) 1236{ 1237 TCGLabelQemuLdst *label = new_ldst_label(s); 1238 1239 label->is_ld = is_ld; 1240 label->oi = oi; 1241 label->type = ext; 1242 label->datalo_reg = datalo; 1243 label->datahi_reg = datahi; 1244 label->addrlo_reg = addrlo; 1245 label->addrhi_reg = addrhi; 1246 label->raddr = tcg_splitwx_to_rx(raddr); 1247 label->label_ptr[0] = label_ptr[0]; 1248 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1249 label->label_ptr[1] = label_ptr[1]; 1250 } 1251} 1252 1253static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1254{ 1255 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1256 TCGMemOpIdx oi = l->oi; 1257 MemOp opc = get_memop(oi); 1258 TCGReg v0; 1259 int i; 1260 1261 /* resolve label address */ 1262 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1263 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1264 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1265 return false; 1266 } 1267 1268 i = 1; 1269 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1270 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1271 } else { 1272 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1273 } 1274 i = tcg_out_call_iarg_imm(s, i, oi); 1275 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); 1276 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); 1277 /* delay slot */ 1278 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1279 1280 v0 = l->datalo_reg; 1281 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 1282 /* We eliminated V0 from the possible output registers, so it 1283 cannot be clobbered here. So we must move V1 first. */ 1284 if (MIPS_BE) { 1285 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); 1286 v0 = l->datahi_reg; 1287 } else { 1288 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); 1289 } 1290 } 1291 1292 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1293 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1294 return false; 1295 } 1296 1297 /* delay slot */ 1298 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { 1299 /* we always sign-extend 32-bit loads */ 1300 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); 1301 } else { 1302 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); 1303 } 1304 return true; 1305} 1306 1307static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1308{ 1309 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1310 TCGMemOpIdx oi = l->oi; 1311 MemOp opc = get_memop(oi); 1312 MemOp s_bits = opc & MO_SIZE; 1313 int i; 1314 1315 /* resolve label address */ 1316 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1317 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1318 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1319 return false; 1320 } 1321 1322 i = 1; 1323 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1324 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1325 } else { 1326 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1327 } 1328 switch (s_bits) { 1329 case MO_8: 1330 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); 1331 break; 1332 case MO_16: 1333 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); 1334 break; 1335 case MO_32: 1336 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1337 break; 1338 case MO_64: 1339 if (TCG_TARGET_REG_BITS == 32) { 1340 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); 1341 } else { 1342 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1343 } 1344 break; 1345 default: 1346 tcg_abort(); 1347 } 1348 i = tcg_out_call_iarg_imm(s, i, oi); 1349 1350 /* Tail call to the store helper. Thus force the return address 1351 computation to take place in the return address register. */ 1352 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); 1353 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); 1354 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); 1355 /* delay slot */ 1356 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1357 return true; 1358} 1359#endif 1360 1361static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1362 TCGReg base, MemOp opc, bool is_64) 1363{ 1364 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1365 case MO_UB: 1366 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1367 break; 1368 case MO_SB: 1369 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1370 break; 1371 case MO_UW | MO_BSWAP: 1372 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1373 tcg_out_bswap16(s, lo, TCG_TMP1); 1374 break; 1375 case MO_UW: 1376 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1377 break; 1378 case MO_SW | MO_BSWAP: 1379 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1380 tcg_out_bswap16s(s, lo, TCG_TMP1); 1381 break; 1382 case MO_SW: 1383 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1384 break; 1385 case MO_UL | MO_BSWAP: 1386 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1387 if (use_mips32r2_instructions) { 1388 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1389 tcg_out_bswap32u(s, lo, lo); 1390 } else { 1391 tcg_out_bswap_subr(s, bswap32u_addr); 1392 /* delay slot */ 1393 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); 1394 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1395 } 1396 break; 1397 } 1398 /* FALLTHRU */ 1399 case MO_SL | MO_BSWAP: 1400 if (use_mips32r2_instructions) { 1401 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1402 tcg_out_bswap32(s, lo, lo); 1403 } else { 1404 tcg_out_bswap_subr(s, bswap32_addr); 1405 /* delay slot */ 1406 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1407 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); 1408 } 1409 break; 1410 case MO_UL: 1411 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1412 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1413 break; 1414 } 1415 /* FALLTHRU */ 1416 case MO_SL: 1417 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1418 break; 1419 case MO_Q | MO_BSWAP: 1420 if (TCG_TARGET_REG_BITS == 64) { 1421 if (use_mips32r2_instructions) { 1422 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1423 tcg_out_bswap64(s, lo, lo); 1424 } else { 1425 tcg_out_bswap_subr(s, bswap64_addr); 1426 /* delay slot */ 1427 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); 1428 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1429 } 1430 } else if (use_mips32r2_instructions) { 1431 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1432 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); 1433 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1434 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1435 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1436 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1437 } else { 1438 tcg_out_bswap_subr(s, bswap32_addr); 1439 /* delay slot */ 1440 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1441 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); 1442 tcg_out_bswap_subr(s, bswap32_addr); 1443 /* delay slot */ 1444 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1445 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1446 } 1447 break; 1448 case MO_Q: 1449 /* Prefer to load from offset 0 first, but allow for overlap. */ 1450 if (TCG_TARGET_REG_BITS == 64) { 1451 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1452 } else if (MIPS_BE ? hi != base : lo == base) { 1453 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1454 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1455 } else { 1456 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1457 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1458 } 1459 break; 1460 default: 1461 tcg_abort(); 1462 } 1463} 1464 1465static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1466{ 1467 TCGReg addr_regl, addr_regh __attribute__((unused)); 1468 TCGReg data_regl, data_regh; 1469 TCGMemOpIdx oi; 1470 MemOp opc; 1471#if defined(CONFIG_SOFTMMU) 1472 tcg_insn_unit *label_ptr[2]; 1473#endif 1474 TCGReg base = TCG_REG_A0; 1475 1476 data_regl = *args++; 1477 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1478 addr_regl = *args++; 1479 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1480 oi = *args++; 1481 opc = get_memop(oi); 1482 1483#if defined(CONFIG_SOFTMMU) 1484 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); 1485 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1486 add_qemu_ldst_label(s, 1, oi, 1487 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1488 data_regl, data_regh, addr_regl, addr_regh, 1489 s->code_ptr, label_ptr); 1490#else 1491 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1492 tcg_out_ext32u(s, base, addr_regl); 1493 addr_regl = base; 1494 } 1495 if (guest_base == 0 && data_regl != addr_regl) { 1496 base = addr_regl; 1497 } else if (guest_base == (int16_t)guest_base) { 1498 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1499 } else { 1500 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1501 } 1502 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1503#endif 1504} 1505 1506static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1507 TCGReg base, MemOp opc) 1508{ 1509 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1510 if ((lo | hi) == 0) { 1511 opc &= ~MO_BSWAP; 1512 } 1513 1514 switch (opc & (MO_SIZE | MO_BSWAP)) { 1515 case MO_8: 1516 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1517 break; 1518 1519 case MO_16 | MO_BSWAP: 1520 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff); 1521 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1); 1522 lo = TCG_TMP1; 1523 /* FALLTHRU */ 1524 case MO_16: 1525 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1526 break; 1527 1528 case MO_32 | MO_BSWAP: 1529 tcg_out_bswap32(s, TCG_TMP3, lo); 1530 lo = TCG_TMP3; 1531 /* FALLTHRU */ 1532 case MO_32: 1533 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1534 break; 1535 1536 case MO_64 | MO_BSWAP: 1537 if (TCG_TARGET_REG_BITS == 64) { 1538 tcg_out_bswap64(s, TCG_TMP3, lo); 1539 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); 1540 } else if (use_mips32r2_instructions) { 1541 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); 1542 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); 1543 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1544 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1545 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); 1546 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); 1547 } else { 1548 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi); 1549 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); 1550 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo); 1551 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); 1552 } 1553 break; 1554 case MO_64: 1555 if (TCG_TARGET_REG_BITS == 64) { 1556 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1557 } else { 1558 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1559 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1560 } 1561 break; 1562 1563 default: 1564 tcg_abort(); 1565 } 1566} 1567 1568static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1569{ 1570 TCGReg addr_regl, addr_regh __attribute__((unused)); 1571 TCGReg data_regl, data_regh; 1572 TCGMemOpIdx oi; 1573 MemOp opc; 1574#if defined(CONFIG_SOFTMMU) 1575 tcg_insn_unit *label_ptr[2]; 1576#endif 1577 TCGReg base = TCG_REG_A0; 1578 1579 data_regl = *args++; 1580 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1581 addr_regl = *args++; 1582 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1583 oi = *args++; 1584 opc = get_memop(oi); 1585 1586#if defined(CONFIG_SOFTMMU) 1587 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); 1588 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1589 add_qemu_ldst_label(s, 0, oi, 1590 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1591 data_regl, data_regh, addr_regl, addr_regh, 1592 s->code_ptr, label_ptr); 1593#else 1594 base = TCG_REG_A0; 1595 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1596 tcg_out_ext32u(s, base, addr_regl); 1597 addr_regl = base; 1598 } 1599 if (guest_base == 0) { 1600 base = addr_regl; 1601 } else if (guest_base == (int16_t)guest_base) { 1602 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1603 } else { 1604 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1605 } 1606 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1607#endif 1608} 1609 1610static void tcg_out_mb(TCGContext *s, TCGArg a0) 1611{ 1612 static const MIPSInsn sync[] = { 1613 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1614 as the former is an ordering barrier and the latter 1615 is a completion barrier. */ 1616 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1617 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1618 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1619 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1620 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1621 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1622 }; 1623 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1624} 1625 1626static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1627 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1628{ 1629 if (use_mips32r6_instructions) { 1630 if (a2 == width) { 1631 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1632 } else { 1633 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1634 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1635 } 1636 } else { 1637 if (a2 == width) { 1638 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1639 } else if (a0 == a2) { 1640 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1641 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1642 } else if (a0 != a1) { 1643 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1644 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1645 } else { 1646 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1647 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1648 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1649 } 1650 } 1651} 1652 1653static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 1654 const TCGArg args[TCG_MAX_OP_ARGS], 1655 const int const_args[TCG_MAX_OP_ARGS]) 1656{ 1657 MIPSInsn i1, i2; 1658 TCGArg a0, a1, a2; 1659 int c2; 1660 1661 /* 1662 * Note that many operands use the constraint set "rZ". 1663 * We make use of the fact that 0 is the ZERO register, 1664 * and hence such cases need not check for const_args. 1665 */ 1666 a0 = args[0]; 1667 a1 = args[1]; 1668 a2 = args[2]; 1669 c2 = const_args[2]; 1670 1671 switch (opc) { 1672 case INDEX_op_exit_tb: 1673 { 1674 TCGReg b0 = TCG_REG_ZERO; 1675 1676 a0 = (intptr_t)a0; 1677 if (a0 & ~0xffff) { 1678 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 1679 b0 = TCG_REG_V0; 1680 } 1681 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1682 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, 1683 (uintptr_t)tb_ret_addr); 1684 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1685 } 1686 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 1687 } 1688 break; 1689 case INDEX_op_goto_tb: 1690 if (s->tb_jmp_insn_offset) { 1691 /* direct jump method */ 1692 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); 1693 /* Avoid clobbering the address during retranslation. */ 1694 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); 1695 } else { 1696 /* indirect jump method */ 1697 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 1698 (uintptr_t)(s->tb_jmp_target_addr + a0)); 1699 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1700 } 1701 tcg_out_nop(s); 1702 set_jmp_reset_offset(s, a0); 1703 break; 1704 case INDEX_op_goto_ptr: 1705 /* jmp to the given host address (could be epilogue) */ 1706 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1707 tcg_out_nop(s); 1708 break; 1709 case INDEX_op_br: 1710 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1711 arg_label(a0)); 1712 break; 1713 1714 case INDEX_op_ld8u_i32: 1715 case INDEX_op_ld8u_i64: 1716 i1 = OPC_LBU; 1717 goto do_ldst; 1718 case INDEX_op_ld8s_i32: 1719 case INDEX_op_ld8s_i64: 1720 i1 = OPC_LB; 1721 goto do_ldst; 1722 case INDEX_op_ld16u_i32: 1723 case INDEX_op_ld16u_i64: 1724 i1 = OPC_LHU; 1725 goto do_ldst; 1726 case INDEX_op_ld16s_i32: 1727 case INDEX_op_ld16s_i64: 1728 i1 = OPC_LH; 1729 goto do_ldst; 1730 case INDEX_op_ld_i32: 1731 case INDEX_op_ld32s_i64: 1732 i1 = OPC_LW; 1733 goto do_ldst; 1734 case INDEX_op_ld32u_i64: 1735 i1 = OPC_LWU; 1736 goto do_ldst; 1737 case INDEX_op_ld_i64: 1738 i1 = OPC_LD; 1739 goto do_ldst; 1740 case INDEX_op_st8_i32: 1741 case INDEX_op_st8_i64: 1742 i1 = OPC_SB; 1743 goto do_ldst; 1744 case INDEX_op_st16_i32: 1745 case INDEX_op_st16_i64: 1746 i1 = OPC_SH; 1747 goto do_ldst; 1748 case INDEX_op_st_i32: 1749 case INDEX_op_st32_i64: 1750 i1 = OPC_SW; 1751 goto do_ldst; 1752 case INDEX_op_st_i64: 1753 i1 = OPC_SD; 1754 do_ldst: 1755 tcg_out_ldst(s, i1, a0, a1, a2); 1756 break; 1757 1758 case INDEX_op_add_i32: 1759 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1760 goto do_binary; 1761 case INDEX_op_add_i64: 1762 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1763 goto do_binary; 1764 case INDEX_op_or_i32: 1765 case INDEX_op_or_i64: 1766 i1 = OPC_OR, i2 = OPC_ORI; 1767 goto do_binary; 1768 case INDEX_op_xor_i32: 1769 case INDEX_op_xor_i64: 1770 i1 = OPC_XOR, i2 = OPC_XORI; 1771 do_binary: 1772 if (c2) { 1773 tcg_out_opc_imm(s, i2, a0, a1, a2); 1774 break; 1775 } 1776 do_binaryv: 1777 tcg_out_opc_reg(s, i1, a0, a1, a2); 1778 break; 1779 1780 case INDEX_op_sub_i32: 1781 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1782 goto do_subtract; 1783 case INDEX_op_sub_i64: 1784 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1785 do_subtract: 1786 if (c2) { 1787 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1788 break; 1789 } 1790 goto do_binaryv; 1791 case INDEX_op_and_i32: 1792 if (c2 && a2 != (uint16_t)a2) { 1793 int msb = ctz32(~a2) - 1; 1794 tcg_debug_assert(use_mips32r2_instructions); 1795 tcg_debug_assert(is_p2m1(a2)); 1796 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1797 break; 1798 } 1799 i1 = OPC_AND, i2 = OPC_ANDI; 1800 goto do_binary; 1801 case INDEX_op_and_i64: 1802 if (c2 && a2 != (uint16_t)a2) { 1803 int msb = ctz64(~a2) - 1; 1804 tcg_debug_assert(use_mips32r2_instructions); 1805 tcg_debug_assert(is_p2m1(a2)); 1806 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1807 break; 1808 } 1809 i1 = OPC_AND, i2 = OPC_ANDI; 1810 goto do_binary; 1811 case INDEX_op_nor_i32: 1812 case INDEX_op_nor_i64: 1813 i1 = OPC_NOR; 1814 goto do_binaryv; 1815 1816 case INDEX_op_mul_i32: 1817 if (use_mips32_instructions) { 1818 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1819 break; 1820 } 1821 i1 = OPC_MULT, i2 = OPC_MFLO; 1822 goto do_hilo1; 1823 case INDEX_op_mulsh_i32: 1824 if (use_mips32r6_instructions) { 1825 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1826 break; 1827 } 1828 i1 = OPC_MULT, i2 = OPC_MFHI; 1829 goto do_hilo1; 1830 case INDEX_op_muluh_i32: 1831 if (use_mips32r6_instructions) { 1832 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1833 break; 1834 } 1835 i1 = OPC_MULTU, i2 = OPC_MFHI; 1836 goto do_hilo1; 1837 case INDEX_op_div_i32: 1838 if (use_mips32r6_instructions) { 1839 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1840 break; 1841 } 1842 i1 = OPC_DIV, i2 = OPC_MFLO; 1843 goto do_hilo1; 1844 case INDEX_op_divu_i32: 1845 if (use_mips32r6_instructions) { 1846 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1847 break; 1848 } 1849 i1 = OPC_DIVU, i2 = OPC_MFLO; 1850 goto do_hilo1; 1851 case INDEX_op_rem_i32: 1852 if (use_mips32r6_instructions) { 1853 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1854 break; 1855 } 1856 i1 = OPC_DIV, i2 = OPC_MFHI; 1857 goto do_hilo1; 1858 case INDEX_op_remu_i32: 1859 if (use_mips32r6_instructions) { 1860 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1861 break; 1862 } 1863 i1 = OPC_DIVU, i2 = OPC_MFHI; 1864 goto do_hilo1; 1865 case INDEX_op_mul_i64: 1866 if (use_mips32r6_instructions) { 1867 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1868 break; 1869 } 1870 i1 = OPC_DMULT, i2 = OPC_MFLO; 1871 goto do_hilo1; 1872 case INDEX_op_mulsh_i64: 1873 if (use_mips32r6_instructions) { 1874 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1875 break; 1876 } 1877 i1 = OPC_DMULT, i2 = OPC_MFHI; 1878 goto do_hilo1; 1879 case INDEX_op_muluh_i64: 1880 if (use_mips32r6_instructions) { 1881 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1882 break; 1883 } 1884 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1885 goto do_hilo1; 1886 case INDEX_op_div_i64: 1887 if (use_mips32r6_instructions) { 1888 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1889 break; 1890 } 1891 i1 = OPC_DDIV, i2 = OPC_MFLO; 1892 goto do_hilo1; 1893 case INDEX_op_divu_i64: 1894 if (use_mips32r6_instructions) { 1895 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1896 break; 1897 } 1898 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1899 goto do_hilo1; 1900 case INDEX_op_rem_i64: 1901 if (use_mips32r6_instructions) { 1902 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1903 break; 1904 } 1905 i1 = OPC_DDIV, i2 = OPC_MFHI; 1906 goto do_hilo1; 1907 case INDEX_op_remu_i64: 1908 if (use_mips32r6_instructions) { 1909 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1910 break; 1911 } 1912 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1913 do_hilo1: 1914 tcg_out_opc_reg(s, i1, 0, a1, a2); 1915 tcg_out_opc_reg(s, i2, a0, 0, 0); 1916 break; 1917 1918 case INDEX_op_muls2_i32: 1919 i1 = OPC_MULT; 1920 goto do_hilo2; 1921 case INDEX_op_mulu2_i32: 1922 i1 = OPC_MULTU; 1923 goto do_hilo2; 1924 case INDEX_op_muls2_i64: 1925 i1 = OPC_DMULT; 1926 goto do_hilo2; 1927 case INDEX_op_mulu2_i64: 1928 i1 = OPC_DMULTU; 1929 do_hilo2: 1930 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1931 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1932 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1933 break; 1934 1935 case INDEX_op_not_i32: 1936 case INDEX_op_not_i64: 1937 i1 = OPC_NOR; 1938 goto do_unary; 1939 case INDEX_op_bswap16_i32: 1940 case INDEX_op_bswap16_i64: 1941 i1 = OPC_WSBH; 1942 goto do_unary; 1943 case INDEX_op_ext8s_i32: 1944 case INDEX_op_ext8s_i64: 1945 i1 = OPC_SEB; 1946 goto do_unary; 1947 case INDEX_op_ext16s_i32: 1948 case INDEX_op_ext16s_i64: 1949 i1 = OPC_SEH; 1950 do_unary: 1951 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1952 break; 1953 1954 case INDEX_op_bswap32_i32: 1955 tcg_out_bswap32(s, a0, a1); 1956 break; 1957 case INDEX_op_bswap32_i64: 1958 tcg_out_bswap32u(s, a0, a1); 1959 break; 1960 case INDEX_op_bswap64_i64: 1961 tcg_out_bswap64(s, a0, a1); 1962 break; 1963 case INDEX_op_extrh_i64_i32: 1964 tcg_out_dsra(s, a0, a1, 32); 1965 break; 1966 case INDEX_op_ext32s_i64: 1967 case INDEX_op_ext_i32_i64: 1968 case INDEX_op_extrl_i64_i32: 1969 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); 1970 break; 1971 case INDEX_op_ext32u_i64: 1972 case INDEX_op_extu_i32_i64: 1973 tcg_out_ext32u(s, a0, a1); 1974 break; 1975 1976 case INDEX_op_sar_i32: 1977 i1 = OPC_SRAV, i2 = OPC_SRA; 1978 goto do_shift; 1979 case INDEX_op_shl_i32: 1980 i1 = OPC_SLLV, i2 = OPC_SLL; 1981 goto do_shift; 1982 case INDEX_op_shr_i32: 1983 i1 = OPC_SRLV, i2 = OPC_SRL; 1984 goto do_shift; 1985 case INDEX_op_rotr_i32: 1986 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1987 do_shift: 1988 if (c2) { 1989 tcg_out_opc_sa(s, i2, a0, a1, a2); 1990 break; 1991 } 1992 do_shiftv: 1993 tcg_out_opc_reg(s, i1, a0, a2, a1); 1994 break; 1995 case INDEX_op_rotl_i32: 1996 if (c2) { 1997 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 1998 } else { 1999 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2000 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 2001 } 2002 break; 2003 case INDEX_op_sar_i64: 2004 if (c2) { 2005 tcg_out_dsra(s, a0, a1, a2); 2006 break; 2007 } 2008 i1 = OPC_DSRAV; 2009 goto do_shiftv; 2010 case INDEX_op_shl_i64: 2011 if (c2) { 2012 tcg_out_dsll(s, a0, a1, a2); 2013 break; 2014 } 2015 i1 = OPC_DSLLV; 2016 goto do_shiftv; 2017 case INDEX_op_shr_i64: 2018 if (c2) { 2019 tcg_out_dsrl(s, a0, a1, a2); 2020 break; 2021 } 2022 i1 = OPC_DSRLV; 2023 goto do_shiftv; 2024 case INDEX_op_rotr_i64: 2025 if (c2) { 2026 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2027 break; 2028 } 2029 i1 = OPC_DROTRV; 2030 goto do_shiftv; 2031 case INDEX_op_rotl_i64: 2032 if (c2) { 2033 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2034 } else { 2035 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2036 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2037 } 2038 break; 2039 2040 case INDEX_op_clz_i32: 2041 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2042 break; 2043 case INDEX_op_clz_i64: 2044 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2045 break; 2046 2047 case INDEX_op_deposit_i32: 2048 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2049 break; 2050 case INDEX_op_deposit_i64: 2051 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2052 args[3] + args[4] - 1, args[3]); 2053 break; 2054 case INDEX_op_extract_i32: 2055 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2056 break; 2057 case INDEX_op_extract_i64: 2058 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2059 args[3] - 1, a2); 2060 break; 2061 2062 case INDEX_op_brcond_i32: 2063 case INDEX_op_brcond_i64: 2064 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2065 break; 2066 case INDEX_op_brcond2_i32: 2067 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2068 break; 2069 2070 case INDEX_op_movcond_i32: 2071 case INDEX_op_movcond_i64: 2072 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2073 break; 2074 2075 case INDEX_op_setcond_i32: 2076 case INDEX_op_setcond_i64: 2077 tcg_out_setcond(s, args[3], a0, a1, a2); 2078 break; 2079 case INDEX_op_setcond2_i32: 2080 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2081 break; 2082 2083 case INDEX_op_qemu_ld_i32: 2084 tcg_out_qemu_ld(s, args, false); 2085 break; 2086 case INDEX_op_qemu_ld_i64: 2087 tcg_out_qemu_ld(s, args, true); 2088 break; 2089 case INDEX_op_qemu_st_i32: 2090 tcg_out_qemu_st(s, args, false); 2091 break; 2092 case INDEX_op_qemu_st_i64: 2093 tcg_out_qemu_st(s, args, true); 2094 break; 2095 2096 case INDEX_op_add2_i32: 2097 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2098 const_args[4], const_args[5], false); 2099 break; 2100 case INDEX_op_sub2_i32: 2101 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2102 const_args[4], const_args[5], true); 2103 break; 2104 2105 case INDEX_op_mb: 2106 tcg_out_mb(s, a0); 2107 break; 2108 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2109 case INDEX_op_mov_i64: 2110 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2111 default: 2112 tcg_abort(); 2113 } 2114} 2115 2116static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2117{ 2118 switch (op) { 2119 case INDEX_op_goto_ptr: 2120 return C_O0_I1(r); 2121 2122 case INDEX_op_ld8u_i32: 2123 case INDEX_op_ld8s_i32: 2124 case INDEX_op_ld16u_i32: 2125 case INDEX_op_ld16s_i32: 2126 case INDEX_op_ld_i32: 2127 case INDEX_op_not_i32: 2128 case INDEX_op_bswap16_i32: 2129 case INDEX_op_bswap32_i32: 2130 case INDEX_op_ext8s_i32: 2131 case INDEX_op_ext16s_i32: 2132 case INDEX_op_extract_i32: 2133 case INDEX_op_ld8u_i64: 2134 case INDEX_op_ld8s_i64: 2135 case INDEX_op_ld16u_i64: 2136 case INDEX_op_ld16s_i64: 2137 case INDEX_op_ld32s_i64: 2138 case INDEX_op_ld32u_i64: 2139 case INDEX_op_ld_i64: 2140 case INDEX_op_not_i64: 2141 case INDEX_op_bswap16_i64: 2142 case INDEX_op_bswap32_i64: 2143 case INDEX_op_bswap64_i64: 2144 case INDEX_op_ext8s_i64: 2145 case INDEX_op_ext16s_i64: 2146 case INDEX_op_ext32s_i64: 2147 case INDEX_op_ext32u_i64: 2148 case INDEX_op_ext_i32_i64: 2149 case INDEX_op_extu_i32_i64: 2150 case INDEX_op_extrl_i64_i32: 2151 case INDEX_op_extrh_i64_i32: 2152 case INDEX_op_extract_i64: 2153 return C_O1_I1(r, r); 2154 2155 case INDEX_op_st8_i32: 2156 case INDEX_op_st16_i32: 2157 case INDEX_op_st_i32: 2158 case INDEX_op_st8_i64: 2159 case INDEX_op_st16_i64: 2160 case INDEX_op_st32_i64: 2161 case INDEX_op_st_i64: 2162 return C_O0_I2(rZ, r); 2163 2164 case INDEX_op_add_i32: 2165 case INDEX_op_add_i64: 2166 return C_O1_I2(r, r, rJ); 2167 case INDEX_op_sub_i32: 2168 case INDEX_op_sub_i64: 2169 return C_O1_I2(r, rZ, rN); 2170 case INDEX_op_mul_i32: 2171 case INDEX_op_mulsh_i32: 2172 case INDEX_op_muluh_i32: 2173 case INDEX_op_div_i32: 2174 case INDEX_op_divu_i32: 2175 case INDEX_op_rem_i32: 2176 case INDEX_op_remu_i32: 2177 case INDEX_op_nor_i32: 2178 case INDEX_op_setcond_i32: 2179 case INDEX_op_mul_i64: 2180 case INDEX_op_mulsh_i64: 2181 case INDEX_op_muluh_i64: 2182 case INDEX_op_div_i64: 2183 case INDEX_op_divu_i64: 2184 case INDEX_op_rem_i64: 2185 case INDEX_op_remu_i64: 2186 case INDEX_op_nor_i64: 2187 case INDEX_op_setcond_i64: 2188 return C_O1_I2(r, rZ, rZ); 2189 case INDEX_op_muls2_i32: 2190 case INDEX_op_mulu2_i32: 2191 case INDEX_op_muls2_i64: 2192 case INDEX_op_mulu2_i64: 2193 return C_O2_I2(r, r, r, r); 2194 case INDEX_op_and_i32: 2195 case INDEX_op_and_i64: 2196 return C_O1_I2(r, r, rIK); 2197 case INDEX_op_or_i32: 2198 case INDEX_op_xor_i32: 2199 case INDEX_op_or_i64: 2200 case INDEX_op_xor_i64: 2201 return C_O1_I2(r, r, rI); 2202 case INDEX_op_shl_i32: 2203 case INDEX_op_shr_i32: 2204 case INDEX_op_sar_i32: 2205 case INDEX_op_rotr_i32: 2206 case INDEX_op_rotl_i32: 2207 case INDEX_op_shl_i64: 2208 case INDEX_op_shr_i64: 2209 case INDEX_op_sar_i64: 2210 case INDEX_op_rotr_i64: 2211 case INDEX_op_rotl_i64: 2212 return C_O1_I2(r, r, ri); 2213 case INDEX_op_clz_i32: 2214 case INDEX_op_clz_i64: 2215 return C_O1_I2(r, r, rWZ); 2216 2217 case INDEX_op_deposit_i32: 2218 case INDEX_op_deposit_i64: 2219 return C_O1_I2(r, 0, rZ); 2220 case INDEX_op_brcond_i32: 2221 case INDEX_op_brcond_i64: 2222 return C_O0_I2(rZ, rZ); 2223 case INDEX_op_movcond_i32: 2224 case INDEX_op_movcond_i64: 2225 return (use_mips32r6_instructions 2226 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2227 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2228 case INDEX_op_add2_i32: 2229 case INDEX_op_sub2_i32: 2230 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2231 case INDEX_op_setcond2_i32: 2232 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2233 case INDEX_op_brcond2_i32: 2234 return C_O0_I4(rZ, rZ, rZ, rZ); 2235 2236 case INDEX_op_qemu_ld_i32: 2237 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2238 ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); 2239 case INDEX_op_qemu_st_i32: 2240 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2241 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); 2242 case INDEX_op_qemu_ld_i64: 2243 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) 2244 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) 2245 : C_O2_I2(r, r, L, L)); 2246 case INDEX_op_qemu_st_i64: 2247 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) 2248 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) 2249 : C_O0_I4(SZ, SZ, S, S)); 2250 2251 default: 2252 g_assert_not_reached(); 2253 } 2254} 2255 2256static const int tcg_target_callee_save_regs[] = { 2257 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2258 TCG_REG_S1, 2259 TCG_REG_S2, 2260 TCG_REG_S3, 2261 TCG_REG_S4, 2262 TCG_REG_S5, 2263 TCG_REG_S6, 2264 TCG_REG_S7, 2265 TCG_REG_S8, 2266 TCG_REG_RA, /* should be last for ABI compliance */ 2267}; 2268 2269/* The Linux kernel doesn't provide any information about the available 2270 instruction set. Probe it using a signal handler. */ 2271 2272 2273#ifndef use_movnz_instructions 2274bool use_movnz_instructions = false; 2275#endif 2276 2277#ifndef use_mips32_instructions 2278bool use_mips32_instructions = false; 2279#endif 2280 2281#ifndef use_mips32r2_instructions 2282bool use_mips32r2_instructions = false; 2283#endif 2284 2285static volatile sig_atomic_t got_sigill; 2286 2287static void sigill_handler(int signo, siginfo_t *si, void *data) 2288{ 2289 /* Skip the faulty instruction */ 2290 ucontext_t *uc = (ucontext_t *)data; 2291 uc->uc_mcontext.pc += 4; 2292 2293 got_sigill = 1; 2294} 2295 2296static void tcg_target_detect_isa(void) 2297{ 2298 struct sigaction sa_old, sa_new; 2299 2300 memset(&sa_new, 0, sizeof(sa_new)); 2301 sa_new.sa_flags = SA_SIGINFO; 2302 sa_new.sa_sigaction = sigill_handler; 2303 sigaction(SIGILL, &sa_new, &sa_old); 2304 2305 /* Probe for movn/movz, necessary to implement movcond. */ 2306#ifndef use_movnz_instructions 2307 got_sigill = 0; 2308 asm volatile(".set push\n" 2309 ".set mips32\n" 2310 "movn $zero, $zero, $zero\n" 2311 "movz $zero, $zero, $zero\n" 2312 ".set pop\n" 2313 : : : ); 2314 use_movnz_instructions = !got_sigill; 2315#endif 2316 2317 /* Probe for MIPS32 instructions. As no subsetting is allowed 2318 by the specification, it is only necessary to probe for one 2319 of the instructions. */ 2320#ifndef use_mips32_instructions 2321 got_sigill = 0; 2322 asm volatile(".set push\n" 2323 ".set mips32\n" 2324 "mul $zero, $zero\n" 2325 ".set pop\n" 2326 : : : ); 2327 use_mips32_instructions = !got_sigill; 2328#endif 2329 2330 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2331 available. As no subsetting is allowed by the specification, 2332 it is only necessary to probe for one of the instructions. */ 2333#ifndef use_mips32r2_instructions 2334 if (use_mips32_instructions) { 2335 got_sigill = 0; 2336 asm volatile(".set push\n" 2337 ".set mips32r2\n" 2338 "seb $zero, $zero\n" 2339 ".set pop\n" 2340 : : : ); 2341 use_mips32r2_instructions = !got_sigill; 2342 } 2343#endif 2344 2345 sigaction(SIGILL, &sa_old, NULL); 2346} 2347 2348static tcg_insn_unit *align_code_ptr(TCGContext *s) 2349{ 2350 uintptr_t p = (uintptr_t)s->code_ptr; 2351 if (p & 15) { 2352 p = (p + 15) & -16; 2353 s->code_ptr = (void *)p; 2354 } 2355 return s->code_ptr; 2356} 2357 2358/* Stack frame parameters. */ 2359#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2360#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2361#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2362 2363#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2364 + TCG_TARGET_STACK_ALIGN - 1) \ 2365 & -TCG_TARGET_STACK_ALIGN) 2366#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2367 2368/* We're expecting to be able to use an immediate for frame allocation. */ 2369QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2370 2371/* Generate global QEMU prologue and epilogue code */ 2372static void tcg_target_qemu_prologue(TCGContext *s) 2373{ 2374 int i; 2375 2376 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2377 2378 /* TB prologue */ 2379 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2380 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2381 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2382 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2383 } 2384 2385#ifndef CONFIG_SOFTMMU 2386 if (guest_base) { 2387 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2388 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2389 } 2390#endif 2391 2392 /* Call generated code */ 2393 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2394 /* delay slot */ 2395 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2396 2397 /* 2398 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2399 * and fall through to the rest of the epilogue. 2400 */ 2401 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2402 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2403 2404 /* TB epilogue */ 2405 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2406 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2407 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2408 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2409 } 2410 2411 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2412 /* delay slot */ 2413 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2414 2415 if (use_mips32r2_instructions) { 2416 return; 2417 } 2418 2419 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2420 clobbers TCG_TMP1, TCG_TMP2. */ 2421 2422 /* 2423 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2424 */ 2425 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2426 /* t3 = (ssss)d000 */ 2427 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2428 /* t1 = 000a */ 2429 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2430 /* t2 = 00c0 */ 2431 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2432 /* t3 = d00a */ 2433 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2434 /* t1 = 0abc */ 2435 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2436 /* t2 = 0c00 */ 2437 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2438 /* t1 = 00b0 */ 2439 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2440 /* t3 = dc0a */ 2441 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2442 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2443 /* t3 = dcba -- delay slot */ 2444 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2445 2446 if (TCG_TARGET_REG_BITS == 32) { 2447 return; 2448 } 2449 2450 /* 2451 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2452 */ 2453 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2454 /* t1 = (0000)000d */ 2455 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2456 /* t3 = 000a */ 2457 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2458 /* t1 = (0000)d000 */ 2459 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2460 /* t2 = 00c0 */ 2461 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2462 /* t3 = d00a */ 2463 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2464 /* t1 = 0abc */ 2465 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2466 /* t2 = 0c00 */ 2467 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2468 /* t1 = 00b0 */ 2469 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2470 /* t3 = dc0a */ 2471 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2472 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2473 /* t3 = dcba -- delay slot */ 2474 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2475 2476 /* 2477 * bswap64 -- 64-bit swap. a0 = abcdefgh 2478 */ 2479 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2480 /* t3 = h0000000 */ 2481 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2482 /* t1 = 0000000a */ 2483 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2484 2485 /* t2 = 000000g0 */ 2486 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2487 /* t3 = h000000a */ 2488 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2489 /* t1 = 00000abc */ 2490 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2491 /* t2 = 0g000000 */ 2492 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2493 /* t1 = 000000b0 */ 2494 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2495 2496 /* t3 = hg00000a */ 2497 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2498 /* t2 = 0000abcd */ 2499 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2500 /* t3 = hg0000ba */ 2501 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2502 2503 /* t1 = 000000c0 */ 2504 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2505 /* t2 = 0000000d */ 2506 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2507 /* t1 = 00000c00 */ 2508 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2509 /* t2 = 0000d000 */ 2510 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2511 2512 /* t3 = hg000cba */ 2513 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2514 /* t1 = 00abcdef */ 2515 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2516 /* t3 = hg00dcba */ 2517 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2518 2519 /* t2 = 0000000f */ 2520 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2521 /* t1 = 000000e0 */ 2522 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2523 /* t2 = 00f00000 */ 2524 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2525 /* t1 = 000e0000 */ 2526 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2527 2528 /* t3 = hgf0dcba */ 2529 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2530 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2531 /* t3 = hgfedcba -- delay slot */ 2532 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2533} 2534 2535static void tcg_target_init(TCGContext *s) 2536{ 2537 tcg_target_detect_isa(); 2538 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2539 if (TCG_TARGET_REG_BITS == 64) { 2540 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2541 } 2542 2543 tcg_target_call_clobber_regs = 0; 2544 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2545 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2546 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2547 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2548 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2549 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2550 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2551 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2552 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2553 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2554 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2555 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2556 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2557 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2558 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2559 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2560 2561 s->reserved_regs = 0; 2562 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2563 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2564 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2565 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2566 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2567 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2568 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2569 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2570 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2571 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2572} 2573 2574void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, 2575 uintptr_t jmp_rw, uintptr_t addr) 2576{ 2577 qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); 2578 flush_idcache_range(jmp_rx, jmp_rw, 4); 2579} 2580 2581typedef struct { 2582 DebugFrameHeader h; 2583 uint8_t fde_def_cfa[4]; 2584 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2585} DebugFrame; 2586 2587#define ELF_HOST_MACHINE EM_MIPS 2588/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2589 which is good because they're really quite complicated for MIPS. */ 2590 2591static const DebugFrame debug_frame = { 2592 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2593 .h.cie.id = -1, 2594 .h.cie.version = 1, 2595 .h.cie.code_align = 1, 2596 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2597 .h.cie.return_column = TCG_REG_RA, 2598 2599 /* Total FDE size does not include the "len" member. */ 2600 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2601 2602 .fde_def_cfa = { 2603 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2604 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2605 (FRAME_SIZE >> 7) 2606 }, 2607 .fde_reg_ofs = { 2608 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2609 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2610 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2611 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2612 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2613 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2614 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2615 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2616 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2617 } 2618}; 2619 2620void tcg_register_jit(const void *buf, size_t buf_size) 2621{ 2622 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2623} 2624