1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28 29#if HOST_BIG_ENDIAN 30# define MIPS_BE 1 31#else 32# define MIPS_BE 0 33#endif 34 35#if TCG_TARGET_REG_BITS == 32 36# define LO_OFF (MIPS_BE * 4) 37# define HI_OFF (4 - LO_OFF) 38#else 39/* To assert at compile-time that these values are never used 40 for TCG_TARGET_REG_BITS == 64. */ 41int link_error(void); 42# define LO_OFF link_error() 43# define HI_OFF link_error() 44#endif 45 46#ifdef CONFIG_DEBUG_TCG 47static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 48 "zero", 49 "at", 50 "v0", 51 "v1", 52 "a0", 53 "a1", 54 "a2", 55 "a3", 56 "t0", 57 "t1", 58 "t2", 59 "t3", 60 "t4", 61 "t5", 62 "t6", 63 "t7", 64 "s0", 65 "s1", 66 "s2", 67 "s3", 68 "s4", 69 "s5", 70 "s6", 71 "s7", 72 "t8", 73 "t9", 74 "k0", 75 "k1", 76 "gp", 77 "sp", 78 "s8", 79 "ra", 80}; 81#endif 82 83#define TCG_TMP0 TCG_REG_AT 84#define TCG_TMP1 TCG_REG_T9 85#define TCG_TMP2 TCG_REG_T8 86#define TCG_TMP3 TCG_REG_T7 87 88#ifndef CONFIG_SOFTMMU 89#define TCG_GUEST_BASE_REG TCG_REG_S1 90#endif 91 92/* check if we really need so many registers :P */ 93static const int tcg_target_reg_alloc_order[] = { 94 /* Call saved registers. */ 95 TCG_REG_S0, 96 TCG_REG_S1, 97 TCG_REG_S2, 98 TCG_REG_S3, 99 TCG_REG_S4, 100 TCG_REG_S5, 101 TCG_REG_S6, 102 TCG_REG_S7, 103 TCG_REG_S8, 104 105 /* Call clobbered registers. */ 106 TCG_REG_T4, 107 TCG_REG_T5, 108 TCG_REG_T6, 109 TCG_REG_T7, 110 TCG_REG_T8, 111 TCG_REG_T9, 112 TCG_REG_V1, 113 TCG_REG_V0, 114 115 /* Argument registers, opposite order of allocation. */ 116 TCG_REG_T3, 117 TCG_REG_T2, 118 TCG_REG_T1, 119 TCG_REG_T0, 120 TCG_REG_A3, 121 TCG_REG_A2, 122 TCG_REG_A1, 123 TCG_REG_A0, 124}; 125 126static const TCGReg tcg_target_call_iarg_regs[] = { 127 TCG_REG_A0, 128 TCG_REG_A1, 129 TCG_REG_A2, 130 TCG_REG_A3, 131#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 132 TCG_REG_T0, 133 TCG_REG_T1, 134 TCG_REG_T2, 135 TCG_REG_T3, 136#endif 137}; 138 139static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 140{ 141 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 142 tcg_debug_assert(slot >= 0 && slot <= 1); 143 return TCG_REG_V0 + slot; 144} 145 146static const tcg_insn_unit *tb_ret_addr; 147static const tcg_insn_unit *bswap32_addr; 148static const tcg_insn_unit *bswap32u_addr; 149static const tcg_insn_unit *bswap64_addr; 150 151static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 152{ 153 /* Let the compiler perform the right-shift as part of the arithmetic. */ 154 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 155 ptrdiff_t disp = target - (src_rx + 1); 156 if (disp == (int16_t)disp) { 157 *src_rw = deposit32(*src_rw, 0, 16, disp); 158 return true; 159 } 160 return false; 161} 162 163static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 164 intptr_t value, intptr_t addend) 165{ 166 tcg_debug_assert(type == R_MIPS_PC16); 167 tcg_debug_assert(addend == 0); 168 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 169} 170 171#define TCG_CT_CONST_ZERO 0x100 172#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 173#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 174#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 175#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 176#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 177 178#define ALL_GENERAL_REGS 0xffffffffu 179#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) 180 181#ifdef CONFIG_SOFTMMU 182#define ALL_QLOAD_REGS \ 183 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) 184#define ALL_QSTORE_REGS \ 185 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ 186 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ 187 : (1 << TCG_REG_A1))) 188#else 189#define ALL_QLOAD_REGS NOA0_REGS 190#define ALL_QSTORE_REGS NOA0_REGS 191#endif 192 193 194static bool is_p2m1(tcg_target_long val) 195{ 196 return val && ((val + 1) & val) == 0; 197} 198 199/* test if a constant matches the constraint */ 200static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 201{ 202 if (ct & TCG_CT_CONST) { 203 return 1; 204 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_P2M1) 213 && use_mips32r2_instructions && is_p2m1(val)) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_WSZ) 216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 217 return 1; 218 } 219 return 0; 220} 221 222/* instruction opcodes */ 223typedef enum { 224 OPC_J = 002 << 26, 225 OPC_JAL = 003 << 26, 226 OPC_BEQ = 004 << 26, 227 OPC_BNE = 005 << 26, 228 OPC_BLEZ = 006 << 26, 229 OPC_BGTZ = 007 << 26, 230 OPC_ADDIU = 011 << 26, 231 OPC_SLTI = 012 << 26, 232 OPC_SLTIU = 013 << 26, 233 OPC_ANDI = 014 << 26, 234 OPC_ORI = 015 << 26, 235 OPC_XORI = 016 << 26, 236 OPC_LUI = 017 << 26, 237 OPC_BNEL = 025 << 26, 238 OPC_BNEZALC_R6 = 030 << 26, 239 OPC_DADDIU = 031 << 26, 240 OPC_LDL = 032 << 26, 241 OPC_LDR = 033 << 26, 242 OPC_LB = 040 << 26, 243 OPC_LH = 041 << 26, 244 OPC_LWL = 042 << 26, 245 OPC_LW = 043 << 26, 246 OPC_LBU = 044 << 26, 247 OPC_LHU = 045 << 26, 248 OPC_LWR = 046 << 26, 249 OPC_LWU = 047 << 26, 250 OPC_SB = 050 << 26, 251 OPC_SH = 051 << 26, 252 OPC_SWL = 052 << 26, 253 OPC_SW = 053 << 26, 254 OPC_SDL = 054 << 26, 255 OPC_SDR = 055 << 26, 256 OPC_SWR = 056 << 26, 257 OPC_LD = 067 << 26, 258 OPC_SD = 077 << 26, 259 260 OPC_SPECIAL = 000 << 26, 261 OPC_SLL = OPC_SPECIAL | 000, 262 OPC_SRL = OPC_SPECIAL | 002, 263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 264 OPC_SRA = OPC_SPECIAL | 003, 265 OPC_SLLV = OPC_SPECIAL | 004, 266 OPC_SRLV = OPC_SPECIAL | 006, 267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 268 OPC_SRAV = OPC_SPECIAL | 007, 269 OPC_JR_R5 = OPC_SPECIAL | 010, 270 OPC_JALR = OPC_SPECIAL | 011, 271 OPC_MOVZ = OPC_SPECIAL | 012, 272 OPC_MOVN = OPC_SPECIAL | 013, 273 OPC_SYNC = OPC_SPECIAL | 017, 274 OPC_MFHI = OPC_SPECIAL | 020, 275 OPC_MFLO = OPC_SPECIAL | 022, 276 OPC_DSLLV = OPC_SPECIAL | 024, 277 OPC_DSRLV = OPC_SPECIAL | 026, 278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 279 OPC_DSRAV = OPC_SPECIAL | 027, 280 OPC_MULT = OPC_SPECIAL | 030, 281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 282 OPC_MUH = OPC_SPECIAL | 030 | 0300, 283 OPC_MULTU = OPC_SPECIAL | 031, 284 OPC_MULU = OPC_SPECIAL | 031 | 0200, 285 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 286 OPC_DIV = OPC_SPECIAL | 032, 287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 288 OPC_MOD = OPC_SPECIAL | 032 | 0300, 289 OPC_DIVU = OPC_SPECIAL | 033, 290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 291 OPC_MODU = OPC_SPECIAL | 033 | 0300, 292 OPC_DMULT = OPC_SPECIAL | 034, 293 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 294 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 295 OPC_DMULTU = OPC_SPECIAL | 035, 296 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 298 OPC_DDIV = OPC_SPECIAL | 036, 299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 300 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 301 OPC_DDIVU = OPC_SPECIAL | 037, 302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 303 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 304 OPC_ADDU = OPC_SPECIAL | 041, 305 OPC_SUBU = OPC_SPECIAL | 043, 306 OPC_AND = OPC_SPECIAL | 044, 307 OPC_OR = OPC_SPECIAL | 045, 308 OPC_XOR = OPC_SPECIAL | 046, 309 OPC_NOR = OPC_SPECIAL | 047, 310 OPC_SLT = OPC_SPECIAL | 052, 311 OPC_SLTU = OPC_SPECIAL | 053, 312 OPC_DADDU = OPC_SPECIAL | 055, 313 OPC_DSUBU = OPC_SPECIAL | 057, 314 OPC_SELEQZ = OPC_SPECIAL | 065, 315 OPC_SELNEZ = OPC_SPECIAL | 067, 316 OPC_DSLL = OPC_SPECIAL | 070, 317 OPC_DSRL = OPC_SPECIAL | 072, 318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 319 OPC_DSRA = OPC_SPECIAL | 073, 320 OPC_DSLL32 = OPC_SPECIAL | 074, 321 OPC_DSRL32 = OPC_SPECIAL | 076, 322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 323 OPC_DSRA32 = OPC_SPECIAL | 077, 324 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 326 327 OPC_REGIMM = 001 << 26, 328 OPC_BLTZ = OPC_REGIMM | (000 << 16), 329 OPC_BGEZ = OPC_REGIMM | (001 << 16), 330 331 OPC_SPECIAL2 = 034 << 26, 332 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 333 OPC_CLZ = OPC_SPECIAL2 | 040, 334 OPC_DCLZ = OPC_SPECIAL2 | 044, 335 336 OPC_SPECIAL3 = 037 << 26, 337 OPC_EXT = OPC_SPECIAL3 | 000, 338 OPC_DEXTM = OPC_SPECIAL3 | 001, 339 OPC_DEXTU = OPC_SPECIAL3 | 002, 340 OPC_DEXT = OPC_SPECIAL3 | 003, 341 OPC_INS = OPC_SPECIAL3 | 004, 342 OPC_DINSM = OPC_SPECIAL3 | 005, 343 OPC_DINSU = OPC_SPECIAL3 | 006, 344 OPC_DINS = OPC_SPECIAL3 | 007, 345 OPC_WSBH = OPC_SPECIAL3 | 00240, 346 OPC_DSBH = OPC_SPECIAL3 | 00244, 347 OPC_DSHD = OPC_SPECIAL3 | 00544, 348 OPC_SEB = OPC_SPECIAL3 | 02040, 349 OPC_SEH = OPC_SPECIAL3 | 03040, 350 351 /* MIPS r6 doesn't have JR, JALR should be used instead */ 352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 353 354 /* 355 * MIPS r6 replaces MUL with an alternative encoding which is 356 * backwards-compatible at the assembly level. 357 */ 358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 359 360 /* MIPS r6 introduced names for weaker variants of SYNC. These are 361 backward compatible to previous architecture revisions. */ 362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 367 368 /* Aliases for convenience. */ 369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 371 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 372 ? OPC_SRL : OPC_DSRL, 373} MIPSInsn; 374 375/* 376 * Type reg 377 */ 378static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 379 TCGReg rd, TCGReg rs, TCGReg rt) 380{ 381 int32_t inst; 382 383 inst = opc; 384 inst |= (rs & 0x1F) << 21; 385 inst |= (rt & 0x1F) << 16; 386 inst |= (rd & 0x1F) << 11; 387 tcg_out32(s, inst); 388} 389 390/* 391 * Type immediate 392 */ 393static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 394 TCGReg rt, TCGReg rs, TCGArg imm) 395{ 396 int32_t inst; 397 398 inst = opc; 399 inst |= (rs & 0x1F) << 21; 400 inst |= (rt & 0x1F) << 16; 401 inst |= (imm & 0xffff); 402 tcg_out32(s, inst); 403} 404 405/* 406 * Type bitfield 407 */ 408static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 409 TCGReg rs, int msb, int lsb) 410{ 411 int32_t inst; 412 413 inst = opc; 414 inst |= (rs & 0x1F) << 21; 415 inst |= (rt & 0x1F) << 16; 416 inst |= (msb & 0x1F) << 11; 417 inst |= (lsb & 0x1F) << 6; 418 tcg_out32(s, inst); 419} 420 421static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 422 MIPSInsn oph, TCGReg rt, TCGReg rs, 423 int msb, int lsb) 424{ 425 if (lsb >= 32) { 426 opc = oph; 427 msb -= 32; 428 lsb -= 32; 429 } else if (msb >= 32) { 430 opc = opm; 431 msb -= 32; 432 } 433 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 434} 435 436/* 437 * Type branch 438 */ 439static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 440{ 441 tcg_out_opc_imm(s, opc, rt, rs, 0); 442} 443 444/* 445 * Type sa 446 */ 447static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 448 TCGReg rd, TCGReg rt, TCGArg sa) 449{ 450 int32_t inst; 451 452 inst = opc; 453 inst |= (rt & 0x1F) << 16; 454 inst |= (rd & 0x1F) << 11; 455 inst |= (sa & 0x1F) << 6; 456 tcg_out32(s, inst); 457 458} 459 460static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 461 TCGReg rd, TCGReg rt, TCGArg sa) 462{ 463 int32_t inst; 464 465 inst = (sa & 32 ? opc2 : opc1); 466 inst |= (rt & 0x1F) << 16; 467 inst |= (rd & 0x1F) << 11; 468 inst |= (sa & 0x1F) << 6; 469 tcg_out32(s, inst); 470} 471 472/* 473 * Type jump. 474 * Returns true if the branch was in range and the insn was emitted. 475 */ 476static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 477{ 478 uintptr_t dest = (uintptr_t)target; 479 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 480 int32_t inst; 481 482 /* The pc-region branch happens within the 256MB region of 483 the delay slot (thus the +4). */ 484 if ((from ^ dest) & -(1 << 28)) { 485 return false; 486 } 487 tcg_debug_assert((dest & 3) == 0); 488 489 inst = opc; 490 inst |= (dest >> 2) & 0x3ffffff; 491 tcg_out32(s, inst); 492 return true; 493} 494 495static void tcg_out_nop(TCGContext *s) 496{ 497 tcg_out32(s, 0); 498} 499 500static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 501{ 502 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 503} 504 505static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 506{ 507 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 508} 509 510static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 511{ 512 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 513} 514 515static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 516{ 517 /* Simple reg-reg move, optimising out the 'do nothing' case */ 518 if (ret != arg) { 519 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 520 } 521 return true; 522} 523 524static void tcg_out_movi(TCGContext *s, TCGType type, 525 TCGReg ret, tcg_target_long arg) 526{ 527 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 528 arg = (int32_t)arg; 529 } 530 if (arg == (int16_t)arg) { 531 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 532 return; 533 } 534 if (arg == (uint16_t)arg) { 535 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 536 return; 537 } 538 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 539 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 540 } else { 541 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 542 if (arg & 0xffff0000ull) { 543 tcg_out_dsll(s, ret, ret, 16); 544 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 545 tcg_out_dsll(s, ret, ret, 16); 546 } else { 547 tcg_out_dsll(s, ret, ret, 32); 548 } 549 } 550 if (arg & 0xffff) { 551 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 552 } 553} 554 555static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 556{ 557 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); 558 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 559} 560 561static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 562{ 563 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 564} 565 566static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 567{ 568 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); 569 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 570} 571 572static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 573{ 574 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 575} 576 577static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 578{ 579 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 580 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 581} 582 583static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 584{ 585 if (rd != rs) { 586 tcg_out_ext32s(s, rd, rs); 587 } 588} 589 590static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 591{ 592 tcg_out_ext32u(s, rd, rs); 593} 594 595static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 596{ 597 tcg_out_ext32s(s, rd, rs); 598} 599 600static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 601{ 602 return false; 603} 604 605static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 606 tcg_target_long imm) 607{ 608 /* This function is only used for passing structs by reference. */ 609 g_assert_not_reached(); 610} 611 612static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 613{ 614 /* ret and arg can't be register tmp0 */ 615 tcg_debug_assert(ret != TCG_TMP0); 616 tcg_debug_assert(arg != TCG_TMP0); 617 618 /* With arg = abcd: */ 619 if (use_mips32r2_instructions) { 620 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 621 if (flags & TCG_BSWAP_OS) { 622 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 623 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 624 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 625 } 626 return; 627 } 628 629 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 630 if (!(flags & TCG_BSWAP_IZ)) { 631 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 632 } 633 if (flags & TCG_BSWAP_OS) { 634 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 635 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 636 } else { 637 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 638 if (flags & TCG_BSWAP_OZ) { 639 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 640 } 641 } 642 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 643} 644 645static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 646{ 647 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 648 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 649 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 650 } 651} 652 653static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 654{ 655 if (use_mips32r2_instructions) { 656 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 657 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 658 if (flags & TCG_BSWAP_OZ) { 659 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 660 } 661 } else { 662 if (flags & TCG_BSWAP_OZ) { 663 tcg_out_bswap_subr(s, bswap32u_addr); 664 } else { 665 tcg_out_bswap_subr(s, bswap32_addr); 666 } 667 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 668 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 669 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 670 } 671} 672 673static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 674{ 675 if (use_mips32r2_instructions) { 676 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 677 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 678 } else { 679 tcg_out_bswap_subr(s, bswap64_addr); 680 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 681 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 682 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 683 } 684} 685 686static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 687{ 688 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 689 if (use_mips32r2_instructions) { 690 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 691 } else { 692 tcg_out_dsll(s, ret, arg, 32); 693 tcg_out_dsrl(s, ret, ret, 32); 694 } 695} 696 697static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 698 TCGReg addr, intptr_t ofs) 699{ 700 int16_t lo = ofs; 701 if (ofs != lo) { 702 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 703 if (addr != TCG_REG_ZERO) { 704 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 705 } 706 addr = TCG_TMP0; 707 } 708 tcg_out_opc_imm(s, opc, data, addr, lo); 709} 710 711static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 712 TCGReg arg1, intptr_t arg2) 713{ 714 MIPSInsn opc = OPC_LD; 715 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 716 opc = OPC_LW; 717 } 718 tcg_out_ldst(s, opc, arg, arg1, arg2); 719} 720 721static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 722 TCGReg arg1, intptr_t arg2) 723{ 724 MIPSInsn opc = OPC_SD; 725 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 726 opc = OPC_SW; 727 } 728 tcg_out_ldst(s, opc, arg, arg1, arg2); 729} 730 731static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 732 TCGReg base, intptr_t ofs) 733{ 734 if (val == 0) { 735 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 736 return true; 737 } 738 return false; 739} 740 741static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 742 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 743 bool cbh, bool is_sub) 744{ 745 TCGReg th = TCG_TMP1; 746 747 /* If we have a negative constant such that negating it would 748 make the high part zero, we can (usually) eliminate one insn. */ 749 if (cbl && cbh && bh == -1 && bl != 0) { 750 bl = -bl; 751 bh = 0; 752 is_sub = !is_sub; 753 } 754 755 /* By operating on the high part first, we get to use the final 756 carry operation to move back from the temporary. */ 757 if (!cbh) { 758 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 759 } else if (bh != 0 || ah == rl) { 760 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 761 } else { 762 th = ah; 763 } 764 765 /* Note that tcg optimization should eliminate the bl == 0 case. */ 766 if (is_sub) { 767 if (cbl) { 768 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 769 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 770 } else { 771 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 772 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 773 } 774 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 775 } else { 776 if (cbl) { 777 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 778 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 779 } else if (rl == al && rl == bl) { 780 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 781 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 782 } else { 783 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 784 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 785 } 786 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 787 } 788} 789 790/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 791#define MIPS_CMP_INV 1 792#define MIPS_CMP_SWAP 2 793 794static const uint8_t mips_cmp_map[16] = { 795 [TCG_COND_LT] = 0, 796 [TCG_COND_LTU] = 0, 797 [TCG_COND_GE] = MIPS_CMP_INV, 798 [TCG_COND_GEU] = MIPS_CMP_INV, 799 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 800 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 801 [TCG_COND_GT] = MIPS_CMP_SWAP, 802 [TCG_COND_GTU] = MIPS_CMP_SWAP, 803}; 804 805static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 806 TCGReg arg1, TCGReg arg2) 807{ 808 MIPSInsn s_opc = OPC_SLTU; 809 int cmp_map; 810 811 switch (cond) { 812 case TCG_COND_EQ: 813 if (arg2 != 0) { 814 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 815 arg1 = ret; 816 } 817 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 818 break; 819 820 case TCG_COND_NE: 821 if (arg2 != 0) { 822 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 823 arg1 = ret; 824 } 825 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 826 break; 827 828 case TCG_COND_LT: 829 case TCG_COND_GE: 830 case TCG_COND_LE: 831 case TCG_COND_GT: 832 s_opc = OPC_SLT; 833 /* FALLTHRU */ 834 835 case TCG_COND_LTU: 836 case TCG_COND_GEU: 837 case TCG_COND_LEU: 838 case TCG_COND_GTU: 839 cmp_map = mips_cmp_map[cond]; 840 if (cmp_map & MIPS_CMP_SWAP) { 841 TCGReg t = arg1; 842 arg1 = arg2; 843 arg2 = t; 844 } 845 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 846 if (cmp_map & MIPS_CMP_INV) { 847 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 848 } 849 break; 850 851 default: 852 g_assert_not_reached(); 853 break; 854 } 855} 856 857static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 858 TCGReg arg2, TCGLabel *l) 859{ 860 static const MIPSInsn b_zero[16] = { 861 [TCG_COND_LT] = OPC_BLTZ, 862 [TCG_COND_GT] = OPC_BGTZ, 863 [TCG_COND_LE] = OPC_BLEZ, 864 [TCG_COND_GE] = OPC_BGEZ, 865 }; 866 867 MIPSInsn s_opc = OPC_SLTU; 868 MIPSInsn b_opc; 869 int cmp_map; 870 871 switch (cond) { 872 case TCG_COND_EQ: 873 b_opc = OPC_BEQ; 874 break; 875 case TCG_COND_NE: 876 b_opc = OPC_BNE; 877 break; 878 879 case TCG_COND_LT: 880 case TCG_COND_GT: 881 case TCG_COND_LE: 882 case TCG_COND_GE: 883 if (arg2 == 0) { 884 b_opc = b_zero[cond]; 885 arg2 = arg1; 886 arg1 = 0; 887 break; 888 } 889 s_opc = OPC_SLT; 890 /* FALLTHRU */ 891 892 case TCG_COND_LTU: 893 case TCG_COND_GTU: 894 case TCG_COND_LEU: 895 case TCG_COND_GEU: 896 cmp_map = mips_cmp_map[cond]; 897 if (cmp_map & MIPS_CMP_SWAP) { 898 TCGReg t = arg1; 899 arg1 = arg2; 900 arg2 = t; 901 } 902 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 903 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 904 arg1 = TCG_TMP0; 905 arg2 = TCG_REG_ZERO; 906 break; 907 908 default: 909 g_assert_not_reached(); 910 break; 911 } 912 913 tcg_out_opc_br(s, b_opc, arg1, arg2); 914 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 915 tcg_out_nop(s); 916} 917 918static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 919 TCGReg al, TCGReg ah, 920 TCGReg bl, TCGReg bh) 921{ 922 /* Merge highpart comparison into AH. */ 923 if (bh != 0) { 924 if (ah != 0) { 925 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 926 ah = tmp0; 927 } else { 928 ah = bh; 929 } 930 } 931 /* Merge lowpart comparison into AL. */ 932 if (bl != 0) { 933 if (al != 0) { 934 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 935 al = tmp1; 936 } else { 937 al = bl; 938 } 939 } 940 /* Merge high and low part comparisons into AL. */ 941 if (ah != 0) { 942 if (al != 0) { 943 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 944 al = tmp0; 945 } else { 946 al = ah; 947 } 948 } 949 return al; 950} 951 952static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 953 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 954{ 955 TCGReg tmp0 = TCG_TMP0; 956 TCGReg tmp1 = ret; 957 958 tcg_debug_assert(ret != TCG_TMP0); 959 if (ret == ah || ret == bh) { 960 tcg_debug_assert(ret != TCG_TMP1); 961 tmp1 = TCG_TMP1; 962 } 963 964 switch (cond) { 965 case TCG_COND_EQ: 966 case TCG_COND_NE: 967 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 968 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 969 break; 970 971 default: 972 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 973 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 974 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 975 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 976 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 977 break; 978 } 979} 980 981static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 982 TCGReg bl, TCGReg bh, TCGLabel *l) 983{ 984 TCGCond b_cond = TCG_COND_NE; 985 TCGReg tmp = TCG_TMP1; 986 987 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 988 With setcond, we emit between 3 and 10 insns and only 1 branch, 989 which ought to get better branch prediction. */ 990 switch (cond) { 991 case TCG_COND_EQ: 992 case TCG_COND_NE: 993 b_cond = cond; 994 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 995 break; 996 997 default: 998 /* Minimize code size by preferring a compare not requiring INV. */ 999 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1000 cond = tcg_invert_cond(cond); 1001 b_cond = TCG_COND_EQ; 1002 } 1003 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 1004 break; 1005 } 1006 1007 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 1008} 1009 1010static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1011 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1012{ 1013 bool eqz = false; 1014 1015 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1016 if (use_mips32r6_instructions && v1 == 0) { 1017 v1 = v2; 1018 v2 = 0; 1019 cond = tcg_invert_cond(cond); 1020 } 1021 1022 switch (cond) { 1023 case TCG_COND_EQ: 1024 eqz = true; 1025 /* FALLTHRU */ 1026 case TCG_COND_NE: 1027 if (c2 != 0) { 1028 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 1029 c1 = TCG_TMP0; 1030 } 1031 break; 1032 1033 default: 1034 /* Minimize code size by preferring a compare not requiring INV. */ 1035 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1036 cond = tcg_invert_cond(cond); 1037 eqz = true; 1038 } 1039 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 1040 c1 = TCG_TMP0; 1041 break; 1042 } 1043 1044 if (use_mips32r6_instructions) { 1045 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1046 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1047 1048 if (v2 != 0) { 1049 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1050 } 1051 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1052 if (v2 != 0) { 1053 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1054 } 1055 } else { 1056 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1057 1058 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1059 1060 /* This should be guaranteed via constraints */ 1061 tcg_debug_assert(v2 == ret); 1062 } 1063} 1064 1065static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1066{ 1067 /* Note that the ABI requires the called function's address to be 1068 loaded into T9, even if a direct branch is in range. */ 1069 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1070 1071 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1072 if (tail) { 1073 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1074 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1075 } 1076 } else { 1077 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1078 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1079 } 1080 } 1081} 1082 1083static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1084 const TCGHelperInfo *info) 1085{ 1086 tcg_out_call_int(s, arg, false); 1087 tcg_out_nop(s); 1088} 1089 1090#if defined(CONFIG_SOFTMMU) 1091static void * const qemu_ld_helpers[(MO_SSIZE | MO_BSWAP) + 1] = { 1092 [MO_UB] = helper_ret_ldub_mmu, 1093 [MO_SB] = helper_ret_ldsb_mmu, 1094 [MO_LEUW] = helper_le_lduw_mmu, 1095 [MO_LESW] = helper_le_ldsw_mmu, 1096 [MO_LEUL] = helper_le_ldul_mmu, 1097 [MO_LEUQ] = helper_le_ldq_mmu, 1098 [MO_BEUW] = helper_be_lduw_mmu, 1099 [MO_BESW] = helper_be_ldsw_mmu, 1100 [MO_BEUL] = helper_be_ldul_mmu, 1101 [MO_BEUQ] = helper_be_ldq_mmu, 1102#if TCG_TARGET_REG_BITS == 64 1103 [MO_LESL] = helper_le_ldsl_mmu, 1104 [MO_BESL] = helper_be_ldsl_mmu, 1105#endif 1106}; 1107 1108static void * const qemu_st_helpers[(MO_SIZE | MO_BSWAP) + 1] = { 1109 [MO_UB] = helper_ret_stb_mmu, 1110 [MO_LEUW] = helper_le_stw_mmu, 1111 [MO_LEUL] = helper_le_stl_mmu, 1112 [MO_LEUQ] = helper_le_stq_mmu, 1113 [MO_BEUW] = helper_be_stw_mmu, 1114 [MO_BEUL] = helper_be_stl_mmu, 1115 [MO_BEUQ] = helper_be_stq_mmu, 1116}; 1117 1118/* Helper routines for marshalling helper function arguments into 1119 * the correct registers and stack. 1120 * I is where we want to put this argument, and is updated and returned 1121 * for the next call. ARG is the argument itself. 1122 * 1123 * We provide routines for arguments which are: immediate, 32 bit 1124 * value in register, 16 and 8 bit values in register (which must be zero 1125 * extended before use) and 64 bit value in a lo:hi register pair. 1126 */ 1127 1128static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) 1129{ 1130 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1131 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); 1132 } else { 1133 /* For N32 and N64, the initial offset is different. But there 1134 we also have 8 argument register so we don't run out here. */ 1135 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1136 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); 1137 } 1138 return i + 1; 1139} 1140 1141static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) 1142{ 1143 TCGReg tmp = TCG_TMP0; 1144 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1145 tmp = tcg_target_call_iarg_regs[i]; 1146 } 1147 tcg_out_ext8u(s, tmp, arg); 1148 return tcg_out_call_iarg_reg(s, i, tmp); 1149} 1150 1151static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) 1152{ 1153 TCGReg tmp = TCG_TMP0; 1154 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1155 tmp = tcg_target_call_iarg_regs[i]; 1156 } 1157 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); 1158 return tcg_out_call_iarg_reg(s, i, tmp); 1159} 1160 1161static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) 1162{ 1163 TCGReg tmp = TCG_TMP0; 1164 if (arg == 0) { 1165 tmp = TCG_REG_ZERO; 1166 } else { 1167 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1168 tmp = tcg_target_call_iarg_regs[i]; 1169 } 1170 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); 1171 } 1172 return tcg_out_call_iarg_reg(s, i, tmp); 1173} 1174 1175static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) 1176{ 1177 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1178 i = (i + 1) & ~1; 1179 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); 1180 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); 1181 return i; 1182} 1183 1184/* We expect to use a 16-bit negative offset from ENV. */ 1185QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1186QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1187 1188/* 1189 * Perform the tlb comparison operation. 1190 * The complete host address is placed in BASE. 1191 * Clobbers TMP0, TMP1, TMP2, TMP3. 1192 */ 1193static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, 1194 TCGReg addrh, MemOpIdx oi, 1195 tcg_insn_unit *label_ptr[2], bool is_load) 1196{ 1197 MemOp opc = get_memop(oi); 1198 unsigned a_bits = get_alignment_bits(opc); 1199 unsigned s_bits = opc & MO_SIZE; 1200 unsigned a_mask = (1 << a_bits) - 1; 1201 unsigned s_mask = (1 << s_bits) - 1; 1202 int mem_index = get_mmuidx(oi); 1203 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1204 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1205 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1206 int add_off = offsetof(CPUTLBEntry, addend); 1207 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) 1208 : offsetof(CPUTLBEntry, addr_write)); 1209 target_ulong tlb_mask; 1210 1211 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1212 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1213 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1214 1215 /* Extract the TLB index from the address into TMP3. */ 1216 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, 1217 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1218 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1219 1220 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1221 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1222 1223 /* Load the (low-half) tlb comparator. */ 1224 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1225 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1226 } else { 1227 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD 1228 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), 1229 TCG_TMP0, TCG_TMP3, cmp_off); 1230 } 1231 1232 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1233 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1234 tcg_out_ext32u(s, base, addrl); 1235 addrl = base; 1236 } 1237 1238 /* 1239 * Mask the page bits, keeping the alignment bits to compare against. 1240 * For unaligned accesses, compare against the end of the access to 1241 * verify that it does not cross a page boundary. 1242 */ 1243 tlb_mask = (target_ulong)TARGET_PAGE_MASK | a_mask; 1244 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, tlb_mask); 1245 if (a_mask >= s_mask) { 1246 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); 1247 } else { 1248 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_TMP2, addrl, s_mask - a_mask); 1249 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1250 } 1251 1252 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 1253 /* Load the tlb addend for the fast path. */ 1254 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1255 } 1256 1257 label_ptr[0] = s->code_ptr; 1258 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1259 1260 /* Load and test the high half tlb comparator. */ 1261 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1262 /* delay slot */ 1263 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1264 1265 /* Load the tlb addend for the fast path. */ 1266 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1267 1268 label_ptr[1] = s->code_ptr; 1269 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); 1270 } 1271 1272 /* delay slot */ 1273 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); 1274} 1275 1276static void add_qemu_ldst_label(TCGContext *s, int is_ld, MemOpIdx oi, 1277 TCGType ext, 1278 TCGReg datalo, TCGReg datahi, 1279 TCGReg addrlo, TCGReg addrhi, 1280 void *raddr, tcg_insn_unit *label_ptr[2]) 1281{ 1282 TCGLabelQemuLdst *label = new_ldst_label(s); 1283 1284 label->is_ld = is_ld; 1285 label->oi = oi; 1286 label->type = ext; 1287 label->datalo_reg = datalo; 1288 label->datahi_reg = datahi; 1289 label->addrlo_reg = addrlo; 1290 label->addrhi_reg = addrhi; 1291 label->raddr = tcg_splitwx_to_rx(raddr); 1292 label->label_ptr[0] = label_ptr[0]; 1293 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1294 label->label_ptr[1] = label_ptr[1]; 1295 } 1296} 1297 1298static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1299{ 1300 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1301 MemOpIdx oi = l->oi; 1302 MemOp opc = get_memop(oi); 1303 TCGReg v0; 1304 int i; 1305 1306 /* resolve label address */ 1307 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1308 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1309 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1310 return false; 1311 } 1312 1313 i = 1; 1314 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1315 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1316 } else { 1317 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1318 } 1319 i = tcg_out_call_iarg_imm(s, i, oi); 1320 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); 1321 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); 1322 /* delay slot */ 1323 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1324 1325 v0 = l->datalo_reg; 1326 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 1327 /* We eliminated V0 from the possible output registers, so it 1328 cannot be clobbered here. So we must move V1 first. */ 1329 if (MIPS_BE) { 1330 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); 1331 v0 = l->datahi_reg; 1332 } else { 1333 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); 1334 } 1335 } 1336 1337 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1338 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1339 return false; 1340 } 1341 1342 /* delay slot */ 1343 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { 1344 /* we always sign-extend 32-bit loads */ 1345 tcg_out_ext32s(s, v0, TCG_REG_V0); 1346 } else { 1347 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); 1348 } 1349 return true; 1350} 1351 1352static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1353{ 1354 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1355 MemOpIdx oi = l->oi; 1356 MemOp opc = get_memop(oi); 1357 MemOp s_bits = opc & MO_SIZE; 1358 int i; 1359 1360 /* resolve label address */ 1361 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1362 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1363 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1364 return false; 1365 } 1366 1367 i = 1; 1368 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1369 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1370 } else { 1371 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1372 } 1373 switch (s_bits) { 1374 case MO_8: 1375 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); 1376 break; 1377 case MO_16: 1378 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); 1379 break; 1380 case MO_32: 1381 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1382 break; 1383 case MO_64: 1384 if (TCG_TARGET_REG_BITS == 32) { 1385 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); 1386 } else { 1387 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1388 } 1389 break; 1390 default: 1391 g_assert_not_reached(); 1392 } 1393 i = tcg_out_call_iarg_imm(s, i, oi); 1394 1395 /* Tail call to the store helper. Thus force the return address 1396 computation to take place in the return address register. */ 1397 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); 1398 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); 1399 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); 1400 /* delay slot */ 1401 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1402 return true; 1403} 1404 1405#else 1406 1407static void tcg_out_test_alignment(TCGContext *s, bool is_ld, TCGReg addrlo, 1408 TCGReg addrhi, unsigned a_bits) 1409{ 1410 unsigned a_mask = (1 << a_bits) - 1; 1411 TCGLabelQemuLdst *l = new_ldst_label(s); 1412 1413 l->is_ld = is_ld; 1414 l->addrlo_reg = addrlo; 1415 l->addrhi_reg = addrhi; 1416 1417 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1418 tcg_debug_assert(a_bits < 16); 1419 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); 1420 1421 l->label_ptr[0] = s->code_ptr; 1422 if (use_mips32r6_instructions) { 1423 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1424 } else { 1425 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1426 tcg_out_nop(s); 1427 } 1428 1429 l->raddr = tcg_splitwx_to_rx(s->code_ptr); 1430} 1431 1432static bool tcg_out_fail_alignment(TCGContext *s, TCGLabelQemuLdst *l) 1433{ 1434 void *target; 1435 1436 if (!reloc_pc16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1437 return false; 1438 } 1439 1440 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1441 /* A0 is env, A1 is skipped, A2:A3 is the uint64_t address. */ 1442 TCGReg a2 = MIPS_BE ? l->addrhi_reg : l->addrlo_reg; 1443 TCGReg a3 = MIPS_BE ? l->addrlo_reg : l->addrhi_reg; 1444 1445 if (a3 != TCG_REG_A2) { 1446 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); 1447 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); 1448 } else if (a2 != TCG_REG_A3) { 1449 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, a3); 1450 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, a2); 1451 } else { 1452 tcg_out_mov(s, TCG_TYPE_I32, TCG_TMP0, TCG_REG_A2); 1453 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A2, TCG_REG_A3); 1454 tcg_out_mov(s, TCG_TYPE_I32, TCG_REG_A3, TCG_TMP0); 1455 } 1456 } else { 1457 tcg_out_mov(s, TCG_TYPE_TL, TCG_REG_A1, l->addrlo_reg); 1458 } 1459 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_A0, TCG_AREG0); 1460 1461 /* 1462 * Tail call to the helper, with the return address back inline. 1463 * We have arrived here via BNEL, so $31 is already set. 1464 */ 1465 target = (l->is_ld ? helper_unaligned_ld : helper_unaligned_st); 1466 tcg_out_call_int(s, target, true); 1467 return true; 1468} 1469 1470static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1471{ 1472 return tcg_out_fail_alignment(s, l); 1473} 1474 1475static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1476{ 1477 return tcg_out_fail_alignment(s, l); 1478} 1479#endif /* SOFTMMU */ 1480 1481static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1482 TCGReg base, MemOp opc, bool is_64) 1483{ 1484 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1485 case MO_UB: 1486 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1487 break; 1488 case MO_SB: 1489 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1490 break; 1491 case MO_UW | MO_BSWAP: 1492 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1493 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ); 1494 break; 1495 case MO_UW: 1496 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1497 break; 1498 case MO_SW | MO_BSWAP: 1499 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1500 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS); 1501 break; 1502 case MO_SW: 1503 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1504 break; 1505 case MO_UL | MO_BSWAP: 1506 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1507 if (use_mips32r2_instructions) { 1508 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1509 tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); 1510 } else { 1511 tcg_out_bswap_subr(s, bswap32u_addr); 1512 /* delay slot */ 1513 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); 1514 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1515 } 1516 break; 1517 } 1518 /* FALLTHRU */ 1519 case MO_SL | MO_BSWAP: 1520 if (use_mips32r2_instructions) { 1521 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1522 tcg_out_bswap32(s, lo, lo, 0); 1523 } else { 1524 tcg_out_bswap_subr(s, bswap32_addr); 1525 /* delay slot */ 1526 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1527 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); 1528 } 1529 break; 1530 case MO_UL: 1531 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1532 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1533 break; 1534 } 1535 /* FALLTHRU */ 1536 case MO_SL: 1537 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1538 break; 1539 case MO_UQ | MO_BSWAP: 1540 if (TCG_TARGET_REG_BITS == 64) { 1541 if (use_mips32r2_instructions) { 1542 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1543 tcg_out_bswap64(s, lo, lo); 1544 } else { 1545 tcg_out_bswap_subr(s, bswap64_addr); 1546 /* delay slot */ 1547 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); 1548 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1549 } 1550 } else if (use_mips32r2_instructions) { 1551 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1552 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); 1553 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1554 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1555 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1556 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1557 } else { 1558 tcg_out_bswap_subr(s, bswap32_addr); 1559 /* delay slot */ 1560 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1561 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); 1562 tcg_out_bswap_subr(s, bswap32_addr); 1563 /* delay slot */ 1564 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1565 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1566 } 1567 break; 1568 case MO_UQ: 1569 /* Prefer to load from offset 0 first, but allow for overlap. */ 1570 if (TCG_TARGET_REG_BITS == 64) { 1571 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1572 } else if (MIPS_BE ? hi != base : lo == base) { 1573 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1574 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1575 } else { 1576 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1577 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1578 } 1579 break; 1580 default: 1581 g_assert_not_reached(); 1582 } 1583} 1584 1585static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1586 TCGReg base, MemOp opc, bool is_64) 1587{ 1588 const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR; 1589 const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL; 1590 const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR; 1591 const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL; 1592 1593 bool sgn = (opc & MO_SIGN); 1594 1595 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1596 case MO_SW | MO_BE: 1597 case MO_UW | MO_BE: 1598 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1599 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1600 if (use_mips32r2_instructions) { 1601 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1602 } else { 1603 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1604 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1605 } 1606 break; 1607 1608 case MO_SW | MO_LE: 1609 case MO_UW | MO_LE: 1610 if (use_mips32r2_instructions && lo != base) { 1611 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1612 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1613 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1614 } else { 1615 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1616 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1617 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1618 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1619 } 1620 break; 1621 1622 case MO_SL: 1623 case MO_UL: 1624 tcg_out_opc_imm(s, lw1, lo, base, 0); 1625 tcg_out_opc_imm(s, lw2, lo, base, 3); 1626 if (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn) { 1627 tcg_out_ext32u(s, lo, lo); 1628 } 1629 break; 1630 1631 case MO_UL | MO_BSWAP: 1632 case MO_SL | MO_BSWAP: 1633 if (use_mips32r2_instructions) { 1634 tcg_out_opc_imm(s, lw1, lo, base, 0); 1635 tcg_out_opc_imm(s, lw2, lo, base, 3); 1636 tcg_out_bswap32(s, lo, lo, 1637 TCG_TARGET_REG_BITS == 64 && is_64 1638 ? (sgn ? TCG_BSWAP_OS : TCG_BSWAP_OZ) : 0); 1639 } else { 1640 const tcg_insn_unit *subr = 1641 (TCG_TARGET_REG_BITS == 64 && is_64 && !sgn 1642 ? bswap32u_addr : bswap32_addr); 1643 1644 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0); 1645 tcg_out_bswap_subr(s, subr); 1646 /* delay slot */ 1647 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 3); 1648 tcg_out_mov(s, is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32, lo, TCG_TMP3); 1649 } 1650 break; 1651 1652 case MO_UQ: 1653 if (TCG_TARGET_REG_BITS == 64) { 1654 tcg_out_opc_imm(s, ld1, lo, base, 0); 1655 tcg_out_opc_imm(s, ld2, lo, base, 7); 1656 } else { 1657 tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0); 1658 tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3); 1659 tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0); 1660 tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3); 1661 } 1662 break; 1663 1664 case MO_UQ | MO_BSWAP: 1665 if (TCG_TARGET_REG_BITS == 64) { 1666 if (use_mips32r2_instructions) { 1667 tcg_out_opc_imm(s, ld1, lo, base, 0); 1668 tcg_out_opc_imm(s, ld2, lo, base, 7); 1669 tcg_out_bswap64(s, lo, lo); 1670 } else { 1671 tcg_out_opc_imm(s, ld1, TCG_TMP0, base, 0); 1672 tcg_out_bswap_subr(s, bswap64_addr); 1673 /* delay slot */ 1674 tcg_out_opc_imm(s, ld2, TCG_TMP0, base, 7); 1675 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1676 } 1677 } else if (use_mips32r2_instructions) { 1678 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); 1679 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); 1680 tcg_out_opc_imm(s, lw1, TCG_TMP1, base, 4 + 0); 1681 tcg_out_opc_imm(s, lw2, TCG_TMP1, base, 4 + 3); 1682 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1683 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1684 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1685 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1686 } else { 1687 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 0 + 0); 1688 tcg_out_bswap_subr(s, bswap32_addr); 1689 /* delay slot */ 1690 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 0 + 3); 1691 tcg_out_opc_imm(s, lw1, TCG_TMP0, base, 4 + 0); 1692 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1693 tcg_out_bswap_subr(s, bswap32_addr); 1694 /* delay slot */ 1695 tcg_out_opc_imm(s, lw2, TCG_TMP0, base, 4 + 3); 1696 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1697 } 1698 break; 1699 1700 default: 1701 g_assert_not_reached(); 1702 } 1703} 1704 1705static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1706{ 1707 TCGReg addr_regl, addr_regh __attribute__((unused)); 1708 TCGReg data_regl, data_regh; 1709 MemOpIdx oi; 1710 MemOp opc; 1711#if defined(CONFIG_SOFTMMU) 1712 tcg_insn_unit *label_ptr[2]; 1713#else 1714#endif 1715 unsigned a_bits, s_bits; 1716 TCGReg base = TCG_REG_A0; 1717 1718 data_regl = *args++; 1719 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1720 addr_regl = *args++; 1721 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1722 oi = *args++; 1723 opc = get_memop(oi); 1724 a_bits = get_alignment_bits(opc); 1725 s_bits = opc & MO_SIZE; 1726 1727 /* 1728 * R6 removes the left/right instructions but requires the 1729 * system to support misaligned memory accesses. 1730 */ 1731#if defined(CONFIG_SOFTMMU) 1732 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); 1733 if (use_mips32r6_instructions || a_bits >= s_bits) { 1734 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1735 } else { 1736 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); 1737 } 1738 add_qemu_ldst_label(s, 1, oi, 1739 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1740 data_regl, data_regh, addr_regl, addr_regh, 1741 s->code_ptr, label_ptr); 1742#else 1743 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1744 tcg_out_ext32u(s, base, addr_regl); 1745 addr_regl = base; 1746 } 1747 if (guest_base == 0 && data_regl != addr_regl) { 1748 base = addr_regl; 1749 } else if (guest_base == (int16_t)guest_base) { 1750 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1751 } else { 1752 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1753 } 1754 if (use_mips32r6_instructions) { 1755 if (a_bits) { 1756 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); 1757 } 1758 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1759 } else { 1760 if (a_bits && a_bits != s_bits) { 1761 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); 1762 } 1763 if (a_bits >= s_bits) { 1764 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1765 } else { 1766 tcg_out_qemu_ld_unalign(s, data_regl, data_regh, base, opc, is_64); 1767 } 1768 } 1769#endif 1770} 1771 1772static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1773 TCGReg base, MemOp opc) 1774{ 1775 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1776 if ((lo | hi) == 0) { 1777 opc &= ~MO_BSWAP; 1778 } 1779 1780 switch (opc & (MO_SIZE | MO_BSWAP)) { 1781 case MO_8: 1782 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1783 break; 1784 1785 case MO_16 | MO_BSWAP: 1786 tcg_out_bswap16(s, TCG_TMP1, lo, 0); 1787 lo = TCG_TMP1; 1788 /* FALLTHRU */ 1789 case MO_16: 1790 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1791 break; 1792 1793 case MO_32 | MO_BSWAP: 1794 tcg_out_bswap32(s, TCG_TMP3, lo, 0); 1795 lo = TCG_TMP3; 1796 /* FALLTHRU */ 1797 case MO_32: 1798 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1799 break; 1800 1801 case MO_64 | MO_BSWAP: 1802 if (TCG_TARGET_REG_BITS == 64) { 1803 tcg_out_bswap64(s, TCG_TMP3, lo); 1804 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); 1805 } else if (use_mips32r2_instructions) { 1806 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); 1807 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); 1808 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1809 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1810 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); 1811 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); 1812 } else { 1813 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); 1814 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); 1815 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); 1816 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); 1817 } 1818 break; 1819 case MO_64: 1820 if (TCG_TARGET_REG_BITS == 64) { 1821 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1822 } else { 1823 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1824 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1825 } 1826 break; 1827 1828 default: 1829 g_assert_not_reached(); 1830 } 1831} 1832 1833static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1834 TCGReg base, MemOp opc) 1835{ 1836 const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR; 1837 const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL; 1838 const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR; 1839 const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL; 1840 1841 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1842 if ((lo | hi) == 0) { 1843 opc &= ~MO_BSWAP; 1844 } 1845 1846 switch (opc & (MO_SIZE | MO_BSWAP)) { 1847 case MO_16 | MO_BE: 1848 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1849 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 0); 1850 tcg_out_opc_imm(s, OPC_SB, lo, base, 1); 1851 break; 1852 1853 case MO_16 | MO_LE: 1854 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1855 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1856 tcg_out_opc_imm(s, OPC_SB, TCG_TMP0, base, 1); 1857 break; 1858 1859 case MO_32 | MO_BSWAP: 1860 tcg_out_bswap32(s, TCG_TMP3, lo, 0); 1861 lo = TCG_TMP3; 1862 /* fall through */ 1863 case MO_32: 1864 tcg_out_opc_imm(s, sw1, lo, base, 0); 1865 tcg_out_opc_imm(s, sw2, lo, base, 3); 1866 break; 1867 1868 case MO_64 | MO_BSWAP: 1869 if (TCG_TARGET_REG_BITS == 64) { 1870 tcg_out_bswap64(s, TCG_TMP3, lo); 1871 lo = TCG_TMP3; 1872 } else if (use_mips32r2_instructions) { 1873 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? hi : lo); 1874 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? lo : hi); 1875 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1876 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1877 hi = MIPS_BE ? TCG_TMP0 : TCG_TMP1; 1878 lo = MIPS_BE ? TCG_TMP1 : TCG_TMP0; 1879 } else { 1880 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); 1881 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 0 + 0); 1882 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 0 + 3); 1883 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); 1884 tcg_out_opc_imm(s, sw1, TCG_TMP3, base, 4 + 0); 1885 tcg_out_opc_imm(s, sw2, TCG_TMP3, base, 4 + 3); 1886 break; 1887 } 1888 /* fall through */ 1889 case MO_64: 1890 if (TCG_TARGET_REG_BITS == 64) { 1891 tcg_out_opc_imm(s, sd1, lo, base, 0); 1892 tcg_out_opc_imm(s, sd2, lo, base, 7); 1893 } else { 1894 tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0); 1895 tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3); 1896 tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0); 1897 tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3); 1898 } 1899 break; 1900 1901 default: 1902 g_assert_not_reached(); 1903 } 1904} 1905static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1906{ 1907 TCGReg addr_regl, addr_regh __attribute__((unused)); 1908 TCGReg data_regl, data_regh; 1909 MemOpIdx oi; 1910 MemOp opc; 1911#if defined(CONFIG_SOFTMMU) 1912 tcg_insn_unit *label_ptr[2]; 1913#endif 1914 unsigned a_bits, s_bits; 1915 TCGReg base = TCG_REG_A0; 1916 1917 data_regl = *args++; 1918 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1919 addr_regl = *args++; 1920 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1921 oi = *args++; 1922 opc = get_memop(oi); 1923 a_bits = get_alignment_bits(opc); 1924 s_bits = opc & MO_SIZE; 1925 1926 /* 1927 * R6 removes the left/right instructions but requires the 1928 * system to support misaligned memory accesses. 1929 */ 1930#if defined(CONFIG_SOFTMMU) 1931 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); 1932 if (use_mips32r6_instructions || a_bits >= s_bits) { 1933 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1934 } else { 1935 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); 1936 } 1937 add_qemu_ldst_label(s, 0, oi, 1938 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1939 data_regl, data_regh, addr_regl, addr_regh, 1940 s->code_ptr, label_ptr); 1941#else 1942 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1943 tcg_out_ext32u(s, base, addr_regl); 1944 addr_regl = base; 1945 } 1946 if (guest_base == 0) { 1947 base = addr_regl; 1948 } else if (guest_base == (int16_t)guest_base) { 1949 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1950 } else { 1951 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1952 } 1953 if (use_mips32r6_instructions) { 1954 if (a_bits) { 1955 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); 1956 } 1957 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1958 } else { 1959 if (a_bits && a_bits != s_bits) { 1960 tcg_out_test_alignment(s, true, addr_regl, addr_regh, a_bits); 1961 } 1962 if (a_bits >= s_bits) { 1963 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1964 } else { 1965 tcg_out_qemu_st_unalign(s, data_regl, data_regh, base, opc); 1966 } 1967 } 1968#endif 1969} 1970 1971static void tcg_out_mb(TCGContext *s, TCGArg a0) 1972{ 1973 static const MIPSInsn sync[] = { 1974 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1975 as the former is an ordering barrier and the latter 1976 is a completion barrier. */ 1977 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1978 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1979 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1980 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1981 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1982 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1983 }; 1984 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1985} 1986 1987static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1988 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1989{ 1990 if (use_mips32r6_instructions) { 1991 if (a2 == width) { 1992 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1993 } else { 1994 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1995 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1996 } 1997 } else { 1998 if (a2 == width) { 1999 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 2000 } else if (a0 == a2) { 2001 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 2002 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 2003 } else if (a0 != a1) { 2004 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 2005 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 2006 } else { 2007 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 2008 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 2009 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 2010 } 2011 } 2012} 2013 2014static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 2015{ 2016 TCGReg b0 = TCG_REG_ZERO; 2017 2018 if (a0 & ~0xffff) { 2019 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 2020 b0 = TCG_REG_V0; 2021 } 2022 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 2023 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 2024 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 2025 } 2026 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 2027} 2028 2029static void tcg_out_goto_tb(TCGContext *s, int which) 2030{ 2031 /* indirect jump method */ 2032 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 2033 get_jmp_target_addr(s, which)); 2034 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 2035 tcg_out_nop(s); 2036 set_jmp_reset_offset(s, which); 2037} 2038 2039void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 2040 uintptr_t jmp_rx, uintptr_t jmp_rw) 2041{ 2042 /* Always indirect, nothing to do */ 2043} 2044 2045static void tcg_out_op(TCGContext *s, TCGOpcode opc, 2046 const TCGArg args[TCG_MAX_OP_ARGS], 2047 const int const_args[TCG_MAX_OP_ARGS]) 2048{ 2049 MIPSInsn i1, i2; 2050 TCGArg a0, a1, a2; 2051 int c2; 2052 2053 /* 2054 * Note that many operands use the constraint set "rZ". 2055 * We make use of the fact that 0 is the ZERO register, 2056 * and hence such cases need not check for const_args. 2057 */ 2058 a0 = args[0]; 2059 a1 = args[1]; 2060 a2 = args[2]; 2061 c2 = const_args[2]; 2062 2063 switch (opc) { 2064 case INDEX_op_goto_ptr: 2065 /* jmp to the given host address (could be epilogue) */ 2066 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2067 tcg_out_nop(s); 2068 break; 2069 case INDEX_op_br: 2070 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 2071 arg_label(a0)); 2072 break; 2073 2074 case INDEX_op_ld8u_i32: 2075 case INDEX_op_ld8u_i64: 2076 i1 = OPC_LBU; 2077 goto do_ldst; 2078 case INDEX_op_ld8s_i32: 2079 case INDEX_op_ld8s_i64: 2080 i1 = OPC_LB; 2081 goto do_ldst; 2082 case INDEX_op_ld16u_i32: 2083 case INDEX_op_ld16u_i64: 2084 i1 = OPC_LHU; 2085 goto do_ldst; 2086 case INDEX_op_ld16s_i32: 2087 case INDEX_op_ld16s_i64: 2088 i1 = OPC_LH; 2089 goto do_ldst; 2090 case INDEX_op_ld_i32: 2091 case INDEX_op_ld32s_i64: 2092 i1 = OPC_LW; 2093 goto do_ldst; 2094 case INDEX_op_ld32u_i64: 2095 i1 = OPC_LWU; 2096 goto do_ldst; 2097 case INDEX_op_ld_i64: 2098 i1 = OPC_LD; 2099 goto do_ldst; 2100 case INDEX_op_st8_i32: 2101 case INDEX_op_st8_i64: 2102 i1 = OPC_SB; 2103 goto do_ldst; 2104 case INDEX_op_st16_i32: 2105 case INDEX_op_st16_i64: 2106 i1 = OPC_SH; 2107 goto do_ldst; 2108 case INDEX_op_st_i32: 2109 case INDEX_op_st32_i64: 2110 i1 = OPC_SW; 2111 goto do_ldst; 2112 case INDEX_op_st_i64: 2113 i1 = OPC_SD; 2114 do_ldst: 2115 tcg_out_ldst(s, i1, a0, a1, a2); 2116 break; 2117 2118 case INDEX_op_add_i32: 2119 i1 = OPC_ADDU, i2 = OPC_ADDIU; 2120 goto do_binary; 2121 case INDEX_op_add_i64: 2122 i1 = OPC_DADDU, i2 = OPC_DADDIU; 2123 goto do_binary; 2124 case INDEX_op_or_i32: 2125 case INDEX_op_or_i64: 2126 i1 = OPC_OR, i2 = OPC_ORI; 2127 goto do_binary; 2128 case INDEX_op_xor_i32: 2129 case INDEX_op_xor_i64: 2130 i1 = OPC_XOR, i2 = OPC_XORI; 2131 do_binary: 2132 if (c2) { 2133 tcg_out_opc_imm(s, i2, a0, a1, a2); 2134 break; 2135 } 2136 do_binaryv: 2137 tcg_out_opc_reg(s, i1, a0, a1, a2); 2138 break; 2139 2140 case INDEX_op_sub_i32: 2141 i1 = OPC_SUBU, i2 = OPC_ADDIU; 2142 goto do_subtract; 2143 case INDEX_op_sub_i64: 2144 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 2145 do_subtract: 2146 if (c2) { 2147 tcg_out_opc_imm(s, i2, a0, a1, -a2); 2148 break; 2149 } 2150 goto do_binaryv; 2151 case INDEX_op_and_i32: 2152 if (c2 && a2 != (uint16_t)a2) { 2153 int msb = ctz32(~a2) - 1; 2154 tcg_debug_assert(use_mips32r2_instructions); 2155 tcg_debug_assert(is_p2m1(a2)); 2156 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 2157 break; 2158 } 2159 i1 = OPC_AND, i2 = OPC_ANDI; 2160 goto do_binary; 2161 case INDEX_op_and_i64: 2162 if (c2 && a2 != (uint16_t)a2) { 2163 int msb = ctz64(~a2) - 1; 2164 tcg_debug_assert(use_mips32r2_instructions); 2165 tcg_debug_assert(is_p2m1(a2)); 2166 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 2167 break; 2168 } 2169 i1 = OPC_AND, i2 = OPC_ANDI; 2170 goto do_binary; 2171 case INDEX_op_nor_i32: 2172 case INDEX_op_nor_i64: 2173 i1 = OPC_NOR; 2174 goto do_binaryv; 2175 2176 case INDEX_op_mul_i32: 2177 if (use_mips32_instructions) { 2178 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 2179 break; 2180 } 2181 i1 = OPC_MULT, i2 = OPC_MFLO; 2182 goto do_hilo1; 2183 case INDEX_op_mulsh_i32: 2184 if (use_mips32r6_instructions) { 2185 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 2186 break; 2187 } 2188 i1 = OPC_MULT, i2 = OPC_MFHI; 2189 goto do_hilo1; 2190 case INDEX_op_muluh_i32: 2191 if (use_mips32r6_instructions) { 2192 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 2193 break; 2194 } 2195 i1 = OPC_MULTU, i2 = OPC_MFHI; 2196 goto do_hilo1; 2197 case INDEX_op_div_i32: 2198 if (use_mips32r6_instructions) { 2199 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 2200 break; 2201 } 2202 i1 = OPC_DIV, i2 = OPC_MFLO; 2203 goto do_hilo1; 2204 case INDEX_op_divu_i32: 2205 if (use_mips32r6_instructions) { 2206 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 2207 break; 2208 } 2209 i1 = OPC_DIVU, i2 = OPC_MFLO; 2210 goto do_hilo1; 2211 case INDEX_op_rem_i32: 2212 if (use_mips32r6_instructions) { 2213 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 2214 break; 2215 } 2216 i1 = OPC_DIV, i2 = OPC_MFHI; 2217 goto do_hilo1; 2218 case INDEX_op_remu_i32: 2219 if (use_mips32r6_instructions) { 2220 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 2221 break; 2222 } 2223 i1 = OPC_DIVU, i2 = OPC_MFHI; 2224 goto do_hilo1; 2225 case INDEX_op_mul_i64: 2226 if (use_mips32r6_instructions) { 2227 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 2228 break; 2229 } 2230 i1 = OPC_DMULT, i2 = OPC_MFLO; 2231 goto do_hilo1; 2232 case INDEX_op_mulsh_i64: 2233 if (use_mips32r6_instructions) { 2234 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 2235 break; 2236 } 2237 i1 = OPC_DMULT, i2 = OPC_MFHI; 2238 goto do_hilo1; 2239 case INDEX_op_muluh_i64: 2240 if (use_mips32r6_instructions) { 2241 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 2242 break; 2243 } 2244 i1 = OPC_DMULTU, i2 = OPC_MFHI; 2245 goto do_hilo1; 2246 case INDEX_op_div_i64: 2247 if (use_mips32r6_instructions) { 2248 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 2249 break; 2250 } 2251 i1 = OPC_DDIV, i2 = OPC_MFLO; 2252 goto do_hilo1; 2253 case INDEX_op_divu_i64: 2254 if (use_mips32r6_instructions) { 2255 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 2256 break; 2257 } 2258 i1 = OPC_DDIVU, i2 = OPC_MFLO; 2259 goto do_hilo1; 2260 case INDEX_op_rem_i64: 2261 if (use_mips32r6_instructions) { 2262 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 2263 break; 2264 } 2265 i1 = OPC_DDIV, i2 = OPC_MFHI; 2266 goto do_hilo1; 2267 case INDEX_op_remu_i64: 2268 if (use_mips32r6_instructions) { 2269 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 2270 break; 2271 } 2272 i1 = OPC_DDIVU, i2 = OPC_MFHI; 2273 do_hilo1: 2274 tcg_out_opc_reg(s, i1, 0, a1, a2); 2275 tcg_out_opc_reg(s, i2, a0, 0, 0); 2276 break; 2277 2278 case INDEX_op_muls2_i32: 2279 i1 = OPC_MULT; 2280 goto do_hilo2; 2281 case INDEX_op_mulu2_i32: 2282 i1 = OPC_MULTU; 2283 goto do_hilo2; 2284 case INDEX_op_muls2_i64: 2285 i1 = OPC_DMULT; 2286 goto do_hilo2; 2287 case INDEX_op_mulu2_i64: 2288 i1 = OPC_DMULTU; 2289 do_hilo2: 2290 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 2291 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 2292 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 2293 break; 2294 2295 case INDEX_op_not_i32: 2296 case INDEX_op_not_i64: 2297 i1 = OPC_NOR; 2298 goto do_unary; 2299 do_unary: 2300 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 2301 break; 2302 2303 case INDEX_op_bswap16_i32: 2304 case INDEX_op_bswap16_i64: 2305 tcg_out_bswap16(s, a0, a1, a2); 2306 break; 2307 case INDEX_op_bswap32_i32: 2308 tcg_out_bswap32(s, a0, a1, 0); 2309 break; 2310 case INDEX_op_bswap32_i64: 2311 tcg_out_bswap32(s, a0, a1, a2); 2312 break; 2313 case INDEX_op_bswap64_i64: 2314 tcg_out_bswap64(s, a0, a1); 2315 break; 2316 case INDEX_op_extrh_i64_i32: 2317 tcg_out_dsra(s, a0, a1, 32); 2318 break; 2319 2320 case INDEX_op_sar_i32: 2321 i1 = OPC_SRAV, i2 = OPC_SRA; 2322 goto do_shift; 2323 case INDEX_op_shl_i32: 2324 i1 = OPC_SLLV, i2 = OPC_SLL; 2325 goto do_shift; 2326 case INDEX_op_shr_i32: 2327 i1 = OPC_SRLV, i2 = OPC_SRL; 2328 goto do_shift; 2329 case INDEX_op_rotr_i32: 2330 i1 = OPC_ROTRV, i2 = OPC_ROTR; 2331 do_shift: 2332 if (c2) { 2333 tcg_out_opc_sa(s, i2, a0, a1, a2); 2334 break; 2335 } 2336 do_shiftv: 2337 tcg_out_opc_reg(s, i1, a0, a2, a1); 2338 break; 2339 case INDEX_op_rotl_i32: 2340 if (c2) { 2341 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 2342 } else { 2343 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2344 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 2345 } 2346 break; 2347 case INDEX_op_sar_i64: 2348 if (c2) { 2349 tcg_out_dsra(s, a0, a1, a2); 2350 break; 2351 } 2352 i1 = OPC_DSRAV; 2353 goto do_shiftv; 2354 case INDEX_op_shl_i64: 2355 if (c2) { 2356 tcg_out_dsll(s, a0, a1, a2); 2357 break; 2358 } 2359 i1 = OPC_DSLLV; 2360 goto do_shiftv; 2361 case INDEX_op_shr_i64: 2362 if (c2) { 2363 tcg_out_dsrl(s, a0, a1, a2); 2364 break; 2365 } 2366 i1 = OPC_DSRLV; 2367 goto do_shiftv; 2368 case INDEX_op_rotr_i64: 2369 if (c2) { 2370 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2371 break; 2372 } 2373 i1 = OPC_DROTRV; 2374 goto do_shiftv; 2375 case INDEX_op_rotl_i64: 2376 if (c2) { 2377 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2378 } else { 2379 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2380 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2381 } 2382 break; 2383 2384 case INDEX_op_clz_i32: 2385 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2386 break; 2387 case INDEX_op_clz_i64: 2388 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2389 break; 2390 2391 case INDEX_op_deposit_i32: 2392 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2393 break; 2394 case INDEX_op_deposit_i64: 2395 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2396 args[3] + args[4] - 1, args[3]); 2397 break; 2398 case INDEX_op_extract_i32: 2399 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2400 break; 2401 case INDEX_op_extract_i64: 2402 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2403 args[3] - 1, a2); 2404 break; 2405 2406 case INDEX_op_brcond_i32: 2407 case INDEX_op_brcond_i64: 2408 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2409 break; 2410 case INDEX_op_brcond2_i32: 2411 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2412 break; 2413 2414 case INDEX_op_movcond_i32: 2415 case INDEX_op_movcond_i64: 2416 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2417 break; 2418 2419 case INDEX_op_setcond_i32: 2420 case INDEX_op_setcond_i64: 2421 tcg_out_setcond(s, args[3], a0, a1, a2); 2422 break; 2423 case INDEX_op_setcond2_i32: 2424 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2425 break; 2426 2427 case INDEX_op_qemu_ld_i32: 2428 tcg_out_qemu_ld(s, args, false); 2429 break; 2430 case INDEX_op_qemu_ld_i64: 2431 tcg_out_qemu_ld(s, args, true); 2432 break; 2433 case INDEX_op_qemu_st_i32: 2434 tcg_out_qemu_st(s, args, false); 2435 break; 2436 case INDEX_op_qemu_st_i64: 2437 tcg_out_qemu_st(s, args, true); 2438 break; 2439 2440 case INDEX_op_add2_i32: 2441 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2442 const_args[4], const_args[5], false); 2443 break; 2444 case INDEX_op_sub2_i32: 2445 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2446 const_args[4], const_args[5], true); 2447 break; 2448 2449 case INDEX_op_mb: 2450 tcg_out_mb(s, a0); 2451 break; 2452 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2453 case INDEX_op_mov_i64: 2454 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2455 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2456 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2457 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2458 case INDEX_op_ext8s_i64: 2459 case INDEX_op_ext8u_i32: 2460 case INDEX_op_ext8u_i64: 2461 case INDEX_op_ext16s_i32: 2462 case INDEX_op_ext16s_i64: 2463 case INDEX_op_ext32s_i64: 2464 case INDEX_op_ext32u_i64: 2465 case INDEX_op_ext_i32_i64: 2466 case INDEX_op_extu_i32_i64: 2467 case INDEX_op_extrl_i64_i32: 2468 default: 2469 g_assert_not_reached(); 2470 } 2471} 2472 2473static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2474{ 2475 switch (op) { 2476 case INDEX_op_goto_ptr: 2477 return C_O0_I1(r); 2478 2479 case INDEX_op_ld8u_i32: 2480 case INDEX_op_ld8s_i32: 2481 case INDEX_op_ld16u_i32: 2482 case INDEX_op_ld16s_i32: 2483 case INDEX_op_ld_i32: 2484 case INDEX_op_not_i32: 2485 case INDEX_op_bswap16_i32: 2486 case INDEX_op_bswap32_i32: 2487 case INDEX_op_ext8s_i32: 2488 case INDEX_op_ext16s_i32: 2489 case INDEX_op_extract_i32: 2490 case INDEX_op_ld8u_i64: 2491 case INDEX_op_ld8s_i64: 2492 case INDEX_op_ld16u_i64: 2493 case INDEX_op_ld16s_i64: 2494 case INDEX_op_ld32s_i64: 2495 case INDEX_op_ld32u_i64: 2496 case INDEX_op_ld_i64: 2497 case INDEX_op_not_i64: 2498 case INDEX_op_bswap16_i64: 2499 case INDEX_op_bswap32_i64: 2500 case INDEX_op_bswap64_i64: 2501 case INDEX_op_ext8s_i64: 2502 case INDEX_op_ext16s_i64: 2503 case INDEX_op_ext32s_i64: 2504 case INDEX_op_ext32u_i64: 2505 case INDEX_op_ext_i32_i64: 2506 case INDEX_op_extu_i32_i64: 2507 case INDEX_op_extrl_i64_i32: 2508 case INDEX_op_extrh_i64_i32: 2509 case INDEX_op_extract_i64: 2510 return C_O1_I1(r, r); 2511 2512 case INDEX_op_st8_i32: 2513 case INDEX_op_st16_i32: 2514 case INDEX_op_st_i32: 2515 case INDEX_op_st8_i64: 2516 case INDEX_op_st16_i64: 2517 case INDEX_op_st32_i64: 2518 case INDEX_op_st_i64: 2519 return C_O0_I2(rZ, r); 2520 2521 case INDEX_op_add_i32: 2522 case INDEX_op_add_i64: 2523 return C_O1_I2(r, r, rJ); 2524 case INDEX_op_sub_i32: 2525 case INDEX_op_sub_i64: 2526 return C_O1_I2(r, rZ, rN); 2527 case INDEX_op_mul_i32: 2528 case INDEX_op_mulsh_i32: 2529 case INDEX_op_muluh_i32: 2530 case INDEX_op_div_i32: 2531 case INDEX_op_divu_i32: 2532 case INDEX_op_rem_i32: 2533 case INDEX_op_remu_i32: 2534 case INDEX_op_nor_i32: 2535 case INDEX_op_setcond_i32: 2536 case INDEX_op_mul_i64: 2537 case INDEX_op_mulsh_i64: 2538 case INDEX_op_muluh_i64: 2539 case INDEX_op_div_i64: 2540 case INDEX_op_divu_i64: 2541 case INDEX_op_rem_i64: 2542 case INDEX_op_remu_i64: 2543 case INDEX_op_nor_i64: 2544 case INDEX_op_setcond_i64: 2545 return C_O1_I2(r, rZ, rZ); 2546 case INDEX_op_muls2_i32: 2547 case INDEX_op_mulu2_i32: 2548 case INDEX_op_muls2_i64: 2549 case INDEX_op_mulu2_i64: 2550 return C_O2_I2(r, r, r, r); 2551 case INDEX_op_and_i32: 2552 case INDEX_op_and_i64: 2553 return C_O1_I2(r, r, rIK); 2554 case INDEX_op_or_i32: 2555 case INDEX_op_xor_i32: 2556 case INDEX_op_or_i64: 2557 case INDEX_op_xor_i64: 2558 return C_O1_I2(r, r, rI); 2559 case INDEX_op_shl_i32: 2560 case INDEX_op_shr_i32: 2561 case INDEX_op_sar_i32: 2562 case INDEX_op_rotr_i32: 2563 case INDEX_op_rotl_i32: 2564 case INDEX_op_shl_i64: 2565 case INDEX_op_shr_i64: 2566 case INDEX_op_sar_i64: 2567 case INDEX_op_rotr_i64: 2568 case INDEX_op_rotl_i64: 2569 return C_O1_I2(r, r, ri); 2570 case INDEX_op_clz_i32: 2571 case INDEX_op_clz_i64: 2572 return C_O1_I2(r, r, rWZ); 2573 2574 case INDEX_op_deposit_i32: 2575 case INDEX_op_deposit_i64: 2576 return C_O1_I2(r, 0, rZ); 2577 case INDEX_op_brcond_i32: 2578 case INDEX_op_brcond_i64: 2579 return C_O0_I2(rZ, rZ); 2580 case INDEX_op_movcond_i32: 2581 case INDEX_op_movcond_i64: 2582 return (use_mips32r6_instructions 2583 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2584 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2585 case INDEX_op_add2_i32: 2586 case INDEX_op_sub2_i32: 2587 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2588 case INDEX_op_setcond2_i32: 2589 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2590 case INDEX_op_brcond2_i32: 2591 return C_O0_I4(rZ, rZ, rZ, rZ); 2592 2593 case INDEX_op_qemu_ld_i32: 2594 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2595 ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); 2596 case INDEX_op_qemu_st_i32: 2597 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2598 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); 2599 case INDEX_op_qemu_ld_i64: 2600 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) 2601 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) 2602 : C_O2_I2(r, r, L, L)); 2603 case INDEX_op_qemu_st_i64: 2604 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) 2605 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) 2606 : C_O0_I4(SZ, SZ, S, S)); 2607 2608 default: 2609 g_assert_not_reached(); 2610 } 2611} 2612 2613static const int tcg_target_callee_save_regs[] = { 2614 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2615 TCG_REG_S1, 2616 TCG_REG_S2, 2617 TCG_REG_S3, 2618 TCG_REG_S4, 2619 TCG_REG_S5, 2620 TCG_REG_S6, 2621 TCG_REG_S7, 2622 TCG_REG_S8, 2623 TCG_REG_RA, /* should be last for ABI compliance */ 2624}; 2625 2626/* The Linux kernel doesn't provide any information about the available 2627 instruction set. Probe it using a signal handler. */ 2628 2629 2630#ifndef use_movnz_instructions 2631bool use_movnz_instructions = false; 2632#endif 2633 2634#ifndef use_mips32_instructions 2635bool use_mips32_instructions = false; 2636#endif 2637 2638#ifndef use_mips32r2_instructions 2639bool use_mips32r2_instructions = false; 2640#endif 2641 2642static volatile sig_atomic_t got_sigill; 2643 2644static void sigill_handler(int signo, siginfo_t *si, void *data) 2645{ 2646 /* Skip the faulty instruction */ 2647 ucontext_t *uc = (ucontext_t *)data; 2648 uc->uc_mcontext.pc += 4; 2649 2650 got_sigill = 1; 2651} 2652 2653static void tcg_target_detect_isa(void) 2654{ 2655 struct sigaction sa_old, sa_new; 2656 2657 memset(&sa_new, 0, sizeof(sa_new)); 2658 sa_new.sa_flags = SA_SIGINFO; 2659 sa_new.sa_sigaction = sigill_handler; 2660 sigaction(SIGILL, &sa_new, &sa_old); 2661 2662 /* Probe for movn/movz, necessary to implement movcond. */ 2663#ifndef use_movnz_instructions 2664 got_sigill = 0; 2665 asm volatile(".set push\n" 2666 ".set mips32\n" 2667 "movn $zero, $zero, $zero\n" 2668 "movz $zero, $zero, $zero\n" 2669 ".set pop\n" 2670 : : : ); 2671 use_movnz_instructions = !got_sigill; 2672#endif 2673 2674 /* Probe for MIPS32 instructions. As no subsetting is allowed 2675 by the specification, it is only necessary to probe for one 2676 of the instructions. */ 2677#ifndef use_mips32_instructions 2678 got_sigill = 0; 2679 asm volatile(".set push\n" 2680 ".set mips32\n" 2681 "mul $zero, $zero\n" 2682 ".set pop\n" 2683 : : : ); 2684 use_mips32_instructions = !got_sigill; 2685#endif 2686 2687 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2688 available. As no subsetting is allowed by the specification, 2689 it is only necessary to probe for one of the instructions. */ 2690#ifndef use_mips32r2_instructions 2691 if (use_mips32_instructions) { 2692 got_sigill = 0; 2693 asm volatile(".set push\n" 2694 ".set mips32r2\n" 2695 "seb $zero, $zero\n" 2696 ".set pop\n" 2697 : : : ); 2698 use_mips32r2_instructions = !got_sigill; 2699 } 2700#endif 2701 2702 sigaction(SIGILL, &sa_old, NULL); 2703} 2704 2705static tcg_insn_unit *align_code_ptr(TCGContext *s) 2706{ 2707 uintptr_t p = (uintptr_t)s->code_ptr; 2708 if (p & 15) { 2709 p = (p + 15) & -16; 2710 s->code_ptr = (void *)p; 2711 } 2712 return s->code_ptr; 2713} 2714 2715/* Stack frame parameters. */ 2716#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2717#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2718#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2719 2720#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2721 + TCG_TARGET_STACK_ALIGN - 1) \ 2722 & -TCG_TARGET_STACK_ALIGN) 2723#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2724 2725/* We're expecting to be able to use an immediate for frame allocation. */ 2726QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2727 2728/* Generate global QEMU prologue and epilogue code */ 2729static void tcg_target_qemu_prologue(TCGContext *s) 2730{ 2731 int i; 2732 2733 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2734 2735 /* TB prologue */ 2736 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2737 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2738 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2739 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2740 } 2741 2742#ifndef CONFIG_SOFTMMU 2743 if (guest_base) { 2744 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2745 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2746 } 2747#endif 2748 2749 /* Call generated code */ 2750 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2751 /* delay slot */ 2752 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2753 2754 /* 2755 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2756 * and fall through to the rest of the epilogue. 2757 */ 2758 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2759 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2760 2761 /* TB epilogue */ 2762 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2763 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2764 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2765 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2766 } 2767 2768 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2769 /* delay slot */ 2770 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2771 2772 if (use_mips32r2_instructions) { 2773 return; 2774 } 2775 2776 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2777 clobbers TCG_TMP1, TCG_TMP2. */ 2778 2779 /* 2780 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2781 */ 2782 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2783 /* t3 = (ssss)d000 */ 2784 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2785 /* t1 = 000a */ 2786 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2787 /* t2 = 00c0 */ 2788 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2789 /* t3 = d00a */ 2790 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2791 /* t1 = 0abc */ 2792 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2793 /* t2 = 0c00 */ 2794 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2795 /* t1 = 00b0 */ 2796 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2797 /* t3 = dc0a */ 2798 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2799 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2800 /* t3 = dcba -- delay slot */ 2801 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2802 2803 if (TCG_TARGET_REG_BITS == 32) { 2804 return; 2805 } 2806 2807 /* 2808 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2809 */ 2810 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2811 /* t1 = (0000)000d */ 2812 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2813 /* t3 = 000a */ 2814 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2815 /* t1 = (0000)d000 */ 2816 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2817 /* t2 = 00c0 */ 2818 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2819 /* t3 = d00a */ 2820 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2821 /* t1 = 0abc */ 2822 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2823 /* t2 = 0c00 */ 2824 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2825 /* t1 = 00b0 */ 2826 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2827 /* t3 = dc0a */ 2828 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2829 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2830 /* t3 = dcba -- delay slot */ 2831 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2832 2833 /* 2834 * bswap64 -- 64-bit swap. a0 = abcdefgh 2835 */ 2836 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2837 /* t3 = h0000000 */ 2838 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2839 /* t1 = 0000000a */ 2840 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2841 2842 /* t2 = 000000g0 */ 2843 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2844 /* t3 = h000000a */ 2845 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2846 /* t1 = 00000abc */ 2847 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2848 /* t2 = 0g000000 */ 2849 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2850 /* t1 = 000000b0 */ 2851 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2852 2853 /* t3 = hg00000a */ 2854 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2855 /* t2 = 0000abcd */ 2856 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2857 /* t3 = hg0000ba */ 2858 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2859 2860 /* t1 = 000000c0 */ 2861 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2862 /* t2 = 0000000d */ 2863 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2864 /* t1 = 00000c00 */ 2865 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2866 /* t2 = 0000d000 */ 2867 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2868 2869 /* t3 = hg000cba */ 2870 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2871 /* t1 = 00abcdef */ 2872 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2873 /* t3 = hg00dcba */ 2874 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2875 2876 /* t2 = 0000000f */ 2877 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2878 /* t1 = 000000e0 */ 2879 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2880 /* t2 = 00f00000 */ 2881 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2882 /* t1 = 000e0000 */ 2883 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2884 2885 /* t3 = hgf0dcba */ 2886 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2887 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2888 /* t3 = hgfedcba -- delay slot */ 2889 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2890} 2891 2892static void tcg_target_init(TCGContext *s) 2893{ 2894 tcg_target_detect_isa(); 2895 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2896 if (TCG_TARGET_REG_BITS == 64) { 2897 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2898 } 2899 2900 tcg_target_call_clobber_regs = 0; 2901 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2902 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2903 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2904 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2905 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2906 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2907 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2908 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2909 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2910 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2911 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2912 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2913 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2914 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2915 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2916 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2917 2918 s->reserved_regs = 0; 2919 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2920 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2921 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2922 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2923 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2924 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2925 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2926 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2927 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2928 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2929} 2930 2931typedef struct { 2932 DebugFrameHeader h; 2933 uint8_t fde_def_cfa[4]; 2934 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2935} DebugFrame; 2936 2937#define ELF_HOST_MACHINE EM_MIPS 2938/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2939 which is good because they're really quite complicated for MIPS. */ 2940 2941static const DebugFrame debug_frame = { 2942 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2943 .h.cie.id = -1, 2944 .h.cie.version = 1, 2945 .h.cie.code_align = 1, 2946 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2947 .h.cie.return_column = TCG_REG_RA, 2948 2949 /* Total FDE size does not include the "len" member. */ 2950 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2951 2952 .fde_def_cfa = { 2953 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2954 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2955 (FRAME_SIZE >> 7) 2956 }, 2957 .fde_reg_ofs = { 2958 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2959 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2960 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2961 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2962 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2963 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2964 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2965 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2966 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2967 } 2968}; 2969 2970void tcg_register_jit(const void *buf, size_t buf_size) 2971{ 2972 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2973} 2974