1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */ 191#define TCG_CT_CONST_WSZ 0x1000 /* word size */ 192 193#define ALL_GENERAL_REGS 0xffffffffu 194 195static bool is_p2m1(tcg_target_long val) 196{ 197 return val && ((val + 1) & val) == 0; 198} 199 200/* test if a constant matches the constraint */ 201static bool tcg_target_const_match(int64_t val, int ct, 202 TCGType type, TCGCond cond, int vece) 203{ 204 if (ct & TCG_CT_CONST) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_P2M1) 213 && use_mips32r2_instructions && is_p2m1(val)) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_WSZ) 216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 217 return 1; 218 } 219 return 0; 220} 221 222/* instruction opcodes */ 223typedef enum { 224 OPC_J = 002 << 26, 225 OPC_JAL = 003 << 26, 226 OPC_BEQ = 004 << 26, 227 OPC_BNE = 005 << 26, 228 OPC_BLEZ = 006 << 26, 229 OPC_BGTZ = 007 << 26, 230 OPC_ADDIU = 011 << 26, 231 OPC_SLTI = 012 << 26, 232 OPC_SLTIU = 013 << 26, 233 OPC_ANDI = 014 << 26, 234 OPC_ORI = 015 << 26, 235 OPC_XORI = 016 << 26, 236 OPC_LUI = 017 << 26, 237 OPC_BNEL = 025 << 26, 238 OPC_BNEZALC_R6 = 030 << 26, 239 OPC_DADDIU = 031 << 26, 240 OPC_LDL = 032 << 26, 241 OPC_LDR = 033 << 26, 242 OPC_LB = 040 << 26, 243 OPC_LH = 041 << 26, 244 OPC_LWL = 042 << 26, 245 OPC_LW = 043 << 26, 246 OPC_LBU = 044 << 26, 247 OPC_LHU = 045 << 26, 248 OPC_LWR = 046 << 26, 249 OPC_LWU = 047 << 26, 250 OPC_SB = 050 << 26, 251 OPC_SH = 051 << 26, 252 OPC_SWL = 052 << 26, 253 OPC_SW = 053 << 26, 254 OPC_SDL = 054 << 26, 255 OPC_SDR = 055 << 26, 256 OPC_SWR = 056 << 26, 257 OPC_LD = 067 << 26, 258 OPC_SD = 077 << 26, 259 260 OPC_SPECIAL = 000 << 26, 261 OPC_SLL = OPC_SPECIAL | 000, 262 OPC_SRL = OPC_SPECIAL | 002, 263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 264 OPC_SRA = OPC_SPECIAL | 003, 265 OPC_SLLV = OPC_SPECIAL | 004, 266 OPC_SRLV = OPC_SPECIAL | 006, 267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 268 OPC_SRAV = OPC_SPECIAL | 007, 269 OPC_JR_R5 = OPC_SPECIAL | 010, 270 OPC_JALR = OPC_SPECIAL | 011, 271 OPC_MOVZ = OPC_SPECIAL | 012, 272 OPC_MOVN = OPC_SPECIAL | 013, 273 OPC_SYNC = OPC_SPECIAL | 017, 274 OPC_MFHI = OPC_SPECIAL | 020, 275 OPC_MFLO = OPC_SPECIAL | 022, 276 OPC_DSLLV = OPC_SPECIAL | 024, 277 OPC_DSRLV = OPC_SPECIAL | 026, 278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 279 OPC_DSRAV = OPC_SPECIAL | 027, 280 OPC_MULT = OPC_SPECIAL | 030, 281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 282 OPC_MUH = OPC_SPECIAL | 030 | 0300, 283 OPC_MULTU = OPC_SPECIAL | 031, 284 OPC_MULU = OPC_SPECIAL | 031 | 0200, 285 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 286 OPC_DIV = OPC_SPECIAL | 032, 287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 288 OPC_MOD = OPC_SPECIAL | 032 | 0300, 289 OPC_DIVU = OPC_SPECIAL | 033, 290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 291 OPC_MODU = OPC_SPECIAL | 033 | 0300, 292 OPC_DMULT = OPC_SPECIAL | 034, 293 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 294 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 295 OPC_DMULTU = OPC_SPECIAL | 035, 296 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 298 OPC_DDIV = OPC_SPECIAL | 036, 299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 300 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 301 OPC_DDIVU = OPC_SPECIAL | 037, 302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 303 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 304 OPC_ADDU = OPC_SPECIAL | 041, 305 OPC_SUBU = OPC_SPECIAL | 043, 306 OPC_AND = OPC_SPECIAL | 044, 307 OPC_OR = OPC_SPECIAL | 045, 308 OPC_XOR = OPC_SPECIAL | 046, 309 OPC_NOR = OPC_SPECIAL | 047, 310 OPC_SLT = OPC_SPECIAL | 052, 311 OPC_SLTU = OPC_SPECIAL | 053, 312 OPC_DADDU = OPC_SPECIAL | 055, 313 OPC_DSUBU = OPC_SPECIAL | 057, 314 OPC_SELEQZ = OPC_SPECIAL | 065, 315 OPC_SELNEZ = OPC_SPECIAL | 067, 316 OPC_DSLL = OPC_SPECIAL | 070, 317 OPC_DSRL = OPC_SPECIAL | 072, 318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 319 OPC_DSRA = OPC_SPECIAL | 073, 320 OPC_DSLL32 = OPC_SPECIAL | 074, 321 OPC_DSRL32 = OPC_SPECIAL | 076, 322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 323 OPC_DSRA32 = OPC_SPECIAL | 077, 324 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 326 327 OPC_REGIMM = 001 << 26, 328 OPC_BLTZ = OPC_REGIMM | (000 << 16), 329 OPC_BGEZ = OPC_REGIMM | (001 << 16), 330 331 OPC_SPECIAL2 = 034 << 26, 332 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 333 OPC_CLZ = OPC_SPECIAL2 | 040, 334 OPC_DCLZ = OPC_SPECIAL2 | 044, 335 336 OPC_SPECIAL3 = 037 << 26, 337 OPC_EXT = OPC_SPECIAL3 | 000, 338 OPC_DEXTM = OPC_SPECIAL3 | 001, 339 OPC_DEXTU = OPC_SPECIAL3 | 002, 340 OPC_DEXT = OPC_SPECIAL3 | 003, 341 OPC_INS = OPC_SPECIAL3 | 004, 342 OPC_DINSM = OPC_SPECIAL3 | 005, 343 OPC_DINSU = OPC_SPECIAL3 | 006, 344 OPC_DINS = OPC_SPECIAL3 | 007, 345 OPC_WSBH = OPC_SPECIAL3 | 00240, 346 OPC_DSBH = OPC_SPECIAL3 | 00244, 347 OPC_DSHD = OPC_SPECIAL3 | 00544, 348 OPC_SEB = OPC_SPECIAL3 | 02040, 349 OPC_SEH = OPC_SPECIAL3 | 03040, 350 351 /* MIPS r6 doesn't have JR, JALR should be used instead */ 352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 353 354 /* 355 * MIPS r6 replaces MUL with an alternative encoding which is 356 * backwards-compatible at the assembly level. 357 */ 358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 359 360 /* MIPS r6 introduced names for weaker variants of SYNC. These are 361 backward compatible to previous architecture revisions. */ 362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 367 368 /* Aliases for convenience. */ 369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 371} MIPSInsn; 372 373/* 374 * Type reg 375 */ 376static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 377 TCGReg rd, TCGReg rs, TCGReg rt) 378{ 379 int32_t inst; 380 381 inst = opc; 382 inst |= (rs & 0x1F) << 21; 383 inst |= (rt & 0x1F) << 16; 384 inst |= (rd & 0x1F) << 11; 385 tcg_out32(s, inst); 386} 387 388/* 389 * Type immediate 390 */ 391static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 392 TCGReg rt, TCGReg rs, TCGArg imm) 393{ 394 int32_t inst; 395 396 inst = opc; 397 inst |= (rs & 0x1F) << 21; 398 inst |= (rt & 0x1F) << 16; 399 inst |= (imm & 0xffff); 400 tcg_out32(s, inst); 401} 402 403/* 404 * Type bitfield 405 */ 406static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 407 TCGReg rs, int msb, int lsb) 408{ 409 int32_t inst; 410 411 inst = opc; 412 inst |= (rs & 0x1F) << 21; 413 inst |= (rt & 0x1F) << 16; 414 inst |= (msb & 0x1F) << 11; 415 inst |= (lsb & 0x1F) << 6; 416 tcg_out32(s, inst); 417} 418 419static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 420 MIPSInsn oph, TCGReg rt, TCGReg rs, 421 int msb, int lsb) 422{ 423 if (lsb >= 32) { 424 opc = oph; 425 msb -= 32; 426 lsb -= 32; 427 } else if (msb >= 32) { 428 opc = opm; 429 msb -= 32; 430 } 431 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 432} 433 434/* 435 * Type branch 436 */ 437static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 438{ 439 tcg_out_opc_imm(s, opc, rt, rs, 0); 440} 441 442/* 443 * Type sa 444 */ 445static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 446 TCGReg rd, TCGReg rt, TCGArg sa) 447{ 448 int32_t inst; 449 450 inst = opc; 451 inst |= (rt & 0x1F) << 16; 452 inst |= (rd & 0x1F) << 11; 453 inst |= (sa & 0x1F) << 6; 454 tcg_out32(s, inst); 455 456} 457 458static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 459 TCGReg rd, TCGReg rt, TCGArg sa) 460{ 461 int32_t inst; 462 463 inst = (sa & 32 ? opc2 : opc1); 464 inst |= (rt & 0x1F) << 16; 465 inst |= (rd & 0x1F) << 11; 466 inst |= (sa & 0x1F) << 6; 467 tcg_out32(s, inst); 468} 469 470/* 471 * Type jump. 472 * Returns true if the branch was in range and the insn was emitted. 473 */ 474static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 475{ 476 uintptr_t dest = (uintptr_t)target; 477 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 478 int32_t inst; 479 480 /* The pc-region branch happens within the 256MB region of 481 the delay slot (thus the +4). */ 482 if ((from ^ dest) & -(1 << 28)) { 483 return false; 484 } 485 tcg_debug_assert((dest & 3) == 0); 486 487 inst = opc; 488 inst |= (dest >> 2) & 0x3ffffff; 489 tcg_out32(s, inst); 490 return true; 491} 492 493static void tcg_out_nop(TCGContext *s) 494{ 495 tcg_out32(s, 0); 496} 497 498static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 499{ 500 memset(p, 0, count * sizeof(tcg_insn_unit)); 501} 502 503static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 504{ 505 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 506} 507 508static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 509{ 510 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 511} 512 513static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 514{ 515 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 516} 517 518static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 519{ 520 /* Simple reg-reg move, optimising out the 'do nothing' case */ 521 if (ret != arg) { 522 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 523 } 524 return true; 525} 526 527static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 528{ 529 if (arg == (int16_t)arg) { 530 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 531 return true; 532 } 533 if (arg == (uint16_t)arg) { 534 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 535 return true; 536 } 537 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 538 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 539 return true; 540 } 541 return false; 542} 543 544static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 545{ 546 /* 547 * All signed 32-bit constants are loadable with two immediates, 548 * and everything else requires more work. 549 */ 550 if (arg == (int32_t)arg) { 551 if (!tcg_out_movi_one(s, ret, arg)) { 552 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 553 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 554 } 555 return true; 556 } 557 return false; 558} 559 560static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 561 tcg_target_long arg, TCGReg tbreg) 562{ 563 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 564 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 565} 566 567static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 568 tcg_target_long arg, TCGReg tbreg) 569{ 570 tcg_target_long tmp; 571 int sh, lo; 572 573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 574 arg = (int32_t)arg; 575 } 576 577 /* Load all 32-bit constants. */ 578 if (tcg_out_movi_two(s, ret, arg)) { 579 return; 580 } 581 assert(TCG_TARGET_REG_BITS == 64); 582 583 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 584 tmp = tcg_tbrel_diff(s, (void *)arg); 585 if (tmp == (int16_t)tmp) { 586 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 587 return; 588 } 589 if (tcg_out_movi_two(s, ret, tmp)) { 590 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 591 return; 592 } 593 594 /* 595 * Load bitmasks with a right-shift. This is good for things 596 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 597 * or similarly using LUI. For this to work, bit 31 must be set. 598 */ 599 if (arg > 0 && (int32_t)arg < 0) { 600 sh = clz64(arg); 601 if (tcg_out_movi_one(s, ret, arg << sh)) { 602 tcg_out_dsrl(s, ret, ret, sh); 603 return; 604 } 605 } 606 607 /* 608 * Load slightly larger constants using left-shift. 609 * Limit this sequence to 3 insns to avoid too much expansion. 610 */ 611 sh = ctz64(arg); 612 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 613 tcg_out_dsll(s, ret, ret, sh); 614 return; 615 } 616 617 /* 618 * Load slightly larger constants using left-shift and add/or. 619 * Prefer addi with a negative immediate when that would produce 620 * a larger shift. For this to work, bits 15 and 16 must be set. 621 */ 622 lo = arg & 0xffff; 623 if (lo) { 624 if ((arg & 0x18000) == 0x18000) { 625 lo = (int16_t)arg; 626 } 627 tmp = arg - lo; 628 sh = ctz64(tmp); 629 tmp >>= sh; 630 if (tcg_out_movi_one(s, ret, tmp)) { 631 tcg_out_dsll(s, ret, ret, sh); 632 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 633 return; 634 } 635 } 636 637 /* Otherwise, put 64-bit constants into the constant pool. */ 638 tcg_out_movi_pool(s, ret, arg, tbreg); 639} 640 641static void tcg_out_movi(TCGContext *s, TCGType type, 642 TCGReg ret, tcg_target_long arg) 643{ 644 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 645 tcg_out_movi_int(s, type, ret, arg, tbreg); 646} 647 648static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 649{ 650 tcg_debug_assert(use_mips32r2_instructions); 651 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 652} 653 654static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 655{ 656 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 657} 658 659static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 660{ 661 tcg_debug_assert(use_mips32r2_instructions); 662 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 663} 664 665static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 666{ 667 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 668} 669 670static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 671{ 672 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 673 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 674} 675 676static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 if (rd != rs) { 679 tcg_out_ext32s(s, rd, rs); 680 } 681} 682 683static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 684{ 685 tcg_out_ext32u(s, rd, rs); 686} 687 688static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 689{ 690 tcg_out_ext32s(s, rd, rs); 691} 692 693static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 694{ 695 return false; 696} 697 698static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 699 tcg_target_long imm) 700{ 701 /* This function is only used for passing structs by reference. */ 702 g_assert_not_reached(); 703} 704 705static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 706{ 707 /* ret and arg can't be register tmp0 */ 708 tcg_debug_assert(ret != TCG_TMP0); 709 tcg_debug_assert(arg != TCG_TMP0); 710 711 /* With arg = abcd: */ 712 if (use_mips32r2_instructions) { 713 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 714 if (flags & TCG_BSWAP_OS) { 715 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 716 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 717 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 718 } 719 return; 720 } 721 722 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 723 if (!(flags & TCG_BSWAP_IZ)) { 724 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 725 } 726 if (flags & TCG_BSWAP_OS) { 727 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 728 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 729 } else { 730 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 731 if (flags & TCG_BSWAP_OZ) { 732 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 733 } 734 } 735 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 736} 737 738static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 739{ 740 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 741 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 742 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 743 } 744} 745 746static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 747{ 748 if (use_mips32r2_instructions) { 749 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 750 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 751 if (flags & TCG_BSWAP_OZ) { 752 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 753 } 754 } else { 755 if (flags & TCG_BSWAP_OZ) { 756 tcg_out_bswap_subr(s, bswap32u_addr); 757 } else { 758 tcg_out_bswap_subr(s, bswap32_addr); 759 } 760 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 761 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 762 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 763 } 764} 765 766static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 767{ 768 if (use_mips32r2_instructions) { 769 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 770 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 771 } else { 772 tcg_out_bswap_subr(s, bswap64_addr); 773 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 774 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 775 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 776 } 777} 778 779static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 780{ 781 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 782 if (use_mips32r2_instructions) { 783 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 784 } else { 785 tcg_out_dsll(s, ret, arg, 32); 786 tcg_out_dsrl(s, ret, ret, 32); 787 } 788} 789 790static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 791 TCGReg addr, intptr_t ofs) 792{ 793 int16_t lo = ofs; 794 if (ofs != lo) { 795 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 796 if (addr != TCG_REG_ZERO) { 797 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 798 } 799 addr = TCG_TMP0; 800 } 801 tcg_out_opc_imm(s, opc, data, addr, lo); 802} 803 804static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 805 TCGReg arg1, intptr_t arg2) 806{ 807 MIPSInsn opc = OPC_LD; 808 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 809 opc = OPC_LW; 810 } 811 tcg_out_ldst(s, opc, arg, arg1, arg2); 812} 813 814static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 815 TCGReg arg1, intptr_t arg2) 816{ 817 MIPSInsn opc = OPC_SD; 818 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 819 opc = OPC_SW; 820 } 821 tcg_out_ldst(s, opc, arg, arg1, arg2); 822} 823 824static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 825 TCGReg base, intptr_t ofs) 826{ 827 if (val == 0) { 828 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 829 return true; 830 } 831 return false; 832} 833 834static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 835 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 836 bool cbh, bool is_sub) 837{ 838 TCGReg th = TCG_TMP1; 839 840 /* If we have a negative constant such that negating it would 841 make the high part zero, we can (usually) eliminate one insn. */ 842 if (cbl && cbh && bh == -1 && bl != 0) { 843 bl = -bl; 844 bh = 0; 845 is_sub = !is_sub; 846 } 847 848 /* By operating on the high part first, we get to use the final 849 carry operation to move back from the temporary. */ 850 if (!cbh) { 851 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 852 } else if (bh != 0 || ah == rl) { 853 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 854 } else { 855 th = ah; 856 } 857 858 /* Note that tcg optimization should eliminate the bl == 0 case. */ 859 if (is_sub) { 860 if (cbl) { 861 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 862 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 863 } else { 864 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 865 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 866 } 867 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 868 } else { 869 if (cbl) { 870 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 871 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 872 } else if (rl == al && rl == bl) { 873 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 874 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 875 } else { 876 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 877 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 878 } 879 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 880 } 881} 882 883#define SETCOND_INV TCG_TARGET_NB_REGS 884#define SETCOND_NEZ (SETCOND_INV << 1) 885#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 886 887static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 888 TCGReg arg1, TCGReg arg2) 889{ 890 int flags = 0; 891 892 switch (cond) { 893 case TCG_COND_EQ: /* -> NE */ 894 case TCG_COND_GE: /* -> LT */ 895 case TCG_COND_GEU: /* -> LTU */ 896 case TCG_COND_LE: /* -> GT */ 897 case TCG_COND_LEU: /* -> GTU */ 898 cond = tcg_invert_cond(cond); 899 flags ^= SETCOND_INV; 900 break; 901 default: 902 break; 903 } 904 905 switch (cond) { 906 case TCG_COND_NE: 907 flags |= SETCOND_NEZ; 908 if (arg2 == 0) { 909 return arg1 | flags; 910 } 911 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 912 break; 913 case TCG_COND_LT: 914 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 915 break; 916 case TCG_COND_LTU: 917 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 918 break; 919 case TCG_COND_GT: 920 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 921 break; 922 case TCG_COND_GTU: 923 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 924 break; 925 default: 926 g_assert_not_reached(); 927 } 928 return ret | flags; 929} 930 931static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 932{ 933 if (tmpflags != ret) { 934 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 935 936 switch (tmpflags & SETCOND_FLAGS) { 937 case SETCOND_INV: 938 /* Intermediate result is boolean: simply invert. */ 939 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 940 break; 941 case SETCOND_NEZ: 942 /* Intermediate result is zero/non-zero: test != 0. */ 943 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 944 break; 945 case SETCOND_NEZ | SETCOND_INV: 946 /* Intermediate result is zero/non-zero: test == 0. */ 947 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 948 break; 949 default: 950 g_assert_not_reached(); 951 } 952 } 953} 954 955static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 956 TCGReg ret, TCGReg arg1, TCGReg arg2) 957{ 958 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 959 tcg_out_setcond_end(s, ret, tmpflags); 960} 961 962static const TCGOutOpSetcond outop_setcond = { 963 .base.static_constraint = C_O1_I2(r, r, rz), 964 .out_rrr = tgen_setcond, 965}; 966 967static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 968 TCGReg ret, TCGReg arg1, TCGReg arg2) 969{ 970 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 971 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 972 973 /* If intermediate result is zero/non-zero: test != 0. */ 974 if (tmpflags & SETCOND_NEZ) { 975 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 976 tmp = ret; 977 } 978 /* Produce the 0/-1 result. */ 979 if (tmpflags & SETCOND_INV) { 980 tcg_out_opc_imm(s, OPC_ADDIU, ret, tmp, -1); 981 } else { 982 tcg_out_opc_reg(s, OPC_SUBU, ret, TCG_REG_ZERO, tmp); 983 } 984} 985 986static const TCGOutOpSetcond outop_negsetcond = { 987 .base.static_constraint = C_O1_I2(r, r, rz), 988 .out_rrr = tgen_negsetcond, 989}; 990 991static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 992 TCGReg arg1, TCGReg arg2, TCGLabel *l) 993{ 994 static const MIPSInsn b_zero[16] = { 995 [TCG_COND_LT] = OPC_BLTZ, 996 [TCG_COND_GT] = OPC_BGTZ, 997 [TCG_COND_LE] = OPC_BLEZ, 998 [TCG_COND_GE] = OPC_BGEZ, 999 }; 1000 1001 MIPSInsn b_opc = 0; 1002 1003 switch (cond) { 1004 case TCG_COND_EQ: 1005 b_opc = OPC_BEQ; 1006 break; 1007 case TCG_COND_NE: 1008 b_opc = OPC_BNE; 1009 break; 1010 case TCG_COND_LT: 1011 case TCG_COND_GT: 1012 case TCG_COND_LE: 1013 case TCG_COND_GE: 1014 if (arg2 == 0) { 1015 b_opc = b_zero[cond]; 1016 arg2 = arg1; 1017 arg1 = 0; 1018 } 1019 break; 1020 default: 1021 break; 1022 } 1023 1024 if (b_opc == 0) { 1025 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 1026 1027 arg2 = TCG_REG_ZERO; 1028 arg1 = tmpflags & ~SETCOND_FLAGS; 1029 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1030 } 1031 1032 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1033 tcg_out_opc_br(s, b_opc, arg1, arg2); 1034 tcg_out_nop(s); 1035} 1036 1037static const TCGOutOpBrcond outop_brcond = { 1038 .base.static_constraint = C_O0_I2(r, rz), 1039 .out_rr = tgen_brcond, 1040}; 1041 1042static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 1043 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1044{ 1045 int flags = 0; 1046 1047 switch (cond) { 1048 case TCG_COND_EQ: 1049 flags |= SETCOND_INV; 1050 /* fall through */ 1051 case TCG_COND_NE: 1052 flags |= SETCOND_NEZ; 1053 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 1054 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 1055 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1056 break; 1057 1058 default: 1059 tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); 1060 tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), 1061 TCG_TMP1, al, bl); 1062 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 1063 tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); 1064 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1065 break; 1066 } 1067 return ret | flags; 1068} 1069 1070static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1071 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1072{ 1073 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1074 tcg_out_setcond_end(s, ret, tmpflags); 1075} 1076 1077static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1078 TCGReg bl, TCGReg bh, TCGLabel *l) 1079{ 1080 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1081 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1082 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1083 1084 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1085 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1086 tcg_out_nop(s); 1087} 1088 1089static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1090 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1091{ 1092 int tmpflags; 1093 bool eqz; 1094 1095 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1096 if (use_mips32r6_instructions && v1 == 0) { 1097 v1 = v2; 1098 v2 = 0; 1099 cond = tcg_invert_cond(cond); 1100 } 1101 1102 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1103 c1 = tmpflags & ~SETCOND_FLAGS; 1104 eqz = tmpflags & SETCOND_INV; 1105 1106 if (use_mips32r6_instructions) { 1107 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1108 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1109 1110 if (v2 != 0) { 1111 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1112 } 1113 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1114 if (v2 != 0) { 1115 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1116 } 1117 return; 1118 } 1119 1120 /* This should be guaranteed via constraints */ 1121 tcg_debug_assert(v2 == ret); 1122 1123 if (use_movnz_instructions) { 1124 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1125 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1126 } else { 1127 /* Invert the condition in order to branch over the move. */ 1128 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1129 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1130 tcg_out_nop(s); 1131 /* Open-code tcg_out_mov, without the nop-move check. */ 1132 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1133 } 1134} 1135 1136static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1137{ 1138 /* 1139 * Note that __mips_abicalls requires the called function's address 1140 * to be loaded into $25 (t9), even if a direct branch is in range. 1141 * 1142 * For n64, always drop the pointer into the constant pool. 1143 * We can re-use helper addresses often and do not want any 1144 * of the longer sequences tcg_out_movi may try. 1145 */ 1146 if (sizeof(uintptr_t) == 8) { 1147 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1148 } else { 1149 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1150 } 1151 1152 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1153 if (tail) { 1154 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1155 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1156 } 1157 } else { 1158 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1159 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1160 } 1161 } 1162} 1163 1164static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1165 const TCGHelperInfo *info) 1166{ 1167 tcg_out_call_int(s, arg, false); 1168 tcg_out_nop(s); 1169} 1170 1171/* We have four temps, we might as well expose three of them. */ 1172static const TCGLdstHelperParam ldst_helper_param = { 1173 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1174}; 1175 1176static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1177{ 1178 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1179 MemOp opc = get_memop(l->oi); 1180 1181 /* resolve label address */ 1182 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1183 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1184 return false; 1185 } 1186 1187 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1188 1189 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1190 /* delay slot */ 1191 tcg_out_nop(s); 1192 1193 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1194 1195 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1196 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1197 return false; 1198 } 1199 1200 /* delay slot */ 1201 tcg_out_nop(s); 1202 return true; 1203} 1204 1205static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1206{ 1207 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1208 MemOp opc = get_memop(l->oi); 1209 1210 /* resolve label address */ 1211 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1212 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1213 return false; 1214 } 1215 1216 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1217 1218 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1219 /* delay slot */ 1220 tcg_out_nop(s); 1221 1222 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1223 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1224 return false; 1225 } 1226 1227 /* delay slot */ 1228 tcg_out_nop(s); 1229 return true; 1230} 1231 1232typedef struct { 1233 TCGReg base; 1234 TCGAtomAlign aa; 1235} HostAddress; 1236 1237bool tcg_target_has_memory_bswap(MemOp memop) 1238{ 1239 return false; 1240} 1241 1242/* We expect to use a 16-bit negative offset from ENV. */ 1243#define MIN_TLB_MASK_TABLE_OFS -32768 1244 1245/* 1246 * For system-mode, perform the TLB load and compare. 1247 * For user-mode, perform any required alignment tests. 1248 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1249 * is required and fill in @h with the host address for the fast path. 1250 */ 1251static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1252 TCGReg addr, MemOpIdx oi, bool is_ld) 1253{ 1254 TCGType addr_type = s->addr_type; 1255 TCGLabelQemuLdst *ldst = NULL; 1256 MemOp opc = get_memop(oi); 1257 MemOp a_bits; 1258 unsigned s_bits = opc & MO_SIZE; 1259 unsigned a_mask; 1260 TCGReg base; 1261 1262 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1263 a_bits = h->aa.align; 1264 a_mask = (1 << a_bits) - 1; 1265 1266 if (tcg_use_softmmu) { 1267 unsigned s_mask = (1 << s_bits) - 1; 1268 int mem_index = get_mmuidx(oi); 1269 int fast_off = tlb_mask_table_ofs(s, mem_index); 1270 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1271 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1272 int add_off = offsetof(CPUTLBEntry, addend); 1273 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1274 : offsetof(CPUTLBEntry, addr_write); 1275 1276 ldst = new_ldst_label(s); 1277 ldst->is_ld = is_ld; 1278 ldst->oi = oi; 1279 ldst->addr_reg = addr; 1280 1281 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1282 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1283 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1284 1285 /* Extract the TLB index from the address into TMP3. */ 1286 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1287 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1288 s->page_bits - CPU_TLB_ENTRY_BITS); 1289 } else { 1290 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1291 } 1292 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1293 1294 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1295 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1296 1297 /* Load the tlb comparator. */ 1298 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1299 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1300 cmp_off + HOST_BIG_ENDIAN * 4); 1301 } else { 1302 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1303 } 1304 1305 /* Load the tlb addend for the fast path. */ 1306 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1307 1308 /* 1309 * Mask the page bits, keeping the alignment bits to compare against. 1310 * For unaligned accesses, compare against the end of the access to 1311 * verify that it does not cross a page boundary. 1312 */ 1313 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1314 if (a_mask < s_mask) { 1315 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1316 || addr_type == TCG_TYPE_I32 1317 ? OPC_ADDIU : OPC_DADDIU), 1318 TCG_TMP2, addr, s_mask - a_mask); 1319 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1320 } else { 1321 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1322 } 1323 1324 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1325 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1326 tcg_out_ext32u(s, TCG_TMP2, addr); 1327 addr = TCG_TMP2; 1328 } 1329 1330 ldst->label_ptr[0] = s->code_ptr; 1331 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1332 1333 /* delay slot */ 1334 base = TCG_TMP3; 1335 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1336 } else { 1337 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1338 ldst = new_ldst_label(s); 1339 1340 ldst->is_ld = is_ld; 1341 ldst->oi = oi; 1342 ldst->addr_reg = addr; 1343 1344 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1345 tcg_debug_assert(a_bits < 16); 1346 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1347 1348 ldst->label_ptr[0] = s->code_ptr; 1349 if (use_mips32r6_instructions) { 1350 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1351 } else { 1352 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1353 tcg_out_nop(s); 1354 } 1355 } 1356 1357 base = addr; 1358 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1359 tcg_out_ext32u(s, TCG_REG_A0, base); 1360 base = TCG_REG_A0; 1361 } 1362 if (guest_base) { 1363 if (guest_base == (int16_t)guest_base) { 1364 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1365 } else { 1366 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1367 TCG_GUEST_BASE_REG); 1368 } 1369 base = TCG_REG_A0; 1370 } 1371 } 1372 1373 h->base = base; 1374 return ldst; 1375} 1376 1377static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1378 TCGReg base, MemOp opc, TCGType type) 1379{ 1380 switch (opc & MO_SSIZE) { 1381 case MO_UB: 1382 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1383 break; 1384 case MO_SB: 1385 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1386 break; 1387 case MO_UW: 1388 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1389 break; 1390 case MO_SW: 1391 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1392 break; 1393 case MO_UL: 1394 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1395 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1396 break; 1397 } 1398 /* FALLTHRU */ 1399 case MO_SL: 1400 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1401 break; 1402 case MO_UQ: 1403 /* Prefer to load from offset 0 first, but allow for overlap. */ 1404 if (TCG_TARGET_REG_BITS == 64) { 1405 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1406 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1407 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1408 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1409 } else { 1410 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1411 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1412 } 1413 break; 1414 default: 1415 g_assert_not_reached(); 1416 } 1417} 1418 1419static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1420 TCGReg base, MemOp opc, TCGType type) 1421{ 1422 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1423 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1424 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1425 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1426 bool sgn = opc & MO_SIGN; 1427 1428 switch (opc & MO_SIZE) { 1429 case MO_16: 1430 if (HOST_BIG_ENDIAN) { 1431 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1432 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1433 if (use_mips32r2_instructions) { 1434 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1435 } else { 1436 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1437 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1438 } 1439 } else if (use_mips32r2_instructions && lo != base) { 1440 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1441 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1442 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1443 } else { 1444 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1445 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1446 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1447 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1448 } 1449 break; 1450 1451 case MO_32: 1452 tcg_out_opc_imm(s, lw1, lo, base, 0); 1453 tcg_out_opc_imm(s, lw2, lo, base, 3); 1454 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1455 tcg_out_ext32u(s, lo, lo); 1456 } 1457 break; 1458 1459 case MO_64: 1460 if (TCG_TARGET_REG_BITS == 64) { 1461 tcg_out_opc_imm(s, ld1, lo, base, 0); 1462 tcg_out_opc_imm(s, ld2, lo, base, 7); 1463 } else { 1464 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1465 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1466 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1467 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1468 } 1469 break; 1470 1471 default: 1472 g_assert_not_reached(); 1473 } 1474} 1475 1476static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1477 TCGReg addr, MemOpIdx oi, TCGType data_type) 1478{ 1479 MemOp opc = get_memop(oi); 1480 TCGLabelQemuLdst *ldst; 1481 HostAddress h; 1482 1483 ldst = prepare_host_addr(s, &h, addr, oi, true); 1484 1485 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1486 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1487 } else { 1488 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1489 } 1490 1491 if (ldst) { 1492 ldst->type = data_type; 1493 ldst->datalo_reg = datalo; 1494 ldst->datahi_reg = datahi; 1495 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1496 } 1497} 1498 1499static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1500 TCGReg base, MemOp opc) 1501{ 1502 switch (opc & MO_SIZE) { 1503 case MO_8: 1504 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1505 break; 1506 case MO_16: 1507 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1508 break; 1509 case MO_32: 1510 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1511 break; 1512 case MO_64: 1513 if (TCG_TARGET_REG_BITS == 64) { 1514 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1515 } else { 1516 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1517 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1518 } 1519 break; 1520 default: 1521 g_assert_not_reached(); 1522 } 1523} 1524 1525static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1526 TCGReg base, MemOp opc) 1527{ 1528 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1529 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1530 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1531 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1532 1533 switch (opc & MO_SIZE) { 1534 case MO_16: 1535 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1536 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1537 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1538 break; 1539 1540 case MO_32: 1541 tcg_out_opc_imm(s, sw1, lo, base, 0); 1542 tcg_out_opc_imm(s, sw2, lo, base, 3); 1543 break; 1544 1545 case MO_64: 1546 if (TCG_TARGET_REG_BITS == 64) { 1547 tcg_out_opc_imm(s, sd1, lo, base, 0); 1548 tcg_out_opc_imm(s, sd2, lo, base, 7); 1549 } else { 1550 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1551 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1552 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1553 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1554 } 1555 break; 1556 1557 default: 1558 g_assert_not_reached(); 1559 } 1560} 1561 1562static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1563 TCGReg addr, MemOpIdx oi, TCGType data_type) 1564{ 1565 MemOp opc = get_memop(oi); 1566 TCGLabelQemuLdst *ldst; 1567 HostAddress h; 1568 1569 ldst = prepare_host_addr(s, &h, addr, oi, false); 1570 1571 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1572 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1573 } else { 1574 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1575 } 1576 1577 if (ldst) { 1578 ldst->type = data_type; 1579 ldst->datalo_reg = datalo; 1580 ldst->datahi_reg = datahi; 1581 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1582 } 1583} 1584 1585static void tcg_out_mb(TCGContext *s, TCGArg a0) 1586{ 1587 static const MIPSInsn sync[] = { 1588 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1589 as the former is an ordering barrier and the latter 1590 is a completion barrier. */ 1591 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1592 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1593 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1594 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1595 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1596 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1597 }; 1598 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1599} 1600 1601static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1602{ 1603 TCGReg base = TCG_REG_ZERO; 1604 int16_t lo = 0; 1605 1606 if (a0) { 1607 intptr_t ofs; 1608 if (TCG_TARGET_REG_BITS == 64) { 1609 ofs = tcg_tbrel_diff(s, (void *)a0); 1610 lo = ofs; 1611 if (ofs == lo) { 1612 base = TCG_REG_TB; 1613 } else { 1614 base = TCG_REG_V0; 1615 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1616 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1617 } 1618 } else { 1619 ofs = a0; 1620 lo = ofs; 1621 base = TCG_REG_V0; 1622 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1623 } 1624 } 1625 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1626 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1627 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1628 } 1629 /* delay slot */ 1630 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1631} 1632 1633static void tcg_out_goto_tb(TCGContext *s, int which) 1634{ 1635 intptr_t ofs = get_jmp_target_addr(s, which); 1636 TCGReg base, dest; 1637 1638 /* indirect jump method */ 1639 if (TCG_TARGET_REG_BITS == 64) { 1640 dest = TCG_REG_TB; 1641 base = TCG_REG_TB; 1642 ofs = tcg_tbrel_diff(s, (void *)ofs); 1643 } else { 1644 dest = TCG_TMP0; 1645 base = TCG_REG_ZERO; 1646 } 1647 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1648 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1649 /* delay slot */ 1650 tcg_out_nop(s); 1651 1652 set_jmp_reset_offset(s, which); 1653 if (TCG_TARGET_REG_BITS == 64) { 1654 /* For the unlinked case, need to reset TCG_REG_TB. */ 1655 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1656 -tcg_current_code_size(s)); 1657 } 1658} 1659 1660void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1661 uintptr_t jmp_rx, uintptr_t jmp_rw) 1662{ 1663 /* Always indirect, nothing to do */ 1664} 1665 1666 1667static void tgen_add(TCGContext *s, TCGType type, 1668 TCGReg a0, TCGReg a1, TCGReg a2) 1669{ 1670 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1671 tcg_out_opc_reg(s, insn, a0, a1, a2); 1672} 1673 1674static void tgen_addi(TCGContext *s, TCGType type, 1675 TCGReg a0, TCGReg a1, tcg_target_long a2) 1676{ 1677 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1678 tcg_out_opc_imm(s, insn, a0, a1, a2); 1679} 1680 1681static const TCGOutOpBinary outop_add = { 1682 .base.static_constraint = C_O1_I2(r, r, rJ), 1683 .out_rrr = tgen_add, 1684 .out_rri = tgen_addi, 1685}; 1686 1687static void tgen_and(TCGContext *s, TCGType type, 1688 TCGReg a0, TCGReg a1, TCGReg a2) 1689{ 1690 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1691} 1692 1693static void tgen_andi(TCGContext *s, TCGType type, 1694 TCGReg a0, TCGReg a1, tcg_target_long a2) 1695{ 1696 int msb; 1697 1698 if (a2 == (uint16_t)a2) { 1699 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1700 return; 1701 } 1702 1703 tcg_debug_assert(use_mips32r2_instructions); 1704 tcg_debug_assert(is_p2m1(a2)); 1705 msb = ctz64(~a2) - 1; 1706 if (type == TCG_TYPE_I32) { 1707 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1708 } else { 1709 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1710 } 1711} 1712 1713static const TCGOutOpBinary outop_and = { 1714 .base.static_constraint = C_O1_I2(r, r, rIK), 1715 .out_rrr = tgen_and, 1716 .out_rri = tgen_andi, 1717}; 1718 1719static const TCGOutOpBinary outop_andc = { 1720 .base.static_constraint = C_NotImplemented, 1721}; 1722 1723static void tgen_clz(TCGContext *s, TCGType type, 1724 TCGReg a0, TCGReg a1, TCGReg a2) 1725{ 1726 if (use_mips32r6_instructions) { 1727 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1728 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1729 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1730 } else { 1731 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1732 if (a0 == a2) { 1733 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1734 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1735 } else if (a0 != a1) { 1736 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1737 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1738 } else { 1739 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1740 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1741 tcg_out_mov(s, type, a0, TCG_TMP0); 1742 } 1743 } 1744} 1745 1746static void tgen_clzi(TCGContext *s, TCGType type, 1747 TCGReg a0, TCGReg a1, tcg_target_long a2) 1748{ 1749 if (a2 == 0) { 1750 tgen_clz(s, type, a0, a1, TCG_REG_ZERO); 1751 } else if (use_mips32r6_instructions) { 1752 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1753 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1754 } else { 1755 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1756 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1757 } 1758} 1759 1760static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 1761{ 1762 return use_mips32r2_instructions ? C_O1_I2(r, r, rzW) : C_NotImplemented; 1763} 1764 1765static const TCGOutOpBinary outop_clz = { 1766 .base.static_constraint = C_Dynamic, 1767 .base.dynamic_constraint = cset_clz, 1768 .out_rrr = tgen_clz, 1769 .out_rri = tgen_clzi, 1770}; 1771 1772static const TCGOutOpUnary outop_ctpop = { 1773 .base.static_constraint = C_NotImplemented, 1774}; 1775 1776static const TCGOutOpBinary outop_ctz = { 1777 .base.static_constraint = C_NotImplemented, 1778}; 1779 1780static void tgen_divs(TCGContext *s, TCGType type, 1781 TCGReg a0, TCGReg a1, TCGReg a2) 1782{ 1783 if (use_mips32r6_instructions) { 1784 if (type == TCG_TYPE_I32) { 1785 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1786 } else { 1787 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1788 } 1789 } else { 1790 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1791 tcg_out_opc_reg(s, insn, 0, a1, a2); 1792 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1793 } 1794} 1795 1796static const TCGOutOpBinary outop_divs = { 1797 .base.static_constraint = C_O1_I2(r, r, r), 1798 .out_rrr = tgen_divs, 1799}; 1800 1801static const TCGOutOpDivRem outop_divs2 = { 1802 .base.static_constraint = C_NotImplemented, 1803}; 1804 1805static void tgen_divu(TCGContext *s, TCGType type, 1806 TCGReg a0, TCGReg a1, TCGReg a2) 1807{ 1808 if (use_mips32r6_instructions) { 1809 if (type == TCG_TYPE_I32) { 1810 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1811 } else { 1812 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1813 } 1814 } else { 1815 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1816 tcg_out_opc_reg(s, insn, 0, a1, a2); 1817 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1818 } 1819} 1820 1821static const TCGOutOpBinary outop_divu = { 1822 .base.static_constraint = C_O1_I2(r, r, r), 1823 .out_rrr = tgen_divu, 1824}; 1825 1826static const TCGOutOpDivRem outop_divu2 = { 1827 .base.static_constraint = C_NotImplemented, 1828}; 1829 1830static const TCGOutOpBinary outop_eqv = { 1831 .base.static_constraint = C_NotImplemented, 1832}; 1833 1834static void tgen_mul(TCGContext *s, TCGType type, 1835 TCGReg a0, TCGReg a1, TCGReg a2) 1836{ 1837 MIPSInsn insn; 1838 1839 if (type == TCG_TYPE_I32) { 1840 if (use_mips32_instructions) { 1841 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1842 return; 1843 } 1844 insn = OPC_MULT; 1845 } else { 1846 if (use_mips32r6_instructions) { 1847 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1848 return; 1849 } 1850 insn = OPC_DMULT; 1851 } 1852 tcg_out_opc_reg(s, insn, 0, a1, a2); 1853 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1854} 1855 1856static const TCGOutOpBinary outop_mul = { 1857 .base.static_constraint = C_O1_I2(r, r, r), 1858 .out_rrr = tgen_mul, 1859}; 1860 1861static void tgen_muls2(TCGContext *s, TCGType type, 1862 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1863{ 1864 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1865 tcg_out_opc_reg(s, insn, 0, a2, a3); 1866 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1867 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1868} 1869 1870static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1871{ 1872 return use_mips32r6_instructions ? C_NotImplemented : C_O2_I2(r, r, r, r); 1873} 1874 1875static const TCGOutOpMul2 outop_muls2 = { 1876 .base.static_constraint = C_Dynamic, 1877 .base.dynamic_constraint = cset_mul2, 1878 .out_rrrr = tgen_muls2, 1879}; 1880 1881static void tgen_mulsh(TCGContext *s, TCGType type, 1882 TCGReg a0, TCGReg a1, TCGReg a2) 1883{ 1884 if (use_mips32r6_instructions) { 1885 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH; 1886 tcg_out_opc_reg(s, insn, a0, a1, a2); 1887 } else { 1888 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1889 tcg_out_opc_reg(s, insn, 0, a1, a2); 1890 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1891 } 1892} 1893 1894static const TCGOutOpBinary outop_mulsh = { 1895 .base.static_constraint = C_O1_I2(r, r, r), 1896 .out_rrr = tgen_mulsh, 1897}; 1898 1899static void tgen_mulu2(TCGContext *s, TCGType type, 1900 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1901{ 1902 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1903 tcg_out_opc_reg(s, insn, 0, a2, a3); 1904 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1905 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1906} 1907 1908static const TCGOutOpMul2 outop_mulu2 = { 1909 .base.static_constraint = C_Dynamic, 1910 .base.dynamic_constraint = cset_mul2, 1911 .out_rrrr = tgen_mulu2, 1912}; 1913 1914static void tgen_muluh(TCGContext *s, TCGType type, 1915 TCGReg a0, TCGReg a1, TCGReg a2) 1916{ 1917 if (use_mips32r6_instructions) { 1918 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; 1919 tcg_out_opc_reg(s, insn, a0, a1, a2); 1920 } else { 1921 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1922 tcg_out_opc_reg(s, insn, 0, a1, a2); 1923 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1924 } 1925} 1926 1927static const TCGOutOpBinary outop_muluh = { 1928 .base.static_constraint = C_O1_I2(r, r, r), 1929 .out_rrr = tgen_muluh, 1930}; 1931 1932static const TCGOutOpBinary outop_nand = { 1933 .base.static_constraint = C_NotImplemented, 1934}; 1935 1936static void tgen_nor(TCGContext *s, TCGType type, 1937 TCGReg a0, TCGReg a1, TCGReg a2) 1938{ 1939 tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); 1940} 1941 1942static const TCGOutOpBinary outop_nor = { 1943 .base.static_constraint = C_O1_I2(r, r, r), 1944 .out_rrr = tgen_nor, 1945}; 1946 1947static void tgen_or(TCGContext *s, TCGType type, 1948 TCGReg a0, TCGReg a1, TCGReg a2) 1949{ 1950 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1951} 1952 1953static void tgen_ori(TCGContext *s, TCGType type, 1954 TCGReg a0, TCGReg a1, tcg_target_long a2) 1955{ 1956 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1957} 1958 1959static const TCGOutOpBinary outop_or = { 1960 .base.static_constraint = C_O1_I2(r, r, rI), 1961 .out_rrr = tgen_or, 1962 .out_rri = tgen_ori, 1963}; 1964 1965static const TCGOutOpBinary outop_orc = { 1966 .base.static_constraint = C_NotImplemented, 1967}; 1968 1969static void tgen_rems(TCGContext *s, TCGType type, 1970 TCGReg a0, TCGReg a1, TCGReg a2) 1971{ 1972 if (use_mips32r6_instructions) { 1973 if (type == TCG_TYPE_I32) { 1974 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1975 } else { 1976 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1977 } 1978 } else { 1979 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1980 tcg_out_opc_reg(s, insn, 0, a1, a2); 1981 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1982 } 1983} 1984 1985static const TCGOutOpBinary outop_rems = { 1986 .base.static_constraint = C_O1_I2(r, r, r), 1987 .out_rrr = tgen_rems, 1988}; 1989 1990static void tgen_remu(TCGContext *s, TCGType type, 1991 TCGReg a0, TCGReg a1, TCGReg a2) 1992{ 1993 if (use_mips32r6_instructions) { 1994 if (type == TCG_TYPE_I32) { 1995 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1996 } else { 1997 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1998 } 1999 } else { 2000 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 2001 tcg_out_opc_reg(s, insn, 0, a1, a2); 2002 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 2003 } 2004} 2005 2006static const TCGOutOpBinary outop_remu = { 2007 .base.static_constraint = C_O1_I2(r, r, r), 2008 .out_rrr = tgen_remu, 2009}; 2010 2011static const TCGOutOpBinary outop_rotl = { 2012 .base.static_constraint = C_NotImplemented, 2013}; 2014 2015static TCGConstraintSetIndex cset_rotr(TCGType type, unsigned flags) 2016{ 2017 return use_mips32r2_instructions ? C_O1_I2(r, r, ri) : C_NotImplemented; 2018} 2019 2020static void tgen_rotr(TCGContext *s, TCGType type, 2021 TCGReg a0, TCGReg a1, TCGReg a2) 2022{ 2023 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; 2024 tcg_out_opc_reg(s, insn, a0, a1, a2); 2025} 2026 2027static void tgen_rotri(TCGContext *s, TCGType type, 2028 TCGReg a0, TCGReg a1, tcg_target_long a2) 2029{ 2030 if (type == TCG_TYPE_I32) { 2031 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); 2032 } else { 2033 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2034 } 2035} 2036 2037static const TCGOutOpBinary outop_rotr = { 2038 .base.static_constraint = C_Dynamic, 2039 .base.dynamic_constraint = cset_rotr, 2040 .out_rrr = tgen_rotr, 2041 .out_rri = tgen_rotri, 2042}; 2043 2044static void tgen_sar(TCGContext *s, TCGType type, 2045 TCGReg a0, TCGReg a1, TCGReg a2) 2046{ 2047 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; 2048 tcg_out_opc_reg(s, insn, a0, a1, a2); 2049} 2050 2051static void tgen_sari(TCGContext *s, TCGType type, 2052 TCGReg a0, TCGReg a1, tcg_target_long a2) 2053{ 2054 if (type == TCG_TYPE_I32) { 2055 tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); 2056 } else { 2057 tcg_out_dsra(s, a0, a1, a2); 2058 } 2059} 2060 2061static const TCGOutOpBinary outop_sar = { 2062 .base.static_constraint = C_O1_I2(r, r, ri), 2063 .out_rrr = tgen_sar, 2064 .out_rri = tgen_sari, 2065}; 2066 2067static void tgen_shl(TCGContext *s, TCGType type, 2068 TCGReg a0, TCGReg a1, TCGReg a2) 2069{ 2070 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; 2071 tcg_out_opc_reg(s, insn, a0, a1, a2); 2072} 2073 2074static void tgen_shli(TCGContext *s, TCGType type, 2075 TCGReg a0, TCGReg a1, tcg_target_long a2) 2076{ 2077 if (type == TCG_TYPE_I32) { 2078 tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); 2079 } else { 2080 tcg_out_dsll(s, a0, a1, a2); 2081 } 2082} 2083 2084static const TCGOutOpBinary outop_shl = { 2085 .base.static_constraint = C_O1_I2(r, r, ri), 2086 .out_rrr = tgen_shl, 2087 .out_rri = tgen_shli, 2088}; 2089 2090static void tgen_shr(TCGContext *s, TCGType type, 2091 TCGReg a0, TCGReg a1, TCGReg a2) 2092{ 2093 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; 2094 tcg_out_opc_reg(s, insn, a0, a1, a2); 2095} 2096 2097static void tgen_shri(TCGContext *s, TCGType type, 2098 TCGReg a0, TCGReg a1, tcg_target_long a2) 2099{ 2100 if (type == TCG_TYPE_I32) { 2101 tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); 2102 } else { 2103 tcg_out_dsrl(s, a0, a1, a2); 2104 } 2105} 2106 2107static const TCGOutOpBinary outop_shr = { 2108 .base.static_constraint = C_O1_I2(r, r, ri), 2109 .out_rrr = tgen_shr, 2110 .out_rri = tgen_shri, 2111}; 2112 2113static void tgen_sub(TCGContext *s, TCGType type, 2114 TCGReg a0, TCGReg a1, TCGReg a2) 2115{ 2116 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU; 2117 tcg_out_opc_reg(s, insn, a0, a1, a2); 2118} 2119 2120static const TCGOutOpSubtract outop_sub = { 2121 .base.static_constraint = C_O1_I2(r, r, r), 2122 .out_rrr = tgen_sub, 2123}; 2124 2125static void tgen_xor(TCGContext *s, TCGType type, 2126 TCGReg a0, TCGReg a1, TCGReg a2) 2127{ 2128 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2129} 2130 2131static void tgen_xori(TCGContext *s, TCGType type, 2132 TCGReg a0, TCGReg a1, tcg_target_long a2) 2133{ 2134 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2135} 2136 2137static const TCGOutOpBinary outop_xor = { 2138 .base.static_constraint = C_O1_I2(r, r, rI), 2139 .out_rrr = tgen_xor, 2140 .out_rri = tgen_xori, 2141}; 2142 2143static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2144{ 2145 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2146} 2147 2148static const TCGOutOpUnary outop_neg = { 2149 .base.static_constraint = C_O1_I1(r, r), 2150 .out_rr = tgen_neg, 2151}; 2152 2153static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2154{ 2155 tgen_nor(s, type, a0, TCG_REG_ZERO, a1); 2156} 2157 2158static const TCGOutOpUnary outop_not = { 2159 .base.static_constraint = C_O1_I1(r, r), 2160 .out_rr = tgen_not, 2161}; 2162 2163 2164static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2165 const TCGArg args[TCG_MAX_OP_ARGS], 2166 const int const_args[TCG_MAX_OP_ARGS]) 2167{ 2168 MIPSInsn i1; 2169 TCGArg a0, a1, a2; 2170 2171 a0 = args[0]; 2172 a1 = args[1]; 2173 a2 = args[2]; 2174 2175 switch (opc) { 2176 case INDEX_op_goto_ptr: 2177 /* jmp to the given host address (could be epilogue) */ 2178 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2179 if (TCG_TARGET_REG_BITS == 64) { 2180 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 2181 } else { 2182 tcg_out_nop(s); 2183 } 2184 break; 2185 case INDEX_op_br: 2186 tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, 2187 TCG_REG_ZERO, TCG_REG_ZERO, arg_label(a0)); 2188 break; 2189 2190 case INDEX_op_ld8u_i32: 2191 case INDEX_op_ld8u_i64: 2192 i1 = OPC_LBU; 2193 goto do_ldst; 2194 case INDEX_op_ld8s_i32: 2195 case INDEX_op_ld8s_i64: 2196 i1 = OPC_LB; 2197 goto do_ldst; 2198 case INDEX_op_ld16u_i32: 2199 case INDEX_op_ld16u_i64: 2200 i1 = OPC_LHU; 2201 goto do_ldst; 2202 case INDEX_op_ld16s_i32: 2203 case INDEX_op_ld16s_i64: 2204 i1 = OPC_LH; 2205 goto do_ldst; 2206 case INDEX_op_ld_i32: 2207 case INDEX_op_ld32s_i64: 2208 i1 = OPC_LW; 2209 goto do_ldst; 2210 case INDEX_op_ld32u_i64: 2211 i1 = OPC_LWU; 2212 goto do_ldst; 2213 case INDEX_op_ld_i64: 2214 i1 = OPC_LD; 2215 goto do_ldst; 2216 case INDEX_op_st8_i32: 2217 case INDEX_op_st8_i64: 2218 i1 = OPC_SB; 2219 goto do_ldst; 2220 case INDEX_op_st16_i32: 2221 case INDEX_op_st16_i64: 2222 i1 = OPC_SH; 2223 goto do_ldst; 2224 case INDEX_op_st_i32: 2225 case INDEX_op_st32_i64: 2226 i1 = OPC_SW; 2227 goto do_ldst; 2228 case INDEX_op_st_i64: 2229 i1 = OPC_SD; 2230 do_ldst: 2231 tcg_out_ldst(s, i1, a0, a1, a2); 2232 break; 2233 2234 case INDEX_op_bswap16_i32: 2235 case INDEX_op_bswap16_i64: 2236 tcg_out_bswap16(s, a0, a1, a2); 2237 break; 2238 case INDEX_op_bswap32_i32: 2239 tcg_out_bswap32(s, a0, a1, 0); 2240 break; 2241 case INDEX_op_bswap32_i64: 2242 tcg_out_bswap32(s, a0, a1, a2); 2243 break; 2244 case INDEX_op_bswap64_i64: 2245 tcg_out_bswap64(s, a0, a1); 2246 break; 2247 case INDEX_op_extrh_i64_i32: 2248 tcg_out_dsra(s, a0, a1, 32); 2249 break; 2250 2251 case INDEX_op_deposit_i32: 2252 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2253 break; 2254 case INDEX_op_deposit_i64: 2255 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2256 args[3] + args[4] - 1, args[3]); 2257 break; 2258 2259 case INDEX_op_extract_i32: 2260 if (a2 == 0 && args[3] <= 16) { 2261 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2262 } else { 2263 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2264 } 2265 break; 2266 case INDEX_op_extract_i64: 2267 if (a2 == 0 && args[3] <= 16) { 2268 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2269 } else { 2270 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2271 a0, a1, args[3] - 1, a2); 2272 } 2273 break; 2274 2275 case INDEX_op_sextract_i64: 2276 if (a2 == 0 && args[3] == 32) { 2277 tcg_out_ext32s(s, a0, a1); 2278 break; 2279 } 2280 /* FALLTHRU */ 2281 case INDEX_op_sextract_i32: 2282 if (a2 == 0 && args[3] == 8) { 2283 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 2284 } else if (a2 == 0 && args[3] == 16) { 2285 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 2286 } else { 2287 g_assert_not_reached(); 2288 } 2289 break; 2290 2291 case INDEX_op_brcond2_i32: 2292 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2293 break; 2294 2295 case INDEX_op_movcond_i32: 2296 case INDEX_op_movcond_i64: 2297 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2298 break; 2299 2300 case INDEX_op_setcond2_i32: 2301 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2302 break; 2303 2304 case INDEX_op_qemu_ld_i32: 2305 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2306 break; 2307 case INDEX_op_qemu_ld_i64: 2308 if (TCG_TARGET_REG_BITS == 64) { 2309 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2310 } else { 2311 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2312 } 2313 break; 2314 2315 case INDEX_op_qemu_st_i32: 2316 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2317 break; 2318 case INDEX_op_qemu_st_i64: 2319 if (TCG_TARGET_REG_BITS == 64) { 2320 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2321 } else { 2322 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2323 } 2324 break; 2325 2326 case INDEX_op_add2_i32: 2327 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2328 const_args[4], const_args[5], false); 2329 break; 2330 case INDEX_op_sub2_i32: 2331 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2332 const_args[4], const_args[5], true); 2333 break; 2334 2335 case INDEX_op_mb: 2336 tcg_out_mb(s, a0); 2337 break; 2338 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2339 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2340 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2341 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2342 case INDEX_op_extu_i32_i64: 2343 case INDEX_op_extrl_i64_i32: 2344 default: 2345 g_assert_not_reached(); 2346 } 2347} 2348 2349static TCGConstraintSetIndex 2350tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2351{ 2352 switch (op) { 2353 case INDEX_op_goto_ptr: 2354 return C_O0_I1(r); 2355 2356 case INDEX_op_ld8u_i32: 2357 case INDEX_op_ld8s_i32: 2358 case INDEX_op_ld16u_i32: 2359 case INDEX_op_ld16s_i32: 2360 case INDEX_op_ld_i32: 2361 case INDEX_op_bswap16_i32: 2362 case INDEX_op_bswap32_i32: 2363 case INDEX_op_extract_i32: 2364 case INDEX_op_sextract_i32: 2365 case INDEX_op_ld8u_i64: 2366 case INDEX_op_ld8s_i64: 2367 case INDEX_op_ld16u_i64: 2368 case INDEX_op_ld16s_i64: 2369 case INDEX_op_ld32s_i64: 2370 case INDEX_op_ld32u_i64: 2371 case INDEX_op_ld_i64: 2372 case INDEX_op_bswap16_i64: 2373 case INDEX_op_bswap32_i64: 2374 case INDEX_op_bswap64_i64: 2375 case INDEX_op_ext_i32_i64: 2376 case INDEX_op_extu_i32_i64: 2377 case INDEX_op_extrl_i64_i32: 2378 case INDEX_op_extrh_i64_i32: 2379 case INDEX_op_extract_i64: 2380 case INDEX_op_sextract_i64: 2381 return C_O1_I1(r, r); 2382 2383 case INDEX_op_st8_i32: 2384 case INDEX_op_st16_i32: 2385 case INDEX_op_st_i32: 2386 case INDEX_op_st8_i64: 2387 case INDEX_op_st16_i64: 2388 case INDEX_op_st32_i64: 2389 case INDEX_op_st_i64: 2390 return C_O0_I2(rz, r); 2391 2392 case INDEX_op_deposit_i32: 2393 case INDEX_op_deposit_i64: 2394 return C_O1_I2(r, 0, rz); 2395 case INDEX_op_movcond_i32: 2396 case INDEX_op_movcond_i64: 2397 return (use_mips32r6_instructions 2398 ? C_O1_I4(r, rz, rz, rz, rz) 2399 : C_O1_I4(r, rz, rz, rz, 0)); 2400 case INDEX_op_add2_i32: 2401 case INDEX_op_sub2_i32: 2402 return C_O2_I4(r, r, rz, rz, rN, rN); 2403 case INDEX_op_setcond2_i32: 2404 return C_O1_I4(r, rz, rz, rz, rz); 2405 case INDEX_op_brcond2_i32: 2406 return C_O0_I4(rz, rz, rz, rz); 2407 2408 case INDEX_op_qemu_ld_i32: 2409 return C_O1_I1(r, r); 2410 case INDEX_op_qemu_st_i32: 2411 return C_O0_I2(rz, r); 2412 case INDEX_op_qemu_ld_i64: 2413 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2414 case INDEX_op_qemu_st_i64: 2415 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2416 2417 default: 2418 return C_NotImplemented; 2419 } 2420} 2421 2422static const int tcg_target_callee_save_regs[] = { 2423 TCG_REG_S0, 2424 TCG_REG_S1, 2425 TCG_REG_S2, 2426 TCG_REG_S3, 2427 TCG_REG_S4, 2428 TCG_REG_S5, 2429 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2430 TCG_REG_S7, /* used for guest_base */ 2431 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2432 TCG_REG_RA, /* should be last for ABI compliance */ 2433}; 2434 2435/* The Linux kernel doesn't provide any information about the available 2436 instruction set. Probe it using a signal handler. */ 2437 2438 2439#ifndef use_movnz_instructions 2440bool use_movnz_instructions = false; 2441#endif 2442 2443#ifndef use_mips32_instructions 2444bool use_mips32_instructions = false; 2445#endif 2446 2447#ifndef use_mips32r2_instructions 2448bool use_mips32r2_instructions = false; 2449#endif 2450 2451static volatile sig_atomic_t got_sigill; 2452 2453static void sigill_handler(int signo, siginfo_t *si, void *data) 2454{ 2455 /* Skip the faulty instruction */ 2456 ucontext_t *uc = (ucontext_t *)data; 2457 uc->uc_mcontext.pc += 4; 2458 2459 got_sigill = 1; 2460} 2461 2462static void tcg_target_detect_isa(void) 2463{ 2464 struct sigaction sa_old, sa_new; 2465 2466 memset(&sa_new, 0, sizeof(sa_new)); 2467 sa_new.sa_flags = SA_SIGINFO; 2468 sa_new.sa_sigaction = sigill_handler; 2469 sigaction(SIGILL, &sa_new, &sa_old); 2470 2471 /* Probe for movn/movz, necessary to implement movcond. */ 2472#ifndef use_movnz_instructions 2473 got_sigill = 0; 2474 asm volatile(".set push\n" 2475 ".set mips32\n" 2476 "movn $zero, $zero, $zero\n" 2477 "movz $zero, $zero, $zero\n" 2478 ".set pop\n" 2479 : : : ); 2480 use_movnz_instructions = !got_sigill; 2481#endif 2482 2483 /* Probe for MIPS32 instructions. As no subsetting is allowed 2484 by the specification, it is only necessary to probe for one 2485 of the instructions. */ 2486#ifndef use_mips32_instructions 2487 got_sigill = 0; 2488 asm volatile(".set push\n" 2489 ".set mips32\n" 2490 "mul $zero, $zero\n" 2491 ".set pop\n" 2492 : : : ); 2493 use_mips32_instructions = !got_sigill; 2494#endif 2495 2496 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2497 available. As no subsetting is allowed by the specification, 2498 it is only necessary to probe for one of the instructions. */ 2499#ifndef use_mips32r2_instructions 2500 if (use_mips32_instructions) { 2501 got_sigill = 0; 2502 asm volatile(".set push\n" 2503 ".set mips32r2\n" 2504 "seb $zero, $zero\n" 2505 ".set pop\n" 2506 : : : ); 2507 use_mips32r2_instructions = !got_sigill; 2508 } 2509#endif 2510 2511 sigaction(SIGILL, &sa_old, NULL); 2512} 2513 2514static tcg_insn_unit *align_code_ptr(TCGContext *s) 2515{ 2516 uintptr_t p = (uintptr_t)s->code_ptr; 2517 if (p & 15) { 2518 p = (p + 15) & -16; 2519 s->code_ptr = (void *)p; 2520 } 2521 return s->code_ptr; 2522} 2523 2524/* Stack frame parameters. */ 2525#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2526#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2527#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2528 2529#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2530 + TCG_TARGET_STACK_ALIGN - 1) \ 2531 & -TCG_TARGET_STACK_ALIGN) 2532#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2533 2534/* We're expecting to be able to use an immediate for frame allocation. */ 2535QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2536 2537/* Generate global QEMU prologue and epilogue code */ 2538static void tcg_target_qemu_prologue(TCGContext *s) 2539{ 2540 int i; 2541 2542 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2543 2544 /* TB prologue */ 2545 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2546 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2547 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2548 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2549 } 2550 2551 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2552 /* 2553 * The function call abi for n32 and n64 will have loaded $25 (t9) 2554 * with the address of the prologue, so we can use that instead 2555 * of TCG_REG_TB. 2556 */ 2557#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2558# error "Unknown mips abi" 2559#endif 2560 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2561 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2562 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2563 } 2564 2565 if (TCG_TARGET_REG_BITS == 64) { 2566 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2567 } 2568 2569 /* Call generated code */ 2570 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2571 /* delay slot */ 2572 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2573 2574 /* 2575 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2576 * and fall through to the rest of the epilogue. 2577 */ 2578 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2579 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2580 2581 /* TB epilogue */ 2582 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2583 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2584 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2585 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2586 } 2587 2588 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2589 /* delay slot */ 2590 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2591 2592 if (use_mips32r2_instructions) { 2593 return; 2594 } 2595 2596 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2597 clobbers TCG_TMP1, TCG_TMP2. */ 2598 2599 /* 2600 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2601 */ 2602 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2603 /* t3 = (ssss)d000 */ 2604 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2605 /* t1 = 000a */ 2606 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2607 /* t2 = 00c0 */ 2608 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2609 /* t3 = d00a */ 2610 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2611 /* t1 = 0abc */ 2612 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2613 /* t2 = 0c00 */ 2614 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2615 /* t1 = 00b0 */ 2616 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2617 /* t3 = dc0a */ 2618 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2619 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2620 /* t3 = dcba -- delay slot */ 2621 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2622 2623 if (TCG_TARGET_REG_BITS == 32) { 2624 return; 2625 } 2626 2627 /* 2628 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2629 */ 2630 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2631 /* t1 = (0000)000d */ 2632 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2633 /* t3 = 000a */ 2634 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2635 /* t1 = (0000)d000 */ 2636 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2637 /* t2 = 00c0 */ 2638 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2639 /* t3 = d00a */ 2640 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2641 /* t1 = 0abc */ 2642 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2643 /* t2 = 0c00 */ 2644 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2645 /* t1 = 00b0 */ 2646 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2647 /* t3 = dc0a */ 2648 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2649 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2650 /* t3 = dcba -- delay slot */ 2651 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2652 2653 /* 2654 * bswap64 -- 64-bit swap. a0 = abcdefgh 2655 */ 2656 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2657 /* t3 = h0000000 */ 2658 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2659 /* t1 = 0000000a */ 2660 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2661 2662 /* t2 = 000000g0 */ 2663 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2664 /* t3 = h000000a */ 2665 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2666 /* t1 = 00000abc */ 2667 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2668 /* t2 = 0g000000 */ 2669 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2670 /* t1 = 000000b0 */ 2671 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2672 2673 /* t3 = hg00000a */ 2674 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2675 /* t2 = 0000abcd */ 2676 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2677 /* t3 = hg0000ba */ 2678 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2679 2680 /* t1 = 000000c0 */ 2681 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2682 /* t2 = 0000000d */ 2683 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2684 /* t1 = 00000c00 */ 2685 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2686 /* t2 = 0000d000 */ 2687 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2688 2689 /* t3 = hg000cba */ 2690 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2691 /* t1 = 00abcdef */ 2692 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2693 /* t3 = hg00dcba */ 2694 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2695 2696 /* t2 = 0000000f */ 2697 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2698 /* t1 = 000000e0 */ 2699 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2700 /* t2 = 00f00000 */ 2701 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2702 /* t1 = 000e0000 */ 2703 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2704 2705 /* t3 = hgf0dcba */ 2706 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2707 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2708 /* t3 = hgfedcba -- delay slot */ 2709 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2710} 2711 2712static void tcg_out_tb_start(TCGContext *s) 2713{ 2714 /* nothing to do */ 2715} 2716 2717static void tcg_target_init(TCGContext *s) 2718{ 2719 tcg_target_detect_isa(); 2720 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2721 if (TCG_TARGET_REG_BITS == 64) { 2722 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2723 } 2724 2725 tcg_target_call_clobber_regs = 0; 2726 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2727 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2728 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2729 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2730 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2731 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2732 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2733 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2734 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2735 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2736 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2737 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2738 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2741 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2742 2743 s->reserved_regs = 0; 2744 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2745 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2746 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2747 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2748 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2749 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2750 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2751 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2752 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2753 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2754 if (TCG_TARGET_REG_BITS == 64) { 2755 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2756 } 2757} 2758 2759typedef struct { 2760 DebugFrameHeader h; 2761 uint8_t fde_def_cfa[4]; 2762 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2763} DebugFrame; 2764 2765#define ELF_HOST_MACHINE EM_MIPS 2766/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2767 which is good because they're really quite complicated for MIPS. */ 2768 2769static const DebugFrame debug_frame = { 2770 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2771 .h.cie.id = -1, 2772 .h.cie.version = 1, 2773 .h.cie.code_align = 1, 2774 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2775 .h.cie.return_column = TCG_REG_RA, 2776 2777 /* Total FDE size does not include the "len" member. */ 2778 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2779 2780 .fde_def_cfa = { 2781 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2782 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2783 (FRAME_SIZE >> 7) 2784 }, 2785 .fde_reg_ofs = { 2786 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2787 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2788 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2789 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2790 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2791 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2792 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2793 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2794 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2795 } 2796}; 2797 2798void tcg_register_jit(const void *buf, size_t buf_size) 2799{ 2800 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2801} 2802