1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28#include "../tcg-pool.c.inc" 29 30#if TCG_TARGET_REG_BITS == 32 31# define LO_OFF (HOST_BIG_ENDIAN * 4) 32# define HI_OFF (4 - LO_OFF) 33#else 34/* Assert at compile-time that these values are never used for 64-bit. */ 35# define LO_OFF ({ qemu_build_not_reached(); 0; }) 36# define HI_OFF ({ qemu_build_not_reached(); 0; }) 37#endif 38 39#ifdef CONFIG_DEBUG_TCG 40static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 41 "zero", 42 "at", 43 "v0", 44 "v1", 45 "a0", 46 "a1", 47 "a2", 48 "a3", 49 "t0", 50 "t1", 51 "t2", 52 "t3", 53 "t4", 54 "t5", 55 "t6", 56 "t7", 57 "s0", 58 "s1", 59 "s2", 60 "s3", 61 "s4", 62 "s5", 63 "s6", 64 "s7", 65 "t8", 66 "t9", 67 "k0", 68 "k1", 69 "gp", 70 "sp", 71 "s8", 72 "ra", 73}; 74#endif 75 76#define TCG_TMP0 TCG_REG_AT 77#define TCG_TMP1 TCG_REG_T9 78#define TCG_TMP2 TCG_REG_T8 79#define TCG_TMP3 TCG_REG_T7 80 81#ifndef CONFIG_SOFTMMU 82#define TCG_GUEST_BASE_REG TCG_REG_S7 83#endif 84#if TCG_TARGET_REG_BITS == 64 85#define TCG_REG_TB TCG_REG_S6 86#else 87#define TCG_REG_TB (qemu_build_not_reached(), TCG_REG_ZERO) 88#endif 89 90/* check if we really need so many registers :P */ 91static const int tcg_target_reg_alloc_order[] = { 92 /* Call saved registers. */ 93 TCG_REG_S0, 94 TCG_REG_S1, 95 TCG_REG_S2, 96 TCG_REG_S3, 97 TCG_REG_S4, 98 TCG_REG_S5, 99 TCG_REG_S6, 100 TCG_REG_S7, 101 TCG_REG_S8, 102 103 /* Call clobbered registers. */ 104 TCG_REG_T4, 105 TCG_REG_T5, 106 TCG_REG_T6, 107 TCG_REG_T7, 108 TCG_REG_T8, 109 TCG_REG_T9, 110 TCG_REG_V1, 111 TCG_REG_V0, 112 113 /* Argument registers, opposite order of allocation. */ 114 TCG_REG_T3, 115 TCG_REG_T2, 116 TCG_REG_T1, 117 TCG_REG_T0, 118 TCG_REG_A3, 119 TCG_REG_A2, 120 TCG_REG_A1, 121 TCG_REG_A0, 122}; 123 124static const TCGReg tcg_target_call_iarg_regs[] = { 125 TCG_REG_A0, 126 TCG_REG_A1, 127 TCG_REG_A2, 128 TCG_REG_A3, 129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 130 TCG_REG_T0, 131 TCG_REG_T1, 132 TCG_REG_T2, 133 TCG_REG_T3, 134#endif 135}; 136 137static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 138{ 139 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 140 tcg_debug_assert(slot >= 0 && slot <= 1); 141 return TCG_REG_V0 + slot; 142} 143 144static const tcg_insn_unit *tb_ret_addr; 145static const tcg_insn_unit *bswap32_addr; 146static const tcg_insn_unit *bswap32u_addr; 147static const tcg_insn_unit *bswap64_addr; 148 149static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 150{ 151 /* Let the compiler perform the right-shift as part of the arithmetic. */ 152 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 153 ptrdiff_t disp = target - (src_rx + 1); 154 if (disp == (int16_t)disp) { 155 *src_rw = deposit32(*src_rw, 0, 16, disp); 156 return true; 157 } 158 return false; 159} 160 161static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 162 intptr_t value, intptr_t addend) 163{ 164 value += addend; 165 switch (type) { 166 case R_MIPS_PC16: 167 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 168 case R_MIPS_16: 169 if (value != (int16_t)value) { 170 return false; 171 } 172 *code_ptr = deposit32(*code_ptr, 0, 16, value); 173 return true; 174 } 175 g_assert_not_reached(); 176} 177 178#define TCG_CT_CONST_ZERO 0x100 179#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 180#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 181#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 182#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 183#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 184 185#define ALL_GENERAL_REGS 0xffffffffu 186 187static bool is_p2m1(tcg_target_long val) 188{ 189 return val && ((val + 1) & val) == 0; 190} 191 192/* test if a constant matches the constraint */ 193static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 194{ 195 if (ct & TCG_CT_CONST) { 196 return 1; 197 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 198 return 1; 199 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 200 return 1; 201 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 202 return 1; 203 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 204 return 1; 205 } else if ((ct & TCG_CT_CONST_P2M1) 206 && use_mips32r2_instructions && is_p2m1(val)) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_WSZ) 209 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 210 return 1; 211 } 212 return 0; 213} 214 215/* instruction opcodes */ 216typedef enum { 217 OPC_J = 002 << 26, 218 OPC_JAL = 003 << 26, 219 OPC_BEQ = 004 << 26, 220 OPC_BNE = 005 << 26, 221 OPC_BLEZ = 006 << 26, 222 OPC_BGTZ = 007 << 26, 223 OPC_ADDIU = 011 << 26, 224 OPC_SLTI = 012 << 26, 225 OPC_SLTIU = 013 << 26, 226 OPC_ANDI = 014 << 26, 227 OPC_ORI = 015 << 26, 228 OPC_XORI = 016 << 26, 229 OPC_LUI = 017 << 26, 230 OPC_BNEL = 025 << 26, 231 OPC_BNEZALC_R6 = 030 << 26, 232 OPC_DADDIU = 031 << 26, 233 OPC_LDL = 032 << 26, 234 OPC_LDR = 033 << 26, 235 OPC_LB = 040 << 26, 236 OPC_LH = 041 << 26, 237 OPC_LWL = 042 << 26, 238 OPC_LW = 043 << 26, 239 OPC_LBU = 044 << 26, 240 OPC_LHU = 045 << 26, 241 OPC_LWR = 046 << 26, 242 OPC_LWU = 047 << 26, 243 OPC_SB = 050 << 26, 244 OPC_SH = 051 << 26, 245 OPC_SWL = 052 << 26, 246 OPC_SW = 053 << 26, 247 OPC_SDL = 054 << 26, 248 OPC_SDR = 055 << 26, 249 OPC_SWR = 056 << 26, 250 OPC_LD = 067 << 26, 251 OPC_SD = 077 << 26, 252 253 OPC_SPECIAL = 000 << 26, 254 OPC_SLL = OPC_SPECIAL | 000, 255 OPC_SRL = OPC_SPECIAL | 002, 256 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 257 OPC_SRA = OPC_SPECIAL | 003, 258 OPC_SLLV = OPC_SPECIAL | 004, 259 OPC_SRLV = OPC_SPECIAL | 006, 260 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 261 OPC_SRAV = OPC_SPECIAL | 007, 262 OPC_JR_R5 = OPC_SPECIAL | 010, 263 OPC_JALR = OPC_SPECIAL | 011, 264 OPC_MOVZ = OPC_SPECIAL | 012, 265 OPC_MOVN = OPC_SPECIAL | 013, 266 OPC_SYNC = OPC_SPECIAL | 017, 267 OPC_MFHI = OPC_SPECIAL | 020, 268 OPC_MFLO = OPC_SPECIAL | 022, 269 OPC_DSLLV = OPC_SPECIAL | 024, 270 OPC_DSRLV = OPC_SPECIAL | 026, 271 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 272 OPC_DSRAV = OPC_SPECIAL | 027, 273 OPC_MULT = OPC_SPECIAL | 030, 274 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 275 OPC_MUH = OPC_SPECIAL | 030 | 0300, 276 OPC_MULTU = OPC_SPECIAL | 031, 277 OPC_MULU = OPC_SPECIAL | 031 | 0200, 278 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 279 OPC_DIV = OPC_SPECIAL | 032, 280 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 281 OPC_MOD = OPC_SPECIAL | 032 | 0300, 282 OPC_DIVU = OPC_SPECIAL | 033, 283 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 284 OPC_MODU = OPC_SPECIAL | 033 | 0300, 285 OPC_DMULT = OPC_SPECIAL | 034, 286 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 287 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 288 OPC_DMULTU = OPC_SPECIAL | 035, 289 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 290 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 291 OPC_DDIV = OPC_SPECIAL | 036, 292 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 293 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 294 OPC_DDIVU = OPC_SPECIAL | 037, 295 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 296 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 297 OPC_ADDU = OPC_SPECIAL | 041, 298 OPC_SUBU = OPC_SPECIAL | 043, 299 OPC_AND = OPC_SPECIAL | 044, 300 OPC_OR = OPC_SPECIAL | 045, 301 OPC_XOR = OPC_SPECIAL | 046, 302 OPC_NOR = OPC_SPECIAL | 047, 303 OPC_SLT = OPC_SPECIAL | 052, 304 OPC_SLTU = OPC_SPECIAL | 053, 305 OPC_DADDU = OPC_SPECIAL | 055, 306 OPC_DSUBU = OPC_SPECIAL | 057, 307 OPC_SELEQZ = OPC_SPECIAL | 065, 308 OPC_SELNEZ = OPC_SPECIAL | 067, 309 OPC_DSLL = OPC_SPECIAL | 070, 310 OPC_DSRL = OPC_SPECIAL | 072, 311 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 312 OPC_DSRA = OPC_SPECIAL | 073, 313 OPC_DSLL32 = OPC_SPECIAL | 074, 314 OPC_DSRL32 = OPC_SPECIAL | 076, 315 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 316 OPC_DSRA32 = OPC_SPECIAL | 077, 317 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 318 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 319 320 OPC_REGIMM = 001 << 26, 321 OPC_BLTZ = OPC_REGIMM | (000 << 16), 322 OPC_BGEZ = OPC_REGIMM | (001 << 16), 323 324 OPC_SPECIAL2 = 034 << 26, 325 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 326 OPC_CLZ = OPC_SPECIAL2 | 040, 327 OPC_DCLZ = OPC_SPECIAL2 | 044, 328 329 OPC_SPECIAL3 = 037 << 26, 330 OPC_EXT = OPC_SPECIAL3 | 000, 331 OPC_DEXTM = OPC_SPECIAL3 | 001, 332 OPC_DEXTU = OPC_SPECIAL3 | 002, 333 OPC_DEXT = OPC_SPECIAL3 | 003, 334 OPC_INS = OPC_SPECIAL3 | 004, 335 OPC_DINSM = OPC_SPECIAL3 | 005, 336 OPC_DINSU = OPC_SPECIAL3 | 006, 337 OPC_DINS = OPC_SPECIAL3 | 007, 338 OPC_WSBH = OPC_SPECIAL3 | 00240, 339 OPC_DSBH = OPC_SPECIAL3 | 00244, 340 OPC_DSHD = OPC_SPECIAL3 | 00544, 341 OPC_SEB = OPC_SPECIAL3 | 02040, 342 OPC_SEH = OPC_SPECIAL3 | 03040, 343 344 /* MIPS r6 doesn't have JR, JALR should be used instead */ 345 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 346 347 /* 348 * MIPS r6 replaces MUL with an alternative encoding which is 349 * backwards-compatible at the assembly level. 350 */ 351 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 352 353 /* MIPS r6 introduced names for weaker variants of SYNC. These are 354 backward compatible to previous architecture revisions. */ 355 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 356 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 357 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 358 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 359 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 360 361 /* Aliases for convenience. */ 362 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 363 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 364} MIPSInsn; 365 366/* 367 * Type reg 368 */ 369static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 370 TCGReg rd, TCGReg rs, TCGReg rt) 371{ 372 int32_t inst; 373 374 inst = opc; 375 inst |= (rs & 0x1F) << 21; 376 inst |= (rt & 0x1F) << 16; 377 inst |= (rd & 0x1F) << 11; 378 tcg_out32(s, inst); 379} 380 381/* 382 * Type immediate 383 */ 384static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 385 TCGReg rt, TCGReg rs, TCGArg imm) 386{ 387 int32_t inst; 388 389 inst = opc; 390 inst |= (rs & 0x1F) << 21; 391 inst |= (rt & 0x1F) << 16; 392 inst |= (imm & 0xffff); 393 tcg_out32(s, inst); 394} 395 396/* 397 * Type bitfield 398 */ 399static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 400 TCGReg rs, int msb, int lsb) 401{ 402 int32_t inst; 403 404 inst = opc; 405 inst |= (rs & 0x1F) << 21; 406 inst |= (rt & 0x1F) << 16; 407 inst |= (msb & 0x1F) << 11; 408 inst |= (lsb & 0x1F) << 6; 409 tcg_out32(s, inst); 410} 411 412static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 413 MIPSInsn oph, TCGReg rt, TCGReg rs, 414 int msb, int lsb) 415{ 416 if (lsb >= 32) { 417 opc = oph; 418 msb -= 32; 419 lsb -= 32; 420 } else if (msb >= 32) { 421 opc = opm; 422 msb -= 32; 423 } 424 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 425} 426 427/* 428 * Type branch 429 */ 430static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 431{ 432 tcg_out_opc_imm(s, opc, rt, rs, 0); 433} 434 435/* 436 * Type sa 437 */ 438static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 439 TCGReg rd, TCGReg rt, TCGArg sa) 440{ 441 int32_t inst; 442 443 inst = opc; 444 inst |= (rt & 0x1F) << 16; 445 inst |= (rd & 0x1F) << 11; 446 inst |= (sa & 0x1F) << 6; 447 tcg_out32(s, inst); 448 449} 450 451static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 452 TCGReg rd, TCGReg rt, TCGArg sa) 453{ 454 int32_t inst; 455 456 inst = (sa & 32 ? opc2 : opc1); 457 inst |= (rt & 0x1F) << 16; 458 inst |= (rd & 0x1F) << 11; 459 inst |= (sa & 0x1F) << 6; 460 tcg_out32(s, inst); 461} 462 463/* 464 * Type jump. 465 * Returns true if the branch was in range and the insn was emitted. 466 */ 467static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 468{ 469 uintptr_t dest = (uintptr_t)target; 470 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 471 int32_t inst; 472 473 /* The pc-region branch happens within the 256MB region of 474 the delay slot (thus the +4). */ 475 if ((from ^ dest) & -(1 << 28)) { 476 return false; 477 } 478 tcg_debug_assert((dest & 3) == 0); 479 480 inst = opc; 481 inst |= (dest >> 2) & 0x3ffffff; 482 tcg_out32(s, inst); 483 return true; 484} 485 486static void tcg_out_nop(TCGContext *s) 487{ 488 tcg_out32(s, 0); 489} 490 491static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 492{ 493 memset(p, 0, count * sizeof(tcg_insn_unit)); 494} 495 496static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 497{ 498 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 499} 500 501static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 502{ 503 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 504} 505 506static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 507{ 508 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 509} 510 511static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 512{ 513 /* Simple reg-reg move, optimising out the 'do nothing' case */ 514 if (ret != arg) { 515 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 516 } 517 return true; 518} 519 520static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 521{ 522 if (arg == (int16_t)arg) { 523 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 524 return true; 525 } 526 if (arg == (uint16_t)arg) { 527 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 528 return true; 529 } 530 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 531 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 532 return true; 533 } 534 return false; 535} 536 537static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 538{ 539 /* 540 * All signed 32-bit constants are loadable with two immediates, 541 * and everything else requires more work. 542 */ 543 if (arg == (int32_t)arg) { 544 if (!tcg_out_movi_one(s, ret, arg)) { 545 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 546 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 547 } 548 return true; 549 } 550 return false; 551} 552 553static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 554 tcg_target_long arg, TCGReg tbreg) 555{ 556 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 557 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 558} 559 560static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 561 tcg_target_long arg, TCGReg tbreg) 562{ 563 tcg_target_long tmp; 564 int sh, lo; 565 566 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 567 arg = (int32_t)arg; 568 } 569 570 /* Load all 32-bit constants. */ 571 if (tcg_out_movi_two(s, ret, arg)) { 572 return; 573 } 574 assert(TCG_TARGET_REG_BITS == 64); 575 576 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 577 tmp = tcg_tbrel_diff(s, (void *)arg); 578 if (tmp == (int16_t)tmp) { 579 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 580 return; 581 } 582 if (tcg_out_movi_two(s, ret, tmp)) { 583 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 584 return; 585 } 586 587 /* 588 * Load bitmasks with a right-shift. This is good for things 589 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 590 * or similarly using LUI. For this to work, bit 31 must be set. 591 */ 592 if (arg > 0 && (int32_t)arg < 0) { 593 sh = clz64(arg); 594 if (tcg_out_movi_one(s, ret, arg << sh)) { 595 tcg_out_dsrl(s, ret, ret, sh); 596 return; 597 } 598 } 599 600 /* 601 * Load slightly larger constants using left-shift. 602 * Limit this sequence to 3 insns to avoid too much expansion. 603 */ 604 sh = ctz64(arg); 605 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 606 tcg_out_dsll(s, ret, ret, sh); 607 return; 608 } 609 610 /* 611 * Load slightly larger constants using left-shift and add/or. 612 * Prefer addi with a negative immediate when that would produce 613 * a larger shift. For this to work, bits 15 and 16 must be set. 614 */ 615 lo = arg & 0xffff; 616 if (lo) { 617 if ((arg & 0x18000) == 0x18000) { 618 lo = (int16_t)arg; 619 } 620 tmp = arg - lo; 621 sh = ctz64(tmp); 622 tmp >>= sh; 623 if (tcg_out_movi_one(s, ret, tmp)) { 624 tcg_out_dsll(s, ret, ret, sh); 625 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 626 return; 627 } 628 } 629 630 /* Otherwise, put 64-bit constants into the constant pool. */ 631 tcg_out_movi_pool(s, ret, arg, tbreg); 632} 633 634static void tcg_out_movi(TCGContext *s, TCGType type, 635 TCGReg ret, tcg_target_long arg) 636{ 637 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 638 tcg_out_movi_int(s, type, ret, arg, tbreg); 639} 640 641static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 642{ 643 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); 644 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 645} 646 647static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 648{ 649 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 650} 651 652static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 653{ 654 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); 655 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 656} 657 658static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 659{ 660 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 661} 662 663static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 664{ 665 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 666 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 667} 668 669static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 670{ 671 if (rd != rs) { 672 tcg_out_ext32s(s, rd, rs); 673 } 674} 675 676static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 tcg_out_ext32u(s, rd, rs); 679} 680 681static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 682{ 683 tcg_out_ext32s(s, rd, rs); 684} 685 686static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 687{ 688 return false; 689} 690 691static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 692 tcg_target_long imm) 693{ 694 /* This function is only used for passing structs by reference. */ 695 g_assert_not_reached(); 696} 697 698static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 699{ 700 /* ret and arg can't be register tmp0 */ 701 tcg_debug_assert(ret != TCG_TMP0); 702 tcg_debug_assert(arg != TCG_TMP0); 703 704 /* With arg = abcd: */ 705 if (use_mips32r2_instructions) { 706 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 707 if (flags & TCG_BSWAP_OS) { 708 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 709 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 710 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 711 } 712 return; 713 } 714 715 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 716 if (!(flags & TCG_BSWAP_IZ)) { 717 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 718 } 719 if (flags & TCG_BSWAP_OS) { 720 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 721 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 722 } else { 723 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 724 if (flags & TCG_BSWAP_OZ) { 725 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 726 } 727 } 728 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 729} 730 731static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 732{ 733 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 734 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 735 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 736 } 737} 738 739static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 740{ 741 if (use_mips32r2_instructions) { 742 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 743 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 744 if (flags & TCG_BSWAP_OZ) { 745 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 746 } 747 } else { 748 if (flags & TCG_BSWAP_OZ) { 749 tcg_out_bswap_subr(s, bswap32u_addr); 750 } else { 751 tcg_out_bswap_subr(s, bswap32_addr); 752 } 753 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 754 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 755 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 756 } 757} 758 759static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 760{ 761 if (use_mips32r2_instructions) { 762 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 763 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 764 } else { 765 tcg_out_bswap_subr(s, bswap64_addr); 766 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 767 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 768 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 769 } 770} 771 772static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 773{ 774 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 775 if (use_mips32r2_instructions) { 776 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 777 } else { 778 tcg_out_dsll(s, ret, arg, 32); 779 tcg_out_dsrl(s, ret, ret, 32); 780 } 781} 782 783static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 784 TCGReg addr, intptr_t ofs) 785{ 786 int16_t lo = ofs; 787 if (ofs != lo) { 788 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 789 if (addr != TCG_REG_ZERO) { 790 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 791 } 792 addr = TCG_TMP0; 793 } 794 tcg_out_opc_imm(s, opc, data, addr, lo); 795} 796 797static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 798 TCGReg arg1, intptr_t arg2) 799{ 800 MIPSInsn opc = OPC_LD; 801 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 802 opc = OPC_LW; 803 } 804 tcg_out_ldst(s, opc, arg, arg1, arg2); 805} 806 807static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 808 TCGReg arg1, intptr_t arg2) 809{ 810 MIPSInsn opc = OPC_SD; 811 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 812 opc = OPC_SW; 813 } 814 tcg_out_ldst(s, opc, arg, arg1, arg2); 815} 816 817static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 818 TCGReg base, intptr_t ofs) 819{ 820 if (val == 0) { 821 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 822 return true; 823 } 824 return false; 825} 826 827static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 828 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 829 bool cbh, bool is_sub) 830{ 831 TCGReg th = TCG_TMP1; 832 833 /* If we have a negative constant such that negating it would 834 make the high part zero, we can (usually) eliminate one insn. */ 835 if (cbl && cbh && bh == -1 && bl != 0) { 836 bl = -bl; 837 bh = 0; 838 is_sub = !is_sub; 839 } 840 841 /* By operating on the high part first, we get to use the final 842 carry operation to move back from the temporary. */ 843 if (!cbh) { 844 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 845 } else if (bh != 0 || ah == rl) { 846 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 847 } else { 848 th = ah; 849 } 850 851 /* Note that tcg optimization should eliminate the bl == 0 case. */ 852 if (is_sub) { 853 if (cbl) { 854 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 855 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 856 } else { 857 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 858 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 859 } 860 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 861 } else { 862 if (cbl) { 863 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 864 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 865 } else if (rl == al && rl == bl) { 866 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 867 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 868 } else { 869 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 870 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 871 } 872 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 873 } 874} 875 876/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 877#define MIPS_CMP_INV 1 878#define MIPS_CMP_SWAP 2 879 880static const uint8_t mips_cmp_map[16] = { 881 [TCG_COND_LT] = 0, 882 [TCG_COND_LTU] = 0, 883 [TCG_COND_GE] = MIPS_CMP_INV, 884 [TCG_COND_GEU] = MIPS_CMP_INV, 885 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 886 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 887 [TCG_COND_GT] = MIPS_CMP_SWAP, 888 [TCG_COND_GTU] = MIPS_CMP_SWAP, 889}; 890 891static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 892 TCGReg arg1, TCGReg arg2) 893{ 894 MIPSInsn s_opc = OPC_SLTU; 895 int cmp_map; 896 897 switch (cond) { 898 case TCG_COND_EQ: 899 if (arg2 != 0) { 900 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 901 arg1 = ret; 902 } 903 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 904 break; 905 906 case TCG_COND_NE: 907 if (arg2 != 0) { 908 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 909 arg1 = ret; 910 } 911 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 912 break; 913 914 case TCG_COND_LT: 915 case TCG_COND_GE: 916 case TCG_COND_LE: 917 case TCG_COND_GT: 918 s_opc = OPC_SLT; 919 /* FALLTHRU */ 920 921 case TCG_COND_LTU: 922 case TCG_COND_GEU: 923 case TCG_COND_LEU: 924 case TCG_COND_GTU: 925 cmp_map = mips_cmp_map[cond]; 926 if (cmp_map & MIPS_CMP_SWAP) { 927 TCGReg t = arg1; 928 arg1 = arg2; 929 arg2 = t; 930 } 931 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 932 if (cmp_map & MIPS_CMP_INV) { 933 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 934 } 935 break; 936 937 default: 938 g_assert_not_reached(); 939 break; 940 } 941} 942 943static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 944 TCGReg arg2, TCGLabel *l) 945{ 946 static const MIPSInsn b_zero[16] = { 947 [TCG_COND_LT] = OPC_BLTZ, 948 [TCG_COND_GT] = OPC_BGTZ, 949 [TCG_COND_LE] = OPC_BLEZ, 950 [TCG_COND_GE] = OPC_BGEZ, 951 }; 952 953 MIPSInsn s_opc = OPC_SLTU; 954 MIPSInsn b_opc; 955 int cmp_map; 956 957 switch (cond) { 958 case TCG_COND_EQ: 959 b_opc = OPC_BEQ; 960 break; 961 case TCG_COND_NE: 962 b_opc = OPC_BNE; 963 break; 964 965 case TCG_COND_LT: 966 case TCG_COND_GT: 967 case TCG_COND_LE: 968 case TCG_COND_GE: 969 if (arg2 == 0) { 970 b_opc = b_zero[cond]; 971 arg2 = arg1; 972 arg1 = 0; 973 break; 974 } 975 s_opc = OPC_SLT; 976 /* FALLTHRU */ 977 978 case TCG_COND_LTU: 979 case TCG_COND_GTU: 980 case TCG_COND_LEU: 981 case TCG_COND_GEU: 982 cmp_map = mips_cmp_map[cond]; 983 if (cmp_map & MIPS_CMP_SWAP) { 984 TCGReg t = arg1; 985 arg1 = arg2; 986 arg2 = t; 987 } 988 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 989 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 990 arg1 = TCG_TMP0; 991 arg2 = TCG_REG_ZERO; 992 break; 993 994 default: 995 g_assert_not_reached(); 996 break; 997 } 998 999 tcg_out_opc_br(s, b_opc, arg1, arg2); 1000 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 1001 tcg_out_nop(s); 1002} 1003 1004static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 1005 TCGReg al, TCGReg ah, 1006 TCGReg bl, TCGReg bh) 1007{ 1008 /* Merge highpart comparison into AH. */ 1009 if (bh != 0) { 1010 if (ah != 0) { 1011 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 1012 ah = tmp0; 1013 } else { 1014 ah = bh; 1015 } 1016 } 1017 /* Merge lowpart comparison into AL. */ 1018 if (bl != 0) { 1019 if (al != 0) { 1020 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 1021 al = tmp1; 1022 } else { 1023 al = bl; 1024 } 1025 } 1026 /* Merge high and low part comparisons into AL. */ 1027 if (ah != 0) { 1028 if (al != 0) { 1029 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 1030 al = tmp0; 1031 } else { 1032 al = ah; 1033 } 1034 } 1035 return al; 1036} 1037 1038static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1039 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1040{ 1041 TCGReg tmp0 = TCG_TMP0; 1042 TCGReg tmp1 = ret; 1043 1044 tcg_debug_assert(ret != TCG_TMP0); 1045 if (ret == ah || ret == bh) { 1046 tcg_debug_assert(ret != TCG_TMP1); 1047 tmp1 = TCG_TMP1; 1048 } 1049 1050 switch (cond) { 1051 case TCG_COND_EQ: 1052 case TCG_COND_NE: 1053 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 1054 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 1055 break; 1056 1057 default: 1058 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 1059 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 1060 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 1061 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 1062 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 1063 break; 1064 } 1065} 1066 1067static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1068 TCGReg bl, TCGReg bh, TCGLabel *l) 1069{ 1070 TCGCond b_cond = TCG_COND_NE; 1071 TCGReg tmp = TCG_TMP1; 1072 1073 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 1074 With setcond, we emit between 3 and 10 insns and only 1 branch, 1075 which ought to get better branch prediction. */ 1076 switch (cond) { 1077 case TCG_COND_EQ: 1078 case TCG_COND_NE: 1079 b_cond = cond; 1080 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 1081 break; 1082 1083 default: 1084 /* Minimize code size by preferring a compare not requiring INV. */ 1085 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1086 cond = tcg_invert_cond(cond); 1087 b_cond = TCG_COND_EQ; 1088 } 1089 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 1090 break; 1091 } 1092 1093 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 1094} 1095 1096static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1097 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1098{ 1099 bool eqz = false; 1100 1101 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1102 if (use_mips32r6_instructions && v1 == 0) { 1103 v1 = v2; 1104 v2 = 0; 1105 cond = tcg_invert_cond(cond); 1106 } 1107 1108 switch (cond) { 1109 case TCG_COND_EQ: 1110 eqz = true; 1111 /* FALLTHRU */ 1112 case TCG_COND_NE: 1113 if (c2 != 0) { 1114 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 1115 c1 = TCG_TMP0; 1116 } 1117 break; 1118 1119 default: 1120 /* Minimize code size by preferring a compare not requiring INV. */ 1121 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1122 cond = tcg_invert_cond(cond); 1123 eqz = true; 1124 } 1125 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 1126 c1 = TCG_TMP0; 1127 break; 1128 } 1129 1130 if (use_mips32r6_instructions) { 1131 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1132 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1133 1134 if (v2 != 0) { 1135 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1136 } 1137 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1138 if (v2 != 0) { 1139 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1140 } 1141 } else { 1142 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1143 1144 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1145 1146 /* This should be guaranteed via constraints */ 1147 tcg_debug_assert(v2 == ret); 1148 } 1149} 1150 1151static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1152{ 1153 /* 1154 * Note that __mips_abicalls requires the called function's address 1155 * to be loaded into $25 (t9), even if a direct branch is in range. 1156 * 1157 * For n64, always drop the pointer into the constant pool. 1158 * We can re-use helper addresses often and do not want any 1159 * of the longer sequences tcg_out_movi may try. 1160 */ 1161 if (sizeof(uintptr_t) == 8) { 1162 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1163 } else { 1164 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1165 } 1166 1167 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1168 if (tail) { 1169 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1170 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1171 } 1172 } else { 1173 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1174 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1175 } 1176 } 1177} 1178 1179static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1180 const TCGHelperInfo *info) 1181{ 1182 tcg_out_call_int(s, arg, false); 1183 tcg_out_nop(s); 1184} 1185 1186/* We have four temps, we might as well expose three of them. */ 1187static const TCGLdstHelperParam ldst_helper_param = { 1188 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1189}; 1190 1191static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1192{ 1193 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1194 MemOp opc = get_memop(l->oi); 1195 1196 /* resolve label address */ 1197 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1198 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1199 return false; 1200 } 1201 1202 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1203 1204 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1205 /* delay slot */ 1206 tcg_out_nop(s); 1207 1208 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1209 1210 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1211 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1212 return false; 1213 } 1214 1215 /* delay slot */ 1216 tcg_out_nop(s); 1217 return true; 1218} 1219 1220static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1221{ 1222 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1223 MemOp opc = get_memop(l->oi); 1224 1225 /* resolve label address */ 1226 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1227 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1228 return false; 1229 } 1230 1231 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1232 1233 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1234 /* delay slot */ 1235 tcg_out_nop(s); 1236 1237 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1238 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1239 return false; 1240 } 1241 1242 /* delay slot */ 1243 tcg_out_nop(s); 1244 return true; 1245} 1246 1247typedef struct { 1248 TCGReg base; 1249 TCGAtomAlign aa; 1250} HostAddress; 1251 1252bool tcg_target_has_memory_bswap(MemOp memop) 1253{ 1254 return false; 1255} 1256 1257/* 1258 * For softmmu, perform the TLB load and compare. 1259 * For useronly, perform any required alignment tests. 1260 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1261 * is required and fill in @h with the host address for the fast path. 1262 */ 1263static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1264 TCGReg addrlo, TCGReg addrhi, 1265 MemOpIdx oi, bool is_ld) 1266{ 1267 TCGType addr_type = s->addr_type; 1268 TCGLabelQemuLdst *ldst = NULL; 1269 MemOp opc = get_memop(oi); 1270 MemOp a_bits; 1271 unsigned s_bits = opc & MO_SIZE; 1272 unsigned a_mask; 1273 TCGReg base; 1274 1275 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1276 a_bits = h->aa.align; 1277 a_mask = (1 << a_bits) - 1; 1278 1279#ifdef CONFIG_SOFTMMU 1280 unsigned s_mask = (1 << s_bits) - 1; 1281 int mem_index = get_mmuidx(oi); 1282 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1283 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1284 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1285 int add_off = offsetof(CPUTLBEntry, addend); 1286 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1287 : offsetof(CPUTLBEntry, addr_write); 1288 1289 ldst = new_ldst_label(s); 1290 ldst->is_ld = is_ld; 1291 ldst->oi = oi; 1292 ldst->addrlo_reg = addrlo; 1293 ldst->addrhi_reg = addrhi; 1294 1295 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1296 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1297 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1298 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1299 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1300 1301 /* Extract the TLB index from the address into TMP3. */ 1302 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1303 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, 1304 s->page_bits - CPU_TLB_ENTRY_BITS); 1305 } else { 1306 tcg_out_dsrl(s, TCG_TMP3, addrlo, 1307 s->page_bits - CPU_TLB_ENTRY_BITS); 1308 } 1309 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1310 1311 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1312 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1313 1314 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { 1315 /* Load the tlb comparator. */ 1316 tcg_out_ld(s, addr_type, TCG_TMP0, TCG_TMP3, cmp_off); 1317 /* Load the tlb addend for the fast path. */ 1318 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1319 } else { 1320 /* Load the low half of the tlb comparator. */ 1321 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1322 } 1323 1324 /* 1325 * Mask the page bits, keeping the alignment bits to compare against. 1326 * For unaligned accesses, compare against the end of the access to 1327 * verify that it does not cross a page boundary. 1328 */ 1329 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1330 if (a_mask < s_mask) { 1331 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1332 tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP2, addrlo, s_mask - a_mask); 1333 } else { 1334 tcg_out_opc_imm(s, OPC_DADDIU, TCG_TMP2, addrlo, s_mask - a_mask); 1335 } 1336 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1337 } else { 1338 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); 1339 } 1340 1341 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1342 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1343 tcg_out_ext32u(s, TCG_TMP2, addrlo); 1344 addrlo = TCG_TMP2; 1345 } 1346 1347 ldst->label_ptr[0] = s->code_ptr; 1348 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1349 1350 /* Load and test the high half tlb comparator. */ 1351 if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { 1352 /* delay slot */ 1353 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1354 1355 /* Load the tlb addend for the fast path. */ 1356 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1357 1358 ldst->label_ptr[1] = s->code_ptr; 1359 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); 1360 } 1361 1362 /* delay slot */ 1363 base = TCG_TMP3; 1364 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); 1365#else 1366 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1367 ldst = new_ldst_label(s); 1368 1369 ldst->is_ld = is_ld; 1370 ldst->oi = oi; 1371 ldst->addrlo_reg = addrlo; 1372 ldst->addrhi_reg = addrhi; 1373 1374 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1375 tcg_debug_assert(a_bits < 16); 1376 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); 1377 1378 ldst->label_ptr[0] = s->code_ptr; 1379 if (use_mips32r6_instructions) { 1380 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1381 } else { 1382 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1383 tcg_out_nop(s); 1384 } 1385 } 1386 1387 base = addrlo; 1388 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1389 tcg_out_ext32u(s, TCG_REG_A0, base); 1390 base = TCG_REG_A0; 1391 } 1392 if (guest_base) { 1393 if (guest_base == (int16_t)guest_base) { 1394 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1395 } else { 1396 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1397 TCG_GUEST_BASE_REG); 1398 } 1399 base = TCG_REG_A0; 1400 } 1401#endif 1402 1403 h->base = base; 1404 return ldst; 1405} 1406 1407static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1408 TCGReg base, MemOp opc, TCGType type) 1409{ 1410 switch (opc & MO_SSIZE) { 1411 case MO_UB: 1412 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1413 break; 1414 case MO_SB: 1415 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1416 break; 1417 case MO_UW: 1418 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1419 break; 1420 case MO_SW: 1421 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1422 break; 1423 case MO_UL: 1424 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1425 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1426 break; 1427 } 1428 /* FALLTHRU */ 1429 case MO_SL: 1430 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1431 break; 1432 case MO_UQ: 1433 /* Prefer to load from offset 0 first, but allow for overlap. */ 1434 if (TCG_TARGET_REG_BITS == 64) { 1435 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1436 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1437 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1438 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1439 } else { 1440 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1441 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1442 } 1443 break; 1444 default: 1445 g_assert_not_reached(); 1446 } 1447} 1448 1449static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1450 TCGReg base, MemOp opc, TCGType type) 1451{ 1452 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1453 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1454 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1455 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1456 bool sgn = opc & MO_SIGN; 1457 1458 switch (opc & MO_SIZE) { 1459 case MO_16: 1460 if (HOST_BIG_ENDIAN) { 1461 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1462 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1463 if (use_mips32r2_instructions) { 1464 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1465 } else { 1466 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1467 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1468 } 1469 } else if (use_mips32r2_instructions && lo != base) { 1470 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1471 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1472 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1473 } else { 1474 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1475 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1476 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1477 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1478 } 1479 break; 1480 1481 case MO_32: 1482 tcg_out_opc_imm(s, lw1, lo, base, 0); 1483 tcg_out_opc_imm(s, lw2, lo, base, 3); 1484 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1485 tcg_out_ext32u(s, lo, lo); 1486 } 1487 break; 1488 1489 case MO_64: 1490 if (TCG_TARGET_REG_BITS == 64) { 1491 tcg_out_opc_imm(s, ld1, lo, base, 0); 1492 tcg_out_opc_imm(s, ld2, lo, base, 7); 1493 } else { 1494 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1495 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1496 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1497 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1498 } 1499 break; 1500 1501 default: 1502 g_assert_not_reached(); 1503 } 1504} 1505 1506static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1507 TCGReg addrlo, TCGReg addrhi, 1508 MemOpIdx oi, TCGType data_type) 1509{ 1510 MemOp opc = get_memop(oi); 1511 TCGLabelQemuLdst *ldst; 1512 HostAddress h; 1513 1514 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 1515 1516 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1517 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1518 } else { 1519 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1520 } 1521 1522 if (ldst) { 1523 ldst->type = data_type; 1524 ldst->datalo_reg = datalo; 1525 ldst->datahi_reg = datahi; 1526 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1527 } 1528} 1529 1530static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1531 TCGReg base, MemOp opc) 1532{ 1533 switch (opc & MO_SIZE) { 1534 case MO_8: 1535 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1536 break; 1537 case MO_16: 1538 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1539 break; 1540 case MO_32: 1541 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1542 break; 1543 case MO_64: 1544 if (TCG_TARGET_REG_BITS == 64) { 1545 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1546 } else { 1547 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1548 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1549 } 1550 break; 1551 default: 1552 g_assert_not_reached(); 1553 } 1554} 1555 1556static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1557 TCGReg base, MemOp opc) 1558{ 1559 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1560 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1561 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1562 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1563 1564 switch (opc & MO_SIZE) { 1565 case MO_16: 1566 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1567 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1568 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1569 break; 1570 1571 case MO_32: 1572 tcg_out_opc_imm(s, sw1, lo, base, 0); 1573 tcg_out_opc_imm(s, sw2, lo, base, 3); 1574 break; 1575 1576 case MO_64: 1577 if (TCG_TARGET_REG_BITS == 64) { 1578 tcg_out_opc_imm(s, sd1, lo, base, 0); 1579 tcg_out_opc_imm(s, sd2, lo, base, 7); 1580 } else { 1581 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1582 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1583 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1584 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1585 } 1586 break; 1587 1588 default: 1589 g_assert_not_reached(); 1590 } 1591} 1592 1593static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1594 TCGReg addrlo, TCGReg addrhi, 1595 MemOpIdx oi, TCGType data_type) 1596{ 1597 MemOp opc = get_memop(oi); 1598 TCGLabelQemuLdst *ldst; 1599 HostAddress h; 1600 1601 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 1602 1603 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1604 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1605 } else { 1606 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1607 } 1608 1609 if (ldst) { 1610 ldst->type = data_type; 1611 ldst->datalo_reg = datalo; 1612 ldst->datahi_reg = datahi; 1613 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1614 } 1615} 1616 1617static void tcg_out_mb(TCGContext *s, TCGArg a0) 1618{ 1619 static const MIPSInsn sync[] = { 1620 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1621 as the former is an ordering barrier and the latter 1622 is a completion barrier. */ 1623 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1624 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1625 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1626 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1627 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1628 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1629 }; 1630 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1631} 1632 1633static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1634 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1635{ 1636 if (use_mips32r6_instructions) { 1637 if (a2 == width) { 1638 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1639 } else { 1640 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1641 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1642 } 1643 } else { 1644 if (a2 == width) { 1645 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1646 } else if (a0 == a2) { 1647 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1648 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1649 } else if (a0 != a1) { 1650 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1651 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1652 } else { 1653 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1654 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1655 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1656 } 1657 } 1658} 1659 1660static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1661{ 1662 TCGReg base = TCG_REG_ZERO; 1663 int16_t lo = 0; 1664 1665 if (a0) { 1666 intptr_t ofs; 1667 if (TCG_TARGET_REG_BITS == 64) { 1668 ofs = tcg_tbrel_diff(s, (void *)a0); 1669 lo = ofs; 1670 if (ofs == lo) { 1671 base = TCG_REG_TB; 1672 } else { 1673 base = TCG_REG_V0; 1674 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1675 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1676 } 1677 } else { 1678 ofs = a0; 1679 lo = ofs; 1680 base = TCG_REG_V0; 1681 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1682 } 1683 } 1684 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1685 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1686 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1687 } 1688 /* delay slot */ 1689 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1690} 1691 1692static void tcg_out_goto_tb(TCGContext *s, int which) 1693{ 1694 intptr_t ofs = get_jmp_target_addr(s, which); 1695 TCGReg base, dest; 1696 1697 /* indirect jump method */ 1698 if (TCG_TARGET_REG_BITS == 64) { 1699 dest = TCG_REG_TB; 1700 base = TCG_REG_TB; 1701 ofs = tcg_tbrel_diff(s, (void *)ofs); 1702 } else { 1703 dest = TCG_TMP0; 1704 base = TCG_REG_ZERO; 1705 } 1706 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1707 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1708 /* delay slot */ 1709 tcg_out_nop(s); 1710 1711 set_jmp_reset_offset(s, which); 1712 if (TCG_TARGET_REG_BITS == 64) { 1713 /* For the unlinked case, need to reset TCG_REG_TB. */ 1714 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1715 -tcg_current_code_size(s)); 1716 } 1717} 1718 1719void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1720 uintptr_t jmp_rx, uintptr_t jmp_rw) 1721{ 1722 /* Always indirect, nothing to do */ 1723} 1724 1725static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1726 const TCGArg args[TCG_MAX_OP_ARGS], 1727 const int const_args[TCG_MAX_OP_ARGS]) 1728{ 1729 MIPSInsn i1, i2; 1730 TCGArg a0, a1, a2; 1731 int c2; 1732 1733 /* 1734 * Note that many operands use the constraint set "rZ". 1735 * We make use of the fact that 0 is the ZERO register, 1736 * and hence such cases need not check for const_args. 1737 */ 1738 a0 = args[0]; 1739 a1 = args[1]; 1740 a2 = args[2]; 1741 c2 = const_args[2]; 1742 1743 switch (opc) { 1744 case INDEX_op_goto_ptr: 1745 /* jmp to the given host address (could be epilogue) */ 1746 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1747 if (TCG_TARGET_REG_BITS == 64) { 1748 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 1749 } else { 1750 tcg_out_nop(s); 1751 } 1752 break; 1753 case INDEX_op_br: 1754 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1755 arg_label(a0)); 1756 break; 1757 1758 case INDEX_op_ld8u_i32: 1759 case INDEX_op_ld8u_i64: 1760 i1 = OPC_LBU; 1761 goto do_ldst; 1762 case INDEX_op_ld8s_i32: 1763 case INDEX_op_ld8s_i64: 1764 i1 = OPC_LB; 1765 goto do_ldst; 1766 case INDEX_op_ld16u_i32: 1767 case INDEX_op_ld16u_i64: 1768 i1 = OPC_LHU; 1769 goto do_ldst; 1770 case INDEX_op_ld16s_i32: 1771 case INDEX_op_ld16s_i64: 1772 i1 = OPC_LH; 1773 goto do_ldst; 1774 case INDEX_op_ld_i32: 1775 case INDEX_op_ld32s_i64: 1776 i1 = OPC_LW; 1777 goto do_ldst; 1778 case INDEX_op_ld32u_i64: 1779 i1 = OPC_LWU; 1780 goto do_ldst; 1781 case INDEX_op_ld_i64: 1782 i1 = OPC_LD; 1783 goto do_ldst; 1784 case INDEX_op_st8_i32: 1785 case INDEX_op_st8_i64: 1786 i1 = OPC_SB; 1787 goto do_ldst; 1788 case INDEX_op_st16_i32: 1789 case INDEX_op_st16_i64: 1790 i1 = OPC_SH; 1791 goto do_ldst; 1792 case INDEX_op_st_i32: 1793 case INDEX_op_st32_i64: 1794 i1 = OPC_SW; 1795 goto do_ldst; 1796 case INDEX_op_st_i64: 1797 i1 = OPC_SD; 1798 do_ldst: 1799 tcg_out_ldst(s, i1, a0, a1, a2); 1800 break; 1801 1802 case INDEX_op_add_i32: 1803 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1804 goto do_binary; 1805 case INDEX_op_add_i64: 1806 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1807 goto do_binary; 1808 case INDEX_op_or_i32: 1809 case INDEX_op_or_i64: 1810 i1 = OPC_OR, i2 = OPC_ORI; 1811 goto do_binary; 1812 case INDEX_op_xor_i32: 1813 case INDEX_op_xor_i64: 1814 i1 = OPC_XOR, i2 = OPC_XORI; 1815 do_binary: 1816 if (c2) { 1817 tcg_out_opc_imm(s, i2, a0, a1, a2); 1818 break; 1819 } 1820 do_binaryv: 1821 tcg_out_opc_reg(s, i1, a0, a1, a2); 1822 break; 1823 1824 case INDEX_op_sub_i32: 1825 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1826 goto do_subtract; 1827 case INDEX_op_sub_i64: 1828 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1829 do_subtract: 1830 if (c2) { 1831 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1832 break; 1833 } 1834 goto do_binaryv; 1835 case INDEX_op_and_i32: 1836 if (c2 && a2 != (uint16_t)a2) { 1837 int msb = ctz32(~a2) - 1; 1838 tcg_debug_assert(use_mips32r2_instructions); 1839 tcg_debug_assert(is_p2m1(a2)); 1840 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1841 break; 1842 } 1843 i1 = OPC_AND, i2 = OPC_ANDI; 1844 goto do_binary; 1845 case INDEX_op_and_i64: 1846 if (c2 && a2 != (uint16_t)a2) { 1847 int msb = ctz64(~a2) - 1; 1848 tcg_debug_assert(use_mips32r2_instructions); 1849 tcg_debug_assert(is_p2m1(a2)); 1850 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1851 break; 1852 } 1853 i1 = OPC_AND, i2 = OPC_ANDI; 1854 goto do_binary; 1855 case INDEX_op_nor_i32: 1856 case INDEX_op_nor_i64: 1857 i1 = OPC_NOR; 1858 goto do_binaryv; 1859 1860 case INDEX_op_mul_i32: 1861 if (use_mips32_instructions) { 1862 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1863 break; 1864 } 1865 i1 = OPC_MULT, i2 = OPC_MFLO; 1866 goto do_hilo1; 1867 case INDEX_op_mulsh_i32: 1868 if (use_mips32r6_instructions) { 1869 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1870 break; 1871 } 1872 i1 = OPC_MULT, i2 = OPC_MFHI; 1873 goto do_hilo1; 1874 case INDEX_op_muluh_i32: 1875 if (use_mips32r6_instructions) { 1876 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1877 break; 1878 } 1879 i1 = OPC_MULTU, i2 = OPC_MFHI; 1880 goto do_hilo1; 1881 case INDEX_op_div_i32: 1882 if (use_mips32r6_instructions) { 1883 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1884 break; 1885 } 1886 i1 = OPC_DIV, i2 = OPC_MFLO; 1887 goto do_hilo1; 1888 case INDEX_op_divu_i32: 1889 if (use_mips32r6_instructions) { 1890 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1891 break; 1892 } 1893 i1 = OPC_DIVU, i2 = OPC_MFLO; 1894 goto do_hilo1; 1895 case INDEX_op_rem_i32: 1896 if (use_mips32r6_instructions) { 1897 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1898 break; 1899 } 1900 i1 = OPC_DIV, i2 = OPC_MFHI; 1901 goto do_hilo1; 1902 case INDEX_op_remu_i32: 1903 if (use_mips32r6_instructions) { 1904 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1905 break; 1906 } 1907 i1 = OPC_DIVU, i2 = OPC_MFHI; 1908 goto do_hilo1; 1909 case INDEX_op_mul_i64: 1910 if (use_mips32r6_instructions) { 1911 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1912 break; 1913 } 1914 i1 = OPC_DMULT, i2 = OPC_MFLO; 1915 goto do_hilo1; 1916 case INDEX_op_mulsh_i64: 1917 if (use_mips32r6_instructions) { 1918 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1919 break; 1920 } 1921 i1 = OPC_DMULT, i2 = OPC_MFHI; 1922 goto do_hilo1; 1923 case INDEX_op_muluh_i64: 1924 if (use_mips32r6_instructions) { 1925 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1926 break; 1927 } 1928 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1929 goto do_hilo1; 1930 case INDEX_op_div_i64: 1931 if (use_mips32r6_instructions) { 1932 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1933 break; 1934 } 1935 i1 = OPC_DDIV, i2 = OPC_MFLO; 1936 goto do_hilo1; 1937 case INDEX_op_divu_i64: 1938 if (use_mips32r6_instructions) { 1939 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1940 break; 1941 } 1942 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1943 goto do_hilo1; 1944 case INDEX_op_rem_i64: 1945 if (use_mips32r6_instructions) { 1946 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1947 break; 1948 } 1949 i1 = OPC_DDIV, i2 = OPC_MFHI; 1950 goto do_hilo1; 1951 case INDEX_op_remu_i64: 1952 if (use_mips32r6_instructions) { 1953 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1954 break; 1955 } 1956 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1957 do_hilo1: 1958 tcg_out_opc_reg(s, i1, 0, a1, a2); 1959 tcg_out_opc_reg(s, i2, a0, 0, 0); 1960 break; 1961 1962 case INDEX_op_muls2_i32: 1963 i1 = OPC_MULT; 1964 goto do_hilo2; 1965 case INDEX_op_mulu2_i32: 1966 i1 = OPC_MULTU; 1967 goto do_hilo2; 1968 case INDEX_op_muls2_i64: 1969 i1 = OPC_DMULT; 1970 goto do_hilo2; 1971 case INDEX_op_mulu2_i64: 1972 i1 = OPC_DMULTU; 1973 do_hilo2: 1974 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1975 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1976 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1977 break; 1978 1979 case INDEX_op_not_i32: 1980 case INDEX_op_not_i64: 1981 i1 = OPC_NOR; 1982 goto do_unary; 1983 do_unary: 1984 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1985 break; 1986 1987 case INDEX_op_bswap16_i32: 1988 case INDEX_op_bswap16_i64: 1989 tcg_out_bswap16(s, a0, a1, a2); 1990 break; 1991 case INDEX_op_bswap32_i32: 1992 tcg_out_bswap32(s, a0, a1, 0); 1993 break; 1994 case INDEX_op_bswap32_i64: 1995 tcg_out_bswap32(s, a0, a1, a2); 1996 break; 1997 case INDEX_op_bswap64_i64: 1998 tcg_out_bswap64(s, a0, a1); 1999 break; 2000 case INDEX_op_extrh_i64_i32: 2001 tcg_out_dsra(s, a0, a1, 32); 2002 break; 2003 2004 case INDEX_op_sar_i32: 2005 i1 = OPC_SRAV, i2 = OPC_SRA; 2006 goto do_shift; 2007 case INDEX_op_shl_i32: 2008 i1 = OPC_SLLV, i2 = OPC_SLL; 2009 goto do_shift; 2010 case INDEX_op_shr_i32: 2011 i1 = OPC_SRLV, i2 = OPC_SRL; 2012 goto do_shift; 2013 case INDEX_op_rotr_i32: 2014 i1 = OPC_ROTRV, i2 = OPC_ROTR; 2015 do_shift: 2016 if (c2) { 2017 tcg_out_opc_sa(s, i2, a0, a1, a2); 2018 break; 2019 } 2020 do_shiftv: 2021 tcg_out_opc_reg(s, i1, a0, a2, a1); 2022 break; 2023 case INDEX_op_rotl_i32: 2024 if (c2) { 2025 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 2026 } else { 2027 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2028 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 2029 } 2030 break; 2031 case INDEX_op_sar_i64: 2032 if (c2) { 2033 tcg_out_dsra(s, a0, a1, a2); 2034 break; 2035 } 2036 i1 = OPC_DSRAV; 2037 goto do_shiftv; 2038 case INDEX_op_shl_i64: 2039 if (c2) { 2040 tcg_out_dsll(s, a0, a1, a2); 2041 break; 2042 } 2043 i1 = OPC_DSLLV; 2044 goto do_shiftv; 2045 case INDEX_op_shr_i64: 2046 if (c2) { 2047 tcg_out_dsrl(s, a0, a1, a2); 2048 break; 2049 } 2050 i1 = OPC_DSRLV; 2051 goto do_shiftv; 2052 case INDEX_op_rotr_i64: 2053 if (c2) { 2054 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2055 break; 2056 } 2057 i1 = OPC_DROTRV; 2058 goto do_shiftv; 2059 case INDEX_op_rotl_i64: 2060 if (c2) { 2061 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2062 } else { 2063 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2064 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2065 } 2066 break; 2067 2068 case INDEX_op_clz_i32: 2069 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2070 break; 2071 case INDEX_op_clz_i64: 2072 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2073 break; 2074 2075 case INDEX_op_deposit_i32: 2076 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2077 break; 2078 case INDEX_op_deposit_i64: 2079 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2080 args[3] + args[4] - 1, args[3]); 2081 break; 2082 case INDEX_op_extract_i32: 2083 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2084 break; 2085 case INDEX_op_extract_i64: 2086 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2087 args[3] - 1, a2); 2088 break; 2089 2090 case INDEX_op_brcond_i32: 2091 case INDEX_op_brcond_i64: 2092 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2093 break; 2094 case INDEX_op_brcond2_i32: 2095 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2096 break; 2097 2098 case INDEX_op_movcond_i32: 2099 case INDEX_op_movcond_i64: 2100 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2101 break; 2102 2103 case INDEX_op_setcond_i32: 2104 case INDEX_op_setcond_i64: 2105 tcg_out_setcond(s, args[3], a0, a1, a2); 2106 break; 2107 case INDEX_op_setcond2_i32: 2108 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2109 break; 2110 2111 case INDEX_op_qemu_ld_a64_i32: 2112 if (TCG_TARGET_REG_BITS == 32) { 2113 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 2114 break; 2115 } 2116 /* fall through */ 2117 case INDEX_op_qemu_ld_a32_i32: 2118 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 2119 break; 2120 case INDEX_op_qemu_ld_a32_i64: 2121 if (TCG_TARGET_REG_BITS == 64) { 2122 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2123 } else { 2124 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 2125 } 2126 break; 2127 case INDEX_op_qemu_ld_a64_i64: 2128 if (TCG_TARGET_REG_BITS == 64) { 2129 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2130 } else { 2131 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2132 } 2133 break; 2134 2135 case INDEX_op_qemu_st_a64_i32: 2136 if (TCG_TARGET_REG_BITS == 32) { 2137 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 2138 break; 2139 } 2140 /* fall through */ 2141 case INDEX_op_qemu_st_a32_i32: 2142 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 2143 break; 2144 case INDEX_op_qemu_st_a32_i64: 2145 if (TCG_TARGET_REG_BITS == 64) { 2146 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2147 } else { 2148 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 2149 } 2150 break; 2151 case INDEX_op_qemu_st_a64_i64: 2152 if (TCG_TARGET_REG_BITS == 64) { 2153 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2154 } else { 2155 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2156 } 2157 break; 2158 2159 case INDEX_op_add2_i32: 2160 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2161 const_args[4], const_args[5], false); 2162 break; 2163 case INDEX_op_sub2_i32: 2164 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2165 const_args[4], const_args[5], true); 2166 break; 2167 2168 case INDEX_op_mb: 2169 tcg_out_mb(s, a0); 2170 break; 2171 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2172 case INDEX_op_mov_i64: 2173 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2174 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2175 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2176 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2177 case INDEX_op_ext8s_i64: 2178 case INDEX_op_ext8u_i32: 2179 case INDEX_op_ext8u_i64: 2180 case INDEX_op_ext16s_i32: 2181 case INDEX_op_ext16s_i64: 2182 case INDEX_op_ext32s_i64: 2183 case INDEX_op_ext32u_i64: 2184 case INDEX_op_ext_i32_i64: 2185 case INDEX_op_extu_i32_i64: 2186 case INDEX_op_extrl_i64_i32: 2187 default: 2188 g_assert_not_reached(); 2189 } 2190} 2191 2192static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2193{ 2194 switch (op) { 2195 case INDEX_op_goto_ptr: 2196 return C_O0_I1(r); 2197 2198 case INDEX_op_ld8u_i32: 2199 case INDEX_op_ld8s_i32: 2200 case INDEX_op_ld16u_i32: 2201 case INDEX_op_ld16s_i32: 2202 case INDEX_op_ld_i32: 2203 case INDEX_op_not_i32: 2204 case INDEX_op_bswap16_i32: 2205 case INDEX_op_bswap32_i32: 2206 case INDEX_op_ext8s_i32: 2207 case INDEX_op_ext16s_i32: 2208 case INDEX_op_extract_i32: 2209 case INDEX_op_ld8u_i64: 2210 case INDEX_op_ld8s_i64: 2211 case INDEX_op_ld16u_i64: 2212 case INDEX_op_ld16s_i64: 2213 case INDEX_op_ld32s_i64: 2214 case INDEX_op_ld32u_i64: 2215 case INDEX_op_ld_i64: 2216 case INDEX_op_not_i64: 2217 case INDEX_op_bswap16_i64: 2218 case INDEX_op_bswap32_i64: 2219 case INDEX_op_bswap64_i64: 2220 case INDEX_op_ext8s_i64: 2221 case INDEX_op_ext16s_i64: 2222 case INDEX_op_ext32s_i64: 2223 case INDEX_op_ext32u_i64: 2224 case INDEX_op_ext_i32_i64: 2225 case INDEX_op_extu_i32_i64: 2226 case INDEX_op_extrl_i64_i32: 2227 case INDEX_op_extrh_i64_i32: 2228 case INDEX_op_extract_i64: 2229 return C_O1_I1(r, r); 2230 2231 case INDEX_op_st8_i32: 2232 case INDEX_op_st16_i32: 2233 case INDEX_op_st_i32: 2234 case INDEX_op_st8_i64: 2235 case INDEX_op_st16_i64: 2236 case INDEX_op_st32_i64: 2237 case INDEX_op_st_i64: 2238 return C_O0_I2(rZ, r); 2239 2240 case INDEX_op_add_i32: 2241 case INDEX_op_add_i64: 2242 return C_O1_I2(r, r, rJ); 2243 case INDEX_op_sub_i32: 2244 case INDEX_op_sub_i64: 2245 return C_O1_I2(r, rZ, rN); 2246 case INDEX_op_mul_i32: 2247 case INDEX_op_mulsh_i32: 2248 case INDEX_op_muluh_i32: 2249 case INDEX_op_div_i32: 2250 case INDEX_op_divu_i32: 2251 case INDEX_op_rem_i32: 2252 case INDEX_op_remu_i32: 2253 case INDEX_op_nor_i32: 2254 case INDEX_op_setcond_i32: 2255 case INDEX_op_mul_i64: 2256 case INDEX_op_mulsh_i64: 2257 case INDEX_op_muluh_i64: 2258 case INDEX_op_div_i64: 2259 case INDEX_op_divu_i64: 2260 case INDEX_op_rem_i64: 2261 case INDEX_op_remu_i64: 2262 case INDEX_op_nor_i64: 2263 case INDEX_op_setcond_i64: 2264 return C_O1_I2(r, rZ, rZ); 2265 case INDEX_op_muls2_i32: 2266 case INDEX_op_mulu2_i32: 2267 case INDEX_op_muls2_i64: 2268 case INDEX_op_mulu2_i64: 2269 return C_O2_I2(r, r, r, r); 2270 case INDEX_op_and_i32: 2271 case INDEX_op_and_i64: 2272 return C_O1_I2(r, r, rIK); 2273 case INDEX_op_or_i32: 2274 case INDEX_op_xor_i32: 2275 case INDEX_op_or_i64: 2276 case INDEX_op_xor_i64: 2277 return C_O1_I2(r, r, rI); 2278 case INDEX_op_shl_i32: 2279 case INDEX_op_shr_i32: 2280 case INDEX_op_sar_i32: 2281 case INDEX_op_rotr_i32: 2282 case INDEX_op_rotl_i32: 2283 case INDEX_op_shl_i64: 2284 case INDEX_op_shr_i64: 2285 case INDEX_op_sar_i64: 2286 case INDEX_op_rotr_i64: 2287 case INDEX_op_rotl_i64: 2288 return C_O1_I2(r, r, ri); 2289 case INDEX_op_clz_i32: 2290 case INDEX_op_clz_i64: 2291 return C_O1_I2(r, r, rWZ); 2292 2293 case INDEX_op_deposit_i32: 2294 case INDEX_op_deposit_i64: 2295 return C_O1_I2(r, 0, rZ); 2296 case INDEX_op_brcond_i32: 2297 case INDEX_op_brcond_i64: 2298 return C_O0_I2(rZ, rZ); 2299 case INDEX_op_movcond_i32: 2300 case INDEX_op_movcond_i64: 2301 return (use_mips32r6_instructions 2302 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2303 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2304 case INDEX_op_add2_i32: 2305 case INDEX_op_sub2_i32: 2306 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2307 case INDEX_op_setcond2_i32: 2308 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2309 case INDEX_op_brcond2_i32: 2310 return C_O0_I4(rZ, rZ, rZ, rZ); 2311 2312 case INDEX_op_qemu_ld_a32_i32: 2313 return C_O1_I1(r, r); 2314 case INDEX_op_qemu_ld_a64_i32: 2315 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r); 2316 case INDEX_op_qemu_st_a32_i32: 2317 return C_O0_I2(rZ, r); 2318 case INDEX_op_qemu_st_a64_i32: 2319 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r); 2320 case INDEX_op_qemu_ld_a32_i64: 2321 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2322 case INDEX_op_qemu_ld_a64_i64: 2323 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r); 2324 case INDEX_op_qemu_st_a32_i64: 2325 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r); 2326 case INDEX_op_qemu_st_a64_i64: 2327 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) 2328 : C_O0_I4(rZ, rZ, r, r)); 2329 2330 default: 2331 g_assert_not_reached(); 2332 } 2333} 2334 2335static const int tcg_target_callee_save_regs[] = { 2336 TCG_REG_S0, 2337 TCG_REG_S1, 2338 TCG_REG_S2, 2339 TCG_REG_S3, 2340 TCG_REG_S4, 2341 TCG_REG_S5, 2342 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2343 TCG_REG_S7, /* used for guest_base */ 2344 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2345 TCG_REG_RA, /* should be last for ABI compliance */ 2346}; 2347 2348/* The Linux kernel doesn't provide any information about the available 2349 instruction set. Probe it using a signal handler. */ 2350 2351 2352#ifndef use_movnz_instructions 2353bool use_movnz_instructions = false; 2354#endif 2355 2356#ifndef use_mips32_instructions 2357bool use_mips32_instructions = false; 2358#endif 2359 2360#ifndef use_mips32r2_instructions 2361bool use_mips32r2_instructions = false; 2362#endif 2363 2364static volatile sig_atomic_t got_sigill; 2365 2366static void sigill_handler(int signo, siginfo_t *si, void *data) 2367{ 2368 /* Skip the faulty instruction */ 2369 ucontext_t *uc = (ucontext_t *)data; 2370 uc->uc_mcontext.pc += 4; 2371 2372 got_sigill = 1; 2373} 2374 2375static void tcg_target_detect_isa(void) 2376{ 2377 struct sigaction sa_old, sa_new; 2378 2379 memset(&sa_new, 0, sizeof(sa_new)); 2380 sa_new.sa_flags = SA_SIGINFO; 2381 sa_new.sa_sigaction = sigill_handler; 2382 sigaction(SIGILL, &sa_new, &sa_old); 2383 2384 /* Probe for movn/movz, necessary to implement movcond. */ 2385#ifndef use_movnz_instructions 2386 got_sigill = 0; 2387 asm volatile(".set push\n" 2388 ".set mips32\n" 2389 "movn $zero, $zero, $zero\n" 2390 "movz $zero, $zero, $zero\n" 2391 ".set pop\n" 2392 : : : ); 2393 use_movnz_instructions = !got_sigill; 2394#endif 2395 2396 /* Probe for MIPS32 instructions. As no subsetting is allowed 2397 by the specification, it is only necessary to probe for one 2398 of the instructions. */ 2399#ifndef use_mips32_instructions 2400 got_sigill = 0; 2401 asm volatile(".set push\n" 2402 ".set mips32\n" 2403 "mul $zero, $zero\n" 2404 ".set pop\n" 2405 : : : ); 2406 use_mips32_instructions = !got_sigill; 2407#endif 2408 2409 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2410 available. As no subsetting is allowed by the specification, 2411 it is only necessary to probe for one of the instructions. */ 2412#ifndef use_mips32r2_instructions 2413 if (use_mips32_instructions) { 2414 got_sigill = 0; 2415 asm volatile(".set push\n" 2416 ".set mips32r2\n" 2417 "seb $zero, $zero\n" 2418 ".set pop\n" 2419 : : : ); 2420 use_mips32r2_instructions = !got_sigill; 2421 } 2422#endif 2423 2424 sigaction(SIGILL, &sa_old, NULL); 2425} 2426 2427static tcg_insn_unit *align_code_ptr(TCGContext *s) 2428{ 2429 uintptr_t p = (uintptr_t)s->code_ptr; 2430 if (p & 15) { 2431 p = (p + 15) & -16; 2432 s->code_ptr = (void *)p; 2433 } 2434 return s->code_ptr; 2435} 2436 2437/* Stack frame parameters. */ 2438#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2439#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2440#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2441 2442#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2443 + TCG_TARGET_STACK_ALIGN - 1) \ 2444 & -TCG_TARGET_STACK_ALIGN) 2445#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2446 2447/* We're expecting to be able to use an immediate for frame allocation. */ 2448QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2449 2450/* Generate global QEMU prologue and epilogue code */ 2451static void tcg_target_qemu_prologue(TCGContext *s) 2452{ 2453 int i; 2454 2455 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2456 2457 /* TB prologue */ 2458 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2459 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2460 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2461 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2462 } 2463 2464#ifndef CONFIG_SOFTMMU 2465 if (guest_base != (int16_t)guest_base) { 2466 /* 2467 * The function call abi for n32 and n64 will have loaded $25 (t9) 2468 * with the address of the prologue, so we can use that instead 2469 * of TCG_REG_TB. 2470 */ 2471#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2472# error "Unknown mips abi" 2473#endif 2474 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2475 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2476 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2477 } 2478#endif 2479 2480 if (TCG_TARGET_REG_BITS == 64) { 2481 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2482 } 2483 2484 /* Call generated code */ 2485 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2486 /* delay slot */ 2487 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2488 2489 /* 2490 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2491 * and fall through to the rest of the epilogue. 2492 */ 2493 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2494 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2495 2496 /* TB epilogue */ 2497 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2498 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2499 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2500 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2501 } 2502 2503 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2504 /* delay slot */ 2505 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2506 2507 if (use_mips32r2_instructions) { 2508 return; 2509 } 2510 2511 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2512 clobbers TCG_TMP1, TCG_TMP2. */ 2513 2514 /* 2515 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2516 */ 2517 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2518 /* t3 = (ssss)d000 */ 2519 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2520 /* t1 = 000a */ 2521 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2522 /* t2 = 00c0 */ 2523 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2524 /* t3 = d00a */ 2525 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2526 /* t1 = 0abc */ 2527 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2528 /* t2 = 0c00 */ 2529 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2530 /* t1 = 00b0 */ 2531 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2532 /* t3 = dc0a */ 2533 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2534 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2535 /* t3 = dcba -- delay slot */ 2536 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2537 2538 if (TCG_TARGET_REG_BITS == 32) { 2539 return; 2540 } 2541 2542 /* 2543 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2544 */ 2545 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2546 /* t1 = (0000)000d */ 2547 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2548 /* t3 = 000a */ 2549 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2550 /* t1 = (0000)d000 */ 2551 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2552 /* t2 = 00c0 */ 2553 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2554 /* t3 = d00a */ 2555 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2556 /* t1 = 0abc */ 2557 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2558 /* t2 = 0c00 */ 2559 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2560 /* t1 = 00b0 */ 2561 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2562 /* t3 = dc0a */ 2563 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2564 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2565 /* t3 = dcba -- delay slot */ 2566 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2567 2568 /* 2569 * bswap64 -- 64-bit swap. a0 = abcdefgh 2570 */ 2571 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2572 /* t3 = h0000000 */ 2573 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2574 /* t1 = 0000000a */ 2575 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2576 2577 /* t2 = 000000g0 */ 2578 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2579 /* t3 = h000000a */ 2580 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2581 /* t1 = 00000abc */ 2582 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2583 /* t2 = 0g000000 */ 2584 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2585 /* t1 = 000000b0 */ 2586 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2587 2588 /* t3 = hg00000a */ 2589 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2590 /* t2 = 0000abcd */ 2591 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2592 /* t3 = hg0000ba */ 2593 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2594 2595 /* t1 = 000000c0 */ 2596 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2597 /* t2 = 0000000d */ 2598 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2599 /* t1 = 00000c00 */ 2600 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2601 /* t2 = 0000d000 */ 2602 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2603 2604 /* t3 = hg000cba */ 2605 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2606 /* t1 = 00abcdef */ 2607 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2608 /* t3 = hg00dcba */ 2609 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2610 2611 /* t2 = 0000000f */ 2612 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2613 /* t1 = 000000e0 */ 2614 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2615 /* t2 = 00f00000 */ 2616 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2617 /* t1 = 000e0000 */ 2618 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2619 2620 /* t3 = hgf0dcba */ 2621 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2622 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2623 /* t3 = hgfedcba -- delay slot */ 2624 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2625} 2626 2627static void tcg_target_init(TCGContext *s) 2628{ 2629 tcg_target_detect_isa(); 2630 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2631 if (TCG_TARGET_REG_BITS == 64) { 2632 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2633 } 2634 2635 tcg_target_call_clobber_regs = 0; 2636 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2637 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2638 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2639 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2640 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2641 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2642 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2643 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2644 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2645 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2646 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2647 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2648 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2649 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2650 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2651 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2652 2653 s->reserved_regs = 0; 2654 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2655 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2656 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2657 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2658 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2659 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2660 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2661 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2662 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2663 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2664 if (TCG_TARGET_REG_BITS == 64) { 2665 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2666 } 2667} 2668 2669typedef struct { 2670 DebugFrameHeader h; 2671 uint8_t fde_def_cfa[4]; 2672 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2673} DebugFrame; 2674 2675#define ELF_HOST_MACHINE EM_MIPS 2676/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2677 which is good because they're really quite complicated for MIPS. */ 2678 2679static const DebugFrame debug_frame = { 2680 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2681 .h.cie.id = -1, 2682 .h.cie.version = 1, 2683 .h.cie.code_align = 1, 2684 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2685 .h.cie.return_column = TCG_REG_RA, 2686 2687 /* Total FDE size does not include the "len" member. */ 2688 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2689 2690 .fde_def_cfa = { 2691 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2692 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2693 (FRAME_SIZE >> 7) 2694 }, 2695 .fde_reg_ofs = { 2696 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2697 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2698 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2699 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2700 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2701 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2702 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2703 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2704 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2705 } 2706}; 2707 2708void tcg_register_jit(const void *buf, size_t buf_size) 2709{ 2710 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2711} 2712