1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#ifdef HOST_WORDS_BIGENDIAN 28# define MIPS_BE 1 29#else 30# define MIPS_BE 0 31#endif 32 33#if TCG_TARGET_REG_BITS == 32 34# define LO_OFF (MIPS_BE * 4) 35# define HI_OFF (4 - LO_OFF) 36#else 37/* To assert at compile-time that these values are never used 38 for TCG_TARGET_REG_BITS == 64. */ 39int link_error(void); 40# define LO_OFF link_error() 41# define HI_OFF link_error() 42#endif 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "zero", 47 "at", 48 "v0", 49 "v1", 50 "a0", 51 "a1", 52 "a2", 53 "a3", 54 "t0", 55 "t1", 56 "t2", 57 "t3", 58 "t4", 59 "t5", 60 "t6", 61 "t7", 62 "s0", 63 "s1", 64 "s2", 65 "s3", 66 "s4", 67 "s5", 68 "s6", 69 "s7", 70 "t8", 71 "t9", 72 "k0", 73 "k1", 74 "gp", 75 "sp", 76 "s8", 77 "ra", 78}; 79#endif 80 81#define TCG_TMP0 TCG_REG_AT 82#define TCG_TMP1 TCG_REG_T9 83#define TCG_TMP2 TCG_REG_T8 84#define TCG_TMP3 TCG_REG_T7 85 86#ifndef CONFIG_SOFTMMU 87#define TCG_GUEST_BASE_REG TCG_REG_S1 88#endif 89 90/* check if we really need so many registers :P */ 91static const int tcg_target_reg_alloc_order[] = { 92 /* Call saved registers. */ 93 TCG_REG_S0, 94 TCG_REG_S1, 95 TCG_REG_S2, 96 TCG_REG_S3, 97 TCG_REG_S4, 98 TCG_REG_S5, 99 TCG_REG_S6, 100 TCG_REG_S7, 101 TCG_REG_S8, 102 103 /* Call clobbered registers. */ 104 TCG_REG_T4, 105 TCG_REG_T5, 106 TCG_REG_T6, 107 TCG_REG_T7, 108 TCG_REG_T8, 109 TCG_REG_T9, 110 TCG_REG_V1, 111 TCG_REG_V0, 112 113 /* Argument registers, opposite order of allocation. */ 114 TCG_REG_T3, 115 TCG_REG_T2, 116 TCG_REG_T1, 117 TCG_REG_T0, 118 TCG_REG_A3, 119 TCG_REG_A2, 120 TCG_REG_A1, 121 TCG_REG_A0, 122}; 123 124static const TCGReg tcg_target_call_iarg_regs[] = { 125 TCG_REG_A0, 126 TCG_REG_A1, 127 TCG_REG_A2, 128 TCG_REG_A3, 129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 130 TCG_REG_T0, 131 TCG_REG_T1, 132 TCG_REG_T2, 133 TCG_REG_T3, 134#endif 135}; 136 137static const TCGReg tcg_target_call_oarg_regs[2] = { 138 TCG_REG_V0, 139 TCG_REG_V1 140}; 141 142static tcg_insn_unit *tb_ret_addr; 143static tcg_insn_unit *bswap32_addr; 144static tcg_insn_unit *bswap32u_addr; 145static tcg_insn_unit *bswap64_addr; 146 147static inline uint32_t reloc_pc16_val(tcg_insn_unit *pc, 148 const tcg_insn_unit *target) 149{ 150 /* Let the compiler perform the right-shift as part of the arithmetic. */ 151 ptrdiff_t disp = target - (pc + 1); 152 tcg_debug_assert(disp == (int16_t)disp); 153 return disp & 0xffff; 154} 155 156static inline void reloc_pc16(tcg_insn_unit *pc, const tcg_insn_unit *target) 157{ 158 *pc = deposit32(*pc, 0, 16, reloc_pc16_val(pc, target)); 159} 160 161static inline uint32_t reloc_26_val(tcg_insn_unit *pc, tcg_insn_unit *target) 162{ 163 tcg_debug_assert((((uintptr_t)pc ^ (uintptr_t)target) & 0xf0000000) == 0); 164 return ((uintptr_t)target >> 2) & 0x3ffffff; 165} 166 167static inline void reloc_26(tcg_insn_unit *pc, tcg_insn_unit *target) 168{ 169 *pc = deposit32(*pc, 0, 26, reloc_26_val(pc, target)); 170} 171 172static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 173 intptr_t value, intptr_t addend) 174{ 175 tcg_debug_assert(type == R_MIPS_PC16); 176 tcg_debug_assert(addend == 0); 177 reloc_pc16(code_ptr, (tcg_insn_unit *)value); 178 return true; 179} 180 181#define TCG_CT_CONST_ZERO 0x100 182#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 183#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 184#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 185#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 186#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 187 188static inline bool is_p2m1(tcg_target_long val) 189{ 190 return val && ((val + 1) & val) == 0; 191} 192 193/* parse target specific constraints */ 194static const char *target_parse_constraint(TCGArgConstraint *ct, 195 const char *ct_str, TCGType type) 196{ 197 switch(*ct_str++) { 198 case 'r': 199 ct->regs = 0xffffffff; 200 break; 201 case 'L': /* qemu_ld input arg constraint */ 202 ct->regs = 0xffffffff; 203 tcg_regset_reset_reg(ct->regs, TCG_REG_A0); 204#if defined(CONFIG_SOFTMMU) 205 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 206 tcg_regset_reset_reg(ct->regs, TCG_REG_A2); 207 } 208#endif 209 break; 210 case 'S': /* qemu_st constraint */ 211 ct->regs = 0xffffffff; 212 tcg_regset_reset_reg(ct->regs, TCG_REG_A0); 213#if defined(CONFIG_SOFTMMU) 214 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 215 tcg_regset_reset_reg(ct->regs, TCG_REG_A2); 216 tcg_regset_reset_reg(ct->regs, TCG_REG_A3); 217 } else { 218 tcg_regset_reset_reg(ct->regs, TCG_REG_A1); 219 } 220#endif 221 break; 222 case 'I': 223 ct->ct |= TCG_CT_CONST_U16; 224 break; 225 case 'J': 226 ct->ct |= TCG_CT_CONST_S16; 227 break; 228 case 'K': 229 ct->ct |= TCG_CT_CONST_P2M1; 230 break; 231 case 'N': 232 ct->ct |= TCG_CT_CONST_N16; 233 break; 234 case 'W': 235 ct->ct |= TCG_CT_CONST_WSZ; 236 break; 237 case 'Z': 238 /* We are cheating a bit here, using the fact that the register 239 ZERO is also the register number 0. Hence there is no need 240 to check for const_args in each instruction. */ 241 ct->ct |= TCG_CT_CONST_ZERO; 242 break; 243 default: 244 return NULL; 245 } 246 return ct_str; 247} 248 249/* test if a constant matches the constraint */ 250static inline int tcg_target_const_match(tcg_target_long val, TCGType type, 251 const TCGArgConstraint *arg_ct) 252{ 253 int ct; 254 ct = arg_ct->ct; 255 if (ct & TCG_CT_CONST) { 256 return 1; 257 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 258 return 1; 259 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 260 return 1; 261 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 262 return 1; 263 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 264 return 1; 265 } else if ((ct & TCG_CT_CONST_P2M1) 266 && use_mips32r2_instructions && is_p2m1(val)) { 267 return 1; 268 } else if ((ct & TCG_CT_CONST_WSZ) 269 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 270 return 1; 271 } 272 return 0; 273} 274 275/* instruction opcodes */ 276typedef enum { 277 OPC_J = 002 << 26, 278 OPC_JAL = 003 << 26, 279 OPC_BEQ = 004 << 26, 280 OPC_BNE = 005 << 26, 281 OPC_BLEZ = 006 << 26, 282 OPC_BGTZ = 007 << 26, 283 OPC_ADDIU = 011 << 26, 284 OPC_SLTI = 012 << 26, 285 OPC_SLTIU = 013 << 26, 286 OPC_ANDI = 014 << 26, 287 OPC_ORI = 015 << 26, 288 OPC_XORI = 016 << 26, 289 OPC_LUI = 017 << 26, 290 OPC_DADDIU = 031 << 26, 291 OPC_LB = 040 << 26, 292 OPC_LH = 041 << 26, 293 OPC_LW = 043 << 26, 294 OPC_LBU = 044 << 26, 295 OPC_LHU = 045 << 26, 296 OPC_LWU = 047 << 26, 297 OPC_SB = 050 << 26, 298 OPC_SH = 051 << 26, 299 OPC_SW = 053 << 26, 300 OPC_LD = 067 << 26, 301 OPC_SD = 077 << 26, 302 303 OPC_SPECIAL = 000 << 26, 304 OPC_SLL = OPC_SPECIAL | 000, 305 OPC_SRL = OPC_SPECIAL | 002, 306 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 307 OPC_SRA = OPC_SPECIAL | 003, 308 OPC_SLLV = OPC_SPECIAL | 004, 309 OPC_SRLV = OPC_SPECIAL | 006, 310 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 311 OPC_SRAV = OPC_SPECIAL | 007, 312 OPC_JR_R5 = OPC_SPECIAL | 010, 313 OPC_JALR = OPC_SPECIAL | 011, 314 OPC_MOVZ = OPC_SPECIAL | 012, 315 OPC_MOVN = OPC_SPECIAL | 013, 316 OPC_SYNC = OPC_SPECIAL | 017, 317 OPC_MFHI = OPC_SPECIAL | 020, 318 OPC_MFLO = OPC_SPECIAL | 022, 319 OPC_DSLLV = OPC_SPECIAL | 024, 320 OPC_DSRLV = OPC_SPECIAL | 026, 321 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 322 OPC_DSRAV = OPC_SPECIAL | 027, 323 OPC_MULT = OPC_SPECIAL | 030, 324 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 325 OPC_MUH = OPC_SPECIAL | 030 | 0300, 326 OPC_MULTU = OPC_SPECIAL | 031, 327 OPC_MULU = OPC_SPECIAL | 031 | 0200, 328 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 329 OPC_DIV = OPC_SPECIAL | 032, 330 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 331 OPC_MOD = OPC_SPECIAL | 032 | 0300, 332 OPC_DIVU = OPC_SPECIAL | 033, 333 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 334 OPC_MODU = OPC_SPECIAL | 033 | 0300, 335 OPC_DMULT = OPC_SPECIAL | 034, 336 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 337 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 338 OPC_DMULTU = OPC_SPECIAL | 035, 339 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 340 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 341 OPC_DDIV = OPC_SPECIAL | 036, 342 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 343 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 344 OPC_DDIVU = OPC_SPECIAL | 037, 345 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 346 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 347 OPC_ADDU = OPC_SPECIAL | 041, 348 OPC_SUBU = OPC_SPECIAL | 043, 349 OPC_AND = OPC_SPECIAL | 044, 350 OPC_OR = OPC_SPECIAL | 045, 351 OPC_XOR = OPC_SPECIAL | 046, 352 OPC_NOR = OPC_SPECIAL | 047, 353 OPC_SLT = OPC_SPECIAL | 052, 354 OPC_SLTU = OPC_SPECIAL | 053, 355 OPC_DADDU = OPC_SPECIAL | 055, 356 OPC_DSUBU = OPC_SPECIAL | 057, 357 OPC_SELEQZ = OPC_SPECIAL | 065, 358 OPC_SELNEZ = OPC_SPECIAL | 067, 359 OPC_DSLL = OPC_SPECIAL | 070, 360 OPC_DSRL = OPC_SPECIAL | 072, 361 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 362 OPC_DSRA = OPC_SPECIAL | 073, 363 OPC_DSLL32 = OPC_SPECIAL | 074, 364 OPC_DSRL32 = OPC_SPECIAL | 076, 365 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 366 OPC_DSRA32 = OPC_SPECIAL | 077, 367 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 368 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 369 370 OPC_REGIMM = 001 << 26, 371 OPC_BLTZ = OPC_REGIMM | (000 << 16), 372 OPC_BGEZ = OPC_REGIMM | (001 << 16), 373 374 OPC_SPECIAL2 = 034 << 26, 375 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 376 OPC_CLZ = OPC_SPECIAL2 | 040, 377 OPC_DCLZ = OPC_SPECIAL2 | 044, 378 379 OPC_SPECIAL3 = 037 << 26, 380 OPC_EXT = OPC_SPECIAL3 | 000, 381 OPC_DEXTM = OPC_SPECIAL3 | 001, 382 OPC_DEXTU = OPC_SPECIAL3 | 002, 383 OPC_DEXT = OPC_SPECIAL3 | 003, 384 OPC_INS = OPC_SPECIAL3 | 004, 385 OPC_DINSM = OPC_SPECIAL3 | 005, 386 OPC_DINSU = OPC_SPECIAL3 | 006, 387 OPC_DINS = OPC_SPECIAL3 | 007, 388 OPC_WSBH = OPC_SPECIAL3 | 00240, 389 OPC_DSBH = OPC_SPECIAL3 | 00244, 390 OPC_DSHD = OPC_SPECIAL3 | 00544, 391 OPC_SEB = OPC_SPECIAL3 | 02040, 392 OPC_SEH = OPC_SPECIAL3 | 03040, 393 394 /* MIPS r6 doesn't have JR, JALR should be used instead */ 395 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 396 397 /* 398 * MIPS r6 replaces MUL with an alternative encoding which is 399 * backwards-compatible at the assembly level. 400 */ 401 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 402 403 /* MIPS r6 introduced names for weaker variants of SYNC. These are 404 backward compatible to previous architecture revisions. */ 405 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 406 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 407 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 408 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 409 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 410 411 /* Aliases for convenience. */ 412 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 413 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 414 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 415 ? OPC_SRL : OPC_DSRL, 416} MIPSInsn; 417 418/* 419 * Type reg 420 */ 421static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 422 TCGReg rd, TCGReg rs, TCGReg rt) 423{ 424 int32_t inst; 425 426 inst = opc; 427 inst |= (rs & 0x1F) << 21; 428 inst |= (rt & 0x1F) << 16; 429 inst |= (rd & 0x1F) << 11; 430 tcg_out32(s, inst); 431} 432 433/* 434 * Type immediate 435 */ 436static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 437 TCGReg rt, TCGReg rs, TCGArg imm) 438{ 439 int32_t inst; 440 441 inst = opc; 442 inst |= (rs & 0x1F) << 21; 443 inst |= (rt & 0x1F) << 16; 444 inst |= (imm & 0xffff); 445 tcg_out32(s, inst); 446} 447 448/* 449 * Type bitfield 450 */ 451static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 452 TCGReg rs, int msb, int lsb) 453{ 454 int32_t inst; 455 456 inst = opc; 457 inst |= (rs & 0x1F) << 21; 458 inst |= (rt & 0x1F) << 16; 459 inst |= (msb & 0x1F) << 11; 460 inst |= (lsb & 0x1F) << 6; 461 tcg_out32(s, inst); 462} 463 464static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 465 MIPSInsn oph, TCGReg rt, TCGReg rs, 466 int msb, int lsb) 467{ 468 if (lsb >= 32) { 469 opc = oph; 470 msb -= 32; 471 lsb -= 32; 472 } else if (msb >= 32) { 473 opc = opm; 474 msb -= 32; 475 } 476 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 477} 478 479/* 480 * Type branch 481 */ 482static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, 483 TCGReg rt, TCGReg rs) 484{ 485 tcg_out_opc_imm(s, opc, rt, rs, 0); 486} 487 488/* 489 * Type sa 490 */ 491static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 492 TCGReg rd, TCGReg rt, TCGArg sa) 493{ 494 int32_t inst; 495 496 inst = opc; 497 inst |= (rt & 0x1F) << 16; 498 inst |= (rd & 0x1F) << 11; 499 inst |= (sa & 0x1F) << 6; 500 tcg_out32(s, inst); 501 502} 503 504static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 505 TCGReg rd, TCGReg rt, TCGArg sa) 506{ 507 int32_t inst; 508 509 inst = (sa & 32 ? opc2 : opc1); 510 inst |= (rt & 0x1F) << 16; 511 inst |= (rd & 0x1F) << 11; 512 inst |= (sa & 0x1F) << 6; 513 tcg_out32(s, inst); 514} 515 516/* 517 * Type jump. 518 * Returns true if the branch was in range and the insn was emitted. 519 */ 520static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 521{ 522 uintptr_t dest = (uintptr_t)target; 523 uintptr_t from = (uintptr_t)s->code_ptr + 4; 524 int32_t inst; 525 526 /* The pc-region branch happens within the 256MB region of 527 the delay slot (thus the +4). */ 528 if ((from ^ dest) & -(1 << 28)) { 529 return false; 530 } 531 tcg_debug_assert((dest & 3) == 0); 532 533 inst = opc; 534 inst |= (dest >> 2) & 0x3ffffff; 535 tcg_out32(s, inst); 536 return true; 537} 538 539static inline void tcg_out_nop(TCGContext *s) 540{ 541 tcg_out32(s, 0); 542} 543 544static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 545{ 546 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 547} 548 549static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 550{ 551 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 552} 553 554static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 555{ 556 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 557} 558 559static inline bool tcg_out_mov(TCGContext *s, TCGType type, 560 TCGReg ret, TCGReg arg) 561{ 562 /* Simple reg-reg move, optimising out the 'do nothing' case */ 563 if (ret != arg) { 564 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 565 } 566 return true; 567} 568 569static void tcg_out_movi(TCGContext *s, TCGType type, 570 TCGReg ret, tcg_target_long arg) 571{ 572 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 573 arg = (int32_t)arg; 574 } 575 if (arg == (int16_t)arg) { 576 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 577 return; 578 } 579 if (arg == (uint16_t)arg) { 580 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 581 return; 582 } 583 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 584 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 585 } else { 586 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 587 if (arg & 0xffff0000ull) { 588 tcg_out_dsll(s, ret, ret, 16); 589 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 590 tcg_out_dsll(s, ret, ret, 16); 591 } else { 592 tcg_out_dsll(s, ret, ret, 32); 593 } 594 } 595 if (arg & 0xffff) { 596 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 597 } 598} 599 600static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) 601{ 602 if (use_mips32r2_instructions) { 603 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 604 } else { 605 /* ret and arg can't be register at */ 606 if (ret == TCG_TMP0 || arg == TCG_TMP0) { 607 tcg_abort(); 608 } 609 610 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); 611 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); 612 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); 613 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); 614 } 615} 616 617static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) 618{ 619 if (use_mips32r2_instructions) { 620 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 621 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); 622 } else { 623 /* ret and arg can't be register at */ 624 if (ret == TCG_TMP0 || arg == TCG_TMP0) { 625 tcg_abort(); 626 } 627 628 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); 629 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 630 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 631 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); 632 } 633} 634 635static void tcg_out_bswap_subr(TCGContext *s, tcg_insn_unit *sub) 636{ 637 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); 638 tcg_debug_assert(ok); 639} 640 641static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) 642{ 643 if (use_mips32r2_instructions) { 644 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 645 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 646 } else { 647 tcg_out_bswap_subr(s, bswap32_addr); 648 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 649 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 650 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 651 } 652} 653 654static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) 655{ 656 if (use_mips32r2_instructions) { 657 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 658 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 659 tcg_out_dsrl(s, ret, ret, 32); 660 } else { 661 tcg_out_bswap_subr(s, bswap32u_addr); 662 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 663 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 664 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 665 } 666} 667 668static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 669{ 670 if (use_mips32r2_instructions) { 671 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 672 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 673 } else { 674 tcg_out_bswap_subr(s, bswap64_addr); 675 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 676 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 677 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 678 } 679} 680 681static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) 682{ 683 if (use_mips32r2_instructions) { 684 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); 685 } else { 686 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 687 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); 688 } 689} 690 691static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) 692{ 693 if (use_mips32r2_instructions) { 694 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); 695 } else { 696 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); 697 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 698 } 699} 700 701static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 702{ 703 if (use_mips32r2_instructions) { 704 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 705 } else { 706 tcg_out_dsll(s, ret, arg, 32); 707 tcg_out_dsrl(s, ret, ret, 32); 708 } 709} 710 711static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 712 TCGReg addr, intptr_t ofs) 713{ 714 int16_t lo = ofs; 715 if (ofs != lo) { 716 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 717 if (addr != TCG_REG_ZERO) { 718 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 719 } 720 addr = TCG_TMP0; 721 } 722 tcg_out_opc_imm(s, opc, data, addr, lo); 723} 724 725static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 726 TCGReg arg1, intptr_t arg2) 727{ 728 MIPSInsn opc = OPC_LD; 729 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 730 opc = OPC_LW; 731 } 732 tcg_out_ldst(s, opc, arg, arg1, arg2); 733} 734 735static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 736 TCGReg arg1, intptr_t arg2) 737{ 738 MIPSInsn opc = OPC_SD; 739 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 740 opc = OPC_SW; 741 } 742 tcg_out_ldst(s, opc, arg, arg1, arg2); 743} 744 745static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 746 TCGReg base, intptr_t ofs) 747{ 748 if (val == 0) { 749 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 750 return true; 751 } 752 return false; 753} 754 755static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 756 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 757 bool cbh, bool is_sub) 758{ 759 TCGReg th = TCG_TMP1; 760 761 /* If we have a negative constant such that negating it would 762 make the high part zero, we can (usually) eliminate one insn. */ 763 if (cbl && cbh && bh == -1 && bl != 0) { 764 bl = -bl; 765 bh = 0; 766 is_sub = !is_sub; 767 } 768 769 /* By operating on the high part first, we get to use the final 770 carry operation to move back from the temporary. */ 771 if (!cbh) { 772 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 773 } else if (bh != 0 || ah == rl) { 774 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 775 } else { 776 th = ah; 777 } 778 779 /* Note that tcg optimization should eliminate the bl == 0 case. */ 780 if (is_sub) { 781 if (cbl) { 782 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 783 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 784 } else { 785 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 786 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 787 } 788 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 789 } else { 790 if (cbl) { 791 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 792 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 793 } else if (rl == al && rl == bl) { 794 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 795 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 796 } else { 797 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 798 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 799 } 800 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 801 } 802} 803 804/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 805#define MIPS_CMP_INV 1 806#define MIPS_CMP_SWAP 2 807 808static const uint8_t mips_cmp_map[16] = { 809 [TCG_COND_LT] = 0, 810 [TCG_COND_LTU] = 0, 811 [TCG_COND_GE] = MIPS_CMP_INV, 812 [TCG_COND_GEU] = MIPS_CMP_INV, 813 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 814 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 815 [TCG_COND_GT] = MIPS_CMP_SWAP, 816 [TCG_COND_GTU] = MIPS_CMP_SWAP, 817}; 818 819static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 820 TCGReg arg1, TCGReg arg2) 821{ 822 MIPSInsn s_opc = OPC_SLTU; 823 int cmp_map; 824 825 switch (cond) { 826 case TCG_COND_EQ: 827 if (arg2 != 0) { 828 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 829 arg1 = ret; 830 } 831 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 832 break; 833 834 case TCG_COND_NE: 835 if (arg2 != 0) { 836 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 837 arg1 = ret; 838 } 839 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 840 break; 841 842 case TCG_COND_LT: 843 case TCG_COND_GE: 844 case TCG_COND_LE: 845 case TCG_COND_GT: 846 s_opc = OPC_SLT; 847 /* FALLTHRU */ 848 849 case TCG_COND_LTU: 850 case TCG_COND_GEU: 851 case TCG_COND_LEU: 852 case TCG_COND_GTU: 853 cmp_map = mips_cmp_map[cond]; 854 if (cmp_map & MIPS_CMP_SWAP) { 855 TCGReg t = arg1; 856 arg1 = arg2; 857 arg2 = t; 858 } 859 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 860 if (cmp_map & MIPS_CMP_INV) { 861 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 862 } 863 break; 864 865 default: 866 tcg_abort(); 867 break; 868 } 869} 870 871static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 872 TCGReg arg2, TCGLabel *l) 873{ 874 static const MIPSInsn b_zero[16] = { 875 [TCG_COND_LT] = OPC_BLTZ, 876 [TCG_COND_GT] = OPC_BGTZ, 877 [TCG_COND_LE] = OPC_BLEZ, 878 [TCG_COND_GE] = OPC_BGEZ, 879 }; 880 881 MIPSInsn s_opc = OPC_SLTU; 882 MIPSInsn b_opc; 883 int cmp_map; 884 885 switch (cond) { 886 case TCG_COND_EQ: 887 b_opc = OPC_BEQ; 888 break; 889 case TCG_COND_NE: 890 b_opc = OPC_BNE; 891 break; 892 893 case TCG_COND_LT: 894 case TCG_COND_GT: 895 case TCG_COND_LE: 896 case TCG_COND_GE: 897 if (arg2 == 0) { 898 b_opc = b_zero[cond]; 899 arg2 = arg1; 900 arg1 = 0; 901 break; 902 } 903 s_opc = OPC_SLT; 904 /* FALLTHRU */ 905 906 case TCG_COND_LTU: 907 case TCG_COND_GTU: 908 case TCG_COND_LEU: 909 case TCG_COND_GEU: 910 cmp_map = mips_cmp_map[cond]; 911 if (cmp_map & MIPS_CMP_SWAP) { 912 TCGReg t = arg1; 913 arg1 = arg2; 914 arg2 = t; 915 } 916 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 917 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 918 arg1 = TCG_TMP0; 919 arg2 = TCG_REG_ZERO; 920 break; 921 922 default: 923 tcg_abort(); 924 break; 925 } 926 927 tcg_out_opc_br(s, b_opc, arg1, arg2); 928 if (l->has_value) { 929 reloc_pc16(s->code_ptr - 1, l->u.value_ptr); 930 } else { 931 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 932 } 933 tcg_out_nop(s); 934} 935 936static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 937 TCGReg al, TCGReg ah, 938 TCGReg bl, TCGReg bh) 939{ 940 /* Merge highpart comparison into AH. */ 941 if (bh != 0) { 942 if (ah != 0) { 943 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 944 ah = tmp0; 945 } else { 946 ah = bh; 947 } 948 } 949 /* Merge lowpart comparison into AL. */ 950 if (bl != 0) { 951 if (al != 0) { 952 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 953 al = tmp1; 954 } else { 955 al = bl; 956 } 957 } 958 /* Merge high and low part comparisons into AL. */ 959 if (ah != 0) { 960 if (al != 0) { 961 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 962 al = tmp0; 963 } else { 964 al = ah; 965 } 966 } 967 return al; 968} 969 970static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 971 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 972{ 973 TCGReg tmp0 = TCG_TMP0; 974 TCGReg tmp1 = ret; 975 976 tcg_debug_assert(ret != TCG_TMP0); 977 if (ret == ah || ret == bh) { 978 tcg_debug_assert(ret != TCG_TMP1); 979 tmp1 = TCG_TMP1; 980 } 981 982 switch (cond) { 983 case TCG_COND_EQ: 984 case TCG_COND_NE: 985 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 986 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 987 break; 988 989 default: 990 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 991 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 992 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 993 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 994 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 995 break; 996 } 997} 998 999static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1000 TCGReg bl, TCGReg bh, TCGLabel *l) 1001{ 1002 TCGCond b_cond = TCG_COND_NE; 1003 TCGReg tmp = TCG_TMP1; 1004 1005 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 1006 With setcond, we emit between 3 and 10 insns and only 1 branch, 1007 which ought to get better branch prediction. */ 1008 switch (cond) { 1009 case TCG_COND_EQ: 1010 case TCG_COND_NE: 1011 b_cond = cond; 1012 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 1013 break; 1014 1015 default: 1016 /* Minimize code size by preferring a compare not requiring INV. */ 1017 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1018 cond = tcg_invert_cond(cond); 1019 b_cond = TCG_COND_EQ; 1020 } 1021 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 1022 break; 1023 } 1024 1025 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 1026} 1027 1028static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1029 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1030{ 1031 bool eqz = false; 1032 1033 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1034 if (use_mips32r6_instructions && v1 == 0) { 1035 v1 = v2; 1036 v2 = 0; 1037 cond = tcg_invert_cond(cond); 1038 } 1039 1040 switch (cond) { 1041 case TCG_COND_EQ: 1042 eqz = true; 1043 /* FALLTHRU */ 1044 case TCG_COND_NE: 1045 if (c2 != 0) { 1046 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 1047 c1 = TCG_TMP0; 1048 } 1049 break; 1050 1051 default: 1052 /* Minimize code size by preferring a compare not requiring INV. */ 1053 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1054 cond = tcg_invert_cond(cond); 1055 eqz = true; 1056 } 1057 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 1058 c1 = TCG_TMP0; 1059 break; 1060 } 1061 1062 if (use_mips32r6_instructions) { 1063 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1064 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1065 1066 if (v2 != 0) { 1067 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1068 } 1069 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1070 if (v2 != 0) { 1071 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1072 } 1073 } else { 1074 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1075 1076 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1077 1078 /* This should be guaranteed via constraints */ 1079 tcg_debug_assert(v2 == ret); 1080 } 1081} 1082 1083static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1084{ 1085 /* Note that the ABI requires the called function's address to be 1086 loaded into T9, even if a direct branch is in range. */ 1087 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1088 1089 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1090 if (tail) { 1091 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1092 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1093 } 1094 } else { 1095 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1096 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1097 } 1098 } 1099} 1100 1101static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) 1102{ 1103 tcg_out_call_int(s, arg, false); 1104 tcg_out_nop(s); 1105} 1106 1107#if defined(CONFIG_SOFTMMU) 1108#include "../tcg-ldst.c.inc" 1109 1110static void * const qemu_ld_helpers[16] = { 1111 [MO_UB] = helper_ret_ldub_mmu, 1112 [MO_SB] = helper_ret_ldsb_mmu, 1113 [MO_LEUW] = helper_le_lduw_mmu, 1114 [MO_LESW] = helper_le_ldsw_mmu, 1115 [MO_LEUL] = helper_le_ldul_mmu, 1116 [MO_LEQ] = helper_le_ldq_mmu, 1117 [MO_BEUW] = helper_be_lduw_mmu, 1118 [MO_BESW] = helper_be_ldsw_mmu, 1119 [MO_BEUL] = helper_be_ldul_mmu, 1120 [MO_BEQ] = helper_be_ldq_mmu, 1121#if TCG_TARGET_REG_BITS == 64 1122 [MO_LESL] = helper_le_ldsl_mmu, 1123 [MO_BESL] = helper_be_ldsl_mmu, 1124#endif 1125}; 1126 1127static void * const qemu_st_helpers[16] = { 1128 [MO_UB] = helper_ret_stb_mmu, 1129 [MO_LEUW] = helper_le_stw_mmu, 1130 [MO_LEUL] = helper_le_stl_mmu, 1131 [MO_LEQ] = helper_le_stq_mmu, 1132 [MO_BEUW] = helper_be_stw_mmu, 1133 [MO_BEUL] = helper_be_stl_mmu, 1134 [MO_BEQ] = helper_be_stq_mmu, 1135}; 1136 1137/* Helper routines for marshalling helper function arguments into 1138 * the correct registers and stack. 1139 * I is where we want to put this argument, and is updated and returned 1140 * for the next call. ARG is the argument itself. 1141 * 1142 * We provide routines for arguments which are: immediate, 32 bit 1143 * value in register, 16 and 8 bit values in register (which must be zero 1144 * extended before use) and 64 bit value in a lo:hi register pair. 1145 */ 1146 1147static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) 1148{ 1149 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1150 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); 1151 } else { 1152 /* For N32 and N64, the initial offset is different. But there 1153 we also have 8 argument register so we don't run out here. */ 1154 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1155 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); 1156 } 1157 return i + 1; 1158} 1159 1160static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) 1161{ 1162 TCGReg tmp = TCG_TMP0; 1163 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1164 tmp = tcg_target_call_iarg_regs[i]; 1165 } 1166 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); 1167 return tcg_out_call_iarg_reg(s, i, tmp); 1168} 1169 1170static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) 1171{ 1172 TCGReg tmp = TCG_TMP0; 1173 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1174 tmp = tcg_target_call_iarg_regs[i]; 1175 } 1176 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); 1177 return tcg_out_call_iarg_reg(s, i, tmp); 1178} 1179 1180static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) 1181{ 1182 TCGReg tmp = TCG_TMP0; 1183 if (arg == 0) { 1184 tmp = TCG_REG_ZERO; 1185 } else { 1186 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1187 tmp = tcg_target_call_iarg_regs[i]; 1188 } 1189 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); 1190 } 1191 return tcg_out_call_iarg_reg(s, i, tmp); 1192} 1193 1194static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) 1195{ 1196 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1197 i = (i + 1) & ~1; 1198 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); 1199 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); 1200 return i; 1201} 1202 1203/* We expect to use a 16-bit negative offset from ENV. */ 1204QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1205QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1206 1207/* 1208 * Perform the tlb comparison operation. 1209 * The complete host address is placed in BASE. 1210 * Clobbers TMP0, TMP1, TMP2, TMP3. 1211 */ 1212static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, 1213 TCGReg addrh, TCGMemOpIdx oi, 1214 tcg_insn_unit *label_ptr[2], bool is_load) 1215{ 1216 MemOp opc = get_memop(oi); 1217 unsigned s_bits = opc & MO_SIZE; 1218 unsigned a_bits = get_alignment_bits(opc); 1219 int mem_index = get_mmuidx(oi); 1220 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1221 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1222 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1223 int add_off = offsetof(CPUTLBEntry, addend); 1224 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) 1225 : offsetof(CPUTLBEntry, addr_write)); 1226 target_ulong mask; 1227 1228 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1229 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1230 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1231 1232 /* Extract the TLB index from the address into TMP3. */ 1233 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, 1234 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1235 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1236 1237 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1238 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1239 1240 /* We don't currently support unaligned accesses. 1241 We could do so with mips32r6. */ 1242 if (a_bits < s_bits) { 1243 a_bits = s_bits; 1244 } 1245 1246 /* Mask the page bits, keeping the alignment bits to compare against. */ 1247 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 1248 1249 /* Load the (low-half) tlb comparator. */ 1250 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1251 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1252 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); 1253 } else { 1254 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD 1255 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), 1256 TCG_TMP0, TCG_TMP3, cmp_off); 1257 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); 1258 /* No second compare is required here; 1259 load the tlb addend for the fast path. */ 1260 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1261 } 1262 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); 1263 1264 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1265 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1266 tcg_out_ext32u(s, base, addrl); 1267 addrl = base; 1268 } 1269 1270 label_ptr[0] = s->code_ptr; 1271 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1272 1273 /* Load and test the high half tlb comparator. */ 1274 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1275 /* delay slot */ 1276 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1277 1278 /* Load the tlb addend for the fast path. */ 1279 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1280 1281 label_ptr[1] = s->code_ptr; 1282 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); 1283 } 1284 1285 /* delay slot */ 1286 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); 1287} 1288 1289static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, 1290 TCGType ext, 1291 TCGReg datalo, TCGReg datahi, 1292 TCGReg addrlo, TCGReg addrhi, 1293 void *raddr, tcg_insn_unit *label_ptr[2]) 1294{ 1295 TCGLabelQemuLdst *label = new_ldst_label(s); 1296 1297 label->is_ld = is_ld; 1298 label->oi = oi; 1299 label->type = ext; 1300 label->datalo_reg = datalo; 1301 label->datahi_reg = datahi; 1302 label->addrlo_reg = addrlo; 1303 label->addrhi_reg = addrhi; 1304 label->raddr = raddr; 1305 label->label_ptr[0] = label_ptr[0]; 1306 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1307 label->label_ptr[1] = label_ptr[1]; 1308 } 1309} 1310 1311static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1312{ 1313 TCGMemOpIdx oi = l->oi; 1314 MemOp opc = get_memop(oi); 1315 TCGReg v0; 1316 int i; 1317 1318 /* resolve label address */ 1319 reloc_pc16(l->label_ptr[0], s->code_ptr); 1320 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1321 reloc_pc16(l->label_ptr[1], s->code_ptr); 1322 } 1323 1324 i = 1; 1325 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1326 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1327 } else { 1328 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1329 } 1330 i = tcg_out_call_iarg_imm(s, i, oi); 1331 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); 1332 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); 1333 /* delay slot */ 1334 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1335 1336 v0 = l->datalo_reg; 1337 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 1338 /* We eliminated V0 from the possible output registers, so it 1339 cannot be clobbered here. So we must move V1 first. */ 1340 if (MIPS_BE) { 1341 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); 1342 v0 = l->datahi_reg; 1343 } else { 1344 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); 1345 } 1346 } 1347 1348 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1349 reloc_pc16(s->code_ptr - 1, l->raddr); 1350 1351 /* delay slot */ 1352 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { 1353 /* we always sign-extend 32-bit loads */ 1354 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); 1355 } else { 1356 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); 1357 } 1358 return true; 1359} 1360 1361static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1362{ 1363 TCGMemOpIdx oi = l->oi; 1364 MemOp opc = get_memop(oi); 1365 MemOp s_bits = opc & MO_SIZE; 1366 int i; 1367 1368 /* resolve label address */ 1369 reloc_pc16(l->label_ptr[0], s->code_ptr); 1370 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1371 reloc_pc16(l->label_ptr[1], s->code_ptr); 1372 } 1373 1374 i = 1; 1375 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1376 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1377 } else { 1378 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1379 } 1380 switch (s_bits) { 1381 case MO_8: 1382 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); 1383 break; 1384 case MO_16: 1385 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); 1386 break; 1387 case MO_32: 1388 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1389 break; 1390 case MO_64: 1391 if (TCG_TARGET_REG_BITS == 32) { 1392 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); 1393 } else { 1394 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1395 } 1396 break; 1397 default: 1398 tcg_abort(); 1399 } 1400 i = tcg_out_call_iarg_imm(s, i, oi); 1401 1402 /* Tail call to the store helper. Thus force the return address 1403 computation to take place in the return address register. */ 1404 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); 1405 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); 1406 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); 1407 /* delay slot */ 1408 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1409 return true; 1410} 1411#endif 1412 1413static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1414 TCGReg base, MemOp opc, bool is_64) 1415{ 1416 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1417 case MO_UB: 1418 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1419 break; 1420 case MO_SB: 1421 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1422 break; 1423 case MO_UW | MO_BSWAP: 1424 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1425 tcg_out_bswap16(s, lo, TCG_TMP1); 1426 break; 1427 case MO_UW: 1428 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1429 break; 1430 case MO_SW | MO_BSWAP: 1431 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1432 tcg_out_bswap16s(s, lo, TCG_TMP1); 1433 break; 1434 case MO_SW: 1435 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1436 break; 1437 case MO_UL | MO_BSWAP: 1438 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1439 if (use_mips32r2_instructions) { 1440 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1441 tcg_out_bswap32u(s, lo, lo); 1442 } else { 1443 tcg_out_bswap_subr(s, bswap32u_addr); 1444 /* delay slot */ 1445 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); 1446 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1447 } 1448 break; 1449 } 1450 /* FALLTHRU */ 1451 case MO_SL | MO_BSWAP: 1452 if (use_mips32r2_instructions) { 1453 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1454 tcg_out_bswap32(s, lo, lo); 1455 } else { 1456 tcg_out_bswap_subr(s, bswap32_addr); 1457 /* delay slot */ 1458 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1459 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); 1460 } 1461 break; 1462 case MO_UL: 1463 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1464 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1465 break; 1466 } 1467 /* FALLTHRU */ 1468 case MO_SL: 1469 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1470 break; 1471 case MO_Q | MO_BSWAP: 1472 if (TCG_TARGET_REG_BITS == 64) { 1473 if (use_mips32r2_instructions) { 1474 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1475 tcg_out_bswap64(s, lo, lo); 1476 } else { 1477 tcg_out_bswap_subr(s, bswap64_addr); 1478 /* delay slot */ 1479 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); 1480 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1481 } 1482 } else if (use_mips32r2_instructions) { 1483 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1484 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); 1485 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1486 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1487 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1488 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1489 } else { 1490 tcg_out_bswap_subr(s, bswap32_addr); 1491 /* delay slot */ 1492 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1493 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); 1494 tcg_out_bswap_subr(s, bswap32_addr); 1495 /* delay slot */ 1496 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1497 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1498 } 1499 break; 1500 case MO_Q: 1501 /* Prefer to load from offset 0 first, but allow for overlap. */ 1502 if (TCG_TARGET_REG_BITS == 64) { 1503 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1504 } else if (MIPS_BE ? hi != base : lo == base) { 1505 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1506 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1507 } else { 1508 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1509 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1510 } 1511 break; 1512 default: 1513 tcg_abort(); 1514 } 1515} 1516 1517static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1518{ 1519 TCGReg addr_regl, addr_regh __attribute__((unused)); 1520 TCGReg data_regl, data_regh; 1521 TCGMemOpIdx oi; 1522 MemOp opc; 1523#if defined(CONFIG_SOFTMMU) 1524 tcg_insn_unit *label_ptr[2]; 1525#endif 1526 TCGReg base = TCG_REG_A0; 1527 1528 data_regl = *args++; 1529 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1530 addr_regl = *args++; 1531 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1532 oi = *args++; 1533 opc = get_memop(oi); 1534 1535#if defined(CONFIG_SOFTMMU) 1536 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); 1537 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1538 add_qemu_ldst_label(s, 1, oi, 1539 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1540 data_regl, data_regh, addr_regl, addr_regh, 1541 s->code_ptr, label_ptr); 1542#else 1543 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1544 tcg_out_ext32u(s, base, addr_regl); 1545 addr_regl = base; 1546 } 1547 if (guest_base == 0 && data_regl != addr_regl) { 1548 base = addr_regl; 1549 } else if (guest_base == (int16_t)guest_base) { 1550 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1551 } else { 1552 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1553 } 1554 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1555#endif 1556} 1557 1558static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1559 TCGReg base, MemOp opc) 1560{ 1561 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1562 if ((lo | hi) == 0) { 1563 opc &= ~MO_BSWAP; 1564 } 1565 1566 switch (opc & (MO_SIZE | MO_BSWAP)) { 1567 case MO_8: 1568 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1569 break; 1570 1571 case MO_16 | MO_BSWAP: 1572 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff); 1573 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1); 1574 lo = TCG_TMP1; 1575 /* FALLTHRU */ 1576 case MO_16: 1577 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1578 break; 1579 1580 case MO_32 | MO_BSWAP: 1581 tcg_out_bswap32(s, TCG_TMP3, lo); 1582 lo = TCG_TMP3; 1583 /* FALLTHRU */ 1584 case MO_32: 1585 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1586 break; 1587 1588 case MO_64 | MO_BSWAP: 1589 if (TCG_TARGET_REG_BITS == 64) { 1590 tcg_out_bswap64(s, TCG_TMP3, lo); 1591 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); 1592 } else if (use_mips32r2_instructions) { 1593 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); 1594 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); 1595 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1596 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1597 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); 1598 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); 1599 } else { 1600 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi); 1601 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); 1602 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo); 1603 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); 1604 } 1605 break; 1606 case MO_64: 1607 if (TCG_TARGET_REG_BITS == 64) { 1608 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1609 } else { 1610 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1611 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1612 } 1613 break; 1614 1615 default: 1616 tcg_abort(); 1617 } 1618} 1619 1620static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1621{ 1622 TCGReg addr_regl, addr_regh __attribute__((unused)); 1623 TCGReg data_regl, data_regh; 1624 TCGMemOpIdx oi; 1625 MemOp opc; 1626#if defined(CONFIG_SOFTMMU) 1627 tcg_insn_unit *label_ptr[2]; 1628#endif 1629 TCGReg base = TCG_REG_A0; 1630 1631 data_regl = *args++; 1632 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1633 addr_regl = *args++; 1634 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1635 oi = *args++; 1636 opc = get_memop(oi); 1637 1638#if defined(CONFIG_SOFTMMU) 1639 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); 1640 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1641 add_qemu_ldst_label(s, 0, oi, 1642 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1643 data_regl, data_regh, addr_regl, addr_regh, 1644 s->code_ptr, label_ptr); 1645#else 1646 base = TCG_REG_A0; 1647 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1648 tcg_out_ext32u(s, base, addr_regl); 1649 addr_regl = base; 1650 } 1651 if (guest_base == 0) { 1652 base = addr_regl; 1653 } else if (guest_base == (int16_t)guest_base) { 1654 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1655 } else { 1656 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1657 } 1658 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1659#endif 1660} 1661 1662static void tcg_out_mb(TCGContext *s, TCGArg a0) 1663{ 1664 static const MIPSInsn sync[] = { 1665 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1666 as the former is an ordering barrier and the latter 1667 is a completion barrier. */ 1668 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1669 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1670 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1671 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1672 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1673 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1674 }; 1675 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1676} 1677 1678static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1679 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1680{ 1681 if (use_mips32r6_instructions) { 1682 if (a2 == width) { 1683 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1684 } else { 1685 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1686 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1687 } 1688 } else { 1689 if (a2 == width) { 1690 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1691 } else if (a0 == a2) { 1692 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1693 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1694 } else if (a0 != a1) { 1695 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1696 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1697 } else { 1698 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1699 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1700 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1701 } 1702 } 1703} 1704 1705static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 1706 const TCGArg *args, const int *const_args) 1707{ 1708 MIPSInsn i1, i2; 1709 TCGArg a0, a1, a2; 1710 int c2; 1711 1712 a0 = args[0]; 1713 a1 = args[1]; 1714 a2 = args[2]; 1715 c2 = const_args[2]; 1716 1717 switch (opc) { 1718 case INDEX_op_exit_tb: 1719 { 1720 TCGReg b0 = TCG_REG_ZERO; 1721 1722 a0 = (intptr_t)a0; 1723 if (a0 & ~0xffff) { 1724 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 1725 b0 = TCG_REG_V0; 1726 } 1727 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1728 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, 1729 (uintptr_t)tb_ret_addr); 1730 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1731 } 1732 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 1733 } 1734 break; 1735 case INDEX_op_goto_tb: 1736 if (s->tb_jmp_insn_offset) { 1737 /* direct jump method */ 1738 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); 1739 /* Avoid clobbering the address during retranslation. */ 1740 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); 1741 } else { 1742 /* indirect jump method */ 1743 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 1744 (uintptr_t)(s->tb_jmp_target_addr + a0)); 1745 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1746 } 1747 tcg_out_nop(s); 1748 set_jmp_reset_offset(s, a0); 1749 break; 1750 case INDEX_op_goto_ptr: 1751 /* jmp to the given host address (could be epilogue) */ 1752 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1753 tcg_out_nop(s); 1754 break; 1755 case INDEX_op_br: 1756 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1757 arg_label(a0)); 1758 break; 1759 1760 case INDEX_op_ld8u_i32: 1761 case INDEX_op_ld8u_i64: 1762 i1 = OPC_LBU; 1763 goto do_ldst; 1764 case INDEX_op_ld8s_i32: 1765 case INDEX_op_ld8s_i64: 1766 i1 = OPC_LB; 1767 goto do_ldst; 1768 case INDEX_op_ld16u_i32: 1769 case INDEX_op_ld16u_i64: 1770 i1 = OPC_LHU; 1771 goto do_ldst; 1772 case INDEX_op_ld16s_i32: 1773 case INDEX_op_ld16s_i64: 1774 i1 = OPC_LH; 1775 goto do_ldst; 1776 case INDEX_op_ld_i32: 1777 case INDEX_op_ld32s_i64: 1778 i1 = OPC_LW; 1779 goto do_ldst; 1780 case INDEX_op_ld32u_i64: 1781 i1 = OPC_LWU; 1782 goto do_ldst; 1783 case INDEX_op_ld_i64: 1784 i1 = OPC_LD; 1785 goto do_ldst; 1786 case INDEX_op_st8_i32: 1787 case INDEX_op_st8_i64: 1788 i1 = OPC_SB; 1789 goto do_ldst; 1790 case INDEX_op_st16_i32: 1791 case INDEX_op_st16_i64: 1792 i1 = OPC_SH; 1793 goto do_ldst; 1794 case INDEX_op_st_i32: 1795 case INDEX_op_st32_i64: 1796 i1 = OPC_SW; 1797 goto do_ldst; 1798 case INDEX_op_st_i64: 1799 i1 = OPC_SD; 1800 do_ldst: 1801 tcg_out_ldst(s, i1, a0, a1, a2); 1802 break; 1803 1804 case INDEX_op_add_i32: 1805 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1806 goto do_binary; 1807 case INDEX_op_add_i64: 1808 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1809 goto do_binary; 1810 case INDEX_op_or_i32: 1811 case INDEX_op_or_i64: 1812 i1 = OPC_OR, i2 = OPC_ORI; 1813 goto do_binary; 1814 case INDEX_op_xor_i32: 1815 case INDEX_op_xor_i64: 1816 i1 = OPC_XOR, i2 = OPC_XORI; 1817 do_binary: 1818 if (c2) { 1819 tcg_out_opc_imm(s, i2, a0, a1, a2); 1820 break; 1821 } 1822 do_binaryv: 1823 tcg_out_opc_reg(s, i1, a0, a1, a2); 1824 break; 1825 1826 case INDEX_op_sub_i32: 1827 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1828 goto do_subtract; 1829 case INDEX_op_sub_i64: 1830 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1831 do_subtract: 1832 if (c2) { 1833 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1834 break; 1835 } 1836 goto do_binaryv; 1837 case INDEX_op_and_i32: 1838 if (c2 && a2 != (uint16_t)a2) { 1839 int msb = ctz32(~a2) - 1; 1840 tcg_debug_assert(use_mips32r2_instructions); 1841 tcg_debug_assert(is_p2m1(a2)); 1842 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1843 break; 1844 } 1845 i1 = OPC_AND, i2 = OPC_ANDI; 1846 goto do_binary; 1847 case INDEX_op_and_i64: 1848 if (c2 && a2 != (uint16_t)a2) { 1849 int msb = ctz64(~a2) - 1; 1850 tcg_debug_assert(use_mips32r2_instructions); 1851 tcg_debug_assert(is_p2m1(a2)); 1852 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1853 break; 1854 } 1855 i1 = OPC_AND, i2 = OPC_ANDI; 1856 goto do_binary; 1857 case INDEX_op_nor_i32: 1858 case INDEX_op_nor_i64: 1859 i1 = OPC_NOR; 1860 goto do_binaryv; 1861 1862 case INDEX_op_mul_i32: 1863 if (use_mips32_instructions) { 1864 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1865 break; 1866 } 1867 i1 = OPC_MULT, i2 = OPC_MFLO; 1868 goto do_hilo1; 1869 case INDEX_op_mulsh_i32: 1870 if (use_mips32r6_instructions) { 1871 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1872 break; 1873 } 1874 i1 = OPC_MULT, i2 = OPC_MFHI; 1875 goto do_hilo1; 1876 case INDEX_op_muluh_i32: 1877 if (use_mips32r6_instructions) { 1878 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1879 break; 1880 } 1881 i1 = OPC_MULTU, i2 = OPC_MFHI; 1882 goto do_hilo1; 1883 case INDEX_op_div_i32: 1884 if (use_mips32r6_instructions) { 1885 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1886 break; 1887 } 1888 i1 = OPC_DIV, i2 = OPC_MFLO; 1889 goto do_hilo1; 1890 case INDEX_op_divu_i32: 1891 if (use_mips32r6_instructions) { 1892 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1893 break; 1894 } 1895 i1 = OPC_DIVU, i2 = OPC_MFLO; 1896 goto do_hilo1; 1897 case INDEX_op_rem_i32: 1898 if (use_mips32r6_instructions) { 1899 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1900 break; 1901 } 1902 i1 = OPC_DIV, i2 = OPC_MFHI; 1903 goto do_hilo1; 1904 case INDEX_op_remu_i32: 1905 if (use_mips32r6_instructions) { 1906 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1907 break; 1908 } 1909 i1 = OPC_DIVU, i2 = OPC_MFHI; 1910 goto do_hilo1; 1911 case INDEX_op_mul_i64: 1912 if (use_mips32r6_instructions) { 1913 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1914 break; 1915 } 1916 i1 = OPC_DMULT, i2 = OPC_MFLO; 1917 goto do_hilo1; 1918 case INDEX_op_mulsh_i64: 1919 if (use_mips32r6_instructions) { 1920 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1921 break; 1922 } 1923 i1 = OPC_DMULT, i2 = OPC_MFHI; 1924 goto do_hilo1; 1925 case INDEX_op_muluh_i64: 1926 if (use_mips32r6_instructions) { 1927 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1928 break; 1929 } 1930 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1931 goto do_hilo1; 1932 case INDEX_op_div_i64: 1933 if (use_mips32r6_instructions) { 1934 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1935 break; 1936 } 1937 i1 = OPC_DDIV, i2 = OPC_MFLO; 1938 goto do_hilo1; 1939 case INDEX_op_divu_i64: 1940 if (use_mips32r6_instructions) { 1941 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1942 break; 1943 } 1944 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1945 goto do_hilo1; 1946 case INDEX_op_rem_i64: 1947 if (use_mips32r6_instructions) { 1948 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1949 break; 1950 } 1951 i1 = OPC_DDIV, i2 = OPC_MFHI; 1952 goto do_hilo1; 1953 case INDEX_op_remu_i64: 1954 if (use_mips32r6_instructions) { 1955 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1956 break; 1957 } 1958 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1959 do_hilo1: 1960 tcg_out_opc_reg(s, i1, 0, a1, a2); 1961 tcg_out_opc_reg(s, i2, a0, 0, 0); 1962 break; 1963 1964 case INDEX_op_muls2_i32: 1965 i1 = OPC_MULT; 1966 goto do_hilo2; 1967 case INDEX_op_mulu2_i32: 1968 i1 = OPC_MULTU; 1969 goto do_hilo2; 1970 case INDEX_op_muls2_i64: 1971 i1 = OPC_DMULT; 1972 goto do_hilo2; 1973 case INDEX_op_mulu2_i64: 1974 i1 = OPC_DMULTU; 1975 do_hilo2: 1976 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1977 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1978 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1979 break; 1980 1981 case INDEX_op_not_i32: 1982 case INDEX_op_not_i64: 1983 i1 = OPC_NOR; 1984 goto do_unary; 1985 case INDEX_op_bswap16_i32: 1986 case INDEX_op_bswap16_i64: 1987 i1 = OPC_WSBH; 1988 goto do_unary; 1989 case INDEX_op_ext8s_i32: 1990 case INDEX_op_ext8s_i64: 1991 i1 = OPC_SEB; 1992 goto do_unary; 1993 case INDEX_op_ext16s_i32: 1994 case INDEX_op_ext16s_i64: 1995 i1 = OPC_SEH; 1996 do_unary: 1997 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1998 break; 1999 2000 case INDEX_op_bswap32_i32: 2001 tcg_out_bswap32(s, a0, a1); 2002 break; 2003 case INDEX_op_bswap32_i64: 2004 tcg_out_bswap32u(s, a0, a1); 2005 break; 2006 case INDEX_op_bswap64_i64: 2007 tcg_out_bswap64(s, a0, a1); 2008 break; 2009 case INDEX_op_extrh_i64_i32: 2010 tcg_out_dsra(s, a0, a1, 32); 2011 break; 2012 case INDEX_op_ext32s_i64: 2013 case INDEX_op_ext_i32_i64: 2014 case INDEX_op_extrl_i64_i32: 2015 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); 2016 break; 2017 case INDEX_op_ext32u_i64: 2018 case INDEX_op_extu_i32_i64: 2019 tcg_out_ext32u(s, a0, a1); 2020 break; 2021 2022 case INDEX_op_sar_i32: 2023 i1 = OPC_SRAV, i2 = OPC_SRA; 2024 goto do_shift; 2025 case INDEX_op_shl_i32: 2026 i1 = OPC_SLLV, i2 = OPC_SLL; 2027 goto do_shift; 2028 case INDEX_op_shr_i32: 2029 i1 = OPC_SRLV, i2 = OPC_SRL; 2030 goto do_shift; 2031 case INDEX_op_rotr_i32: 2032 i1 = OPC_ROTRV, i2 = OPC_ROTR; 2033 do_shift: 2034 if (c2) { 2035 tcg_out_opc_sa(s, i2, a0, a1, a2); 2036 break; 2037 } 2038 do_shiftv: 2039 tcg_out_opc_reg(s, i1, a0, a2, a1); 2040 break; 2041 case INDEX_op_rotl_i32: 2042 if (c2) { 2043 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 2044 } else { 2045 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2046 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 2047 } 2048 break; 2049 case INDEX_op_sar_i64: 2050 if (c2) { 2051 tcg_out_dsra(s, a0, a1, a2); 2052 break; 2053 } 2054 i1 = OPC_DSRAV; 2055 goto do_shiftv; 2056 case INDEX_op_shl_i64: 2057 if (c2) { 2058 tcg_out_dsll(s, a0, a1, a2); 2059 break; 2060 } 2061 i1 = OPC_DSLLV; 2062 goto do_shiftv; 2063 case INDEX_op_shr_i64: 2064 if (c2) { 2065 tcg_out_dsrl(s, a0, a1, a2); 2066 break; 2067 } 2068 i1 = OPC_DSRLV; 2069 goto do_shiftv; 2070 case INDEX_op_rotr_i64: 2071 if (c2) { 2072 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2073 break; 2074 } 2075 i1 = OPC_DROTRV; 2076 goto do_shiftv; 2077 case INDEX_op_rotl_i64: 2078 if (c2) { 2079 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2080 } else { 2081 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2082 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2083 } 2084 break; 2085 2086 case INDEX_op_clz_i32: 2087 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2088 break; 2089 case INDEX_op_clz_i64: 2090 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2091 break; 2092 2093 case INDEX_op_deposit_i32: 2094 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2095 break; 2096 case INDEX_op_deposit_i64: 2097 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2098 args[3] + args[4] - 1, args[3]); 2099 break; 2100 case INDEX_op_extract_i32: 2101 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2102 break; 2103 case INDEX_op_extract_i64: 2104 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2105 args[3] - 1, a2); 2106 break; 2107 2108 case INDEX_op_brcond_i32: 2109 case INDEX_op_brcond_i64: 2110 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2111 break; 2112 case INDEX_op_brcond2_i32: 2113 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2114 break; 2115 2116 case INDEX_op_movcond_i32: 2117 case INDEX_op_movcond_i64: 2118 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2119 break; 2120 2121 case INDEX_op_setcond_i32: 2122 case INDEX_op_setcond_i64: 2123 tcg_out_setcond(s, args[3], a0, a1, a2); 2124 break; 2125 case INDEX_op_setcond2_i32: 2126 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2127 break; 2128 2129 case INDEX_op_qemu_ld_i32: 2130 tcg_out_qemu_ld(s, args, false); 2131 break; 2132 case INDEX_op_qemu_ld_i64: 2133 tcg_out_qemu_ld(s, args, true); 2134 break; 2135 case INDEX_op_qemu_st_i32: 2136 tcg_out_qemu_st(s, args, false); 2137 break; 2138 case INDEX_op_qemu_st_i64: 2139 tcg_out_qemu_st(s, args, true); 2140 break; 2141 2142 case INDEX_op_add2_i32: 2143 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2144 const_args[4], const_args[5], false); 2145 break; 2146 case INDEX_op_sub2_i32: 2147 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2148 const_args[4], const_args[5], true); 2149 break; 2150 2151 case INDEX_op_mb: 2152 tcg_out_mb(s, a0); 2153 break; 2154 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2155 case INDEX_op_mov_i64: 2156 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ 2157 case INDEX_op_movi_i64: 2158 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2159 default: 2160 tcg_abort(); 2161 } 2162} 2163 2164static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) 2165{ 2166 static const TCGTargetOpDef r = { .args_ct_str = { "r" } }; 2167 static const TCGTargetOpDef r_r = { .args_ct_str = { "r", "r" } }; 2168 static const TCGTargetOpDef r_L = { .args_ct_str = { "r", "L" } }; 2169 static const TCGTargetOpDef rZ_r = { .args_ct_str = { "rZ", "r" } }; 2170 static const TCGTargetOpDef SZ_S = { .args_ct_str = { "SZ", "S" } }; 2171 static const TCGTargetOpDef rZ_rZ = { .args_ct_str = { "rZ", "rZ" } }; 2172 static const TCGTargetOpDef r_r_L = { .args_ct_str = { "r", "r", "L" } }; 2173 static const TCGTargetOpDef r_L_L = { .args_ct_str = { "r", "L", "L" } }; 2174 static const TCGTargetOpDef r_r_ri = { .args_ct_str = { "r", "r", "ri" } }; 2175 static const TCGTargetOpDef r_r_rI = { .args_ct_str = { "r", "r", "rI" } }; 2176 static const TCGTargetOpDef r_r_rJ = { .args_ct_str = { "r", "r", "rJ" } }; 2177 static const TCGTargetOpDef SZ_S_S = { .args_ct_str = { "SZ", "S", "S" } }; 2178 static const TCGTargetOpDef SZ_SZ_S 2179 = { .args_ct_str = { "SZ", "SZ", "S" } }; 2180 static const TCGTargetOpDef SZ_SZ_S_S 2181 = { .args_ct_str = { "SZ", "SZ", "S", "S" } }; 2182 static const TCGTargetOpDef r_rZ_rN 2183 = { .args_ct_str = { "r", "rZ", "rN" } }; 2184 static const TCGTargetOpDef r_rZ_rZ 2185 = { .args_ct_str = { "r", "rZ", "rZ" } }; 2186 static const TCGTargetOpDef r_r_rIK 2187 = { .args_ct_str = { "r", "r", "rIK" } }; 2188 static const TCGTargetOpDef r_r_rWZ 2189 = { .args_ct_str = { "r", "r", "rWZ" } }; 2190 static const TCGTargetOpDef r_r_r_r 2191 = { .args_ct_str = { "r", "r", "r", "r" } }; 2192 static const TCGTargetOpDef r_r_L_L 2193 = { .args_ct_str = { "r", "r", "L", "L" } }; 2194 static const TCGTargetOpDef dep 2195 = { .args_ct_str = { "r", "0", "rZ" } }; 2196 static const TCGTargetOpDef movc 2197 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "0" } }; 2198 static const TCGTargetOpDef movc_r6 2199 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; 2200 static const TCGTargetOpDef add2 2201 = { .args_ct_str = { "r", "r", "rZ", "rZ", "rN", "rN" } }; 2202 static const TCGTargetOpDef br2 2203 = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; 2204 static const TCGTargetOpDef setc2 2205 = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; 2206 2207 switch (op) { 2208 case INDEX_op_goto_ptr: 2209 return &r; 2210 2211 case INDEX_op_ld8u_i32: 2212 case INDEX_op_ld8s_i32: 2213 case INDEX_op_ld16u_i32: 2214 case INDEX_op_ld16s_i32: 2215 case INDEX_op_ld_i32: 2216 case INDEX_op_not_i32: 2217 case INDEX_op_bswap16_i32: 2218 case INDEX_op_bswap32_i32: 2219 case INDEX_op_ext8s_i32: 2220 case INDEX_op_ext16s_i32: 2221 case INDEX_op_extract_i32: 2222 case INDEX_op_ld8u_i64: 2223 case INDEX_op_ld8s_i64: 2224 case INDEX_op_ld16u_i64: 2225 case INDEX_op_ld16s_i64: 2226 case INDEX_op_ld32s_i64: 2227 case INDEX_op_ld32u_i64: 2228 case INDEX_op_ld_i64: 2229 case INDEX_op_not_i64: 2230 case INDEX_op_bswap16_i64: 2231 case INDEX_op_bswap32_i64: 2232 case INDEX_op_bswap64_i64: 2233 case INDEX_op_ext8s_i64: 2234 case INDEX_op_ext16s_i64: 2235 case INDEX_op_ext32s_i64: 2236 case INDEX_op_ext32u_i64: 2237 case INDEX_op_ext_i32_i64: 2238 case INDEX_op_extu_i32_i64: 2239 case INDEX_op_extrl_i64_i32: 2240 case INDEX_op_extrh_i64_i32: 2241 case INDEX_op_extract_i64: 2242 return &r_r; 2243 2244 case INDEX_op_st8_i32: 2245 case INDEX_op_st16_i32: 2246 case INDEX_op_st_i32: 2247 case INDEX_op_st8_i64: 2248 case INDEX_op_st16_i64: 2249 case INDEX_op_st32_i64: 2250 case INDEX_op_st_i64: 2251 return &rZ_r; 2252 2253 case INDEX_op_add_i32: 2254 case INDEX_op_add_i64: 2255 return &r_r_rJ; 2256 case INDEX_op_sub_i32: 2257 case INDEX_op_sub_i64: 2258 return &r_rZ_rN; 2259 case INDEX_op_mul_i32: 2260 case INDEX_op_mulsh_i32: 2261 case INDEX_op_muluh_i32: 2262 case INDEX_op_div_i32: 2263 case INDEX_op_divu_i32: 2264 case INDEX_op_rem_i32: 2265 case INDEX_op_remu_i32: 2266 case INDEX_op_nor_i32: 2267 case INDEX_op_setcond_i32: 2268 case INDEX_op_mul_i64: 2269 case INDEX_op_mulsh_i64: 2270 case INDEX_op_muluh_i64: 2271 case INDEX_op_div_i64: 2272 case INDEX_op_divu_i64: 2273 case INDEX_op_rem_i64: 2274 case INDEX_op_remu_i64: 2275 case INDEX_op_nor_i64: 2276 case INDEX_op_setcond_i64: 2277 return &r_rZ_rZ; 2278 case INDEX_op_muls2_i32: 2279 case INDEX_op_mulu2_i32: 2280 case INDEX_op_muls2_i64: 2281 case INDEX_op_mulu2_i64: 2282 return &r_r_r_r; 2283 case INDEX_op_and_i32: 2284 case INDEX_op_and_i64: 2285 return &r_r_rIK; 2286 case INDEX_op_or_i32: 2287 case INDEX_op_xor_i32: 2288 case INDEX_op_or_i64: 2289 case INDEX_op_xor_i64: 2290 return &r_r_rI; 2291 case INDEX_op_shl_i32: 2292 case INDEX_op_shr_i32: 2293 case INDEX_op_sar_i32: 2294 case INDEX_op_rotr_i32: 2295 case INDEX_op_rotl_i32: 2296 case INDEX_op_shl_i64: 2297 case INDEX_op_shr_i64: 2298 case INDEX_op_sar_i64: 2299 case INDEX_op_rotr_i64: 2300 case INDEX_op_rotl_i64: 2301 return &r_r_ri; 2302 case INDEX_op_clz_i32: 2303 case INDEX_op_clz_i64: 2304 return &r_r_rWZ; 2305 2306 case INDEX_op_deposit_i32: 2307 case INDEX_op_deposit_i64: 2308 return &dep; 2309 case INDEX_op_brcond_i32: 2310 case INDEX_op_brcond_i64: 2311 return &rZ_rZ; 2312 case INDEX_op_movcond_i32: 2313 case INDEX_op_movcond_i64: 2314 return use_mips32r6_instructions ? &movc_r6 : &movc; 2315 2316 case INDEX_op_add2_i32: 2317 case INDEX_op_sub2_i32: 2318 return &add2; 2319 case INDEX_op_setcond2_i32: 2320 return &setc2; 2321 case INDEX_op_brcond2_i32: 2322 return &br2; 2323 2324 case INDEX_op_qemu_ld_i32: 2325 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2326 ? &r_L : &r_L_L); 2327 case INDEX_op_qemu_st_i32: 2328 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2329 ? &SZ_S : &SZ_S_S); 2330 case INDEX_op_qemu_ld_i64: 2331 return (TCG_TARGET_REG_BITS == 64 ? &r_L 2332 : TARGET_LONG_BITS == 32 ? &r_r_L : &r_r_L_L); 2333 case INDEX_op_qemu_st_i64: 2334 return (TCG_TARGET_REG_BITS == 64 ? &SZ_S 2335 : TARGET_LONG_BITS == 32 ? &SZ_SZ_S : &SZ_SZ_S_S); 2336 2337 default: 2338 return NULL; 2339 } 2340} 2341 2342static const int tcg_target_callee_save_regs[] = { 2343 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2344 TCG_REG_S1, 2345 TCG_REG_S2, 2346 TCG_REG_S3, 2347 TCG_REG_S4, 2348 TCG_REG_S5, 2349 TCG_REG_S6, 2350 TCG_REG_S7, 2351 TCG_REG_S8, 2352 TCG_REG_RA, /* should be last for ABI compliance */ 2353}; 2354 2355/* The Linux kernel doesn't provide any information about the available 2356 instruction set. Probe it using a signal handler. */ 2357 2358 2359#ifndef use_movnz_instructions 2360bool use_movnz_instructions = false; 2361#endif 2362 2363#ifndef use_mips32_instructions 2364bool use_mips32_instructions = false; 2365#endif 2366 2367#ifndef use_mips32r2_instructions 2368bool use_mips32r2_instructions = false; 2369#endif 2370 2371static volatile sig_atomic_t got_sigill; 2372 2373static void sigill_handler(int signo, siginfo_t *si, void *data) 2374{ 2375 /* Skip the faulty instruction */ 2376 ucontext_t *uc = (ucontext_t *)data; 2377 uc->uc_mcontext.pc += 4; 2378 2379 got_sigill = 1; 2380} 2381 2382static void tcg_target_detect_isa(void) 2383{ 2384 struct sigaction sa_old, sa_new; 2385 2386 memset(&sa_new, 0, sizeof(sa_new)); 2387 sa_new.sa_flags = SA_SIGINFO; 2388 sa_new.sa_sigaction = sigill_handler; 2389 sigaction(SIGILL, &sa_new, &sa_old); 2390 2391 /* Probe for movn/movz, necessary to implement movcond. */ 2392#ifndef use_movnz_instructions 2393 got_sigill = 0; 2394 asm volatile(".set push\n" 2395 ".set mips32\n" 2396 "movn $zero, $zero, $zero\n" 2397 "movz $zero, $zero, $zero\n" 2398 ".set pop\n" 2399 : : : ); 2400 use_movnz_instructions = !got_sigill; 2401#endif 2402 2403 /* Probe for MIPS32 instructions. As no subsetting is allowed 2404 by the specification, it is only necessary to probe for one 2405 of the instructions. */ 2406#ifndef use_mips32_instructions 2407 got_sigill = 0; 2408 asm volatile(".set push\n" 2409 ".set mips32\n" 2410 "mul $zero, $zero\n" 2411 ".set pop\n" 2412 : : : ); 2413 use_mips32_instructions = !got_sigill; 2414#endif 2415 2416 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2417 available. As no subsetting is allowed by the specification, 2418 it is only necessary to probe for one of the instructions. */ 2419#ifndef use_mips32r2_instructions 2420 if (use_mips32_instructions) { 2421 got_sigill = 0; 2422 asm volatile(".set push\n" 2423 ".set mips32r2\n" 2424 "seb $zero, $zero\n" 2425 ".set pop\n" 2426 : : : ); 2427 use_mips32r2_instructions = !got_sigill; 2428 } 2429#endif 2430 2431 sigaction(SIGILL, &sa_old, NULL); 2432} 2433 2434static tcg_insn_unit *align_code_ptr(TCGContext *s) 2435{ 2436 uintptr_t p = (uintptr_t)s->code_ptr; 2437 if (p & 15) { 2438 p = (p + 15) & -16; 2439 s->code_ptr = (void *)p; 2440 } 2441 return s->code_ptr; 2442} 2443 2444/* Stack frame parameters. */ 2445#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2446#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2447#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2448 2449#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2450 + TCG_TARGET_STACK_ALIGN - 1) \ 2451 & -TCG_TARGET_STACK_ALIGN) 2452#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2453 2454/* We're expecting to be able to use an immediate for frame allocation. */ 2455QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2456 2457/* Generate global QEMU prologue and epilogue code */ 2458static void tcg_target_qemu_prologue(TCGContext *s) 2459{ 2460 int i; 2461 2462 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2463 2464 /* TB prologue */ 2465 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2466 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2467 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2468 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2469 } 2470 2471#ifndef CONFIG_SOFTMMU 2472 if (guest_base) { 2473 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2474 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2475 } 2476#endif 2477 2478 /* Call generated code */ 2479 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2480 /* delay slot */ 2481 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2482 2483 /* 2484 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2485 * and fall through to the rest of the epilogue. 2486 */ 2487 tcg_code_gen_epilogue = s->code_ptr; 2488 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2489 2490 /* TB epilogue */ 2491 tb_ret_addr = s->code_ptr; 2492 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2493 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2494 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2495 } 2496 2497 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2498 /* delay slot */ 2499 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2500 2501 if (use_mips32r2_instructions) { 2502 return; 2503 } 2504 2505 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2506 clobbers TCG_TMP1, TCG_TMP2. */ 2507 2508 /* 2509 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2510 */ 2511 bswap32_addr = align_code_ptr(s); 2512 /* t3 = (ssss)d000 */ 2513 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2514 /* t1 = 000a */ 2515 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2516 /* t2 = 00c0 */ 2517 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2518 /* t3 = d00a */ 2519 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2520 /* t1 = 0abc */ 2521 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2522 /* t2 = 0c00 */ 2523 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2524 /* t1 = 00b0 */ 2525 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2526 /* t3 = dc0a */ 2527 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2528 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2529 /* t3 = dcba -- delay slot */ 2530 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2531 2532 if (TCG_TARGET_REG_BITS == 32) { 2533 return; 2534 } 2535 2536 /* 2537 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2538 */ 2539 bswap32u_addr = align_code_ptr(s); 2540 /* t1 = (0000)000d */ 2541 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2542 /* t3 = 000a */ 2543 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2544 /* t1 = (0000)d000 */ 2545 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2546 /* t2 = 00c0 */ 2547 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2548 /* t3 = d00a */ 2549 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2550 /* t1 = 0abc */ 2551 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2552 /* t2 = 0c00 */ 2553 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2554 /* t1 = 00b0 */ 2555 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2556 /* t3 = dc0a */ 2557 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2558 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2559 /* t3 = dcba -- delay slot */ 2560 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2561 2562 /* 2563 * bswap64 -- 64-bit swap. a0 = abcdefgh 2564 */ 2565 bswap64_addr = align_code_ptr(s); 2566 /* t3 = h0000000 */ 2567 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2568 /* t1 = 0000000a */ 2569 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2570 2571 /* t2 = 000000g0 */ 2572 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2573 /* t3 = h000000a */ 2574 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2575 /* t1 = 00000abc */ 2576 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2577 /* t2 = 0g000000 */ 2578 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2579 /* t1 = 000000b0 */ 2580 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2581 2582 /* t3 = hg00000a */ 2583 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2584 /* t2 = 0000abcd */ 2585 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2586 /* t3 = hg0000ba */ 2587 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2588 2589 /* t1 = 000000c0 */ 2590 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2591 /* t2 = 0000000d */ 2592 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2593 /* t1 = 00000c00 */ 2594 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2595 /* t2 = 0000d000 */ 2596 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2597 2598 /* t3 = hg000cba */ 2599 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2600 /* t1 = 00abcdef */ 2601 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2602 /* t3 = hg00dcba */ 2603 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2604 2605 /* t2 = 0000000f */ 2606 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2607 /* t1 = 000000e0 */ 2608 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2609 /* t2 = 00f00000 */ 2610 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2611 /* t1 = 000e0000 */ 2612 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2613 2614 /* t3 = hgf0dcba */ 2615 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2616 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2617 /* t3 = hgfedcba -- delay slot */ 2618 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2619} 2620 2621static void tcg_target_init(TCGContext *s) 2622{ 2623 tcg_target_detect_isa(); 2624 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2625 if (TCG_TARGET_REG_BITS == 64) { 2626 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2627 } 2628 2629 tcg_target_call_clobber_regs = 0; 2630 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2631 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2632 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2633 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2634 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2635 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2636 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2637 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2638 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2639 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2640 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2641 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2642 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2643 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2644 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2645 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2646 2647 s->reserved_regs = 0; 2648 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2649 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2650 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2651 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2652 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2653 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2654 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2655 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2656 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2657 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2658} 2659 2660void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr, 2661 uintptr_t addr) 2662{ 2663 qatomic_set((uint32_t *)jmp_addr, deposit32(OPC_J, 0, 26, addr >> 2)); 2664 flush_idcache_range(jmp_addr, jmp_addr, 4); 2665} 2666 2667typedef struct { 2668 DebugFrameHeader h; 2669 uint8_t fde_def_cfa[4]; 2670 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2671} DebugFrame; 2672 2673#define ELF_HOST_MACHINE EM_MIPS 2674/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2675 which is good because they're really quite complicated for MIPS. */ 2676 2677static const DebugFrame debug_frame = { 2678 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2679 .h.cie.id = -1, 2680 .h.cie.version = 1, 2681 .h.cie.code_align = 1, 2682 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2683 .h.cie.return_column = TCG_REG_RA, 2684 2685 /* Total FDE size does not include the "len" member. */ 2686 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2687 2688 .fde_def_cfa = { 2689 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2690 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2691 (FRAME_SIZE >> 7) 2692 }, 2693 .fde_reg_ofs = { 2694 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2695 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2696 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2697 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2698 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2699 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2700 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2701 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2702 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2703 } 2704}; 2705 2706void tcg_register_jit(const void *buf, size_t buf_size) 2707{ 2708 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2709} 2710