1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */ 191#define TCG_CT_CONST_WSZ 0x1000 /* word size */ 192 193#define ALL_GENERAL_REGS 0xffffffffu 194 195static bool is_p2m1(tcg_target_long val) 196{ 197 return val && ((val + 1) & val) == 0; 198} 199 200/* test if a constant matches the constraint */ 201static bool tcg_target_const_match(int64_t val, int ct, 202 TCGType type, TCGCond cond, int vece) 203{ 204 if (ct & TCG_CT_CONST) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_P2M1) 213 && use_mips32r2_instructions && is_p2m1(val)) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_WSZ) 216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 217 return 1; 218 } 219 return 0; 220} 221 222/* instruction opcodes */ 223typedef enum { 224 OPC_J = 002 << 26, 225 OPC_JAL = 003 << 26, 226 OPC_BEQ = 004 << 26, 227 OPC_BNE = 005 << 26, 228 OPC_BLEZ = 006 << 26, 229 OPC_BGTZ = 007 << 26, 230 OPC_ADDIU = 011 << 26, 231 OPC_SLTI = 012 << 26, 232 OPC_SLTIU = 013 << 26, 233 OPC_ANDI = 014 << 26, 234 OPC_ORI = 015 << 26, 235 OPC_XORI = 016 << 26, 236 OPC_LUI = 017 << 26, 237 OPC_BNEL = 025 << 26, 238 OPC_BNEZALC_R6 = 030 << 26, 239 OPC_DADDIU = 031 << 26, 240 OPC_LDL = 032 << 26, 241 OPC_LDR = 033 << 26, 242 OPC_LB = 040 << 26, 243 OPC_LH = 041 << 26, 244 OPC_LWL = 042 << 26, 245 OPC_LW = 043 << 26, 246 OPC_LBU = 044 << 26, 247 OPC_LHU = 045 << 26, 248 OPC_LWR = 046 << 26, 249 OPC_LWU = 047 << 26, 250 OPC_SB = 050 << 26, 251 OPC_SH = 051 << 26, 252 OPC_SWL = 052 << 26, 253 OPC_SW = 053 << 26, 254 OPC_SDL = 054 << 26, 255 OPC_SDR = 055 << 26, 256 OPC_SWR = 056 << 26, 257 OPC_LD = 067 << 26, 258 OPC_SD = 077 << 26, 259 260 OPC_SPECIAL = 000 << 26, 261 OPC_SLL = OPC_SPECIAL | 000, 262 OPC_SRL = OPC_SPECIAL | 002, 263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 264 OPC_SRA = OPC_SPECIAL | 003, 265 OPC_SLLV = OPC_SPECIAL | 004, 266 OPC_SRLV = OPC_SPECIAL | 006, 267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 268 OPC_SRAV = OPC_SPECIAL | 007, 269 OPC_JR_R5 = OPC_SPECIAL | 010, 270 OPC_JALR = OPC_SPECIAL | 011, 271 OPC_MOVZ = OPC_SPECIAL | 012, 272 OPC_MOVN = OPC_SPECIAL | 013, 273 OPC_SYNC = OPC_SPECIAL | 017, 274 OPC_MFHI = OPC_SPECIAL | 020, 275 OPC_MFLO = OPC_SPECIAL | 022, 276 OPC_DSLLV = OPC_SPECIAL | 024, 277 OPC_DSRLV = OPC_SPECIAL | 026, 278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 279 OPC_DSRAV = OPC_SPECIAL | 027, 280 OPC_MULT = OPC_SPECIAL | 030, 281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 282 OPC_MUH = OPC_SPECIAL | 030 | 0300, 283 OPC_MULTU = OPC_SPECIAL | 031, 284 OPC_MULU = OPC_SPECIAL | 031 | 0200, 285 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 286 OPC_DIV = OPC_SPECIAL | 032, 287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 288 OPC_MOD = OPC_SPECIAL | 032 | 0300, 289 OPC_DIVU = OPC_SPECIAL | 033, 290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 291 OPC_MODU = OPC_SPECIAL | 033 | 0300, 292 OPC_DMULT = OPC_SPECIAL | 034, 293 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 294 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 295 OPC_DMULTU = OPC_SPECIAL | 035, 296 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 298 OPC_DDIV = OPC_SPECIAL | 036, 299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 300 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 301 OPC_DDIVU = OPC_SPECIAL | 037, 302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 303 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 304 OPC_ADDU = OPC_SPECIAL | 041, 305 OPC_SUBU = OPC_SPECIAL | 043, 306 OPC_AND = OPC_SPECIAL | 044, 307 OPC_OR = OPC_SPECIAL | 045, 308 OPC_XOR = OPC_SPECIAL | 046, 309 OPC_NOR = OPC_SPECIAL | 047, 310 OPC_SLT = OPC_SPECIAL | 052, 311 OPC_SLTU = OPC_SPECIAL | 053, 312 OPC_DADDU = OPC_SPECIAL | 055, 313 OPC_DSUBU = OPC_SPECIAL | 057, 314 OPC_SELEQZ = OPC_SPECIAL | 065, 315 OPC_SELNEZ = OPC_SPECIAL | 067, 316 OPC_DSLL = OPC_SPECIAL | 070, 317 OPC_DSRL = OPC_SPECIAL | 072, 318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 319 OPC_DSRA = OPC_SPECIAL | 073, 320 OPC_DSLL32 = OPC_SPECIAL | 074, 321 OPC_DSRL32 = OPC_SPECIAL | 076, 322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 323 OPC_DSRA32 = OPC_SPECIAL | 077, 324 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 326 327 OPC_REGIMM = 001 << 26, 328 OPC_BLTZ = OPC_REGIMM | (000 << 16), 329 OPC_BGEZ = OPC_REGIMM | (001 << 16), 330 331 OPC_SPECIAL2 = 034 << 26, 332 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 333 OPC_CLZ = OPC_SPECIAL2 | 040, 334 OPC_DCLZ = OPC_SPECIAL2 | 044, 335 336 OPC_SPECIAL3 = 037 << 26, 337 OPC_EXT = OPC_SPECIAL3 | 000, 338 OPC_DEXTM = OPC_SPECIAL3 | 001, 339 OPC_DEXTU = OPC_SPECIAL3 | 002, 340 OPC_DEXT = OPC_SPECIAL3 | 003, 341 OPC_INS = OPC_SPECIAL3 | 004, 342 OPC_DINSM = OPC_SPECIAL3 | 005, 343 OPC_DINSU = OPC_SPECIAL3 | 006, 344 OPC_DINS = OPC_SPECIAL3 | 007, 345 OPC_WSBH = OPC_SPECIAL3 | 00240, 346 OPC_DSBH = OPC_SPECIAL3 | 00244, 347 OPC_DSHD = OPC_SPECIAL3 | 00544, 348 OPC_SEB = OPC_SPECIAL3 | 02040, 349 OPC_SEH = OPC_SPECIAL3 | 03040, 350 351 /* MIPS r6 doesn't have JR, JALR should be used instead */ 352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 353 354 /* 355 * MIPS r6 replaces MUL with an alternative encoding which is 356 * backwards-compatible at the assembly level. 357 */ 358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 359 360 /* MIPS r6 introduced names for weaker variants of SYNC. These are 361 backward compatible to previous architecture revisions. */ 362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 367 368 /* Aliases for convenience. */ 369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 371} MIPSInsn; 372 373/* 374 * Type reg 375 */ 376static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 377 TCGReg rd, TCGReg rs, TCGReg rt) 378{ 379 int32_t inst; 380 381 inst = opc; 382 inst |= (rs & 0x1F) << 21; 383 inst |= (rt & 0x1F) << 16; 384 inst |= (rd & 0x1F) << 11; 385 tcg_out32(s, inst); 386} 387 388/* 389 * Type immediate 390 */ 391static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 392 TCGReg rt, TCGReg rs, TCGArg imm) 393{ 394 int32_t inst; 395 396 inst = opc; 397 inst |= (rs & 0x1F) << 21; 398 inst |= (rt & 0x1F) << 16; 399 inst |= (imm & 0xffff); 400 tcg_out32(s, inst); 401} 402 403/* 404 * Type bitfield 405 */ 406static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 407 TCGReg rs, int msb, int lsb) 408{ 409 int32_t inst; 410 411 inst = opc; 412 inst |= (rs & 0x1F) << 21; 413 inst |= (rt & 0x1F) << 16; 414 inst |= (msb & 0x1F) << 11; 415 inst |= (lsb & 0x1F) << 6; 416 tcg_out32(s, inst); 417} 418 419static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 420 MIPSInsn oph, TCGReg rt, TCGReg rs, 421 int msb, int lsb) 422{ 423 if (lsb >= 32) { 424 opc = oph; 425 msb -= 32; 426 lsb -= 32; 427 } else if (msb >= 32) { 428 opc = opm; 429 msb -= 32; 430 } 431 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 432} 433 434/* 435 * Type branch 436 */ 437static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 438{ 439 tcg_out_opc_imm(s, opc, rt, rs, 0); 440} 441 442/* 443 * Type sa 444 */ 445static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 446 TCGReg rd, TCGReg rt, TCGArg sa) 447{ 448 int32_t inst; 449 450 inst = opc; 451 inst |= (rt & 0x1F) << 16; 452 inst |= (rd & 0x1F) << 11; 453 inst |= (sa & 0x1F) << 6; 454 tcg_out32(s, inst); 455 456} 457 458static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 459 TCGReg rd, TCGReg rt, TCGArg sa) 460{ 461 int32_t inst; 462 463 inst = (sa & 32 ? opc2 : opc1); 464 inst |= (rt & 0x1F) << 16; 465 inst |= (rd & 0x1F) << 11; 466 inst |= (sa & 0x1F) << 6; 467 tcg_out32(s, inst); 468} 469 470/* 471 * Type jump. 472 * Returns true if the branch was in range and the insn was emitted. 473 */ 474static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 475{ 476 uintptr_t dest = (uintptr_t)target; 477 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 478 int32_t inst; 479 480 /* The pc-region branch happens within the 256MB region of 481 the delay slot (thus the +4). */ 482 if ((from ^ dest) & -(1 << 28)) { 483 return false; 484 } 485 tcg_debug_assert((dest & 3) == 0); 486 487 inst = opc; 488 inst |= (dest >> 2) & 0x3ffffff; 489 tcg_out32(s, inst); 490 return true; 491} 492 493static void tcg_out_nop(TCGContext *s) 494{ 495 tcg_out32(s, 0); 496} 497 498static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 499{ 500 memset(p, 0, count * sizeof(tcg_insn_unit)); 501} 502 503static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 504{ 505 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 506} 507 508static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 509{ 510 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 511} 512 513static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 514{ 515 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 516} 517 518static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 519{ 520 /* Simple reg-reg move, optimising out the 'do nothing' case */ 521 if (ret != arg) { 522 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 523 } 524 return true; 525} 526 527static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 528{ 529 if (arg == (int16_t)arg) { 530 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 531 return true; 532 } 533 if (arg == (uint16_t)arg) { 534 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 535 return true; 536 } 537 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 538 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 539 return true; 540 } 541 return false; 542} 543 544static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 545{ 546 /* 547 * All signed 32-bit constants are loadable with two immediates, 548 * and everything else requires more work. 549 */ 550 if (arg == (int32_t)arg) { 551 if (!tcg_out_movi_one(s, ret, arg)) { 552 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 553 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 554 } 555 return true; 556 } 557 return false; 558} 559 560static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 561 tcg_target_long arg, TCGReg tbreg) 562{ 563 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 564 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 565} 566 567static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 568 tcg_target_long arg, TCGReg tbreg) 569{ 570 tcg_target_long tmp; 571 int sh, lo; 572 573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 574 arg = (int32_t)arg; 575 } 576 577 /* Load all 32-bit constants. */ 578 if (tcg_out_movi_two(s, ret, arg)) { 579 return; 580 } 581 assert(TCG_TARGET_REG_BITS == 64); 582 583 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 584 tmp = tcg_tbrel_diff(s, (void *)arg); 585 if (tmp == (int16_t)tmp) { 586 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 587 return; 588 } 589 if (tcg_out_movi_two(s, ret, tmp)) { 590 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 591 return; 592 } 593 594 /* 595 * Load bitmasks with a right-shift. This is good for things 596 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 597 * or similarly using LUI. For this to work, bit 31 must be set. 598 */ 599 if (arg > 0 && (int32_t)arg < 0) { 600 sh = clz64(arg); 601 if (tcg_out_movi_one(s, ret, arg << sh)) { 602 tcg_out_dsrl(s, ret, ret, sh); 603 return; 604 } 605 } 606 607 /* 608 * Load slightly larger constants using left-shift. 609 * Limit this sequence to 3 insns to avoid too much expansion. 610 */ 611 sh = ctz64(arg); 612 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 613 tcg_out_dsll(s, ret, ret, sh); 614 return; 615 } 616 617 /* 618 * Load slightly larger constants using left-shift and add/or. 619 * Prefer addi with a negative immediate when that would produce 620 * a larger shift. For this to work, bits 15 and 16 must be set. 621 */ 622 lo = arg & 0xffff; 623 if (lo) { 624 if ((arg & 0x18000) == 0x18000) { 625 lo = (int16_t)arg; 626 } 627 tmp = arg - lo; 628 sh = ctz64(tmp); 629 tmp >>= sh; 630 if (tcg_out_movi_one(s, ret, tmp)) { 631 tcg_out_dsll(s, ret, ret, sh); 632 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 633 return; 634 } 635 } 636 637 /* Otherwise, put 64-bit constants into the constant pool. */ 638 tcg_out_movi_pool(s, ret, arg, tbreg); 639} 640 641static void tcg_out_movi(TCGContext *s, TCGType type, 642 TCGReg ret, tcg_target_long arg) 643{ 644 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 645 tcg_out_movi_int(s, type, ret, arg, tbreg); 646} 647 648static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 649{ 650 tcg_debug_assert(use_mips32r2_instructions); 651 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 652} 653 654static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 655{ 656 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 657} 658 659static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 660{ 661 tcg_debug_assert(use_mips32r2_instructions); 662 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 663} 664 665static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 666{ 667 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 668} 669 670static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 671{ 672 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 673 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 674} 675 676static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 if (rd != rs) { 679 tcg_out_ext32s(s, rd, rs); 680 } 681} 682 683static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 684{ 685 tcg_out_ext32u(s, rd, rs); 686} 687 688static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 689{ 690 tcg_out_ext32s(s, rd, rs); 691} 692 693static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 694{ 695 return false; 696} 697 698static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 699 tcg_target_long imm) 700{ 701 /* This function is only used for passing structs by reference. */ 702 g_assert_not_reached(); 703} 704 705static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 706{ 707 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 708 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 709 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 710 } 711} 712 713static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 714{ 715 if (use_mips32r2_instructions) { 716 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 717 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 718 } else { 719 tcg_out_bswap_subr(s, bswap64_addr); 720 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 721 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 722 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 723 } 724} 725 726static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 727{ 728 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 729 if (use_mips32r2_instructions) { 730 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 731 } else { 732 tcg_out_dsll(s, ret, arg, 32); 733 tcg_out_dsrl(s, ret, ret, 32); 734 } 735} 736 737static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 738 TCGReg addr, intptr_t ofs) 739{ 740 int16_t lo = ofs; 741 if (ofs != lo) { 742 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 743 if (addr != TCG_REG_ZERO) { 744 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 745 } 746 addr = TCG_TMP0; 747 } 748 tcg_out_opc_imm(s, opc, data, addr, lo); 749} 750 751static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 752 TCGReg arg1, intptr_t arg2) 753{ 754 MIPSInsn opc = OPC_LD; 755 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 756 opc = OPC_LW; 757 } 758 tcg_out_ldst(s, opc, arg, arg1, arg2); 759} 760 761static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 762 TCGReg arg1, intptr_t arg2) 763{ 764 MIPSInsn opc = OPC_SD; 765 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 766 opc = OPC_SW; 767 } 768 tcg_out_ldst(s, opc, arg, arg1, arg2); 769} 770 771static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 772 TCGReg base, intptr_t ofs) 773{ 774 if (val == 0) { 775 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 776 return true; 777 } 778 return false; 779} 780 781static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 782 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 783 bool cbh, bool is_sub) 784{ 785 TCGReg th = TCG_TMP1; 786 787 /* If we have a negative constant such that negating it would 788 make the high part zero, we can (usually) eliminate one insn. */ 789 if (cbl && cbh && bh == -1 && bl != 0) { 790 bl = -bl; 791 bh = 0; 792 is_sub = !is_sub; 793 } 794 795 /* By operating on the high part first, we get to use the final 796 carry operation to move back from the temporary. */ 797 if (!cbh) { 798 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 799 } else if (bh != 0 || ah == rl) { 800 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 801 } else { 802 th = ah; 803 } 804 805 /* Note that tcg optimization should eliminate the bl == 0 case. */ 806 if (is_sub) { 807 if (cbl) { 808 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 809 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 810 } else { 811 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 812 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 813 } 814 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 815 } else { 816 if (cbl) { 817 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 818 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 819 } else if (rl == al && rl == bl) { 820 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 821 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 822 } else { 823 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 824 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 825 } 826 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 827 } 828} 829 830#define SETCOND_INV TCG_TARGET_NB_REGS 831#define SETCOND_NEZ (SETCOND_INV << 1) 832#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 833 834static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 835 TCGReg arg1, TCGReg arg2) 836{ 837 int flags = 0; 838 839 switch (cond) { 840 case TCG_COND_EQ: /* -> NE */ 841 case TCG_COND_GE: /* -> LT */ 842 case TCG_COND_GEU: /* -> LTU */ 843 case TCG_COND_LE: /* -> GT */ 844 case TCG_COND_LEU: /* -> GTU */ 845 cond = tcg_invert_cond(cond); 846 flags ^= SETCOND_INV; 847 break; 848 default: 849 break; 850 } 851 852 switch (cond) { 853 case TCG_COND_NE: 854 flags |= SETCOND_NEZ; 855 if (arg2 == 0) { 856 return arg1 | flags; 857 } 858 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 859 break; 860 case TCG_COND_LT: 861 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 862 break; 863 case TCG_COND_LTU: 864 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 865 break; 866 case TCG_COND_GT: 867 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 868 break; 869 case TCG_COND_GTU: 870 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 871 break; 872 default: 873 g_assert_not_reached(); 874 } 875 return ret | flags; 876} 877 878static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 879{ 880 if (tmpflags != ret) { 881 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 882 883 switch (tmpflags & SETCOND_FLAGS) { 884 case SETCOND_INV: 885 /* Intermediate result is boolean: simply invert. */ 886 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 887 break; 888 case SETCOND_NEZ: 889 /* Intermediate result is zero/non-zero: test != 0. */ 890 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 891 break; 892 case SETCOND_NEZ | SETCOND_INV: 893 /* Intermediate result is zero/non-zero: test == 0. */ 894 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 895 break; 896 default: 897 g_assert_not_reached(); 898 } 899 } 900} 901 902static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 903 TCGReg ret, TCGReg arg1, TCGReg arg2) 904{ 905 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 906 tcg_out_setcond_end(s, ret, tmpflags); 907} 908 909static const TCGOutOpSetcond outop_setcond = { 910 .base.static_constraint = C_O1_I2(r, r, rz), 911 .out_rrr = tgen_setcond, 912}; 913 914static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 915 TCGReg ret, TCGReg arg1, TCGReg arg2) 916{ 917 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 918 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 919 920 /* If intermediate result is zero/non-zero: test != 0. */ 921 if (tmpflags & SETCOND_NEZ) { 922 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 923 tmp = ret; 924 } 925 /* Produce the 0/-1 result. */ 926 if (tmpflags & SETCOND_INV) { 927 tcg_out_opc_imm(s, OPC_ADDIU, ret, tmp, -1); 928 } else { 929 tcg_out_opc_reg(s, OPC_SUBU, ret, TCG_REG_ZERO, tmp); 930 } 931} 932 933static const TCGOutOpSetcond outop_negsetcond = { 934 .base.static_constraint = C_O1_I2(r, r, rz), 935 .out_rrr = tgen_negsetcond, 936}; 937 938static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 939 TCGReg arg1, TCGReg arg2, TCGLabel *l) 940{ 941 static const MIPSInsn b_zero[16] = { 942 [TCG_COND_LT] = OPC_BLTZ, 943 [TCG_COND_GT] = OPC_BGTZ, 944 [TCG_COND_LE] = OPC_BLEZ, 945 [TCG_COND_GE] = OPC_BGEZ, 946 }; 947 948 MIPSInsn b_opc = 0; 949 950 switch (cond) { 951 case TCG_COND_EQ: 952 b_opc = OPC_BEQ; 953 break; 954 case TCG_COND_NE: 955 b_opc = OPC_BNE; 956 break; 957 case TCG_COND_LT: 958 case TCG_COND_GT: 959 case TCG_COND_LE: 960 case TCG_COND_GE: 961 if (arg2 == 0) { 962 b_opc = b_zero[cond]; 963 arg2 = arg1; 964 arg1 = 0; 965 } 966 break; 967 default: 968 break; 969 } 970 971 if (b_opc == 0) { 972 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 973 974 arg2 = TCG_REG_ZERO; 975 arg1 = tmpflags & ~SETCOND_FLAGS; 976 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 977 } 978 979 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 980 tcg_out_opc_br(s, b_opc, arg1, arg2); 981 tcg_out_nop(s); 982} 983 984static const TCGOutOpBrcond outop_brcond = { 985 .base.static_constraint = C_O0_I2(r, rz), 986 .out_rr = tgen_brcond, 987}; 988 989static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 990 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 991{ 992 int flags = 0; 993 994 switch (cond) { 995 case TCG_COND_EQ: 996 flags |= SETCOND_INV; 997 /* fall through */ 998 case TCG_COND_NE: 999 flags |= SETCOND_NEZ; 1000 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 1001 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 1002 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1003 break; 1004 1005 default: 1006 tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); 1007 tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), 1008 TCG_TMP1, al, bl); 1009 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 1010 tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); 1011 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1012 break; 1013 } 1014 return ret | flags; 1015} 1016 1017static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1018 TCGReg al, TCGReg ah, 1019 TCGArg bl, bool const_bl, 1020 TCGArg bh, bool const_bh) 1021{ 1022 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1023 tcg_out_setcond_end(s, ret, tmpflags); 1024} 1025 1026#if TCG_TARGET_REG_BITS != 32 1027__attribute__((unused)) 1028#endif 1029static const TCGOutOpSetcond2 outop_setcond2 = { 1030 .base.static_constraint = C_O1_I4(r, r, r, rz, rz), 1031 .out = tgen_setcond2, 1032}; 1033 1034static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1035 TCGArg bl, bool const_bl, 1036 TCGArg bh, bool const_bh, TCGLabel *l) 1037{ 1038 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1039 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1040 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1041 1042 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1043 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1044 tcg_out_nop(s); 1045} 1046 1047#if TCG_TARGET_REG_BITS != 32 1048__attribute__((unused)) 1049#endif 1050static const TCGOutOpBrcond2 outop_brcond2 = { 1051 .base.static_constraint = C_O0_I4(r, r, rz, rz), 1052 .out = tgen_brcond2, 1053}; 1054 1055static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 1056 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 1057 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 1058{ 1059 int tmpflags; 1060 bool eqz; 1061 1062 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1063 if (use_mips32r6_instructions && v1 == 0) { 1064 v1 = v2; 1065 v2 = 0; 1066 cond = tcg_invert_cond(cond); 1067 } 1068 1069 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1070 c1 = tmpflags & ~SETCOND_FLAGS; 1071 eqz = tmpflags & SETCOND_INV; 1072 1073 if (use_mips32r6_instructions) { 1074 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1075 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1076 1077 if (v2 != 0) { 1078 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1079 } 1080 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1081 if (v2 != 0) { 1082 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1083 } 1084 return; 1085 } 1086 1087 /* This should be guaranteed via constraints */ 1088 tcg_debug_assert(v2 == ret); 1089 1090 if (use_movnz_instructions) { 1091 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1092 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1093 } else { 1094 /* Invert the condition in order to branch over the move. */ 1095 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1096 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1097 tcg_out_nop(s); 1098 /* Open-code tcg_out_mov, without the nop-move check. */ 1099 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1100 } 1101} 1102 1103static const TCGOutOpMovcond outop_movcond = { 1104 .base.static_constraint = (use_mips32r6_instructions 1105 ? C_O1_I4(r, r, rz, rz, rz) 1106 : C_O1_I4(r, r, rz, rz, 0)), 1107 .out = tgen_movcond, 1108}; 1109 1110static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1111{ 1112 /* 1113 * Note that __mips_abicalls requires the called function's address 1114 * to be loaded into $25 (t9), even if a direct branch is in range. 1115 * 1116 * For n64, always drop the pointer into the constant pool. 1117 * We can re-use helper addresses often and do not want any 1118 * of the longer sequences tcg_out_movi may try. 1119 */ 1120 if (sizeof(uintptr_t) == 8) { 1121 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1122 } else { 1123 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1124 } 1125 1126 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1127 if (tail) { 1128 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1129 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1130 } 1131 } else { 1132 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1133 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1134 } 1135 } 1136} 1137 1138static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1139 const TCGHelperInfo *info) 1140{ 1141 tcg_out_call_int(s, arg, false); 1142 tcg_out_nop(s); 1143} 1144 1145/* We have four temps, we might as well expose three of them. */ 1146static const TCGLdstHelperParam ldst_helper_param = { 1147 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1148}; 1149 1150static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1151{ 1152 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1153 MemOp opc = get_memop(l->oi); 1154 1155 /* resolve label address */ 1156 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1157 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1158 return false; 1159 } 1160 1161 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1162 1163 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1164 /* delay slot */ 1165 tcg_out_nop(s); 1166 1167 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1168 1169 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1170 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1171 return false; 1172 } 1173 1174 /* delay slot */ 1175 tcg_out_nop(s); 1176 return true; 1177} 1178 1179static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1180{ 1181 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1182 MemOp opc = get_memop(l->oi); 1183 1184 /* resolve label address */ 1185 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1186 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1187 return false; 1188 } 1189 1190 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1191 1192 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1193 /* delay slot */ 1194 tcg_out_nop(s); 1195 1196 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1197 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1198 return false; 1199 } 1200 1201 /* delay slot */ 1202 tcg_out_nop(s); 1203 return true; 1204} 1205 1206typedef struct { 1207 TCGReg base; 1208 TCGAtomAlign aa; 1209} HostAddress; 1210 1211bool tcg_target_has_memory_bswap(MemOp memop) 1212{ 1213 return false; 1214} 1215 1216/* We expect to use a 16-bit negative offset from ENV. */ 1217#define MIN_TLB_MASK_TABLE_OFS -32768 1218 1219/* 1220 * For system-mode, perform the TLB load and compare. 1221 * For user-mode, perform any required alignment tests. 1222 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1223 * is required and fill in @h with the host address for the fast path. 1224 */ 1225static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1226 TCGReg addr, MemOpIdx oi, bool is_ld) 1227{ 1228 TCGType addr_type = s->addr_type; 1229 TCGLabelQemuLdst *ldst = NULL; 1230 MemOp opc = get_memop(oi); 1231 MemOp a_bits; 1232 unsigned s_bits = opc & MO_SIZE; 1233 unsigned a_mask; 1234 TCGReg base; 1235 1236 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1237 a_bits = h->aa.align; 1238 a_mask = (1 << a_bits) - 1; 1239 1240 if (tcg_use_softmmu) { 1241 unsigned s_mask = (1 << s_bits) - 1; 1242 int mem_index = get_mmuidx(oi); 1243 int fast_off = tlb_mask_table_ofs(s, mem_index); 1244 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1245 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1246 int add_off = offsetof(CPUTLBEntry, addend); 1247 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1248 : offsetof(CPUTLBEntry, addr_write); 1249 1250 ldst = new_ldst_label(s); 1251 ldst->is_ld = is_ld; 1252 ldst->oi = oi; 1253 ldst->addr_reg = addr; 1254 1255 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1256 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1257 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1258 1259 /* Extract the TLB index from the address into TMP3. */ 1260 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1261 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1262 s->page_bits - CPU_TLB_ENTRY_BITS); 1263 } else { 1264 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1265 } 1266 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1267 1268 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1269 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1270 1271 /* Load the tlb comparator. */ 1272 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1273 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1274 cmp_off + HOST_BIG_ENDIAN * 4); 1275 } else { 1276 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1277 } 1278 1279 /* Load the tlb addend for the fast path. */ 1280 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1281 1282 /* 1283 * Mask the page bits, keeping the alignment bits to compare against. 1284 * For unaligned accesses, compare against the end of the access to 1285 * verify that it does not cross a page boundary. 1286 */ 1287 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1288 if (a_mask < s_mask) { 1289 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1290 || addr_type == TCG_TYPE_I32 1291 ? OPC_ADDIU : OPC_DADDIU), 1292 TCG_TMP2, addr, s_mask - a_mask); 1293 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1294 } else { 1295 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1296 } 1297 1298 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1299 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1300 tcg_out_ext32u(s, TCG_TMP2, addr); 1301 addr = TCG_TMP2; 1302 } 1303 1304 ldst->label_ptr[0] = s->code_ptr; 1305 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1306 1307 /* delay slot */ 1308 base = TCG_TMP3; 1309 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1310 } else { 1311 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1312 ldst = new_ldst_label(s); 1313 1314 ldst->is_ld = is_ld; 1315 ldst->oi = oi; 1316 ldst->addr_reg = addr; 1317 1318 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1319 tcg_debug_assert(a_bits < 16); 1320 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1321 1322 ldst->label_ptr[0] = s->code_ptr; 1323 if (use_mips32r6_instructions) { 1324 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1325 } else { 1326 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1327 tcg_out_nop(s); 1328 } 1329 } 1330 1331 base = addr; 1332 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1333 tcg_out_ext32u(s, TCG_REG_A0, base); 1334 base = TCG_REG_A0; 1335 } 1336 if (guest_base) { 1337 if (guest_base == (int16_t)guest_base) { 1338 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1339 } else { 1340 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1341 TCG_GUEST_BASE_REG); 1342 } 1343 base = TCG_REG_A0; 1344 } 1345 } 1346 1347 h->base = base; 1348 return ldst; 1349} 1350 1351static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1352 TCGReg base, MemOp opc, TCGType type) 1353{ 1354 switch (opc & MO_SSIZE) { 1355 case MO_UB: 1356 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1357 break; 1358 case MO_SB: 1359 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1360 break; 1361 case MO_UW: 1362 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1363 break; 1364 case MO_SW: 1365 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1366 break; 1367 case MO_UL: 1368 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1369 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1370 break; 1371 } 1372 /* FALLTHRU */ 1373 case MO_SL: 1374 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1375 break; 1376 case MO_UQ: 1377 /* Prefer to load from offset 0 first, but allow for overlap. */ 1378 if (TCG_TARGET_REG_BITS == 64) { 1379 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1380 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1381 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1382 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1383 } else { 1384 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1385 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1386 } 1387 break; 1388 default: 1389 g_assert_not_reached(); 1390 } 1391} 1392 1393static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1394 TCGReg base, MemOp opc, TCGType type) 1395{ 1396 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1397 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1398 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1399 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1400 bool sgn = opc & MO_SIGN; 1401 1402 switch (opc & MO_SIZE) { 1403 case MO_16: 1404 if (HOST_BIG_ENDIAN) { 1405 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1406 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1407 if (use_mips32r2_instructions) { 1408 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1409 } else { 1410 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1411 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1412 } 1413 } else if (use_mips32r2_instructions && lo != base) { 1414 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1415 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1416 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1417 } else { 1418 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1419 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1420 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1421 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1422 } 1423 break; 1424 1425 case MO_32: 1426 tcg_out_opc_imm(s, lw1, lo, base, 0); 1427 tcg_out_opc_imm(s, lw2, lo, base, 3); 1428 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1429 tcg_out_ext32u(s, lo, lo); 1430 } 1431 break; 1432 1433 case MO_64: 1434 if (TCG_TARGET_REG_BITS == 64) { 1435 tcg_out_opc_imm(s, ld1, lo, base, 0); 1436 tcg_out_opc_imm(s, ld2, lo, base, 7); 1437 } else { 1438 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1439 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1440 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1441 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1442 } 1443 break; 1444 1445 default: 1446 g_assert_not_reached(); 1447 } 1448} 1449 1450static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1451 TCGReg addr, MemOpIdx oi, TCGType data_type) 1452{ 1453 MemOp opc = get_memop(oi); 1454 TCGLabelQemuLdst *ldst; 1455 HostAddress h; 1456 1457 ldst = prepare_host_addr(s, &h, addr, oi, true); 1458 1459 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1460 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1461 } else { 1462 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1463 } 1464 1465 if (ldst) { 1466 ldst->type = data_type; 1467 ldst->datalo_reg = datalo; 1468 ldst->datahi_reg = datahi; 1469 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1470 } 1471} 1472 1473static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1474 TCGReg base, MemOp opc) 1475{ 1476 switch (opc & MO_SIZE) { 1477 case MO_8: 1478 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1479 break; 1480 case MO_16: 1481 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1482 break; 1483 case MO_32: 1484 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1485 break; 1486 case MO_64: 1487 if (TCG_TARGET_REG_BITS == 64) { 1488 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1489 } else { 1490 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1491 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1492 } 1493 break; 1494 default: 1495 g_assert_not_reached(); 1496 } 1497} 1498 1499static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1500 TCGReg base, MemOp opc) 1501{ 1502 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1503 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1504 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1505 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1506 1507 switch (opc & MO_SIZE) { 1508 case MO_16: 1509 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1510 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1511 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1512 break; 1513 1514 case MO_32: 1515 tcg_out_opc_imm(s, sw1, lo, base, 0); 1516 tcg_out_opc_imm(s, sw2, lo, base, 3); 1517 break; 1518 1519 case MO_64: 1520 if (TCG_TARGET_REG_BITS == 64) { 1521 tcg_out_opc_imm(s, sd1, lo, base, 0); 1522 tcg_out_opc_imm(s, sd2, lo, base, 7); 1523 } else { 1524 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1525 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1526 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1527 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1528 } 1529 break; 1530 1531 default: 1532 g_assert_not_reached(); 1533 } 1534} 1535 1536static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1537 TCGReg addr, MemOpIdx oi, TCGType data_type) 1538{ 1539 MemOp opc = get_memop(oi); 1540 TCGLabelQemuLdst *ldst; 1541 HostAddress h; 1542 1543 ldst = prepare_host_addr(s, &h, addr, oi, false); 1544 1545 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1546 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1547 } else { 1548 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1549 } 1550 1551 if (ldst) { 1552 ldst->type = data_type; 1553 ldst->datalo_reg = datalo; 1554 ldst->datahi_reg = datahi; 1555 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1556 } 1557} 1558 1559static void tcg_out_mb(TCGContext *s, TCGArg a0) 1560{ 1561 static const MIPSInsn sync[] = { 1562 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1563 as the former is an ordering barrier and the latter 1564 is a completion barrier. */ 1565 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1566 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1567 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1568 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1569 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1570 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1571 }; 1572 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1573} 1574 1575static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1576{ 1577 TCGReg base = TCG_REG_ZERO; 1578 int16_t lo = 0; 1579 1580 if (a0) { 1581 intptr_t ofs; 1582 if (TCG_TARGET_REG_BITS == 64) { 1583 ofs = tcg_tbrel_diff(s, (void *)a0); 1584 lo = ofs; 1585 if (ofs == lo) { 1586 base = TCG_REG_TB; 1587 } else { 1588 base = TCG_REG_V0; 1589 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1590 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1591 } 1592 } else { 1593 ofs = a0; 1594 lo = ofs; 1595 base = TCG_REG_V0; 1596 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1597 } 1598 } 1599 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1600 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1601 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1602 } 1603 /* delay slot */ 1604 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1605} 1606 1607static void tcg_out_goto_tb(TCGContext *s, int which) 1608{ 1609 intptr_t ofs = get_jmp_target_addr(s, which); 1610 TCGReg base, dest; 1611 1612 /* indirect jump method */ 1613 if (TCG_TARGET_REG_BITS == 64) { 1614 dest = TCG_REG_TB; 1615 base = TCG_REG_TB; 1616 ofs = tcg_tbrel_diff(s, (void *)ofs); 1617 } else { 1618 dest = TCG_TMP0; 1619 base = TCG_REG_ZERO; 1620 } 1621 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1622 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1623 /* delay slot */ 1624 tcg_out_nop(s); 1625 1626 set_jmp_reset_offset(s, which); 1627 if (TCG_TARGET_REG_BITS == 64) { 1628 /* For the unlinked case, need to reset TCG_REG_TB. */ 1629 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1630 -tcg_current_code_size(s)); 1631 } 1632} 1633 1634void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1635 uintptr_t jmp_rx, uintptr_t jmp_rw) 1636{ 1637 /* Always indirect, nothing to do */ 1638} 1639 1640 1641static void tgen_add(TCGContext *s, TCGType type, 1642 TCGReg a0, TCGReg a1, TCGReg a2) 1643{ 1644 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1645 tcg_out_opc_reg(s, insn, a0, a1, a2); 1646} 1647 1648static void tgen_addi(TCGContext *s, TCGType type, 1649 TCGReg a0, TCGReg a1, tcg_target_long a2) 1650{ 1651 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1652 tcg_out_opc_imm(s, insn, a0, a1, a2); 1653} 1654 1655static const TCGOutOpBinary outop_add = { 1656 .base.static_constraint = C_O1_I2(r, r, rJ), 1657 .out_rrr = tgen_add, 1658 .out_rri = tgen_addi, 1659}; 1660 1661static void tgen_and(TCGContext *s, TCGType type, 1662 TCGReg a0, TCGReg a1, TCGReg a2) 1663{ 1664 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1665} 1666 1667static void tgen_andi(TCGContext *s, TCGType type, 1668 TCGReg a0, TCGReg a1, tcg_target_long a2) 1669{ 1670 int msb; 1671 1672 if (a2 == (uint16_t)a2) { 1673 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1674 return; 1675 } 1676 1677 tcg_debug_assert(use_mips32r2_instructions); 1678 tcg_debug_assert(is_p2m1(a2)); 1679 msb = ctz64(~a2) - 1; 1680 if (type == TCG_TYPE_I32) { 1681 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1682 } else { 1683 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1684 } 1685} 1686 1687static const TCGOutOpBinary outop_and = { 1688 .base.static_constraint = C_O1_I2(r, r, rIK), 1689 .out_rrr = tgen_and, 1690 .out_rri = tgen_andi, 1691}; 1692 1693static const TCGOutOpBinary outop_andc = { 1694 .base.static_constraint = C_NotImplemented, 1695}; 1696 1697static void tgen_clz(TCGContext *s, TCGType type, 1698 TCGReg a0, TCGReg a1, TCGReg a2) 1699{ 1700 if (use_mips32r6_instructions) { 1701 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1702 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1703 tgen_movcond(s, TCG_TYPE_REG, TCG_COND_EQ, a0, a1, a2, false, 1704 TCG_TMP0, false, TCG_REG_ZERO, false); 1705 } else { 1706 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1707 if (a0 == a2) { 1708 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1709 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1710 } else if (a0 != a1) { 1711 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1712 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1713 } else { 1714 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1715 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1716 tcg_out_mov(s, type, a0, TCG_TMP0); 1717 } 1718 } 1719} 1720 1721static void tgen_clzi(TCGContext *s, TCGType type, 1722 TCGReg a0, TCGReg a1, tcg_target_long a2) 1723{ 1724 if (a2 == 0) { 1725 tgen_clz(s, type, a0, a1, TCG_REG_ZERO); 1726 } else if (use_mips32r6_instructions) { 1727 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1728 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1729 } else { 1730 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1731 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1732 } 1733} 1734 1735static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 1736{ 1737 return use_mips32r2_instructions ? C_O1_I2(r, r, rzW) : C_NotImplemented; 1738} 1739 1740static const TCGOutOpBinary outop_clz = { 1741 .base.static_constraint = C_Dynamic, 1742 .base.dynamic_constraint = cset_clz, 1743 .out_rrr = tgen_clz, 1744 .out_rri = tgen_clzi, 1745}; 1746 1747static const TCGOutOpUnary outop_ctpop = { 1748 .base.static_constraint = C_NotImplemented, 1749}; 1750 1751static const TCGOutOpBinary outop_ctz = { 1752 .base.static_constraint = C_NotImplemented, 1753}; 1754 1755static void tgen_divs(TCGContext *s, TCGType type, 1756 TCGReg a0, TCGReg a1, TCGReg a2) 1757{ 1758 if (use_mips32r6_instructions) { 1759 if (type == TCG_TYPE_I32) { 1760 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1761 } else { 1762 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1763 } 1764 } else { 1765 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1766 tcg_out_opc_reg(s, insn, 0, a1, a2); 1767 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1768 } 1769} 1770 1771static const TCGOutOpBinary outop_divs = { 1772 .base.static_constraint = C_O1_I2(r, r, r), 1773 .out_rrr = tgen_divs, 1774}; 1775 1776static const TCGOutOpDivRem outop_divs2 = { 1777 .base.static_constraint = C_NotImplemented, 1778}; 1779 1780static void tgen_divu(TCGContext *s, TCGType type, 1781 TCGReg a0, TCGReg a1, TCGReg a2) 1782{ 1783 if (use_mips32r6_instructions) { 1784 if (type == TCG_TYPE_I32) { 1785 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1786 } else { 1787 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1788 } 1789 } else { 1790 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1791 tcg_out_opc_reg(s, insn, 0, a1, a2); 1792 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1793 } 1794} 1795 1796static const TCGOutOpBinary outop_divu = { 1797 .base.static_constraint = C_O1_I2(r, r, r), 1798 .out_rrr = tgen_divu, 1799}; 1800 1801static const TCGOutOpDivRem outop_divu2 = { 1802 .base.static_constraint = C_NotImplemented, 1803}; 1804 1805static const TCGOutOpBinary outop_eqv = { 1806 .base.static_constraint = C_NotImplemented, 1807}; 1808 1809static void tgen_mul(TCGContext *s, TCGType type, 1810 TCGReg a0, TCGReg a1, TCGReg a2) 1811{ 1812 MIPSInsn insn; 1813 1814 if (type == TCG_TYPE_I32) { 1815 if (use_mips32_instructions) { 1816 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1817 return; 1818 } 1819 insn = OPC_MULT; 1820 } else { 1821 if (use_mips32r6_instructions) { 1822 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1823 return; 1824 } 1825 insn = OPC_DMULT; 1826 } 1827 tcg_out_opc_reg(s, insn, 0, a1, a2); 1828 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1829} 1830 1831static const TCGOutOpBinary outop_mul = { 1832 .base.static_constraint = C_O1_I2(r, r, r), 1833 .out_rrr = tgen_mul, 1834}; 1835 1836static void tgen_muls2(TCGContext *s, TCGType type, 1837 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1838{ 1839 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1840 tcg_out_opc_reg(s, insn, 0, a2, a3); 1841 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1842 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1843} 1844 1845static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1846{ 1847 return use_mips32r6_instructions ? C_NotImplemented : C_O2_I2(r, r, r, r); 1848} 1849 1850static const TCGOutOpMul2 outop_muls2 = { 1851 .base.static_constraint = C_Dynamic, 1852 .base.dynamic_constraint = cset_mul2, 1853 .out_rrrr = tgen_muls2, 1854}; 1855 1856static void tgen_mulsh(TCGContext *s, TCGType type, 1857 TCGReg a0, TCGReg a1, TCGReg a2) 1858{ 1859 if (use_mips32r6_instructions) { 1860 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH; 1861 tcg_out_opc_reg(s, insn, a0, a1, a2); 1862 } else { 1863 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1864 tcg_out_opc_reg(s, insn, 0, a1, a2); 1865 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1866 } 1867} 1868 1869static const TCGOutOpBinary outop_mulsh = { 1870 .base.static_constraint = C_O1_I2(r, r, r), 1871 .out_rrr = tgen_mulsh, 1872}; 1873 1874static void tgen_mulu2(TCGContext *s, TCGType type, 1875 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1876{ 1877 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1878 tcg_out_opc_reg(s, insn, 0, a2, a3); 1879 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1880 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1881} 1882 1883static const TCGOutOpMul2 outop_mulu2 = { 1884 .base.static_constraint = C_Dynamic, 1885 .base.dynamic_constraint = cset_mul2, 1886 .out_rrrr = tgen_mulu2, 1887}; 1888 1889static void tgen_muluh(TCGContext *s, TCGType type, 1890 TCGReg a0, TCGReg a1, TCGReg a2) 1891{ 1892 if (use_mips32r6_instructions) { 1893 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; 1894 tcg_out_opc_reg(s, insn, a0, a1, a2); 1895 } else { 1896 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1897 tcg_out_opc_reg(s, insn, 0, a1, a2); 1898 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1899 } 1900} 1901 1902static const TCGOutOpBinary outop_muluh = { 1903 .base.static_constraint = C_O1_I2(r, r, r), 1904 .out_rrr = tgen_muluh, 1905}; 1906 1907static const TCGOutOpBinary outop_nand = { 1908 .base.static_constraint = C_NotImplemented, 1909}; 1910 1911static void tgen_nor(TCGContext *s, TCGType type, 1912 TCGReg a0, TCGReg a1, TCGReg a2) 1913{ 1914 tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); 1915} 1916 1917static const TCGOutOpBinary outop_nor = { 1918 .base.static_constraint = C_O1_I2(r, r, r), 1919 .out_rrr = tgen_nor, 1920}; 1921 1922static void tgen_or(TCGContext *s, TCGType type, 1923 TCGReg a0, TCGReg a1, TCGReg a2) 1924{ 1925 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1926} 1927 1928static void tgen_ori(TCGContext *s, TCGType type, 1929 TCGReg a0, TCGReg a1, tcg_target_long a2) 1930{ 1931 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1932} 1933 1934static const TCGOutOpBinary outop_or = { 1935 .base.static_constraint = C_O1_I2(r, r, rI), 1936 .out_rrr = tgen_or, 1937 .out_rri = tgen_ori, 1938}; 1939 1940static const TCGOutOpBinary outop_orc = { 1941 .base.static_constraint = C_NotImplemented, 1942}; 1943 1944static void tgen_rems(TCGContext *s, TCGType type, 1945 TCGReg a0, TCGReg a1, TCGReg a2) 1946{ 1947 if (use_mips32r6_instructions) { 1948 if (type == TCG_TYPE_I32) { 1949 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1950 } else { 1951 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1952 } 1953 } else { 1954 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1955 tcg_out_opc_reg(s, insn, 0, a1, a2); 1956 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1957 } 1958} 1959 1960static const TCGOutOpBinary outop_rems = { 1961 .base.static_constraint = C_O1_I2(r, r, r), 1962 .out_rrr = tgen_rems, 1963}; 1964 1965static void tgen_remu(TCGContext *s, TCGType type, 1966 TCGReg a0, TCGReg a1, TCGReg a2) 1967{ 1968 if (use_mips32r6_instructions) { 1969 if (type == TCG_TYPE_I32) { 1970 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1971 } else { 1972 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1973 } 1974 } else { 1975 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1976 tcg_out_opc_reg(s, insn, 0, a1, a2); 1977 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1978 } 1979} 1980 1981static const TCGOutOpBinary outop_remu = { 1982 .base.static_constraint = C_O1_I2(r, r, r), 1983 .out_rrr = tgen_remu, 1984}; 1985 1986static const TCGOutOpBinary outop_rotl = { 1987 .base.static_constraint = C_NotImplemented, 1988}; 1989 1990static TCGConstraintSetIndex cset_rotr(TCGType type, unsigned flags) 1991{ 1992 return use_mips32r2_instructions ? C_O1_I2(r, r, ri) : C_NotImplemented; 1993} 1994 1995static void tgen_rotr(TCGContext *s, TCGType type, 1996 TCGReg a0, TCGReg a1, TCGReg a2) 1997{ 1998 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; 1999 tcg_out_opc_reg(s, insn, a0, a1, a2); 2000} 2001 2002static void tgen_rotri(TCGContext *s, TCGType type, 2003 TCGReg a0, TCGReg a1, tcg_target_long a2) 2004{ 2005 if (type == TCG_TYPE_I32) { 2006 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); 2007 } else { 2008 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2009 } 2010} 2011 2012static const TCGOutOpBinary outop_rotr = { 2013 .base.static_constraint = C_Dynamic, 2014 .base.dynamic_constraint = cset_rotr, 2015 .out_rrr = tgen_rotr, 2016 .out_rri = tgen_rotri, 2017}; 2018 2019static void tgen_sar(TCGContext *s, TCGType type, 2020 TCGReg a0, TCGReg a1, TCGReg a2) 2021{ 2022 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; 2023 tcg_out_opc_reg(s, insn, a0, a1, a2); 2024} 2025 2026static void tgen_sari(TCGContext *s, TCGType type, 2027 TCGReg a0, TCGReg a1, tcg_target_long a2) 2028{ 2029 if (type == TCG_TYPE_I32) { 2030 tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); 2031 } else { 2032 tcg_out_dsra(s, a0, a1, a2); 2033 } 2034} 2035 2036static const TCGOutOpBinary outop_sar = { 2037 .base.static_constraint = C_O1_I2(r, r, ri), 2038 .out_rrr = tgen_sar, 2039 .out_rri = tgen_sari, 2040}; 2041 2042static void tgen_shl(TCGContext *s, TCGType type, 2043 TCGReg a0, TCGReg a1, TCGReg a2) 2044{ 2045 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; 2046 tcg_out_opc_reg(s, insn, a0, a1, a2); 2047} 2048 2049static void tgen_shli(TCGContext *s, TCGType type, 2050 TCGReg a0, TCGReg a1, tcg_target_long a2) 2051{ 2052 if (type == TCG_TYPE_I32) { 2053 tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); 2054 } else { 2055 tcg_out_dsll(s, a0, a1, a2); 2056 } 2057} 2058 2059static const TCGOutOpBinary outop_shl = { 2060 .base.static_constraint = C_O1_I2(r, r, ri), 2061 .out_rrr = tgen_shl, 2062 .out_rri = tgen_shli, 2063}; 2064 2065static void tgen_shr(TCGContext *s, TCGType type, 2066 TCGReg a0, TCGReg a1, TCGReg a2) 2067{ 2068 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; 2069 tcg_out_opc_reg(s, insn, a0, a1, a2); 2070} 2071 2072static void tgen_shri(TCGContext *s, TCGType type, 2073 TCGReg a0, TCGReg a1, tcg_target_long a2) 2074{ 2075 if (type == TCG_TYPE_I32) { 2076 tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); 2077 } else { 2078 tcg_out_dsrl(s, a0, a1, a2); 2079 } 2080} 2081 2082static const TCGOutOpBinary outop_shr = { 2083 .base.static_constraint = C_O1_I2(r, r, ri), 2084 .out_rrr = tgen_shr, 2085 .out_rri = tgen_shri, 2086}; 2087 2088static void tgen_sub(TCGContext *s, TCGType type, 2089 TCGReg a0, TCGReg a1, TCGReg a2) 2090{ 2091 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU; 2092 tcg_out_opc_reg(s, insn, a0, a1, a2); 2093} 2094 2095static const TCGOutOpSubtract outop_sub = { 2096 .base.static_constraint = C_O1_I2(r, r, r), 2097 .out_rrr = tgen_sub, 2098}; 2099 2100static void tgen_xor(TCGContext *s, TCGType type, 2101 TCGReg a0, TCGReg a1, TCGReg a2) 2102{ 2103 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2104} 2105 2106static void tgen_xori(TCGContext *s, TCGType type, 2107 TCGReg a0, TCGReg a1, tcg_target_long a2) 2108{ 2109 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2110} 2111 2112static const TCGOutOpBinary outop_xor = { 2113 .base.static_constraint = C_O1_I2(r, r, rI), 2114 .out_rrr = tgen_xor, 2115 .out_rri = tgen_xori, 2116}; 2117 2118static void tgen_bswap16(TCGContext *s, TCGType type, 2119 TCGReg ret, TCGReg arg, unsigned flags) 2120{ 2121 /* With arg = abcd: */ 2122 if (use_mips32r2_instructions) { 2123 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 2124 if (flags & TCG_BSWAP_OS) { 2125 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 2126 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2127 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 2128 } 2129 return; 2130 } 2131 2132 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 2133 if (!(flags & TCG_BSWAP_IZ)) { 2134 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 2135 } 2136 if (flags & TCG_BSWAP_OS) { 2137 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 2138 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 2139 } else { 2140 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 2141 if (flags & TCG_BSWAP_OZ) { 2142 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 2143 } 2144 } 2145 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 2146} 2147 2148static const TCGOutOpBswap outop_bswap16 = { 2149 .base.static_constraint = C_O1_I1(r, r), 2150 .out_rr = tgen_bswap16, 2151}; 2152 2153static void tgen_bswap32(TCGContext *s, TCGType type, 2154 TCGReg ret, TCGReg arg, unsigned flags) 2155{ 2156 if (use_mips32r2_instructions) { 2157 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 2158 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 2159 if (flags & TCG_BSWAP_OZ) { 2160 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 2161 } 2162 } else { 2163 if (flags & TCG_BSWAP_OZ) { 2164 tcg_out_bswap_subr(s, bswap32u_addr); 2165 } else { 2166 tcg_out_bswap_subr(s, bswap32_addr); 2167 } 2168 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2169 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2170 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2171 } 2172} 2173 2174static const TCGOutOpBswap outop_bswap32 = { 2175 .base.static_constraint = C_O1_I1(r, r), 2176 .out_rr = tgen_bswap32, 2177}; 2178 2179static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2180{ 2181 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2182} 2183 2184static const TCGOutOpUnary outop_neg = { 2185 .base.static_constraint = C_O1_I1(r, r), 2186 .out_rr = tgen_neg, 2187}; 2188 2189static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2190{ 2191 tgen_nor(s, type, a0, TCG_REG_ZERO, a1); 2192} 2193 2194static const TCGOutOpUnary outop_not = { 2195 .base.static_constraint = C_O1_I1(r, r), 2196 .out_rr = tgen_not, 2197}; 2198 2199 2200static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2201 const TCGArg args[TCG_MAX_OP_ARGS], 2202 const int const_args[TCG_MAX_OP_ARGS]) 2203{ 2204 MIPSInsn i1; 2205 TCGArg a0, a1, a2; 2206 2207 a0 = args[0]; 2208 a1 = args[1]; 2209 a2 = args[2]; 2210 2211 switch (opc) { 2212 case INDEX_op_goto_ptr: 2213 /* jmp to the given host address (could be epilogue) */ 2214 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2215 if (TCG_TARGET_REG_BITS == 64) { 2216 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 2217 } else { 2218 tcg_out_nop(s); 2219 } 2220 break; 2221 case INDEX_op_br: 2222 tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, 2223 TCG_REG_ZERO, TCG_REG_ZERO, arg_label(a0)); 2224 break; 2225 2226 case INDEX_op_ld8u_i32: 2227 case INDEX_op_ld8u_i64: 2228 i1 = OPC_LBU; 2229 goto do_ldst; 2230 case INDEX_op_ld8s_i32: 2231 case INDEX_op_ld8s_i64: 2232 i1 = OPC_LB; 2233 goto do_ldst; 2234 case INDEX_op_ld16u_i32: 2235 case INDEX_op_ld16u_i64: 2236 i1 = OPC_LHU; 2237 goto do_ldst; 2238 case INDEX_op_ld16s_i32: 2239 case INDEX_op_ld16s_i64: 2240 i1 = OPC_LH; 2241 goto do_ldst; 2242 case INDEX_op_ld_i32: 2243 case INDEX_op_ld32s_i64: 2244 i1 = OPC_LW; 2245 goto do_ldst; 2246 case INDEX_op_ld32u_i64: 2247 i1 = OPC_LWU; 2248 goto do_ldst; 2249 case INDEX_op_ld_i64: 2250 i1 = OPC_LD; 2251 goto do_ldst; 2252 case INDEX_op_st8_i32: 2253 case INDEX_op_st8_i64: 2254 i1 = OPC_SB; 2255 goto do_ldst; 2256 case INDEX_op_st16_i32: 2257 case INDEX_op_st16_i64: 2258 i1 = OPC_SH; 2259 goto do_ldst; 2260 case INDEX_op_st_i32: 2261 case INDEX_op_st32_i64: 2262 i1 = OPC_SW; 2263 goto do_ldst; 2264 case INDEX_op_st_i64: 2265 i1 = OPC_SD; 2266 do_ldst: 2267 tcg_out_ldst(s, i1, a0, a1, a2); 2268 break; 2269 2270 case INDEX_op_bswap64_i64: 2271 tcg_out_bswap64(s, a0, a1); 2272 break; 2273 case INDEX_op_extrh_i64_i32: 2274 tcg_out_dsra(s, a0, a1, 32); 2275 break; 2276 2277 case INDEX_op_deposit_i32: 2278 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2279 break; 2280 case INDEX_op_deposit_i64: 2281 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2282 args[3] + args[4] - 1, args[3]); 2283 break; 2284 2285 case INDEX_op_extract_i32: 2286 if (a2 == 0 && args[3] <= 16) { 2287 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2288 } else { 2289 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2290 } 2291 break; 2292 case INDEX_op_extract_i64: 2293 if (a2 == 0 && args[3] <= 16) { 2294 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2295 } else { 2296 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2297 a0, a1, args[3] - 1, a2); 2298 } 2299 break; 2300 2301 case INDEX_op_sextract_i64: 2302 if (a2 == 0 && args[3] == 32) { 2303 tcg_out_ext32s(s, a0, a1); 2304 break; 2305 } 2306 /* FALLTHRU */ 2307 case INDEX_op_sextract_i32: 2308 if (a2 == 0 && args[3] == 8) { 2309 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 2310 } else if (a2 == 0 && args[3] == 16) { 2311 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 2312 } else { 2313 g_assert_not_reached(); 2314 } 2315 break; 2316 2317 case INDEX_op_qemu_ld_i32: 2318 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2319 break; 2320 case INDEX_op_qemu_ld_i64: 2321 if (TCG_TARGET_REG_BITS == 64) { 2322 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2323 } else { 2324 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2325 } 2326 break; 2327 2328 case INDEX_op_qemu_st_i32: 2329 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2330 break; 2331 case INDEX_op_qemu_st_i64: 2332 if (TCG_TARGET_REG_BITS == 64) { 2333 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2334 } else { 2335 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2336 } 2337 break; 2338 2339 case INDEX_op_add2_i32: 2340 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2341 const_args[4], const_args[5], false); 2342 break; 2343 case INDEX_op_sub2_i32: 2344 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2345 const_args[4], const_args[5], true); 2346 break; 2347 2348 case INDEX_op_mb: 2349 tcg_out_mb(s, a0); 2350 break; 2351 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2352 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2353 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2354 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2355 case INDEX_op_extu_i32_i64: 2356 case INDEX_op_extrl_i64_i32: 2357 default: 2358 g_assert_not_reached(); 2359 } 2360} 2361 2362static TCGConstraintSetIndex 2363tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2364{ 2365 switch (op) { 2366 case INDEX_op_goto_ptr: 2367 return C_O0_I1(r); 2368 2369 case INDEX_op_ld8u_i32: 2370 case INDEX_op_ld8s_i32: 2371 case INDEX_op_ld16u_i32: 2372 case INDEX_op_ld16s_i32: 2373 case INDEX_op_ld_i32: 2374 case INDEX_op_extract_i32: 2375 case INDEX_op_sextract_i32: 2376 case INDEX_op_ld8u_i64: 2377 case INDEX_op_ld8s_i64: 2378 case INDEX_op_ld16u_i64: 2379 case INDEX_op_ld16s_i64: 2380 case INDEX_op_ld32s_i64: 2381 case INDEX_op_ld32u_i64: 2382 case INDEX_op_ld_i64: 2383 case INDEX_op_bswap64_i64: 2384 case INDEX_op_ext_i32_i64: 2385 case INDEX_op_extu_i32_i64: 2386 case INDEX_op_extrl_i64_i32: 2387 case INDEX_op_extrh_i64_i32: 2388 case INDEX_op_extract_i64: 2389 case INDEX_op_sextract_i64: 2390 return C_O1_I1(r, r); 2391 2392 case INDEX_op_st8_i32: 2393 case INDEX_op_st16_i32: 2394 case INDEX_op_st_i32: 2395 case INDEX_op_st8_i64: 2396 case INDEX_op_st16_i64: 2397 case INDEX_op_st32_i64: 2398 case INDEX_op_st_i64: 2399 return C_O0_I2(rz, r); 2400 2401 case INDEX_op_deposit_i32: 2402 case INDEX_op_deposit_i64: 2403 return C_O1_I2(r, 0, rz); 2404 case INDEX_op_add2_i32: 2405 case INDEX_op_sub2_i32: 2406 return C_O2_I4(r, r, rz, rz, rN, rN); 2407 2408 case INDEX_op_qemu_ld_i32: 2409 return C_O1_I1(r, r); 2410 case INDEX_op_qemu_st_i32: 2411 return C_O0_I2(rz, r); 2412 case INDEX_op_qemu_ld_i64: 2413 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2414 case INDEX_op_qemu_st_i64: 2415 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2416 2417 default: 2418 return C_NotImplemented; 2419 } 2420} 2421 2422static const int tcg_target_callee_save_regs[] = { 2423 TCG_REG_S0, 2424 TCG_REG_S1, 2425 TCG_REG_S2, 2426 TCG_REG_S3, 2427 TCG_REG_S4, 2428 TCG_REG_S5, 2429 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2430 TCG_REG_S7, /* used for guest_base */ 2431 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2432 TCG_REG_RA, /* should be last for ABI compliance */ 2433}; 2434 2435/* The Linux kernel doesn't provide any information about the available 2436 instruction set. Probe it using a signal handler. */ 2437 2438 2439#ifndef use_movnz_instructions 2440bool use_movnz_instructions = false; 2441#endif 2442 2443#ifndef use_mips32_instructions 2444bool use_mips32_instructions = false; 2445#endif 2446 2447#ifndef use_mips32r2_instructions 2448bool use_mips32r2_instructions = false; 2449#endif 2450 2451static volatile sig_atomic_t got_sigill; 2452 2453static void sigill_handler(int signo, siginfo_t *si, void *data) 2454{ 2455 /* Skip the faulty instruction */ 2456 ucontext_t *uc = (ucontext_t *)data; 2457 uc->uc_mcontext.pc += 4; 2458 2459 got_sigill = 1; 2460} 2461 2462static void tcg_target_detect_isa(void) 2463{ 2464 struct sigaction sa_old, sa_new; 2465 2466 memset(&sa_new, 0, sizeof(sa_new)); 2467 sa_new.sa_flags = SA_SIGINFO; 2468 sa_new.sa_sigaction = sigill_handler; 2469 sigaction(SIGILL, &sa_new, &sa_old); 2470 2471 /* Probe for movn/movz, necessary to implement movcond. */ 2472#ifndef use_movnz_instructions 2473 got_sigill = 0; 2474 asm volatile(".set push\n" 2475 ".set mips32\n" 2476 "movn $zero, $zero, $zero\n" 2477 "movz $zero, $zero, $zero\n" 2478 ".set pop\n" 2479 : : : ); 2480 use_movnz_instructions = !got_sigill; 2481#endif 2482 2483 /* Probe for MIPS32 instructions. As no subsetting is allowed 2484 by the specification, it is only necessary to probe for one 2485 of the instructions. */ 2486#ifndef use_mips32_instructions 2487 got_sigill = 0; 2488 asm volatile(".set push\n" 2489 ".set mips32\n" 2490 "mul $zero, $zero\n" 2491 ".set pop\n" 2492 : : : ); 2493 use_mips32_instructions = !got_sigill; 2494#endif 2495 2496 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2497 available. As no subsetting is allowed by the specification, 2498 it is only necessary to probe for one of the instructions. */ 2499#ifndef use_mips32r2_instructions 2500 if (use_mips32_instructions) { 2501 got_sigill = 0; 2502 asm volatile(".set push\n" 2503 ".set mips32r2\n" 2504 "seb $zero, $zero\n" 2505 ".set pop\n" 2506 : : : ); 2507 use_mips32r2_instructions = !got_sigill; 2508 } 2509#endif 2510 2511 sigaction(SIGILL, &sa_old, NULL); 2512} 2513 2514static tcg_insn_unit *align_code_ptr(TCGContext *s) 2515{ 2516 uintptr_t p = (uintptr_t)s->code_ptr; 2517 if (p & 15) { 2518 p = (p + 15) & -16; 2519 s->code_ptr = (void *)p; 2520 } 2521 return s->code_ptr; 2522} 2523 2524/* Stack frame parameters. */ 2525#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2526#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2527#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2528 2529#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2530 + TCG_TARGET_STACK_ALIGN - 1) \ 2531 & -TCG_TARGET_STACK_ALIGN) 2532#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2533 2534/* We're expecting to be able to use an immediate for frame allocation. */ 2535QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2536 2537/* Generate global QEMU prologue and epilogue code */ 2538static void tcg_target_qemu_prologue(TCGContext *s) 2539{ 2540 int i; 2541 2542 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2543 2544 /* TB prologue */ 2545 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2546 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2547 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2548 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2549 } 2550 2551 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2552 /* 2553 * The function call abi for n32 and n64 will have loaded $25 (t9) 2554 * with the address of the prologue, so we can use that instead 2555 * of TCG_REG_TB. 2556 */ 2557#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2558# error "Unknown mips abi" 2559#endif 2560 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2561 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2562 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2563 } 2564 2565 if (TCG_TARGET_REG_BITS == 64) { 2566 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2567 } 2568 2569 /* Call generated code */ 2570 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2571 /* delay slot */ 2572 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2573 2574 /* 2575 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2576 * and fall through to the rest of the epilogue. 2577 */ 2578 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2579 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2580 2581 /* TB epilogue */ 2582 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2583 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2584 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2585 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2586 } 2587 2588 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2589 /* delay slot */ 2590 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2591 2592 if (use_mips32r2_instructions) { 2593 return; 2594 } 2595 2596 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2597 clobbers TCG_TMP1, TCG_TMP2. */ 2598 2599 /* 2600 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2601 */ 2602 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2603 /* t3 = (ssss)d000 */ 2604 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2605 /* t1 = 000a */ 2606 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2607 /* t2 = 00c0 */ 2608 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2609 /* t3 = d00a */ 2610 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2611 /* t1 = 0abc */ 2612 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2613 /* t2 = 0c00 */ 2614 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2615 /* t1 = 00b0 */ 2616 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2617 /* t3 = dc0a */ 2618 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2619 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2620 /* t3 = dcba -- delay slot */ 2621 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2622 2623 if (TCG_TARGET_REG_BITS == 32) { 2624 return; 2625 } 2626 2627 /* 2628 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2629 */ 2630 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2631 /* t1 = (0000)000d */ 2632 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2633 /* t3 = 000a */ 2634 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2635 /* t1 = (0000)d000 */ 2636 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2637 /* t2 = 00c0 */ 2638 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2639 /* t3 = d00a */ 2640 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2641 /* t1 = 0abc */ 2642 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2643 /* t2 = 0c00 */ 2644 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2645 /* t1 = 00b0 */ 2646 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2647 /* t3 = dc0a */ 2648 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2649 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2650 /* t3 = dcba -- delay slot */ 2651 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2652 2653 /* 2654 * bswap64 -- 64-bit swap. a0 = abcdefgh 2655 */ 2656 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2657 /* t3 = h0000000 */ 2658 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2659 /* t1 = 0000000a */ 2660 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2661 2662 /* t2 = 000000g0 */ 2663 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2664 /* t3 = h000000a */ 2665 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2666 /* t1 = 00000abc */ 2667 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2668 /* t2 = 0g000000 */ 2669 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2670 /* t1 = 000000b0 */ 2671 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2672 2673 /* t3 = hg00000a */ 2674 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2675 /* t2 = 0000abcd */ 2676 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2677 /* t3 = hg0000ba */ 2678 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2679 2680 /* t1 = 000000c0 */ 2681 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2682 /* t2 = 0000000d */ 2683 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2684 /* t1 = 00000c00 */ 2685 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2686 /* t2 = 0000d000 */ 2687 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2688 2689 /* t3 = hg000cba */ 2690 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2691 /* t1 = 00abcdef */ 2692 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2693 /* t3 = hg00dcba */ 2694 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2695 2696 /* t2 = 0000000f */ 2697 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2698 /* t1 = 000000e0 */ 2699 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2700 /* t2 = 00f00000 */ 2701 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2702 /* t1 = 000e0000 */ 2703 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2704 2705 /* t3 = hgf0dcba */ 2706 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2707 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2708 /* t3 = hgfedcba -- delay slot */ 2709 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2710} 2711 2712static void tcg_out_tb_start(TCGContext *s) 2713{ 2714 /* nothing to do */ 2715} 2716 2717static void tcg_target_init(TCGContext *s) 2718{ 2719 tcg_target_detect_isa(); 2720 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2721 if (TCG_TARGET_REG_BITS == 64) { 2722 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2723 } 2724 2725 tcg_target_call_clobber_regs = 0; 2726 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2727 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2728 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2729 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2730 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2731 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2732 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2733 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2734 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2735 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2736 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2737 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2738 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2741 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2742 2743 s->reserved_regs = 0; 2744 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2745 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2746 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2747 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2748 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2749 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2750 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2751 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2752 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2753 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2754 if (TCG_TARGET_REG_BITS == 64) { 2755 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2756 } 2757} 2758 2759typedef struct { 2760 DebugFrameHeader h; 2761 uint8_t fde_def_cfa[4]; 2762 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2763} DebugFrame; 2764 2765#define ELF_HOST_MACHINE EM_MIPS 2766/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2767 which is good because they're really quite complicated for MIPS. */ 2768 2769static const DebugFrame debug_frame = { 2770 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2771 .h.cie.id = -1, 2772 .h.cie.version = 1, 2773 .h.cie.code_align = 1, 2774 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2775 .h.cie.return_column = TCG_REG_RA, 2776 2777 /* Total FDE size does not include the "len" member. */ 2778 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2779 2780 .fde_def_cfa = { 2781 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2782 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2783 (FRAME_SIZE >> 7) 2784 }, 2785 .fde_reg_ofs = { 2786 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2787 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2788 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2789 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2790 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2791 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2792 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2793 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2794 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2795 } 2796}; 2797 2798void tcg_register_jit(const void *buf, size_t buf_size) 2799{ 2800 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2801} 2802