1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28#include "../tcg-pool.c.inc" 29 30#if TCG_TARGET_REG_BITS == 32 31# define LO_OFF (HOST_BIG_ENDIAN * 4) 32# define HI_OFF (4 - LO_OFF) 33#else 34/* Assert at compile-time that these values are never used for 64-bit. */ 35# define LO_OFF ({ qemu_build_not_reached(); 0; }) 36# define HI_OFF ({ qemu_build_not_reached(); 0; }) 37#endif 38 39#ifdef CONFIG_DEBUG_TCG 40static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 41 "zero", 42 "at", 43 "v0", 44 "v1", 45 "a0", 46 "a1", 47 "a2", 48 "a3", 49 "t0", 50 "t1", 51 "t2", 52 "t3", 53 "t4", 54 "t5", 55 "t6", 56 "t7", 57 "s0", 58 "s1", 59 "s2", 60 "s3", 61 "s4", 62 "s5", 63 "s6", 64 "s7", 65 "t8", 66 "t9", 67 "k0", 68 "k1", 69 "gp", 70 "sp", 71 "s8", 72 "ra", 73}; 74#endif 75 76#define TCG_TMP0 TCG_REG_AT 77#define TCG_TMP1 TCG_REG_T9 78#define TCG_TMP2 TCG_REG_T8 79#define TCG_TMP3 TCG_REG_T7 80 81#define TCG_GUEST_BASE_REG TCG_REG_S7 82#if TCG_TARGET_REG_BITS == 64 83#define TCG_REG_TB TCG_REG_S6 84#else 85#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 86#endif 87 88/* check if we really need so many registers :P */ 89static const int tcg_target_reg_alloc_order[] = { 90 /* Call saved registers. */ 91 TCG_REG_S0, 92 TCG_REG_S1, 93 TCG_REG_S2, 94 TCG_REG_S3, 95 TCG_REG_S4, 96 TCG_REG_S5, 97 TCG_REG_S6, 98 TCG_REG_S7, 99 TCG_REG_S8, 100 101 /* Call clobbered registers. */ 102 TCG_REG_T4, 103 TCG_REG_T5, 104 TCG_REG_T6, 105 TCG_REG_T7, 106 TCG_REG_T8, 107 TCG_REG_T9, 108 TCG_REG_V1, 109 TCG_REG_V0, 110 111 /* Argument registers, opposite order of allocation. */ 112 TCG_REG_T3, 113 TCG_REG_T2, 114 TCG_REG_T1, 115 TCG_REG_T0, 116 TCG_REG_A3, 117 TCG_REG_A2, 118 TCG_REG_A1, 119 TCG_REG_A0, 120}; 121 122static const TCGReg tcg_target_call_iarg_regs[] = { 123 TCG_REG_A0, 124 TCG_REG_A1, 125 TCG_REG_A2, 126 TCG_REG_A3, 127#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 128 TCG_REG_T0, 129 TCG_REG_T1, 130 TCG_REG_T2, 131 TCG_REG_T3, 132#endif 133}; 134 135static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 136{ 137 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 138 tcg_debug_assert(slot >= 0 && slot <= 1); 139 return TCG_REG_V0 + slot; 140} 141 142static const tcg_insn_unit *tb_ret_addr; 143static const tcg_insn_unit *bswap32_addr; 144static const tcg_insn_unit *bswap32u_addr; 145static const tcg_insn_unit *bswap64_addr; 146 147static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 148{ 149 /* Let the compiler perform the right-shift as part of the arithmetic. */ 150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 151 ptrdiff_t disp = target - (src_rx + 1); 152 if (disp == (int16_t)disp) { 153 *src_rw = deposit32(*src_rw, 0, 16, disp); 154 return true; 155 } 156 return false; 157} 158 159static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 160 intptr_t value, intptr_t addend) 161{ 162 value += addend; 163 switch (type) { 164 case R_MIPS_PC16: 165 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 166 case R_MIPS_16: 167 if (value != (int16_t)value) { 168 return false; 169 } 170 *code_ptr = deposit32(*code_ptr, 0, 16, value); 171 return true; 172 } 173 g_assert_not_reached(); 174} 175 176#define TCG_CT_CONST_ZERO 0x100 177#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 178#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 179#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 180#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 181#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 182 183#define ALL_GENERAL_REGS 0xffffffffu 184 185static bool is_p2m1(tcg_target_long val) 186{ 187 return val && ((val + 1) & val) == 0; 188} 189 190/* test if a constant matches the constraint */ 191static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece) 192{ 193 if (ct & TCG_CT_CONST) { 194 return 1; 195 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 196 return 1; 197 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 198 return 1; 199 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 200 return 1; 201 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 202 return 1; 203 } else if ((ct & TCG_CT_CONST_P2M1) 204 && use_mips32r2_instructions && is_p2m1(val)) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_WSZ) 207 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return 1; 209 } 210 return 0; 211} 212 213/* instruction opcodes */ 214typedef enum { 215 OPC_J = 002 << 26, 216 OPC_JAL = 003 << 26, 217 OPC_BEQ = 004 << 26, 218 OPC_BNE = 005 << 26, 219 OPC_BLEZ = 006 << 26, 220 OPC_BGTZ = 007 << 26, 221 OPC_ADDIU = 011 << 26, 222 OPC_SLTI = 012 << 26, 223 OPC_SLTIU = 013 << 26, 224 OPC_ANDI = 014 << 26, 225 OPC_ORI = 015 << 26, 226 OPC_XORI = 016 << 26, 227 OPC_LUI = 017 << 26, 228 OPC_BNEL = 025 << 26, 229 OPC_BNEZALC_R6 = 030 << 26, 230 OPC_DADDIU = 031 << 26, 231 OPC_LDL = 032 << 26, 232 OPC_LDR = 033 << 26, 233 OPC_LB = 040 << 26, 234 OPC_LH = 041 << 26, 235 OPC_LWL = 042 << 26, 236 OPC_LW = 043 << 26, 237 OPC_LBU = 044 << 26, 238 OPC_LHU = 045 << 26, 239 OPC_LWR = 046 << 26, 240 OPC_LWU = 047 << 26, 241 OPC_SB = 050 << 26, 242 OPC_SH = 051 << 26, 243 OPC_SWL = 052 << 26, 244 OPC_SW = 053 << 26, 245 OPC_SDL = 054 << 26, 246 OPC_SDR = 055 << 26, 247 OPC_SWR = 056 << 26, 248 OPC_LD = 067 << 26, 249 OPC_SD = 077 << 26, 250 251 OPC_SPECIAL = 000 << 26, 252 OPC_SLL = OPC_SPECIAL | 000, 253 OPC_SRL = OPC_SPECIAL | 002, 254 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 255 OPC_SRA = OPC_SPECIAL | 003, 256 OPC_SLLV = OPC_SPECIAL | 004, 257 OPC_SRLV = OPC_SPECIAL | 006, 258 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 259 OPC_SRAV = OPC_SPECIAL | 007, 260 OPC_JR_R5 = OPC_SPECIAL | 010, 261 OPC_JALR = OPC_SPECIAL | 011, 262 OPC_MOVZ = OPC_SPECIAL | 012, 263 OPC_MOVN = OPC_SPECIAL | 013, 264 OPC_SYNC = OPC_SPECIAL | 017, 265 OPC_MFHI = OPC_SPECIAL | 020, 266 OPC_MFLO = OPC_SPECIAL | 022, 267 OPC_DSLLV = OPC_SPECIAL | 024, 268 OPC_DSRLV = OPC_SPECIAL | 026, 269 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 270 OPC_DSRAV = OPC_SPECIAL | 027, 271 OPC_MULT = OPC_SPECIAL | 030, 272 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 273 OPC_MUH = OPC_SPECIAL | 030 | 0300, 274 OPC_MULTU = OPC_SPECIAL | 031, 275 OPC_MULU = OPC_SPECIAL | 031 | 0200, 276 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 277 OPC_DIV = OPC_SPECIAL | 032, 278 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 279 OPC_MOD = OPC_SPECIAL | 032 | 0300, 280 OPC_DIVU = OPC_SPECIAL | 033, 281 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 282 OPC_MODU = OPC_SPECIAL | 033 | 0300, 283 OPC_DMULT = OPC_SPECIAL | 034, 284 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 285 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 286 OPC_DMULTU = OPC_SPECIAL | 035, 287 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 288 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 289 OPC_DDIV = OPC_SPECIAL | 036, 290 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 291 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 292 OPC_DDIVU = OPC_SPECIAL | 037, 293 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 294 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 295 OPC_ADDU = OPC_SPECIAL | 041, 296 OPC_SUBU = OPC_SPECIAL | 043, 297 OPC_AND = OPC_SPECIAL | 044, 298 OPC_OR = OPC_SPECIAL | 045, 299 OPC_XOR = OPC_SPECIAL | 046, 300 OPC_NOR = OPC_SPECIAL | 047, 301 OPC_SLT = OPC_SPECIAL | 052, 302 OPC_SLTU = OPC_SPECIAL | 053, 303 OPC_DADDU = OPC_SPECIAL | 055, 304 OPC_DSUBU = OPC_SPECIAL | 057, 305 OPC_SELEQZ = OPC_SPECIAL | 065, 306 OPC_SELNEZ = OPC_SPECIAL | 067, 307 OPC_DSLL = OPC_SPECIAL | 070, 308 OPC_DSRL = OPC_SPECIAL | 072, 309 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 310 OPC_DSRA = OPC_SPECIAL | 073, 311 OPC_DSLL32 = OPC_SPECIAL | 074, 312 OPC_DSRL32 = OPC_SPECIAL | 076, 313 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 314 OPC_DSRA32 = OPC_SPECIAL | 077, 315 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 316 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 317 318 OPC_REGIMM = 001 << 26, 319 OPC_BLTZ = OPC_REGIMM | (000 << 16), 320 OPC_BGEZ = OPC_REGIMM | (001 << 16), 321 322 OPC_SPECIAL2 = 034 << 26, 323 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 324 OPC_CLZ = OPC_SPECIAL2 | 040, 325 OPC_DCLZ = OPC_SPECIAL2 | 044, 326 327 OPC_SPECIAL3 = 037 << 26, 328 OPC_EXT = OPC_SPECIAL3 | 000, 329 OPC_DEXTM = OPC_SPECIAL3 | 001, 330 OPC_DEXTU = OPC_SPECIAL3 | 002, 331 OPC_DEXT = OPC_SPECIAL3 | 003, 332 OPC_INS = OPC_SPECIAL3 | 004, 333 OPC_DINSM = OPC_SPECIAL3 | 005, 334 OPC_DINSU = OPC_SPECIAL3 | 006, 335 OPC_DINS = OPC_SPECIAL3 | 007, 336 OPC_WSBH = OPC_SPECIAL3 | 00240, 337 OPC_DSBH = OPC_SPECIAL3 | 00244, 338 OPC_DSHD = OPC_SPECIAL3 | 00544, 339 OPC_SEB = OPC_SPECIAL3 | 02040, 340 OPC_SEH = OPC_SPECIAL3 | 03040, 341 342 /* MIPS r6 doesn't have JR, JALR should be used instead */ 343 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 344 345 /* 346 * MIPS r6 replaces MUL with an alternative encoding which is 347 * backwards-compatible at the assembly level. 348 */ 349 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 350 351 /* MIPS r6 introduced names for weaker variants of SYNC. These are 352 backward compatible to previous architecture revisions. */ 353 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 354 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 355 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 356 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 357 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 358 359 /* Aliases for convenience. */ 360 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 361 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 362} MIPSInsn; 363 364/* 365 * Type reg 366 */ 367static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 368 TCGReg rd, TCGReg rs, TCGReg rt) 369{ 370 int32_t inst; 371 372 inst = opc; 373 inst |= (rs & 0x1F) << 21; 374 inst |= (rt & 0x1F) << 16; 375 inst |= (rd & 0x1F) << 11; 376 tcg_out32(s, inst); 377} 378 379/* 380 * Type immediate 381 */ 382static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 383 TCGReg rt, TCGReg rs, TCGArg imm) 384{ 385 int32_t inst; 386 387 inst = opc; 388 inst |= (rs & 0x1F) << 21; 389 inst |= (rt & 0x1F) << 16; 390 inst |= (imm & 0xffff); 391 tcg_out32(s, inst); 392} 393 394/* 395 * Type bitfield 396 */ 397static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 398 TCGReg rs, int msb, int lsb) 399{ 400 int32_t inst; 401 402 inst = opc; 403 inst |= (rs & 0x1F) << 21; 404 inst |= (rt & 0x1F) << 16; 405 inst |= (msb & 0x1F) << 11; 406 inst |= (lsb & 0x1F) << 6; 407 tcg_out32(s, inst); 408} 409 410static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 411 MIPSInsn oph, TCGReg rt, TCGReg rs, 412 int msb, int lsb) 413{ 414 if (lsb >= 32) { 415 opc = oph; 416 msb -= 32; 417 lsb -= 32; 418 } else if (msb >= 32) { 419 opc = opm; 420 msb -= 32; 421 } 422 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 423} 424 425/* 426 * Type branch 427 */ 428static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 429{ 430 tcg_out_opc_imm(s, opc, rt, rs, 0); 431} 432 433/* 434 * Type sa 435 */ 436static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 437 TCGReg rd, TCGReg rt, TCGArg sa) 438{ 439 int32_t inst; 440 441 inst = opc; 442 inst |= (rt & 0x1F) << 16; 443 inst |= (rd & 0x1F) << 11; 444 inst |= (sa & 0x1F) << 6; 445 tcg_out32(s, inst); 446 447} 448 449static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 450 TCGReg rd, TCGReg rt, TCGArg sa) 451{ 452 int32_t inst; 453 454 inst = (sa & 32 ? opc2 : opc1); 455 inst |= (rt & 0x1F) << 16; 456 inst |= (rd & 0x1F) << 11; 457 inst |= (sa & 0x1F) << 6; 458 tcg_out32(s, inst); 459} 460 461/* 462 * Type jump. 463 * Returns true if the branch was in range and the insn was emitted. 464 */ 465static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 466{ 467 uintptr_t dest = (uintptr_t)target; 468 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 469 int32_t inst; 470 471 /* The pc-region branch happens within the 256MB region of 472 the delay slot (thus the +4). */ 473 if ((from ^ dest) & -(1 << 28)) { 474 return false; 475 } 476 tcg_debug_assert((dest & 3) == 0); 477 478 inst = opc; 479 inst |= (dest >> 2) & 0x3ffffff; 480 tcg_out32(s, inst); 481 return true; 482} 483 484static void tcg_out_nop(TCGContext *s) 485{ 486 tcg_out32(s, 0); 487} 488 489static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 490{ 491 memset(p, 0, count * sizeof(tcg_insn_unit)); 492} 493 494static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 495{ 496 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 497} 498 499static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 500{ 501 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 502} 503 504static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 505{ 506 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 507} 508 509static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 510{ 511 /* Simple reg-reg move, optimising out the 'do nothing' case */ 512 if (ret != arg) { 513 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 514 } 515 return true; 516} 517 518static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 519{ 520 if (arg == (int16_t)arg) { 521 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 522 return true; 523 } 524 if (arg == (uint16_t)arg) { 525 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 526 return true; 527 } 528 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 529 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 530 return true; 531 } 532 return false; 533} 534 535static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 536{ 537 /* 538 * All signed 32-bit constants are loadable with two immediates, 539 * and everything else requires more work. 540 */ 541 if (arg == (int32_t)arg) { 542 if (!tcg_out_movi_one(s, ret, arg)) { 543 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 544 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 545 } 546 return true; 547 } 548 return false; 549} 550 551static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 552 tcg_target_long arg, TCGReg tbreg) 553{ 554 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 555 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 556} 557 558static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 559 tcg_target_long arg, TCGReg tbreg) 560{ 561 tcg_target_long tmp; 562 int sh, lo; 563 564 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 565 arg = (int32_t)arg; 566 } 567 568 /* Load all 32-bit constants. */ 569 if (tcg_out_movi_two(s, ret, arg)) { 570 return; 571 } 572 assert(TCG_TARGET_REG_BITS == 64); 573 574 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 575 tmp = tcg_tbrel_diff(s, (void *)arg); 576 if (tmp == (int16_t)tmp) { 577 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 578 return; 579 } 580 if (tcg_out_movi_two(s, ret, tmp)) { 581 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 582 return; 583 } 584 585 /* 586 * Load bitmasks with a right-shift. This is good for things 587 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 588 * or similarly using LUI. For this to work, bit 31 must be set. 589 */ 590 if (arg > 0 && (int32_t)arg < 0) { 591 sh = clz64(arg); 592 if (tcg_out_movi_one(s, ret, arg << sh)) { 593 tcg_out_dsrl(s, ret, ret, sh); 594 return; 595 } 596 } 597 598 /* 599 * Load slightly larger constants using left-shift. 600 * Limit this sequence to 3 insns to avoid too much expansion. 601 */ 602 sh = ctz64(arg); 603 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 604 tcg_out_dsll(s, ret, ret, sh); 605 return; 606 } 607 608 /* 609 * Load slightly larger constants using left-shift and add/or. 610 * Prefer addi with a negative immediate when that would produce 611 * a larger shift. For this to work, bits 15 and 16 must be set. 612 */ 613 lo = arg & 0xffff; 614 if (lo) { 615 if ((arg & 0x18000) == 0x18000) { 616 lo = (int16_t)arg; 617 } 618 tmp = arg - lo; 619 sh = ctz64(tmp); 620 tmp >>= sh; 621 if (tcg_out_movi_one(s, ret, tmp)) { 622 tcg_out_dsll(s, ret, ret, sh); 623 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 624 return; 625 } 626 } 627 628 /* Otherwise, put 64-bit constants into the constant pool. */ 629 tcg_out_movi_pool(s, ret, arg, tbreg); 630} 631 632static void tcg_out_movi(TCGContext *s, TCGType type, 633 TCGReg ret, tcg_target_long arg) 634{ 635 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 636 tcg_out_movi_int(s, type, ret, arg, tbreg); 637} 638 639static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 640{ 641 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); 642 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 643} 644 645static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 646{ 647 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 648} 649 650static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 651{ 652 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); 653 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 654} 655 656static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 657{ 658 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 659} 660 661static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 662{ 663 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 664 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 665} 666 667static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 668{ 669 if (rd != rs) { 670 tcg_out_ext32s(s, rd, rs); 671 } 672} 673 674static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 675{ 676 tcg_out_ext32u(s, rd, rs); 677} 678 679static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 680{ 681 tcg_out_ext32s(s, rd, rs); 682} 683 684static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 685{ 686 return false; 687} 688 689static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 690 tcg_target_long imm) 691{ 692 /* This function is only used for passing structs by reference. */ 693 g_assert_not_reached(); 694} 695 696static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 697{ 698 /* ret and arg can't be register tmp0 */ 699 tcg_debug_assert(ret != TCG_TMP0); 700 tcg_debug_assert(arg != TCG_TMP0); 701 702 /* With arg = abcd: */ 703 if (use_mips32r2_instructions) { 704 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 705 if (flags & TCG_BSWAP_OS) { 706 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 707 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 708 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 709 } 710 return; 711 } 712 713 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 714 if (!(flags & TCG_BSWAP_IZ)) { 715 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 716 } 717 if (flags & TCG_BSWAP_OS) { 718 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 719 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 720 } else { 721 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 722 if (flags & TCG_BSWAP_OZ) { 723 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 724 } 725 } 726 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 727} 728 729static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 730{ 731 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 732 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 733 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 734 } 735} 736 737static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 738{ 739 if (use_mips32r2_instructions) { 740 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 741 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 742 if (flags & TCG_BSWAP_OZ) { 743 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 744 } 745 } else { 746 if (flags & TCG_BSWAP_OZ) { 747 tcg_out_bswap_subr(s, bswap32u_addr); 748 } else { 749 tcg_out_bswap_subr(s, bswap32_addr); 750 } 751 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 752 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 753 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 754 } 755} 756 757static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 758{ 759 if (use_mips32r2_instructions) { 760 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 761 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 762 } else { 763 tcg_out_bswap_subr(s, bswap64_addr); 764 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 765 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 766 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 767 } 768} 769 770static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 771{ 772 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 773 if (use_mips32r2_instructions) { 774 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 775 } else { 776 tcg_out_dsll(s, ret, arg, 32); 777 tcg_out_dsrl(s, ret, ret, 32); 778 } 779} 780 781static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 782 TCGReg addr, intptr_t ofs) 783{ 784 int16_t lo = ofs; 785 if (ofs != lo) { 786 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 787 if (addr != TCG_REG_ZERO) { 788 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 789 } 790 addr = TCG_TMP0; 791 } 792 tcg_out_opc_imm(s, opc, data, addr, lo); 793} 794 795static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 796 TCGReg arg1, intptr_t arg2) 797{ 798 MIPSInsn opc = OPC_LD; 799 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 800 opc = OPC_LW; 801 } 802 tcg_out_ldst(s, opc, arg, arg1, arg2); 803} 804 805static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 806 TCGReg arg1, intptr_t arg2) 807{ 808 MIPSInsn opc = OPC_SD; 809 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 810 opc = OPC_SW; 811 } 812 tcg_out_ldst(s, opc, arg, arg1, arg2); 813} 814 815static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 816 TCGReg base, intptr_t ofs) 817{ 818 if (val == 0) { 819 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 820 return true; 821 } 822 return false; 823} 824 825static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 826 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 827 bool cbh, bool is_sub) 828{ 829 TCGReg th = TCG_TMP1; 830 831 /* If we have a negative constant such that negating it would 832 make the high part zero, we can (usually) eliminate one insn. */ 833 if (cbl && cbh && bh == -1 && bl != 0) { 834 bl = -bl; 835 bh = 0; 836 is_sub = !is_sub; 837 } 838 839 /* By operating on the high part first, we get to use the final 840 carry operation to move back from the temporary. */ 841 if (!cbh) { 842 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 843 } else if (bh != 0 || ah == rl) { 844 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 845 } else { 846 th = ah; 847 } 848 849 /* Note that tcg optimization should eliminate the bl == 0 case. */ 850 if (is_sub) { 851 if (cbl) { 852 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 853 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 854 } else { 855 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 856 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 857 } 858 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 859 } else { 860 if (cbl) { 861 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 862 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 863 } else if (rl == al && rl == bl) { 864 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 865 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 866 } else { 867 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 868 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 869 } 870 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 871 } 872} 873 874#define SETCOND_INV TCG_TARGET_NB_REGS 875#define SETCOND_NEZ (SETCOND_INV << 1) 876#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 877 878static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 879 TCGReg arg1, TCGReg arg2) 880{ 881 int flags = 0; 882 883 switch (cond) { 884 case TCG_COND_EQ: /* -> NE */ 885 case TCG_COND_GE: /* -> LT */ 886 case TCG_COND_GEU: /* -> LTU */ 887 case TCG_COND_LE: /* -> GT */ 888 case TCG_COND_LEU: /* -> GTU */ 889 cond = tcg_invert_cond(cond); 890 flags ^= SETCOND_INV; 891 break; 892 default: 893 break; 894 } 895 896 switch (cond) { 897 case TCG_COND_NE: 898 flags |= SETCOND_NEZ; 899 if (arg2 == 0) { 900 return arg1 | flags; 901 } 902 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 903 break; 904 case TCG_COND_LT: 905 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 906 break; 907 case TCG_COND_LTU: 908 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 909 break; 910 case TCG_COND_GT: 911 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 912 break; 913 case TCG_COND_GTU: 914 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 915 break; 916 default: 917 g_assert_not_reached(); 918 } 919 return ret | flags; 920} 921 922static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 923{ 924 if (tmpflags != ret) { 925 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 926 927 switch (tmpflags & SETCOND_FLAGS) { 928 case SETCOND_INV: 929 /* Intermediate result is boolean: simply invert. */ 930 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 931 break; 932 case SETCOND_NEZ: 933 /* Intermediate result is zero/non-zero: test != 0. */ 934 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 935 break; 936 case SETCOND_NEZ | SETCOND_INV: 937 /* Intermediate result is zero/non-zero: test == 0. */ 938 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 939 break; 940 default: 941 g_assert_not_reached(); 942 } 943 } 944} 945 946static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 947 TCGReg arg1, TCGReg arg2) 948{ 949 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 950 tcg_out_setcond_end(s, ret, tmpflags); 951} 952 953static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 954 TCGReg arg2, TCGLabel *l) 955{ 956 static const MIPSInsn b_zero[16] = { 957 [TCG_COND_LT] = OPC_BLTZ, 958 [TCG_COND_GT] = OPC_BGTZ, 959 [TCG_COND_LE] = OPC_BLEZ, 960 [TCG_COND_GE] = OPC_BGEZ, 961 }; 962 963 MIPSInsn b_opc = 0; 964 965 switch (cond) { 966 case TCG_COND_EQ: 967 b_opc = OPC_BEQ; 968 break; 969 case TCG_COND_NE: 970 b_opc = OPC_BNE; 971 break; 972 case TCG_COND_LT: 973 case TCG_COND_GT: 974 case TCG_COND_LE: 975 case TCG_COND_GE: 976 if (arg2 == 0) { 977 b_opc = b_zero[cond]; 978 arg2 = arg1; 979 arg1 = 0; 980 } 981 break; 982 default: 983 break; 984 } 985 986 if (b_opc == 0) { 987 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 988 989 arg2 = TCG_REG_ZERO; 990 arg1 = tmpflags & ~SETCOND_FLAGS; 991 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 992 } 993 994 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 995 tcg_out_opc_br(s, b_opc, arg1, arg2); 996 tcg_out_nop(s); 997} 998 999static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 1000 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1001{ 1002 int flags = 0; 1003 1004 switch (cond) { 1005 case TCG_COND_EQ: 1006 flags |= SETCOND_INV; 1007 /* fall through */ 1008 case TCG_COND_NE: 1009 flags |= SETCOND_NEZ; 1010 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 1011 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 1012 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1013 break; 1014 1015 default: 1016 tcg_out_setcond(s, TCG_COND_EQ, TCG_TMP0, ah, bh); 1017 tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_TMP1, al, bl); 1018 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 1019 tcg_out_setcond(s, tcg_high_cond(cond), TCG_TMP0, ah, bh); 1020 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1021 break; 1022 } 1023 return ret | flags; 1024} 1025 1026static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1027 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1028{ 1029 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1030 tcg_out_setcond_end(s, ret, tmpflags); 1031} 1032 1033static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1034 TCGReg bl, TCGReg bh, TCGLabel *l) 1035{ 1036 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1037 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1038 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1039 1040 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1041 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1042 tcg_out_nop(s); 1043} 1044 1045static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1046 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1047{ 1048 int tmpflags; 1049 bool eqz; 1050 1051 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1052 if (use_mips32r6_instructions && v1 == 0) { 1053 v1 = v2; 1054 v2 = 0; 1055 cond = tcg_invert_cond(cond); 1056 } 1057 1058 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1059 c1 = tmpflags & ~SETCOND_FLAGS; 1060 eqz = tmpflags & SETCOND_INV; 1061 1062 if (use_mips32r6_instructions) { 1063 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1064 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1065 1066 if (v2 != 0) { 1067 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1068 } 1069 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1070 if (v2 != 0) { 1071 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1072 } 1073 return; 1074 } 1075 1076 /* This should be guaranteed via constraints */ 1077 tcg_debug_assert(v2 == ret); 1078 1079 if (use_movnz_instructions) { 1080 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1081 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1082 } else { 1083 /* Invert the condition in order to branch over the move. */ 1084 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1085 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1086 tcg_out_nop(s); 1087 /* Open-code tcg_out_mov, without the nop-move check. */ 1088 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1089 } 1090} 1091 1092static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1093{ 1094 /* 1095 * Note that __mips_abicalls requires the called function's address 1096 * to be loaded into $25 (t9), even if a direct branch is in range. 1097 * 1098 * For n64, always drop the pointer into the constant pool. 1099 * We can re-use helper addresses often and do not want any 1100 * of the longer sequences tcg_out_movi may try. 1101 */ 1102 if (sizeof(uintptr_t) == 8) { 1103 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1104 } else { 1105 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1106 } 1107 1108 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1109 if (tail) { 1110 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1111 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1112 } 1113 } else { 1114 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1115 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1116 } 1117 } 1118} 1119 1120static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1121 const TCGHelperInfo *info) 1122{ 1123 tcg_out_call_int(s, arg, false); 1124 tcg_out_nop(s); 1125} 1126 1127/* We have four temps, we might as well expose three of them. */ 1128static const TCGLdstHelperParam ldst_helper_param = { 1129 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1130}; 1131 1132static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1133{ 1134 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1135 MemOp opc = get_memop(l->oi); 1136 1137 /* resolve label address */ 1138 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1139 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1140 return false; 1141 } 1142 1143 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1144 1145 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1146 /* delay slot */ 1147 tcg_out_nop(s); 1148 1149 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1150 1151 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1152 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1153 return false; 1154 } 1155 1156 /* delay slot */ 1157 tcg_out_nop(s); 1158 return true; 1159} 1160 1161static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1162{ 1163 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1164 MemOp opc = get_memop(l->oi); 1165 1166 /* resolve label address */ 1167 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1168 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1169 return false; 1170 } 1171 1172 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1173 1174 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1175 /* delay slot */ 1176 tcg_out_nop(s); 1177 1178 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1179 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1180 return false; 1181 } 1182 1183 /* delay slot */ 1184 tcg_out_nop(s); 1185 return true; 1186} 1187 1188typedef struct { 1189 TCGReg base; 1190 TCGAtomAlign aa; 1191} HostAddress; 1192 1193bool tcg_target_has_memory_bswap(MemOp memop) 1194{ 1195 return false; 1196} 1197 1198/* We expect to use a 16-bit negative offset from ENV. */ 1199#define MIN_TLB_MASK_TABLE_OFS -32768 1200 1201/* 1202 * For system-mode, perform the TLB load and compare. 1203 * For user-mode, perform any required alignment tests. 1204 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1205 * is required and fill in @h with the host address for the fast path. 1206 */ 1207static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1208 TCGReg addrlo, TCGReg addrhi, 1209 MemOpIdx oi, bool is_ld) 1210{ 1211 TCGType addr_type = s->addr_type; 1212 TCGLabelQemuLdst *ldst = NULL; 1213 MemOp opc = get_memop(oi); 1214 MemOp a_bits; 1215 unsigned s_bits = opc & MO_SIZE; 1216 unsigned a_mask; 1217 TCGReg base; 1218 1219 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1220 a_bits = h->aa.align; 1221 a_mask = (1 << a_bits) - 1; 1222 1223 if (tcg_use_softmmu) { 1224 unsigned s_mask = (1 << s_bits) - 1; 1225 int mem_index = get_mmuidx(oi); 1226 int fast_off = tlb_mask_table_ofs(s, mem_index); 1227 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1228 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1229 int add_off = offsetof(CPUTLBEntry, addend); 1230 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1231 : offsetof(CPUTLBEntry, addr_write); 1232 1233 ldst = new_ldst_label(s); 1234 ldst->is_ld = is_ld; 1235 ldst->oi = oi; 1236 ldst->addrlo_reg = addrlo; 1237 ldst->addrhi_reg = addrhi; 1238 1239 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1240 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1241 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1242 1243 /* Extract the TLB index from the address into TMP3. */ 1244 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1245 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, 1246 s->page_bits - CPU_TLB_ENTRY_BITS); 1247 } else { 1248 tcg_out_dsrl(s, TCG_TMP3, addrlo, 1249 s->page_bits - CPU_TLB_ENTRY_BITS); 1250 } 1251 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1252 1253 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1254 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1255 1256 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1257 /* Load the (low half) tlb comparator. */ 1258 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1259 cmp_off + HOST_BIG_ENDIAN * 4); 1260 } else { 1261 tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off); 1262 } 1263 1264 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { 1265 /* Load the tlb addend for the fast path. */ 1266 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1267 } 1268 1269 /* 1270 * Mask the page bits, keeping the alignment bits to compare against. 1271 * For unaligned accesses, compare against the end of the access to 1272 * verify that it does not cross a page boundary. 1273 */ 1274 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1275 if (a_mask < s_mask) { 1276 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1277 || addr_type == TCG_TYPE_I32 1278 ? OPC_ADDIU : OPC_DADDIU), 1279 TCG_TMP2, addrlo, s_mask - a_mask); 1280 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1281 } else { 1282 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); 1283 } 1284 1285 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1286 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1287 tcg_out_ext32u(s, TCG_TMP2, addrlo); 1288 addrlo = TCG_TMP2; 1289 } 1290 1291 ldst->label_ptr[0] = s->code_ptr; 1292 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1293 1294 /* Load and test the high half tlb comparator. */ 1295 if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { 1296 /* delay slot */ 1297 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1298 1299 /* Load the tlb addend for the fast path. */ 1300 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1301 1302 ldst->label_ptr[1] = s->code_ptr; 1303 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); 1304 } 1305 1306 /* delay slot */ 1307 base = TCG_TMP3; 1308 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); 1309 } else { 1310 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1311 ldst = new_ldst_label(s); 1312 1313 ldst->is_ld = is_ld; 1314 ldst->oi = oi; 1315 ldst->addrlo_reg = addrlo; 1316 ldst->addrhi_reg = addrhi; 1317 1318 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1319 tcg_debug_assert(a_bits < 16); 1320 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); 1321 1322 ldst->label_ptr[0] = s->code_ptr; 1323 if (use_mips32r6_instructions) { 1324 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1325 } else { 1326 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1327 tcg_out_nop(s); 1328 } 1329 } 1330 1331 base = addrlo; 1332 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1333 tcg_out_ext32u(s, TCG_REG_A0, base); 1334 base = TCG_REG_A0; 1335 } 1336 if (guest_base) { 1337 if (guest_base == (int16_t)guest_base) { 1338 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1339 } else { 1340 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1341 TCG_GUEST_BASE_REG); 1342 } 1343 base = TCG_REG_A0; 1344 } 1345 } 1346 1347 h->base = base; 1348 return ldst; 1349} 1350 1351static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1352 TCGReg base, MemOp opc, TCGType type) 1353{ 1354 switch (opc & MO_SSIZE) { 1355 case MO_UB: 1356 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1357 break; 1358 case MO_SB: 1359 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1360 break; 1361 case MO_UW: 1362 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1363 break; 1364 case MO_SW: 1365 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1366 break; 1367 case MO_UL: 1368 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1369 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1370 break; 1371 } 1372 /* FALLTHRU */ 1373 case MO_SL: 1374 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1375 break; 1376 case MO_UQ: 1377 /* Prefer to load from offset 0 first, but allow for overlap. */ 1378 if (TCG_TARGET_REG_BITS == 64) { 1379 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1380 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1381 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1382 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1383 } else { 1384 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1385 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1386 } 1387 break; 1388 default: 1389 g_assert_not_reached(); 1390 } 1391} 1392 1393static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1394 TCGReg base, MemOp opc, TCGType type) 1395{ 1396 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1397 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1398 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1399 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1400 bool sgn = opc & MO_SIGN; 1401 1402 switch (opc & MO_SIZE) { 1403 case MO_16: 1404 if (HOST_BIG_ENDIAN) { 1405 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1406 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1407 if (use_mips32r2_instructions) { 1408 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1409 } else { 1410 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1411 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1412 } 1413 } else if (use_mips32r2_instructions && lo != base) { 1414 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1415 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1416 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1417 } else { 1418 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1419 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1420 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1421 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1422 } 1423 break; 1424 1425 case MO_32: 1426 tcg_out_opc_imm(s, lw1, lo, base, 0); 1427 tcg_out_opc_imm(s, lw2, lo, base, 3); 1428 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1429 tcg_out_ext32u(s, lo, lo); 1430 } 1431 break; 1432 1433 case MO_64: 1434 if (TCG_TARGET_REG_BITS == 64) { 1435 tcg_out_opc_imm(s, ld1, lo, base, 0); 1436 tcg_out_opc_imm(s, ld2, lo, base, 7); 1437 } else { 1438 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1439 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1440 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1441 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1442 } 1443 break; 1444 1445 default: 1446 g_assert_not_reached(); 1447 } 1448} 1449 1450static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1451 TCGReg addrlo, TCGReg addrhi, 1452 MemOpIdx oi, TCGType data_type) 1453{ 1454 MemOp opc = get_memop(oi); 1455 TCGLabelQemuLdst *ldst; 1456 HostAddress h; 1457 1458 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 1459 1460 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1461 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1462 } else { 1463 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1464 } 1465 1466 if (ldst) { 1467 ldst->type = data_type; 1468 ldst->datalo_reg = datalo; 1469 ldst->datahi_reg = datahi; 1470 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1471 } 1472} 1473 1474static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1475 TCGReg base, MemOp opc) 1476{ 1477 switch (opc & MO_SIZE) { 1478 case MO_8: 1479 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1480 break; 1481 case MO_16: 1482 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1483 break; 1484 case MO_32: 1485 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1486 break; 1487 case MO_64: 1488 if (TCG_TARGET_REG_BITS == 64) { 1489 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1490 } else { 1491 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1492 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1493 } 1494 break; 1495 default: 1496 g_assert_not_reached(); 1497 } 1498} 1499 1500static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1501 TCGReg base, MemOp opc) 1502{ 1503 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1504 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1505 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1506 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1507 1508 switch (opc & MO_SIZE) { 1509 case MO_16: 1510 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1511 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1512 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1513 break; 1514 1515 case MO_32: 1516 tcg_out_opc_imm(s, sw1, lo, base, 0); 1517 tcg_out_opc_imm(s, sw2, lo, base, 3); 1518 break; 1519 1520 case MO_64: 1521 if (TCG_TARGET_REG_BITS == 64) { 1522 tcg_out_opc_imm(s, sd1, lo, base, 0); 1523 tcg_out_opc_imm(s, sd2, lo, base, 7); 1524 } else { 1525 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1526 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1527 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1528 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1529 } 1530 break; 1531 1532 default: 1533 g_assert_not_reached(); 1534 } 1535} 1536 1537static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1538 TCGReg addrlo, TCGReg addrhi, 1539 MemOpIdx oi, TCGType data_type) 1540{ 1541 MemOp opc = get_memop(oi); 1542 TCGLabelQemuLdst *ldst; 1543 HostAddress h; 1544 1545 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 1546 1547 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1548 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1549 } else { 1550 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1551 } 1552 1553 if (ldst) { 1554 ldst->type = data_type; 1555 ldst->datalo_reg = datalo; 1556 ldst->datahi_reg = datahi; 1557 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1558 } 1559} 1560 1561static void tcg_out_mb(TCGContext *s, TCGArg a0) 1562{ 1563 static const MIPSInsn sync[] = { 1564 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1565 as the former is an ordering barrier and the latter 1566 is a completion barrier. */ 1567 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1568 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1569 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1570 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1571 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1572 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1573 }; 1574 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1575} 1576 1577static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1578 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1579{ 1580 if (use_mips32r6_instructions) { 1581 if (a2 == width) { 1582 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1583 } else { 1584 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1585 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1586 } 1587 } else { 1588 if (a2 == width) { 1589 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1590 } else if (a0 == a2) { 1591 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1592 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1593 } else if (a0 != a1) { 1594 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1595 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1596 } else { 1597 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1598 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1599 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1600 } 1601 } 1602} 1603 1604static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1605{ 1606 TCGReg base = TCG_REG_ZERO; 1607 int16_t lo = 0; 1608 1609 if (a0) { 1610 intptr_t ofs; 1611 if (TCG_TARGET_REG_BITS == 64) { 1612 ofs = tcg_tbrel_diff(s, (void *)a0); 1613 lo = ofs; 1614 if (ofs == lo) { 1615 base = TCG_REG_TB; 1616 } else { 1617 base = TCG_REG_V0; 1618 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1619 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1620 } 1621 } else { 1622 ofs = a0; 1623 lo = ofs; 1624 base = TCG_REG_V0; 1625 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1626 } 1627 } 1628 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1629 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1630 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1631 } 1632 /* delay slot */ 1633 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1634} 1635 1636static void tcg_out_goto_tb(TCGContext *s, int which) 1637{ 1638 intptr_t ofs = get_jmp_target_addr(s, which); 1639 TCGReg base, dest; 1640 1641 /* indirect jump method */ 1642 if (TCG_TARGET_REG_BITS == 64) { 1643 dest = TCG_REG_TB; 1644 base = TCG_REG_TB; 1645 ofs = tcg_tbrel_diff(s, (void *)ofs); 1646 } else { 1647 dest = TCG_TMP0; 1648 base = TCG_REG_ZERO; 1649 } 1650 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1651 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1652 /* delay slot */ 1653 tcg_out_nop(s); 1654 1655 set_jmp_reset_offset(s, which); 1656 if (TCG_TARGET_REG_BITS == 64) { 1657 /* For the unlinked case, need to reset TCG_REG_TB. */ 1658 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1659 -tcg_current_code_size(s)); 1660 } 1661} 1662 1663void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1664 uintptr_t jmp_rx, uintptr_t jmp_rw) 1665{ 1666 /* Always indirect, nothing to do */ 1667} 1668 1669static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1670 const TCGArg args[TCG_MAX_OP_ARGS], 1671 const int const_args[TCG_MAX_OP_ARGS]) 1672{ 1673 MIPSInsn i1, i2; 1674 TCGArg a0, a1, a2; 1675 int c2; 1676 1677 /* 1678 * Note that many operands use the constraint set "rZ". 1679 * We make use of the fact that 0 is the ZERO register, 1680 * and hence such cases need not check for const_args. 1681 */ 1682 a0 = args[0]; 1683 a1 = args[1]; 1684 a2 = args[2]; 1685 c2 = const_args[2]; 1686 1687 switch (opc) { 1688 case INDEX_op_goto_ptr: 1689 /* jmp to the given host address (could be epilogue) */ 1690 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1691 if (TCG_TARGET_REG_BITS == 64) { 1692 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 1693 } else { 1694 tcg_out_nop(s); 1695 } 1696 break; 1697 case INDEX_op_br: 1698 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1699 arg_label(a0)); 1700 break; 1701 1702 case INDEX_op_ld8u_i32: 1703 case INDEX_op_ld8u_i64: 1704 i1 = OPC_LBU; 1705 goto do_ldst; 1706 case INDEX_op_ld8s_i32: 1707 case INDEX_op_ld8s_i64: 1708 i1 = OPC_LB; 1709 goto do_ldst; 1710 case INDEX_op_ld16u_i32: 1711 case INDEX_op_ld16u_i64: 1712 i1 = OPC_LHU; 1713 goto do_ldst; 1714 case INDEX_op_ld16s_i32: 1715 case INDEX_op_ld16s_i64: 1716 i1 = OPC_LH; 1717 goto do_ldst; 1718 case INDEX_op_ld_i32: 1719 case INDEX_op_ld32s_i64: 1720 i1 = OPC_LW; 1721 goto do_ldst; 1722 case INDEX_op_ld32u_i64: 1723 i1 = OPC_LWU; 1724 goto do_ldst; 1725 case INDEX_op_ld_i64: 1726 i1 = OPC_LD; 1727 goto do_ldst; 1728 case INDEX_op_st8_i32: 1729 case INDEX_op_st8_i64: 1730 i1 = OPC_SB; 1731 goto do_ldst; 1732 case INDEX_op_st16_i32: 1733 case INDEX_op_st16_i64: 1734 i1 = OPC_SH; 1735 goto do_ldst; 1736 case INDEX_op_st_i32: 1737 case INDEX_op_st32_i64: 1738 i1 = OPC_SW; 1739 goto do_ldst; 1740 case INDEX_op_st_i64: 1741 i1 = OPC_SD; 1742 do_ldst: 1743 tcg_out_ldst(s, i1, a0, a1, a2); 1744 break; 1745 1746 case INDEX_op_add_i32: 1747 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1748 goto do_binary; 1749 case INDEX_op_add_i64: 1750 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1751 goto do_binary; 1752 case INDEX_op_or_i32: 1753 case INDEX_op_or_i64: 1754 i1 = OPC_OR, i2 = OPC_ORI; 1755 goto do_binary; 1756 case INDEX_op_xor_i32: 1757 case INDEX_op_xor_i64: 1758 i1 = OPC_XOR, i2 = OPC_XORI; 1759 do_binary: 1760 if (c2) { 1761 tcg_out_opc_imm(s, i2, a0, a1, a2); 1762 break; 1763 } 1764 do_binaryv: 1765 tcg_out_opc_reg(s, i1, a0, a1, a2); 1766 break; 1767 1768 case INDEX_op_sub_i32: 1769 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1770 goto do_subtract; 1771 case INDEX_op_sub_i64: 1772 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1773 do_subtract: 1774 if (c2) { 1775 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1776 break; 1777 } 1778 goto do_binaryv; 1779 case INDEX_op_and_i32: 1780 if (c2 && a2 != (uint16_t)a2) { 1781 int msb = ctz32(~a2) - 1; 1782 tcg_debug_assert(use_mips32r2_instructions); 1783 tcg_debug_assert(is_p2m1(a2)); 1784 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1785 break; 1786 } 1787 i1 = OPC_AND, i2 = OPC_ANDI; 1788 goto do_binary; 1789 case INDEX_op_and_i64: 1790 if (c2 && a2 != (uint16_t)a2) { 1791 int msb = ctz64(~a2) - 1; 1792 tcg_debug_assert(use_mips32r2_instructions); 1793 tcg_debug_assert(is_p2m1(a2)); 1794 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1795 break; 1796 } 1797 i1 = OPC_AND, i2 = OPC_ANDI; 1798 goto do_binary; 1799 case INDEX_op_nor_i32: 1800 case INDEX_op_nor_i64: 1801 i1 = OPC_NOR; 1802 goto do_binaryv; 1803 1804 case INDEX_op_mul_i32: 1805 if (use_mips32_instructions) { 1806 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1807 break; 1808 } 1809 i1 = OPC_MULT, i2 = OPC_MFLO; 1810 goto do_hilo1; 1811 case INDEX_op_mulsh_i32: 1812 if (use_mips32r6_instructions) { 1813 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1814 break; 1815 } 1816 i1 = OPC_MULT, i2 = OPC_MFHI; 1817 goto do_hilo1; 1818 case INDEX_op_muluh_i32: 1819 if (use_mips32r6_instructions) { 1820 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1821 break; 1822 } 1823 i1 = OPC_MULTU, i2 = OPC_MFHI; 1824 goto do_hilo1; 1825 case INDEX_op_div_i32: 1826 if (use_mips32r6_instructions) { 1827 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1828 break; 1829 } 1830 i1 = OPC_DIV, i2 = OPC_MFLO; 1831 goto do_hilo1; 1832 case INDEX_op_divu_i32: 1833 if (use_mips32r6_instructions) { 1834 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1835 break; 1836 } 1837 i1 = OPC_DIVU, i2 = OPC_MFLO; 1838 goto do_hilo1; 1839 case INDEX_op_rem_i32: 1840 if (use_mips32r6_instructions) { 1841 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1842 break; 1843 } 1844 i1 = OPC_DIV, i2 = OPC_MFHI; 1845 goto do_hilo1; 1846 case INDEX_op_remu_i32: 1847 if (use_mips32r6_instructions) { 1848 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1849 break; 1850 } 1851 i1 = OPC_DIVU, i2 = OPC_MFHI; 1852 goto do_hilo1; 1853 case INDEX_op_mul_i64: 1854 if (use_mips32r6_instructions) { 1855 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1856 break; 1857 } 1858 i1 = OPC_DMULT, i2 = OPC_MFLO; 1859 goto do_hilo1; 1860 case INDEX_op_mulsh_i64: 1861 if (use_mips32r6_instructions) { 1862 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1863 break; 1864 } 1865 i1 = OPC_DMULT, i2 = OPC_MFHI; 1866 goto do_hilo1; 1867 case INDEX_op_muluh_i64: 1868 if (use_mips32r6_instructions) { 1869 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1870 break; 1871 } 1872 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1873 goto do_hilo1; 1874 case INDEX_op_div_i64: 1875 if (use_mips32r6_instructions) { 1876 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1877 break; 1878 } 1879 i1 = OPC_DDIV, i2 = OPC_MFLO; 1880 goto do_hilo1; 1881 case INDEX_op_divu_i64: 1882 if (use_mips32r6_instructions) { 1883 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1884 break; 1885 } 1886 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1887 goto do_hilo1; 1888 case INDEX_op_rem_i64: 1889 if (use_mips32r6_instructions) { 1890 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1891 break; 1892 } 1893 i1 = OPC_DDIV, i2 = OPC_MFHI; 1894 goto do_hilo1; 1895 case INDEX_op_remu_i64: 1896 if (use_mips32r6_instructions) { 1897 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1898 break; 1899 } 1900 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1901 do_hilo1: 1902 tcg_out_opc_reg(s, i1, 0, a1, a2); 1903 tcg_out_opc_reg(s, i2, a0, 0, 0); 1904 break; 1905 1906 case INDEX_op_muls2_i32: 1907 i1 = OPC_MULT; 1908 goto do_hilo2; 1909 case INDEX_op_mulu2_i32: 1910 i1 = OPC_MULTU; 1911 goto do_hilo2; 1912 case INDEX_op_muls2_i64: 1913 i1 = OPC_DMULT; 1914 goto do_hilo2; 1915 case INDEX_op_mulu2_i64: 1916 i1 = OPC_DMULTU; 1917 do_hilo2: 1918 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1919 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1920 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1921 break; 1922 1923 case INDEX_op_neg_i32: 1924 i1 = OPC_SUBU; 1925 goto do_unary; 1926 case INDEX_op_neg_i64: 1927 i1 = OPC_DSUBU; 1928 goto do_unary; 1929 case INDEX_op_not_i32: 1930 case INDEX_op_not_i64: 1931 i1 = OPC_NOR; 1932 goto do_unary; 1933 do_unary: 1934 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1935 break; 1936 1937 case INDEX_op_bswap16_i32: 1938 case INDEX_op_bswap16_i64: 1939 tcg_out_bswap16(s, a0, a1, a2); 1940 break; 1941 case INDEX_op_bswap32_i32: 1942 tcg_out_bswap32(s, a0, a1, 0); 1943 break; 1944 case INDEX_op_bswap32_i64: 1945 tcg_out_bswap32(s, a0, a1, a2); 1946 break; 1947 case INDEX_op_bswap64_i64: 1948 tcg_out_bswap64(s, a0, a1); 1949 break; 1950 case INDEX_op_extrh_i64_i32: 1951 tcg_out_dsra(s, a0, a1, 32); 1952 break; 1953 1954 case INDEX_op_sar_i32: 1955 i1 = OPC_SRAV, i2 = OPC_SRA; 1956 goto do_shift; 1957 case INDEX_op_shl_i32: 1958 i1 = OPC_SLLV, i2 = OPC_SLL; 1959 goto do_shift; 1960 case INDEX_op_shr_i32: 1961 i1 = OPC_SRLV, i2 = OPC_SRL; 1962 goto do_shift; 1963 case INDEX_op_rotr_i32: 1964 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1965 do_shift: 1966 if (c2) { 1967 tcg_out_opc_sa(s, i2, a0, a1, a2); 1968 break; 1969 } 1970 do_shiftv: 1971 tcg_out_opc_reg(s, i1, a0, a2, a1); 1972 break; 1973 case INDEX_op_rotl_i32: 1974 if (c2) { 1975 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 1976 } else { 1977 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1978 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 1979 } 1980 break; 1981 case INDEX_op_sar_i64: 1982 if (c2) { 1983 tcg_out_dsra(s, a0, a1, a2); 1984 break; 1985 } 1986 i1 = OPC_DSRAV; 1987 goto do_shiftv; 1988 case INDEX_op_shl_i64: 1989 if (c2) { 1990 tcg_out_dsll(s, a0, a1, a2); 1991 break; 1992 } 1993 i1 = OPC_DSLLV; 1994 goto do_shiftv; 1995 case INDEX_op_shr_i64: 1996 if (c2) { 1997 tcg_out_dsrl(s, a0, a1, a2); 1998 break; 1999 } 2000 i1 = OPC_DSRLV; 2001 goto do_shiftv; 2002 case INDEX_op_rotr_i64: 2003 if (c2) { 2004 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2005 break; 2006 } 2007 i1 = OPC_DROTRV; 2008 goto do_shiftv; 2009 case INDEX_op_rotl_i64: 2010 if (c2) { 2011 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2012 } else { 2013 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2014 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2015 } 2016 break; 2017 2018 case INDEX_op_clz_i32: 2019 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2020 break; 2021 case INDEX_op_clz_i64: 2022 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2023 break; 2024 2025 case INDEX_op_deposit_i32: 2026 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2027 break; 2028 case INDEX_op_deposit_i64: 2029 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2030 args[3] + args[4] - 1, args[3]); 2031 break; 2032 case INDEX_op_extract_i32: 2033 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2034 break; 2035 case INDEX_op_extract_i64: 2036 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2037 args[3] - 1, a2); 2038 break; 2039 2040 case INDEX_op_brcond_i32: 2041 case INDEX_op_brcond_i64: 2042 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2043 break; 2044 case INDEX_op_brcond2_i32: 2045 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2046 break; 2047 2048 case INDEX_op_movcond_i32: 2049 case INDEX_op_movcond_i64: 2050 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2051 break; 2052 2053 case INDEX_op_setcond_i32: 2054 case INDEX_op_setcond_i64: 2055 tcg_out_setcond(s, args[3], a0, a1, a2); 2056 break; 2057 case INDEX_op_setcond2_i32: 2058 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2059 break; 2060 2061 case INDEX_op_qemu_ld_a64_i32: 2062 if (TCG_TARGET_REG_BITS == 32) { 2063 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 2064 break; 2065 } 2066 /* fall through */ 2067 case INDEX_op_qemu_ld_a32_i32: 2068 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 2069 break; 2070 case INDEX_op_qemu_ld_a32_i64: 2071 if (TCG_TARGET_REG_BITS == 64) { 2072 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2073 } else { 2074 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 2075 } 2076 break; 2077 case INDEX_op_qemu_ld_a64_i64: 2078 if (TCG_TARGET_REG_BITS == 64) { 2079 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2080 } else { 2081 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2082 } 2083 break; 2084 2085 case INDEX_op_qemu_st_a64_i32: 2086 if (TCG_TARGET_REG_BITS == 32) { 2087 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 2088 break; 2089 } 2090 /* fall through */ 2091 case INDEX_op_qemu_st_a32_i32: 2092 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 2093 break; 2094 case INDEX_op_qemu_st_a32_i64: 2095 if (TCG_TARGET_REG_BITS == 64) { 2096 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2097 } else { 2098 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 2099 } 2100 break; 2101 case INDEX_op_qemu_st_a64_i64: 2102 if (TCG_TARGET_REG_BITS == 64) { 2103 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2104 } else { 2105 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2106 } 2107 break; 2108 2109 case INDEX_op_add2_i32: 2110 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2111 const_args[4], const_args[5], false); 2112 break; 2113 case INDEX_op_sub2_i32: 2114 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2115 const_args[4], const_args[5], true); 2116 break; 2117 2118 case INDEX_op_mb: 2119 tcg_out_mb(s, a0); 2120 break; 2121 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2122 case INDEX_op_mov_i64: 2123 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2124 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2125 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2126 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2127 case INDEX_op_ext8s_i64: 2128 case INDEX_op_ext8u_i32: 2129 case INDEX_op_ext8u_i64: 2130 case INDEX_op_ext16s_i32: 2131 case INDEX_op_ext16s_i64: 2132 case INDEX_op_ext32s_i64: 2133 case INDEX_op_ext32u_i64: 2134 case INDEX_op_ext_i32_i64: 2135 case INDEX_op_extu_i32_i64: 2136 case INDEX_op_extrl_i64_i32: 2137 default: 2138 g_assert_not_reached(); 2139 } 2140} 2141 2142static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2143{ 2144 switch (op) { 2145 case INDEX_op_goto_ptr: 2146 return C_O0_I1(r); 2147 2148 case INDEX_op_ld8u_i32: 2149 case INDEX_op_ld8s_i32: 2150 case INDEX_op_ld16u_i32: 2151 case INDEX_op_ld16s_i32: 2152 case INDEX_op_ld_i32: 2153 case INDEX_op_neg_i32: 2154 case INDEX_op_not_i32: 2155 case INDEX_op_bswap16_i32: 2156 case INDEX_op_bswap32_i32: 2157 case INDEX_op_ext8s_i32: 2158 case INDEX_op_ext16s_i32: 2159 case INDEX_op_extract_i32: 2160 case INDEX_op_ld8u_i64: 2161 case INDEX_op_ld8s_i64: 2162 case INDEX_op_ld16u_i64: 2163 case INDEX_op_ld16s_i64: 2164 case INDEX_op_ld32s_i64: 2165 case INDEX_op_ld32u_i64: 2166 case INDEX_op_ld_i64: 2167 case INDEX_op_neg_i64: 2168 case INDEX_op_not_i64: 2169 case INDEX_op_bswap16_i64: 2170 case INDEX_op_bswap32_i64: 2171 case INDEX_op_bswap64_i64: 2172 case INDEX_op_ext8s_i64: 2173 case INDEX_op_ext16s_i64: 2174 case INDEX_op_ext32s_i64: 2175 case INDEX_op_ext32u_i64: 2176 case INDEX_op_ext_i32_i64: 2177 case INDEX_op_extu_i32_i64: 2178 case INDEX_op_extrl_i64_i32: 2179 case INDEX_op_extrh_i64_i32: 2180 case INDEX_op_extract_i64: 2181 return C_O1_I1(r, r); 2182 2183 case INDEX_op_st8_i32: 2184 case INDEX_op_st16_i32: 2185 case INDEX_op_st_i32: 2186 case INDEX_op_st8_i64: 2187 case INDEX_op_st16_i64: 2188 case INDEX_op_st32_i64: 2189 case INDEX_op_st_i64: 2190 return C_O0_I2(rZ, r); 2191 2192 case INDEX_op_add_i32: 2193 case INDEX_op_add_i64: 2194 return C_O1_I2(r, r, rJ); 2195 case INDEX_op_sub_i32: 2196 case INDEX_op_sub_i64: 2197 return C_O1_I2(r, rZ, rN); 2198 case INDEX_op_mul_i32: 2199 case INDEX_op_mulsh_i32: 2200 case INDEX_op_muluh_i32: 2201 case INDEX_op_div_i32: 2202 case INDEX_op_divu_i32: 2203 case INDEX_op_rem_i32: 2204 case INDEX_op_remu_i32: 2205 case INDEX_op_nor_i32: 2206 case INDEX_op_setcond_i32: 2207 case INDEX_op_mul_i64: 2208 case INDEX_op_mulsh_i64: 2209 case INDEX_op_muluh_i64: 2210 case INDEX_op_div_i64: 2211 case INDEX_op_divu_i64: 2212 case INDEX_op_rem_i64: 2213 case INDEX_op_remu_i64: 2214 case INDEX_op_nor_i64: 2215 case INDEX_op_setcond_i64: 2216 return C_O1_I2(r, rZ, rZ); 2217 case INDEX_op_muls2_i32: 2218 case INDEX_op_mulu2_i32: 2219 case INDEX_op_muls2_i64: 2220 case INDEX_op_mulu2_i64: 2221 return C_O2_I2(r, r, r, r); 2222 case INDEX_op_and_i32: 2223 case INDEX_op_and_i64: 2224 return C_O1_I2(r, r, rIK); 2225 case INDEX_op_or_i32: 2226 case INDEX_op_xor_i32: 2227 case INDEX_op_or_i64: 2228 case INDEX_op_xor_i64: 2229 return C_O1_I2(r, r, rI); 2230 case INDEX_op_shl_i32: 2231 case INDEX_op_shr_i32: 2232 case INDEX_op_sar_i32: 2233 case INDEX_op_rotr_i32: 2234 case INDEX_op_rotl_i32: 2235 case INDEX_op_shl_i64: 2236 case INDEX_op_shr_i64: 2237 case INDEX_op_sar_i64: 2238 case INDEX_op_rotr_i64: 2239 case INDEX_op_rotl_i64: 2240 return C_O1_I2(r, r, ri); 2241 case INDEX_op_clz_i32: 2242 case INDEX_op_clz_i64: 2243 return C_O1_I2(r, r, rWZ); 2244 2245 case INDEX_op_deposit_i32: 2246 case INDEX_op_deposit_i64: 2247 return C_O1_I2(r, 0, rZ); 2248 case INDEX_op_brcond_i32: 2249 case INDEX_op_brcond_i64: 2250 return C_O0_I2(rZ, rZ); 2251 case INDEX_op_movcond_i32: 2252 case INDEX_op_movcond_i64: 2253 return (use_mips32r6_instructions 2254 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2255 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2256 case INDEX_op_add2_i32: 2257 case INDEX_op_sub2_i32: 2258 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2259 case INDEX_op_setcond2_i32: 2260 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2261 case INDEX_op_brcond2_i32: 2262 return C_O0_I4(rZ, rZ, rZ, rZ); 2263 2264 case INDEX_op_qemu_ld_a32_i32: 2265 return C_O1_I1(r, r); 2266 case INDEX_op_qemu_ld_a64_i32: 2267 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r); 2268 case INDEX_op_qemu_st_a32_i32: 2269 return C_O0_I2(rZ, r); 2270 case INDEX_op_qemu_st_a64_i32: 2271 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r); 2272 case INDEX_op_qemu_ld_a32_i64: 2273 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2274 case INDEX_op_qemu_ld_a64_i64: 2275 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r); 2276 case INDEX_op_qemu_st_a32_i64: 2277 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r); 2278 case INDEX_op_qemu_st_a64_i64: 2279 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) 2280 : C_O0_I4(rZ, rZ, r, r)); 2281 2282 default: 2283 g_assert_not_reached(); 2284 } 2285} 2286 2287static const int tcg_target_callee_save_regs[] = { 2288 TCG_REG_S0, 2289 TCG_REG_S1, 2290 TCG_REG_S2, 2291 TCG_REG_S3, 2292 TCG_REG_S4, 2293 TCG_REG_S5, 2294 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2295 TCG_REG_S7, /* used for guest_base */ 2296 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2297 TCG_REG_RA, /* should be last for ABI compliance */ 2298}; 2299 2300/* The Linux kernel doesn't provide any information about the available 2301 instruction set. Probe it using a signal handler. */ 2302 2303 2304#ifndef use_movnz_instructions 2305bool use_movnz_instructions = false; 2306#endif 2307 2308#ifndef use_mips32_instructions 2309bool use_mips32_instructions = false; 2310#endif 2311 2312#ifndef use_mips32r2_instructions 2313bool use_mips32r2_instructions = false; 2314#endif 2315 2316static volatile sig_atomic_t got_sigill; 2317 2318static void sigill_handler(int signo, siginfo_t *si, void *data) 2319{ 2320 /* Skip the faulty instruction */ 2321 ucontext_t *uc = (ucontext_t *)data; 2322 uc->uc_mcontext.pc += 4; 2323 2324 got_sigill = 1; 2325} 2326 2327static void tcg_target_detect_isa(void) 2328{ 2329 struct sigaction sa_old, sa_new; 2330 2331 memset(&sa_new, 0, sizeof(sa_new)); 2332 sa_new.sa_flags = SA_SIGINFO; 2333 sa_new.sa_sigaction = sigill_handler; 2334 sigaction(SIGILL, &sa_new, &sa_old); 2335 2336 /* Probe for movn/movz, necessary to implement movcond. */ 2337#ifndef use_movnz_instructions 2338 got_sigill = 0; 2339 asm volatile(".set push\n" 2340 ".set mips32\n" 2341 "movn $zero, $zero, $zero\n" 2342 "movz $zero, $zero, $zero\n" 2343 ".set pop\n" 2344 : : : ); 2345 use_movnz_instructions = !got_sigill; 2346#endif 2347 2348 /* Probe for MIPS32 instructions. As no subsetting is allowed 2349 by the specification, it is only necessary to probe for one 2350 of the instructions. */ 2351#ifndef use_mips32_instructions 2352 got_sigill = 0; 2353 asm volatile(".set push\n" 2354 ".set mips32\n" 2355 "mul $zero, $zero\n" 2356 ".set pop\n" 2357 : : : ); 2358 use_mips32_instructions = !got_sigill; 2359#endif 2360 2361 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2362 available. As no subsetting is allowed by the specification, 2363 it is only necessary to probe for one of the instructions. */ 2364#ifndef use_mips32r2_instructions 2365 if (use_mips32_instructions) { 2366 got_sigill = 0; 2367 asm volatile(".set push\n" 2368 ".set mips32r2\n" 2369 "seb $zero, $zero\n" 2370 ".set pop\n" 2371 : : : ); 2372 use_mips32r2_instructions = !got_sigill; 2373 } 2374#endif 2375 2376 sigaction(SIGILL, &sa_old, NULL); 2377} 2378 2379static tcg_insn_unit *align_code_ptr(TCGContext *s) 2380{ 2381 uintptr_t p = (uintptr_t)s->code_ptr; 2382 if (p & 15) { 2383 p = (p + 15) & -16; 2384 s->code_ptr = (void *)p; 2385 } 2386 return s->code_ptr; 2387} 2388 2389/* Stack frame parameters. */ 2390#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2391#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2392#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2393 2394#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2395 + TCG_TARGET_STACK_ALIGN - 1) \ 2396 & -TCG_TARGET_STACK_ALIGN) 2397#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2398 2399/* We're expecting to be able to use an immediate for frame allocation. */ 2400QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2401 2402/* Generate global QEMU prologue and epilogue code */ 2403static void tcg_target_qemu_prologue(TCGContext *s) 2404{ 2405 int i; 2406 2407 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2408 2409 /* TB prologue */ 2410 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2411 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2412 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2413 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2414 } 2415 2416 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2417 /* 2418 * The function call abi for n32 and n64 will have loaded $25 (t9) 2419 * with the address of the prologue, so we can use that instead 2420 * of TCG_REG_TB. 2421 */ 2422#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2423# error "Unknown mips abi" 2424#endif 2425 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2426 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2427 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2428 } 2429 2430 if (TCG_TARGET_REG_BITS == 64) { 2431 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2432 } 2433 2434 /* Call generated code */ 2435 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2436 /* delay slot */ 2437 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2438 2439 /* 2440 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2441 * and fall through to the rest of the epilogue. 2442 */ 2443 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2444 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2445 2446 /* TB epilogue */ 2447 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2448 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2449 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2450 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2451 } 2452 2453 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2454 /* delay slot */ 2455 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2456 2457 if (use_mips32r2_instructions) { 2458 return; 2459 } 2460 2461 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2462 clobbers TCG_TMP1, TCG_TMP2. */ 2463 2464 /* 2465 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2466 */ 2467 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2468 /* t3 = (ssss)d000 */ 2469 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2470 /* t1 = 000a */ 2471 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2472 /* t2 = 00c0 */ 2473 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2474 /* t3 = d00a */ 2475 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2476 /* t1 = 0abc */ 2477 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2478 /* t2 = 0c00 */ 2479 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2480 /* t1 = 00b0 */ 2481 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2482 /* t3 = dc0a */ 2483 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2484 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2485 /* t3 = dcba -- delay slot */ 2486 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2487 2488 if (TCG_TARGET_REG_BITS == 32) { 2489 return; 2490 } 2491 2492 /* 2493 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2494 */ 2495 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2496 /* t1 = (0000)000d */ 2497 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2498 /* t3 = 000a */ 2499 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2500 /* t1 = (0000)d000 */ 2501 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2502 /* t2 = 00c0 */ 2503 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2504 /* t3 = d00a */ 2505 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2506 /* t1 = 0abc */ 2507 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2508 /* t2 = 0c00 */ 2509 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2510 /* t1 = 00b0 */ 2511 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2512 /* t3 = dc0a */ 2513 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2514 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2515 /* t3 = dcba -- delay slot */ 2516 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2517 2518 /* 2519 * bswap64 -- 64-bit swap. a0 = abcdefgh 2520 */ 2521 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2522 /* t3 = h0000000 */ 2523 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2524 /* t1 = 0000000a */ 2525 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2526 2527 /* t2 = 000000g0 */ 2528 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2529 /* t3 = h000000a */ 2530 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2531 /* t1 = 00000abc */ 2532 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2533 /* t2 = 0g000000 */ 2534 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2535 /* t1 = 000000b0 */ 2536 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2537 2538 /* t3 = hg00000a */ 2539 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2540 /* t2 = 0000abcd */ 2541 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2542 /* t3 = hg0000ba */ 2543 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2544 2545 /* t1 = 000000c0 */ 2546 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2547 /* t2 = 0000000d */ 2548 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2549 /* t1 = 00000c00 */ 2550 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2551 /* t2 = 0000d000 */ 2552 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2553 2554 /* t3 = hg000cba */ 2555 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2556 /* t1 = 00abcdef */ 2557 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2558 /* t3 = hg00dcba */ 2559 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2560 2561 /* t2 = 0000000f */ 2562 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2563 /* t1 = 000000e0 */ 2564 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2565 /* t2 = 00f00000 */ 2566 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2567 /* t1 = 000e0000 */ 2568 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2569 2570 /* t3 = hgf0dcba */ 2571 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2572 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2573 /* t3 = hgfedcba -- delay slot */ 2574 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2575} 2576 2577static void tcg_out_tb_start(TCGContext *s) 2578{ 2579 /* nothing to do */ 2580} 2581 2582static void tcg_target_init(TCGContext *s) 2583{ 2584 tcg_target_detect_isa(); 2585 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2586 if (TCG_TARGET_REG_BITS == 64) { 2587 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2588 } 2589 2590 tcg_target_call_clobber_regs = 0; 2591 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2592 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2593 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2594 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2595 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2596 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2597 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2598 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2599 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2600 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2601 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2602 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2603 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2604 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2605 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2606 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2607 2608 s->reserved_regs = 0; 2609 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2610 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2611 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2612 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2613 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2614 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2615 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2616 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2617 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2618 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2619 if (TCG_TARGET_REG_BITS == 64) { 2620 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2621 } 2622} 2623 2624typedef struct { 2625 DebugFrameHeader h; 2626 uint8_t fde_def_cfa[4]; 2627 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2628} DebugFrame; 2629 2630#define ELF_HOST_MACHINE EM_MIPS 2631/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2632 which is good because they're really quite complicated for MIPS. */ 2633 2634static const DebugFrame debug_frame = { 2635 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2636 .h.cie.id = -1, 2637 .h.cie.version = 1, 2638 .h.cie.code_align = 1, 2639 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2640 .h.cie.return_column = TCG_REG_RA, 2641 2642 /* Total FDE size does not include the "len" member. */ 2643 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2644 2645 .fde_def_cfa = { 2646 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2647 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2648 (FRAME_SIZE >> 7) 2649 }, 2650 .fde_reg_ofs = { 2651 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2652 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2653 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2654 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2655 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2656 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2657 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2658 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2659 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2660 } 2661}; 2662 2663void tcg_register_jit(const void *buf, size_t buf_size) 2664{ 2665 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2666} 2667