1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_ZERO 0x100 188#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 189#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 190#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 191#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 192#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 193 194#define ALL_GENERAL_REGS 0xffffffffu 195 196static bool is_p2m1(tcg_target_long val) 197{ 198 return val && ((val + 1) & val) == 0; 199} 200 201/* test if a constant matches the constraint */ 202static bool tcg_target_const_match(int64_t val, int ct, 203 TCGType type, TCGCond cond, int vece) 204{ 205 if (ct & TCG_CT_CONST) { 206 return 1; 207 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 208 return 1; 209 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 210 return 1; 211 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 212 return 1; 213 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_P2M1) 216 && use_mips32r2_instructions && is_p2m1(val)) { 217 return 1; 218 } else if ((ct & TCG_CT_CONST_WSZ) 219 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 220 return 1; 221 } 222 return 0; 223} 224 225/* instruction opcodes */ 226typedef enum { 227 OPC_J = 002 << 26, 228 OPC_JAL = 003 << 26, 229 OPC_BEQ = 004 << 26, 230 OPC_BNE = 005 << 26, 231 OPC_BLEZ = 006 << 26, 232 OPC_BGTZ = 007 << 26, 233 OPC_ADDIU = 011 << 26, 234 OPC_SLTI = 012 << 26, 235 OPC_SLTIU = 013 << 26, 236 OPC_ANDI = 014 << 26, 237 OPC_ORI = 015 << 26, 238 OPC_XORI = 016 << 26, 239 OPC_LUI = 017 << 26, 240 OPC_BNEL = 025 << 26, 241 OPC_BNEZALC_R6 = 030 << 26, 242 OPC_DADDIU = 031 << 26, 243 OPC_LDL = 032 << 26, 244 OPC_LDR = 033 << 26, 245 OPC_LB = 040 << 26, 246 OPC_LH = 041 << 26, 247 OPC_LWL = 042 << 26, 248 OPC_LW = 043 << 26, 249 OPC_LBU = 044 << 26, 250 OPC_LHU = 045 << 26, 251 OPC_LWR = 046 << 26, 252 OPC_LWU = 047 << 26, 253 OPC_SB = 050 << 26, 254 OPC_SH = 051 << 26, 255 OPC_SWL = 052 << 26, 256 OPC_SW = 053 << 26, 257 OPC_SDL = 054 << 26, 258 OPC_SDR = 055 << 26, 259 OPC_SWR = 056 << 26, 260 OPC_LD = 067 << 26, 261 OPC_SD = 077 << 26, 262 263 OPC_SPECIAL = 000 << 26, 264 OPC_SLL = OPC_SPECIAL | 000, 265 OPC_SRL = OPC_SPECIAL | 002, 266 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 267 OPC_SRA = OPC_SPECIAL | 003, 268 OPC_SLLV = OPC_SPECIAL | 004, 269 OPC_SRLV = OPC_SPECIAL | 006, 270 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 271 OPC_SRAV = OPC_SPECIAL | 007, 272 OPC_JR_R5 = OPC_SPECIAL | 010, 273 OPC_JALR = OPC_SPECIAL | 011, 274 OPC_MOVZ = OPC_SPECIAL | 012, 275 OPC_MOVN = OPC_SPECIAL | 013, 276 OPC_SYNC = OPC_SPECIAL | 017, 277 OPC_MFHI = OPC_SPECIAL | 020, 278 OPC_MFLO = OPC_SPECIAL | 022, 279 OPC_DSLLV = OPC_SPECIAL | 024, 280 OPC_DSRLV = OPC_SPECIAL | 026, 281 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 282 OPC_DSRAV = OPC_SPECIAL | 027, 283 OPC_MULT = OPC_SPECIAL | 030, 284 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 285 OPC_MUH = OPC_SPECIAL | 030 | 0300, 286 OPC_MULTU = OPC_SPECIAL | 031, 287 OPC_MULU = OPC_SPECIAL | 031 | 0200, 288 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 289 OPC_DIV = OPC_SPECIAL | 032, 290 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 291 OPC_MOD = OPC_SPECIAL | 032 | 0300, 292 OPC_DIVU = OPC_SPECIAL | 033, 293 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 294 OPC_MODU = OPC_SPECIAL | 033 | 0300, 295 OPC_DMULT = OPC_SPECIAL | 034, 296 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 297 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 298 OPC_DMULTU = OPC_SPECIAL | 035, 299 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 300 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 301 OPC_DDIV = OPC_SPECIAL | 036, 302 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 303 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 304 OPC_DDIVU = OPC_SPECIAL | 037, 305 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 306 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 307 OPC_ADDU = OPC_SPECIAL | 041, 308 OPC_SUBU = OPC_SPECIAL | 043, 309 OPC_AND = OPC_SPECIAL | 044, 310 OPC_OR = OPC_SPECIAL | 045, 311 OPC_XOR = OPC_SPECIAL | 046, 312 OPC_NOR = OPC_SPECIAL | 047, 313 OPC_SLT = OPC_SPECIAL | 052, 314 OPC_SLTU = OPC_SPECIAL | 053, 315 OPC_DADDU = OPC_SPECIAL | 055, 316 OPC_DSUBU = OPC_SPECIAL | 057, 317 OPC_SELEQZ = OPC_SPECIAL | 065, 318 OPC_SELNEZ = OPC_SPECIAL | 067, 319 OPC_DSLL = OPC_SPECIAL | 070, 320 OPC_DSRL = OPC_SPECIAL | 072, 321 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 322 OPC_DSRA = OPC_SPECIAL | 073, 323 OPC_DSLL32 = OPC_SPECIAL | 074, 324 OPC_DSRL32 = OPC_SPECIAL | 076, 325 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 326 OPC_DSRA32 = OPC_SPECIAL | 077, 327 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 328 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 329 330 OPC_REGIMM = 001 << 26, 331 OPC_BLTZ = OPC_REGIMM | (000 << 16), 332 OPC_BGEZ = OPC_REGIMM | (001 << 16), 333 334 OPC_SPECIAL2 = 034 << 26, 335 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 336 OPC_CLZ = OPC_SPECIAL2 | 040, 337 OPC_DCLZ = OPC_SPECIAL2 | 044, 338 339 OPC_SPECIAL3 = 037 << 26, 340 OPC_EXT = OPC_SPECIAL3 | 000, 341 OPC_DEXTM = OPC_SPECIAL3 | 001, 342 OPC_DEXTU = OPC_SPECIAL3 | 002, 343 OPC_DEXT = OPC_SPECIAL3 | 003, 344 OPC_INS = OPC_SPECIAL3 | 004, 345 OPC_DINSM = OPC_SPECIAL3 | 005, 346 OPC_DINSU = OPC_SPECIAL3 | 006, 347 OPC_DINS = OPC_SPECIAL3 | 007, 348 OPC_WSBH = OPC_SPECIAL3 | 00240, 349 OPC_DSBH = OPC_SPECIAL3 | 00244, 350 OPC_DSHD = OPC_SPECIAL3 | 00544, 351 OPC_SEB = OPC_SPECIAL3 | 02040, 352 OPC_SEH = OPC_SPECIAL3 | 03040, 353 354 /* MIPS r6 doesn't have JR, JALR should be used instead */ 355 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 356 357 /* 358 * MIPS r6 replaces MUL with an alternative encoding which is 359 * backwards-compatible at the assembly level. 360 */ 361 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 362 363 /* MIPS r6 introduced names for weaker variants of SYNC. These are 364 backward compatible to previous architecture revisions. */ 365 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 366 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 367 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 368 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 369 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 370 371 /* Aliases for convenience. */ 372 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 373 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 374} MIPSInsn; 375 376/* 377 * Type reg 378 */ 379static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 380 TCGReg rd, TCGReg rs, TCGReg rt) 381{ 382 int32_t inst; 383 384 inst = opc; 385 inst |= (rs & 0x1F) << 21; 386 inst |= (rt & 0x1F) << 16; 387 inst |= (rd & 0x1F) << 11; 388 tcg_out32(s, inst); 389} 390 391/* 392 * Type immediate 393 */ 394static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 395 TCGReg rt, TCGReg rs, TCGArg imm) 396{ 397 int32_t inst; 398 399 inst = opc; 400 inst |= (rs & 0x1F) << 21; 401 inst |= (rt & 0x1F) << 16; 402 inst |= (imm & 0xffff); 403 tcg_out32(s, inst); 404} 405 406/* 407 * Type bitfield 408 */ 409static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 410 TCGReg rs, int msb, int lsb) 411{ 412 int32_t inst; 413 414 inst = opc; 415 inst |= (rs & 0x1F) << 21; 416 inst |= (rt & 0x1F) << 16; 417 inst |= (msb & 0x1F) << 11; 418 inst |= (lsb & 0x1F) << 6; 419 tcg_out32(s, inst); 420} 421 422static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 423 MIPSInsn oph, TCGReg rt, TCGReg rs, 424 int msb, int lsb) 425{ 426 if (lsb >= 32) { 427 opc = oph; 428 msb -= 32; 429 lsb -= 32; 430 } else if (msb >= 32) { 431 opc = opm; 432 msb -= 32; 433 } 434 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 435} 436 437/* 438 * Type branch 439 */ 440static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 441{ 442 tcg_out_opc_imm(s, opc, rt, rs, 0); 443} 444 445/* 446 * Type sa 447 */ 448static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 449 TCGReg rd, TCGReg rt, TCGArg sa) 450{ 451 int32_t inst; 452 453 inst = opc; 454 inst |= (rt & 0x1F) << 16; 455 inst |= (rd & 0x1F) << 11; 456 inst |= (sa & 0x1F) << 6; 457 tcg_out32(s, inst); 458 459} 460 461static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 462 TCGReg rd, TCGReg rt, TCGArg sa) 463{ 464 int32_t inst; 465 466 inst = (sa & 32 ? opc2 : opc1); 467 inst |= (rt & 0x1F) << 16; 468 inst |= (rd & 0x1F) << 11; 469 inst |= (sa & 0x1F) << 6; 470 tcg_out32(s, inst); 471} 472 473/* 474 * Type jump. 475 * Returns true if the branch was in range and the insn was emitted. 476 */ 477static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 478{ 479 uintptr_t dest = (uintptr_t)target; 480 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 481 int32_t inst; 482 483 /* The pc-region branch happens within the 256MB region of 484 the delay slot (thus the +4). */ 485 if ((from ^ dest) & -(1 << 28)) { 486 return false; 487 } 488 tcg_debug_assert((dest & 3) == 0); 489 490 inst = opc; 491 inst |= (dest >> 2) & 0x3ffffff; 492 tcg_out32(s, inst); 493 return true; 494} 495 496static void tcg_out_nop(TCGContext *s) 497{ 498 tcg_out32(s, 0); 499} 500 501static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 502{ 503 memset(p, 0, count * sizeof(tcg_insn_unit)); 504} 505 506static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 507{ 508 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 509} 510 511static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 512{ 513 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 514} 515 516static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 517{ 518 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 519} 520 521static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 522{ 523 /* Simple reg-reg move, optimising out the 'do nothing' case */ 524 if (ret != arg) { 525 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 526 } 527 return true; 528} 529 530static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 531{ 532 if (arg == (int16_t)arg) { 533 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 534 return true; 535 } 536 if (arg == (uint16_t)arg) { 537 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 538 return true; 539 } 540 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 541 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 542 return true; 543 } 544 return false; 545} 546 547static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 548{ 549 /* 550 * All signed 32-bit constants are loadable with two immediates, 551 * and everything else requires more work. 552 */ 553 if (arg == (int32_t)arg) { 554 if (!tcg_out_movi_one(s, ret, arg)) { 555 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 556 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 557 } 558 return true; 559 } 560 return false; 561} 562 563static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 564 tcg_target_long arg, TCGReg tbreg) 565{ 566 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 567 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 568} 569 570static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 571 tcg_target_long arg, TCGReg tbreg) 572{ 573 tcg_target_long tmp; 574 int sh, lo; 575 576 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 577 arg = (int32_t)arg; 578 } 579 580 /* Load all 32-bit constants. */ 581 if (tcg_out_movi_two(s, ret, arg)) { 582 return; 583 } 584 assert(TCG_TARGET_REG_BITS == 64); 585 586 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 587 tmp = tcg_tbrel_diff(s, (void *)arg); 588 if (tmp == (int16_t)tmp) { 589 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 590 return; 591 } 592 if (tcg_out_movi_two(s, ret, tmp)) { 593 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 594 return; 595 } 596 597 /* 598 * Load bitmasks with a right-shift. This is good for things 599 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 600 * or similarly using LUI. For this to work, bit 31 must be set. 601 */ 602 if (arg > 0 && (int32_t)arg < 0) { 603 sh = clz64(arg); 604 if (tcg_out_movi_one(s, ret, arg << sh)) { 605 tcg_out_dsrl(s, ret, ret, sh); 606 return; 607 } 608 } 609 610 /* 611 * Load slightly larger constants using left-shift. 612 * Limit this sequence to 3 insns to avoid too much expansion. 613 */ 614 sh = ctz64(arg); 615 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 616 tcg_out_dsll(s, ret, ret, sh); 617 return; 618 } 619 620 /* 621 * Load slightly larger constants using left-shift and add/or. 622 * Prefer addi with a negative immediate when that would produce 623 * a larger shift. For this to work, bits 15 and 16 must be set. 624 */ 625 lo = arg & 0xffff; 626 if (lo) { 627 if ((arg & 0x18000) == 0x18000) { 628 lo = (int16_t)arg; 629 } 630 tmp = arg - lo; 631 sh = ctz64(tmp); 632 tmp >>= sh; 633 if (tcg_out_movi_one(s, ret, tmp)) { 634 tcg_out_dsll(s, ret, ret, sh); 635 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 636 return; 637 } 638 } 639 640 /* Otherwise, put 64-bit constants into the constant pool. */ 641 tcg_out_movi_pool(s, ret, arg, tbreg); 642} 643 644static void tcg_out_movi(TCGContext *s, TCGType type, 645 TCGReg ret, tcg_target_long arg) 646{ 647 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 648 tcg_out_movi_int(s, type, ret, arg, tbreg); 649} 650 651static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 652{ 653 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); 654 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 655} 656 657static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 658{ 659 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 660} 661 662static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 663{ 664 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); 665 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 666} 667 668static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 669{ 670 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 671} 672 673static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 674{ 675 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 676 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 677} 678 679static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 680{ 681 if (rd != rs) { 682 tcg_out_ext32s(s, rd, rs); 683 } 684} 685 686static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 687{ 688 tcg_out_ext32u(s, rd, rs); 689} 690 691static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 692{ 693 tcg_out_ext32s(s, rd, rs); 694} 695 696static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 697{ 698 return false; 699} 700 701static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 702 tcg_target_long imm) 703{ 704 /* This function is only used for passing structs by reference. */ 705 g_assert_not_reached(); 706} 707 708static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 709{ 710 /* ret and arg can't be register tmp0 */ 711 tcg_debug_assert(ret != TCG_TMP0); 712 tcg_debug_assert(arg != TCG_TMP0); 713 714 /* With arg = abcd: */ 715 if (use_mips32r2_instructions) { 716 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 717 if (flags & TCG_BSWAP_OS) { 718 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 719 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 720 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 721 } 722 return; 723 } 724 725 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 726 if (!(flags & TCG_BSWAP_IZ)) { 727 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 728 } 729 if (flags & TCG_BSWAP_OS) { 730 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 731 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 732 } else { 733 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 734 if (flags & TCG_BSWAP_OZ) { 735 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 736 } 737 } 738 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 739} 740 741static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 742{ 743 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 744 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 745 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 746 } 747} 748 749static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 750{ 751 if (use_mips32r2_instructions) { 752 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 753 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 754 if (flags & TCG_BSWAP_OZ) { 755 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 756 } 757 } else { 758 if (flags & TCG_BSWAP_OZ) { 759 tcg_out_bswap_subr(s, bswap32u_addr); 760 } else { 761 tcg_out_bswap_subr(s, bswap32_addr); 762 } 763 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 764 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 765 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 766 } 767} 768 769static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 770{ 771 if (use_mips32r2_instructions) { 772 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 773 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 774 } else { 775 tcg_out_bswap_subr(s, bswap64_addr); 776 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 777 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 778 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 779 } 780} 781 782static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 783{ 784 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 785 if (use_mips32r2_instructions) { 786 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 787 } else { 788 tcg_out_dsll(s, ret, arg, 32); 789 tcg_out_dsrl(s, ret, ret, 32); 790 } 791} 792 793static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 794 TCGReg addr, intptr_t ofs) 795{ 796 int16_t lo = ofs; 797 if (ofs != lo) { 798 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 799 if (addr != TCG_REG_ZERO) { 800 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 801 } 802 addr = TCG_TMP0; 803 } 804 tcg_out_opc_imm(s, opc, data, addr, lo); 805} 806 807static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 808 TCGReg arg1, intptr_t arg2) 809{ 810 MIPSInsn opc = OPC_LD; 811 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 812 opc = OPC_LW; 813 } 814 tcg_out_ldst(s, opc, arg, arg1, arg2); 815} 816 817static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 818 TCGReg arg1, intptr_t arg2) 819{ 820 MIPSInsn opc = OPC_SD; 821 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 822 opc = OPC_SW; 823 } 824 tcg_out_ldst(s, opc, arg, arg1, arg2); 825} 826 827static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 828 TCGReg base, intptr_t ofs) 829{ 830 if (val == 0) { 831 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 832 return true; 833 } 834 return false; 835} 836 837static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 838 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 839 bool cbh, bool is_sub) 840{ 841 TCGReg th = TCG_TMP1; 842 843 /* If we have a negative constant such that negating it would 844 make the high part zero, we can (usually) eliminate one insn. */ 845 if (cbl && cbh && bh == -1 && bl != 0) { 846 bl = -bl; 847 bh = 0; 848 is_sub = !is_sub; 849 } 850 851 /* By operating on the high part first, we get to use the final 852 carry operation to move back from the temporary. */ 853 if (!cbh) { 854 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 855 } else if (bh != 0 || ah == rl) { 856 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 857 } else { 858 th = ah; 859 } 860 861 /* Note that tcg optimization should eliminate the bl == 0 case. */ 862 if (is_sub) { 863 if (cbl) { 864 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 865 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 866 } else { 867 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 868 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 869 } 870 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 871 } else { 872 if (cbl) { 873 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 874 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 875 } else if (rl == al && rl == bl) { 876 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 877 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 878 } else { 879 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 880 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 881 } 882 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 883 } 884} 885 886#define SETCOND_INV TCG_TARGET_NB_REGS 887#define SETCOND_NEZ (SETCOND_INV << 1) 888#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 889 890static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 891 TCGReg arg1, TCGReg arg2) 892{ 893 int flags = 0; 894 895 switch (cond) { 896 case TCG_COND_EQ: /* -> NE */ 897 case TCG_COND_GE: /* -> LT */ 898 case TCG_COND_GEU: /* -> LTU */ 899 case TCG_COND_LE: /* -> GT */ 900 case TCG_COND_LEU: /* -> GTU */ 901 cond = tcg_invert_cond(cond); 902 flags ^= SETCOND_INV; 903 break; 904 default: 905 break; 906 } 907 908 switch (cond) { 909 case TCG_COND_NE: 910 flags |= SETCOND_NEZ; 911 if (arg2 == 0) { 912 return arg1 | flags; 913 } 914 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 915 break; 916 case TCG_COND_LT: 917 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 918 break; 919 case TCG_COND_LTU: 920 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 921 break; 922 case TCG_COND_GT: 923 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 924 break; 925 case TCG_COND_GTU: 926 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 927 break; 928 default: 929 g_assert_not_reached(); 930 } 931 return ret | flags; 932} 933 934static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 935{ 936 if (tmpflags != ret) { 937 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 938 939 switch (tmpflags & SETCOND_FLAGS) { 940 case SETCOND_INV: 941 /* Intermediate result is boolean: simply invert. */ 942 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 943 break; 944 case SETCOND_NEZ: 945 /* Intermediate result is zero/non-zero: test != 0. */ 946 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 947 break; 948 case SETCOND_NEZ | SETCOND_INV: 949 /* Intermediate result is zero/non-zero: test == 0. */ 950 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 951 break; 952 default: 953 g_assert_not_reached(); 954 } 955 } 956} 957 958static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 959 TCGReg arg1, TCGReg arg2) 960{ 961 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 962 tcg_out_setcond_end(s, ret, tmpflags); 963} 964 965static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 966 TCGReg arg2, TCGLabel *l) 967{ 968 static const MIPSInsn b_zero[16] = { 969 [TCG_COND_LT] = OPC_BLTZ, 970 [TCG_COND_GT] = OPC_BGTZ, 971 [TCG_COND_LE] = OPC_BLEZ, 972 [TCG_COND_GE] = OPC_BGEZ, 973 }; 974 975 MIPSInsn b_opc = 0; 976 977 switch (cond) { 978 case TCG_COND_EQ: 979 b_opc = OPC_BEQ; 980 break; 981 case TCG_COND_NE: 982 b_opc = OPC_BNE; 983 break; 984 case TCG_COND_LT: 985 case TCG_COND_GT: 986 case TCG_COND_LE: 987 case TCG_COND_GE: 988 if (arg2 == 0) { 989 b_opc = b_zero[cond]; 990 arg2 = arg1; 991 arg1 = 0; 992 } 993 break; 994 default: 995 break; 996 } 997 998 if (b_opc == 0) { 999 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 1000 1001 arg2 = TCG_REG_ZERO; 1002 arg1 = tmpflags & ~SETCOND_FLAGS; 1003 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1004 } 1005 1006 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1007 tcg_out_opc_br(s, b_opc, arg1, arg2); 1008 tcg_out_nop(s); 1009} 1010 1011static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 1012 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1013{ 1014 int flags = 0; 1015 1016 switch (cond) { 1017 case TCG_COND_EQ: 1018 flags |= SETCOND_INV; 1019 /* fall through */ 1020 case TCG_COND_NE: 1021 flags |= SETCOND_NEZ; 1022 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 1023 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 1024 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1025 break; 1026 1027 default: 1028 tcg_out_setcond(s, TCG_COND_EQ, TCG_TMP0, ah, bh); 1029 tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_TMP1, al, bl); 1030 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 1031 tcg_out_setcond(s, tcg_high_cond(cond), TCG_TMP0, ah, bh); 1032 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1033 break; 1034 } 1035 return ret | flags; 1036} 1037 1038static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1039 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1040{ 1041 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1042 tcg_out_setcond_end(s, ret, tmpflags); 1043} 1044 1045static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1046 TCGReg bl, TCGReg bh, TCGLabel *l) 1047{ 1048 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1049 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1050 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1051 1052 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1053 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1054 tcg_out_nop(s); 1055} 1056 1057static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1058 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1059{ 1060 int tmpflags; 1061 bool eqz; 1062 1063 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1064 if (use_mips32r6_instructions && v1 == 0) { 1065 v1 = v2; 1066 v2 = 0; 1067 cond = tcg_invert_cond(cond); 1068 } 1069 1070 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1071 c1 = tmpflags & ~SETCOND_FLAGS; 1072 eqz = tmpflags & SETCOND_INV; 1073 1074 if (use_mips32r6_instructions) { 1075 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1076 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1077 1078 if (v2 != 0) { 1079 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1080 } 1081 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1082 if (v2 != 0) { 1083 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1084 } 1085 return; 1086 } 1087 1088 /* This should be guaranteed via constraints */ 1089 tcg_debug_assert(v2 == ret); 1090 1091 if (use_movnz_instructions) { 1092 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1093 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1094 } else { 1095 /* Invert the condition in order to branch over the move. */ 1096 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1097 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1098 tcg_out_nop(s); 1099 /* Open-code tcg_out_mov, without the nop-move check. */ 1100 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1101 } 1102} 1103 1104static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1105{ 1106 /* 1107 * Note that __mips_abicalls requires the called function's address 1108 * to be loaded into $25 (t9), even if a direct branch is in range. 1109 * 1110 * For n64, always drop the pointer into the constant pool. 1111 * We can re-use helper addresses often and do not want any 1112 * of the longer sequences tcg_out_movi may try. 1113 */ 1114 if (sizeof(uintptr_t) == 8) { 1115 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1116 } else { 1117 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1118 } 1119 1120 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1121 if (tail) { 1122 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1123 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1124 } 1125 } else { 1126 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1127 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1128 } 1129 } 1130} 1131 1132static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1133 const TCGHelperInfo *info) 1134{ 1135 tcg_out_call_int(s, arg, false); 1136 tcg_out_nop(s); 1137} 1138 1139/* We have four temps, we might as well expose three of them. */ 1140static const TCGLdstHelperParam ldst_helper_param = { 1141 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1142}; 1143 1144static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1145{ 1146 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1147 MemOp opc = get_memop(l->oi); 1148 1149 /* resolve label address */ 1150 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1151 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1152 return false; 1153 } 1154 1155 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1156 1157 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1158 /* delay slot */ 1159 tcg_out_nop(s); 1160 1161 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1162 1163 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1164 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1165 return false; 1166 } 1167 1168 /* delay slot */ 1169 tcg_out_nop(s); 1170 return true; 1171} 1172 1173static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1174{ 1175 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1176 MemOp opc = get_memop(l->oi); 1177 1178 /* resolve label address */ 1179 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1180 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1181 return false; 1182 } 1183 1184 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1185 1186 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1187 /* delay slot */ 1188 tcg_out_nop(s); 1189 1190 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1191 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1192 return false; 1193 } 1194 1195 /* delay slot */ 1196 tcg_out_nop(s); 1197 return true; 1198} 1199 1200typedef struct { 1201 TCGReg base; 1202 TCGAtomAlign aa; 1203} HostAddress; 1204 1205bool tcg_target_has_memory_bswap(MemOp memop) 1206{ 1207 return false; 1208} 1209 1210/* We expect to use a 16-bit negative offset from ENV. */ 1211#define MIN_TLB_MASK_TABLE_OFS -32768 1212 1213/* 1214 * For system-mode, perform the TLB load and compare. 1215 * For user-mode, perform any required alignment tests. 1216 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1217 * is required and fill in @h with the host address for the fast path. 1218 */ 1219static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1220 TCGReg addr, MemOpIdx oi, bool is_ld) 1221{ 1222 TCGType addr_type = s->addr_type; 1223 TCGLabelQemuLdst *ldst = NULL; 1224 MemOp opc = get_memop(oi); 1225 MemOp a_bits; 1226 unsigned s_bits = opc & MO_SIZE; 1227 unsigned a_mask; 1228 TCGReg base; 1229 1230 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1231 a_bits = h->aa.align; 1232 a_mask = (1 << a_bits) - 1; 1233 1234 if (tcg_use_softmmu) { 1235 unsigned s_mask = (1 << s_bits) - 1; 1236 int mem_index = get_mmuidx(oi); 1237 int fast_off = tlb_mask_table_ofs(s, mem_index); 1238 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1239 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1240 int add_off = offsetof(CPUTLBEntry, addend); 1241 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1242 : offsetof(CPUTLBEntry, addr_write); 1243 1244 ldst = new_ldst_label(s); 1245 ldst->is_ld = is_ld; 1246 ldst->oi = oi; 1247 ldst->addr_reg = addr; 1248 1249 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1250 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1251 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1252 1253 /* Extract the TLB index from the address into TMP3. */ 1254 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1255 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1256 s->page_bits - CPU_TLB_ENTRY_BITS); 1257 } else { 1258 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1259 } 1260 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1261 1262 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1263 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1264 1265 /* Load the tlb comparator. */ 1266 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1267 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1268 cmp_off + HOST_BIG_ENDIAN * 4); 1269 } else { 1270 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1271 } 1272 1273 /* Load the tlb addend for the fast path. */ 1274 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1275 1276 /* 1277 * Mask the page bits, keeping the alignment bits to compare against. 1278 * For unaligned accesses, compare against the end of the access to 1279 * verify that it does not cross a page boundary. 1280 */ 1281 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1282 if (a_mask < s_mask) { 1283 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1284 || addr_type == TCG_TYPE_I32 1285 ? OPC_ADDIU : OPC_DADDIU), 1286 TCG_TMP2, addr, s_mask - a_mask); 1287 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1288 } else { 1289 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1290 } 1291 1292 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1293 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1294 tcg_out_ext32u(s, TCG_TMP2, addr); 1295 addr = TCG_TMP2; 1296 } 1297 1298 ldst->label_ptr[0] = s->code_ptr; 1299 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1300 1301 /* delay slot */ 1302 base = TCG_TMP3; 1303 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1304 } else { 1305 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1306 ldst = new_ldst_label(s); 1307 1308 ldst->is_ld = is_ld; 1309 ldst->oi = oi; 1310 ldst->addr_reg = addr; 1311 1312 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1313 tcg_debug_assert(a_bits < 16); 1314 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1315 1316 ldst->label_ptr[0] = s->code_ptr; 1317 if (use_mips32r6_instructions) { 1318 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1319 } else { 1320 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1321 tcg_out_nop(s); 1322 } 1323 } 1324 1325 base = addr; 1326 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1327 tcg_out_ext32u(s, TCG_REG_A0, base); 1328 base = TCG_REG_A0; 1329 } 1330 if (guest_base) { 1331 if (guest_base == (int16_t)guest_base) { 1332 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1333 } else { 1334 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1335 TCG_GUEST_BASE_REG); 1336 } 1337 base = TCG_REG_A0; 1338 } 1339 } 1340 1341 h->base = base; 1342 return ldst; 1343} 1344 1345static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1346 TCGReg base, MemOp opc, TCGType type) 1347{ 1348 switch (opc & MO_SSIZE) { 1349 case MO_UB: 1350 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1351 break; 1352 case MO_SB: 1353 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1354 break; 1355 case MO_UW: 1356 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1357 break; 1358 case MO_SW: 1359 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1360 break; 1361 case MO_UL: 1362 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1363 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1364 break; 1365 } 1366 /* FALLTHRU */ 1367 case MO_SL: 1368 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1369 break; 1370 case MO_UQ: 1371 /* Prefer to load from offset 0 first, but allow for overlap. */ 1372 if (TCG_TARGET_REG_BITS == 64) { 1373 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1374 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1375 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1376 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1377 } else { 1378 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1379 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1380 } 1381 break; 1382 default: 1383 g_assert_not_reached(); 1384 } 1385} 1386 1387static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1388 TCGReg base, MemOp opc, TCGType type) 1389{ 1390 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1391 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1392 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1393 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1394 bool sgn = opc & MO_SIGN; 1395 1396 switch (opc & MO_SIZE) { 1397 case MO_16: 1398 if (HOST_BIG_ENDIAN) { 1399 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1400 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1401 if (use_mips32r2_instructions) { 1402 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1403 } else { 1404 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1405 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1406 } 1407 } else if (use_mips32r2_instructions && lo != base) { 1408 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1409 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1410 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1411 } else { 1412 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1413 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1414 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1415 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1416 } 1417 break; 1418 1419 case MO_32: 1420 tcg_out_opc_imm(s, lw1, lo, base, 0); 1421 tcg_out_opc_imm(s, lw2, lo, base, 3); 1422 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1423 tcg_out_ext32u(s, lo, lo); 1424 } 1425 break; 1426 1427 case MO_64: 1428 if (TCG_TARGET_REG_BITS == 64) { 1429 tcg_out_opc_imm(s, ld1, lo, base, 0); 1430 tcg_out_opc_imm(s, ld2, lo, base, 7); 1431 } else { 1432 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1433 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1434 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1435 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1436 } 1437 break; 1438 1439 default: 1440 g_assert_not_reached(); 1441 } 1442} 1443 1444static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1445 TCGReg addr, MemOpIdx oi, TCGType data_type) 1446{ 1447 MemOp opc = get_memop(oi); 1448 TCGLabelQemuLdst *ldst; 1449 HostAddress h; 1450 1451 ldst = prepare_host_addr(s, &h, addr, oi, true); 1452 1453 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1454 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1455 } else { 1456 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1457 } 1458 1459 if (ldst) { 1460 ldst->type = data_type; 1461 ldst->datalo_reg = datalo; 1462 ldst->datahi_reg = datahi; 1463 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1464 } 1465} 1466 1467static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1468 TCGReg base, MemOp opc) 1469{ 1470 switch (opc & MO_SIZE) { 1471 case MO_8: 1472 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1473 break; 1474 case MO_16: 1475 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1476 break; 1477 case MO_32: 1478 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1479 break; 1480 case MO_64: 1481 if (TCG_TARGET_REG_BITS == 64) { 1482 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1483 } else { 1484 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1485 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1486 } 1487 break; 1488 default: 1489 g_assert_not_reached(); 1490 } 1491} 1492 1493static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1494 TCGReg base, MemOp opc) 1495{ 1496 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1497 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1498 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1499 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1500 1501 switch (opc & MO_SIZE) { 1502 case MO_16: 1503 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1504 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1505 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1506 break; 1507 1508 case MO_32: 1509 tcg_out_opc_imm(s, sw1, lo, base, 0); 1510 tcg_out_opc_imm(s, sw2, lo, base, 3); 1511 break; 1512 1513 case MO_64: 1514 if (TCG_TARGET_REG_BITS == 64) { 1515 tcg_out_opc_imm(s, sd1, lo, base, 0); 1516 tcg_out_opc_imm(s, sd2, lo, base, 7); 1517 } else { 1518 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1519 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1520 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1521 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1522 } 1523 break; 1524 1525 default: 1526 g_assert_not_reached(); 1527 } 1528} 1529 1530static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1531 TCGReg addr, MemOpIdx oi, TCGType data_type) 1532{ 1533 MemOp opc = get_memop(oi); 1534 TCGLabelQemuLdst *ldst; 1535 HostAddress h; 1536 1537 ldst = prepare_host_addr(s, &h, addr, oi, false); 1538 1539 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1540 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1541 } else { 1542 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1543 } 1544 1545 if (ldst) { 1546 ldst->type = data_type; 1547 ldst->datalo_reg = datalo; 1548 ldst->datahi_reg = datahi; 1549 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1550 } 1551} 1552 1553static void tcg_out_mb(TCGContext *s, TCGArg a0) 1554{ 1555 static const MIPSInsn sync[] = { 1556 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1557 as the former is an ordering barrier and the latter 1558 is a completion barrier. */ 1559 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1560 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1561 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1562 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1563 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1564 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1565 }; 1566 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1567} 1568 1569static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1570 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1571{ 1572 if (use_mips32r6_instructions) { 1573 if (a2 == width) { 1574 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1575 } else { 1576 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1577 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1578 } 1579 } else { 1580 if (a2 == width) { 1581 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1582 } else if (a0 == a2) { 1583 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1584 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1585 } else if (a0 != a1) { 1586 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1587 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1588 } else { 1589 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1590 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1591 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1592 } 1593 } 1594} 1595 1596static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1597{ 1598 TCGReg base = TCG_REG_ZERO; 1599 int16_t lo = 0; 1600 1601 if (a0) { 1602 intptr_t ofs; 1603 if (TCG_TARGET_REG_BITS == 64) { 1604 ofs = tcg_tbrel_diff(s, (void *)a0); 1605 lo = ofs; 1606 if (ofs == lo) { 1607 base = TCG_REG_TB; 1608 } else { 1609 base = TCG_REG_V0; 1610 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1611 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1612 } 1613 } else { 1614 ofs = a0; 1615 lo = ofs; 1616 base = TCG_REG_V0; 1617 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1618 } 1619 } 1620 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1621 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1622 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1623 } 1624 /* delay slot */ 1625 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1626} 1627 1628static void tcg_out_goto_tb(TCGContext *s, int which) 1629{ 1630 intptr_t ofs = get_jmp_target_addr(s, which); 1631 TCGReg base, dest; 1632 1633 /* indirect jump method */ 1634 if (TCG_TARGET_REG_BITS == 64) { 1635 dest = TCG_REG_TB; 1636 base = TCG_REG_TB; 1637 ofs = tcg_tbrel_diff(s, (void *)ofs); 1638 } else { 1639 dest = TCG_TMP0; 1640 base = TCG_REG_ZERO; 1641 } 1642 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1643 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1644 /* delay slot */ 1645 tcg_out_nop(s); 1646 1647 set_jmp_reset_offset(s, which); 1648 if (TCG_TARGET_REG_BITS == 64) { 1649 /* For the unlinked case, need to reset TCG_REG_TB. */ 1650 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1651 -tcg_current_code_size(s)); 1652 } 1653} 1654 1655void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1656 uintptr_t jmp_rx, uintptr_t jmp_rw) 1657{ 1658 /* Always indirect, nothing to do */ 1659} 1660 1661static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1662 const TCGArg args[TCG_MAX_OP_ARGS], 1663 const int const_args[TCG_MAX_OP_ARGS]) 1664{ 1665 MIPSInsn i1, i2; 1666 TCGArg a0, a1, a2; 1667 int c2; 1668 1669 /* 1670 * Note that many operands use the constraint set "rZ". 1671 * We make use of the fact that 0 is the ZERO register, 1672 * and hence such cases need not check for const_args. 1673 */ 1674 a0 = args[0]; 1675 a1 = args[1]; 1676 a2 = args[2]; 1677 c2 = const_args[2]; 1678 1679 switch (opc) { 1680 case INDEX_op_goto_ptr: 1681 /* jmp to the given host address (could be epilogue) */ 1682 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1683 if (TCG_TARGET_REG_BITS == 64) { 1684 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 1685 } else { 1686 tcg_out_nop(s); 1687 } 1688 break; 1689 case INDEX_op_br: 1690 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1691 arg_label(a0)); 1692 break; 1693 1694 case INDEX_op_ld8u_i32: 1695 case INDEX_op_ld8u_i64: 1696 i1 = OPC_LBU; 1697 goto do_ldst; 1698 case INDEX_op_ld8s_i32: 1699 case INDEX_op_ld8s_i64: 1700 i1 = OPC_LB; 1701 goto do_ldst; 1702 case INDEX_op_ld16u_i32: 1703 case INDEX_op_ld16u_i64: 1704 i1 = OPC_LHU; 1705 goto do_ldst; 1706 case INDEX_op_ld16s_i32: 1707 case INDEX_op_ld16s_i64: 1708 i1 = OPC_LH; 1709 goto do_ldst; 1710 case INDEX_op_ld_i32: 1711 case INDEX_op_ld32s_i64: 1712 i1 = OPC_LW; 1713 goto do_ldst; 1714 case INDEX_op_ld32u_i64: 1715 i1 = OPC_LWU; 1716 goto do_ldst; 1717 case INDEX_op_ld_i64: 1718 i1 = OPC_LD; 1719 goto do_ldst; 1720 case INDEX_op_st8_i32: 1721 case INDEX_op_st8_i64: 1722 i1 = OPC_SB; 1723 goto do_ldst; 1724 case INDEX_op_st16_i32: 1725 case INDEX_op_st16_i64: 1726 i1 = OPC_SH; 1727 goto do_ldst; 1728 case INDEX_op_st_i32: 1729 case INDEX_op_st32_i64: 1730 i1 = OPC_SW; 1731 goto do_ldst; 1732 case INDEX_op_st_i64: 1733 i1 = OPC_SD; 1734 do_ldst: 1735 tcg_out_ldst(s, i1, a0, a1, a2); 1736 break; 1737 1738 case INDEX_op_add_i32: 1739 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1740 goto do_binary; 1741 case INDEX_op_add_i64: 1742 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1743 goto do_binary; 1744 case INDEX_op_or_i32: 1745 case INDEX_op_or_i64: 1746 i1 = OPC_OR, i2 = OPC_ORI; 1747 goto do_binary; 1748 case INDEX_op_xor_i32: 1749 case INDEX_op_xor_i64: 1750 i1 = OPC_XOR, i2 = OPC_XORI; 1751 do_binary: 1752 if (c2) { 1753 tcg_out_opc_imm(s, i2, a0, a1, a2); 1754 break; 1755 } 1756 do_binaryv: 1757 tcg_out_opc_reg(s, i1, a0, a1, a2); 1758 break; 1759 1760 case INDEX_op_sub_i32: 1761 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1762 goto do_subtract; 1763 case INDEX_op_sub_i64: 1764 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1765 do_subtract: 1766 if (c2) { 1767 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1768 break; 1769 } 1770 goto do_binaryv; 1771 case INDEX_op_and_i32: 1772 if (c2 && a2 != (uint16_t)a2) { 1773 int msb = ctz32(~a2) - 1; 1774 tcg_debug_assert(use_mips32r2_instructions); 1775 tcg_debug_assert(is_p2m1(a2)); 1776 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1777 break; 1778 } 1779 i1 = OPC_AND, i2 = OPC_ANDI; 1780 goto do_binary; 1781 case INDEX_op_and_i64: 1782 if (c2 && a2 != (uint16_t)a2) { 1783 int msb = ctz64(~a2) - 1; 1784 tcg_debug_assert(use_mips32r2_instructions); 1785 tcg_debug_assert(is_p2m1(a2)); 1786 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1787 break; 1788 } 1789 i1 = OPC_AND, i2 = OPC_ANDI; 1790 goto do_binary; 1791 case INDEX_op_nor_i32: 1792 case INDEX_op_nor_i64: 1793 i1 = OPC_NOR; 1794 goto do_binaryv; 1795 1796 case INDEX_op_mul_i32: 1797 if (use_mips32_instructions) { 1798 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1799 break; 1800 } 1801 i1 = OPC_MULT, i2 = OPC_MFLO; 1802 goto do_hilo1; 1803 case INDEX_op_mulsh_i32: 1804 if (use_mips32r6_instructions) { 1805 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1806 break; 1807 } 1808 i1 = OPC_MULT, i2 = OPC_MFHI; 1809 goto do_hilo1; 1810 case INDEX_op_muluh_i32: 1811 if (use_mips32r6_instructions) { 1812 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1813 break; 1814 } 1815 i1 = OPC_MULTU, i2 = OPC_MFHI; 1816 goto do_hilo1; 1817 case INDEX_op_div_i32: 1818 if (use_mips32r6_instructions) { 1819 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1820 break; 1821 } 1822 i1 = OPC_DIV, i2 = OPC_MFLO; 1823 goto do_hilo1; 1824 case INDEX_op_divu_i32: 1825 if (use_mips32r6_instructions) { 1826 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1827 break; 1828 } 1829 i1 = OPC_DIVU, i2 = OPC_MFLO; 1830 goto do_hilo1; 1831 case INDEX_op_rem_i32: 1832 if (use_mips32r6_instructions) { 1833 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1834 break; 1835 } 1836 i1 = OPC_DIV, i2 = OPC_MFHI; 1837 goto do_hilo1; 1838 case INDEX_op_remu_i32: 1839 if (use_mips32r6_instructions) { 1840 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1841 break; 1842 } 1843 i1 = OPC_DIVU, i2 = OPC_MFHI; 1844 goto do_hilo1; 1845 case INDEX_op_mul_i64: 1846 if (use_mips32r6_instructions) { 1847 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1848 break; 1849 } 1850 i1 = OPC_DMULT, i2 = OPC_MFLO; 1851 goto do_hilo1; 1852 case INDEX_op_mulsh_i64: 1853 if (use_mips32r6_instructions) { 1854 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1855 break; 1856 } 1857 i1 = OPC_DMULT, i2 = OPC_MFHI; 1858 goto do_hilo1; 1859 case INDEX_op_muluh_i64: 1860 if (use_mips32r6_instructions) { 1861 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1862 break; 1863 } 1864 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1865 goto do_hilo1; 1866 case INDEX_op_div_i64: 1867 if (use_mips32r6_instructions) { 1868 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1869 break; 1870 } 1871 i1 = OPC_DDIV, i2 = OPC_MFLO; 1872 goto do_hilo1; 1873 case INDEX_op_divu_i64: 1874 if (use_mips32r6_instructions) { 1875 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1876 break; 1877 } 1878 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1879 goto do_hilo1; 1880 case INDEX_op_rem_i64: 1881 if (use_mips32r6_instructions) { 1882 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1883 break; 1884 } 1885 i1 = OPC_DDIV, i2 = OPC_MFHI; 1886 goto do_hilo1; 1887 case INDEX_op_remu_i64: 1888 if (use_mips32r6_instructions) { 1889 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1890 break; 1891 } 1892 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1893 do_hilo1: 1894 tcg_out_opc_reg(s, i1, 0, a1, a2); 1895 tcg_out_opc_reg(s, i2, a0, 0, 0); 1896 break; 1897 1898 case INDEX_op_muls2_i32: 1899 i1 = OPC_MULT; 1900 goto do_hilo2; 1901 case INDEX_op_mulu2_i32: 1902 i1 = OPC_MULTU; 1903 goto do_hilo2; 1904 case INDEX_op_muls2_i64: 1905 i1 = OPC_DMULT; 1906 goto do_hilo2; 1907 case INDEX_op_mulu2_i64: 1908 i1 = OPC_DMULTU; 1909 do_hilo2: 1910 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1911 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1912 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1913 break; 1914 1915 case INDEX_op_neg_i32: 1916 i1 = OPC_SUBU; 1917 goto do_unary; 1918 case INDEX_op_neg_i64: 1919 i1 = OPC_DSUBU; 1920 goto do_unary; 1921 case INDEX_op_not_i32: 1922 case INDEX_op_not_i64: 1923 i1 = OPC_NOR; 1924 goto do_unary; 1925 do_unary: 1926 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1927 break; 1928 1929 case INDEX_op_bswap16_i32: 1930 case INDEX_op_bswap16_i64: 1931 tcg_out_bswap16(s, a0, a1, a2); 1932 break; 1933 case INDEX_op_bswap32_i32: 1934 tcg_out_bswap32(s, a0, a1, 0); 1935 break; 1936 case INDEX_op_bswap32_i64: 1937 tcg_out_bswap32(s, a0, a1, a2); 1938 break; 1939 case INDEX_op_bswap64_i64: 1940 tcg_out_bswap64(s, a0, a1); 1941 break; 1942 case INDEX_op_extrh_i64_i32: 1943 tcg_out_dsra(s, a0, a1, 32); 1944 break; 1945 1946 case INDEX_op_sar_i32: 1947 i1 = OPC_SRAV, i2 = OPC_SRA; 1948 goto do_shift; 1949 case INDEX_op_shl_i32: 1950 i1 = OPC_SLLV, i2 = OPC_SLL; 1951 goto do_shift; 1952 case INDEX_op_shr_i32: 1953 i1 = OPC_SRLV, i2 = OPC_SRL; 1954 goto do_shift; 1955 case INDEX_op_rotr_i32: 1956 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1957 do_shift: 1958 if (c2) { 1959 tcg_out_opc_sa(s, i2, a0, a1, a2); 1960 break; 1961 } 1962 do_shiftv: 1963 tcg_out_opc_reg(s, i1, a0, a2, a1); 1964 break; 1965 case INDEX_op_rotl_i32: 1966 if (c2) { 1967 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 1968 } else { 1969 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1970 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 1971 } 1972 break; 1973 case INDEX_op_sar_i64: 1974 if (c2) { 1975 tcg_out_dsra(s, a0, a1, a2); 1976 break; 1977 } 1978 i1 = OPC_DSRAV; 1979 goto do_shiftv; 1980 case INDEX_op_shl_i64: 1981 if (c2) { 1982 tcg_out_dsll(s, a0, a1, a2); 1983 break; 1984 } 1985 i1 = OPC_DSLLV; 1986 goto do_shiftv; 1987 case INDEX_op_shr_i64: 1988 if (c2) { 1989 tcg_out_dsrl(s, a0, a1, a2); 1990 break; 1991 } 1992 i1 = OPC_DSRLV; 1993 goto do_shiftv; 1994 case INDEX_op_rotr_i64: 1995 if (c2) { 1996 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 1997 break; 1998 } 1999 i1 = OPC_DROTRV; 2000 goto do_shiftv; 2001 case INDEX_op_rotl_i64: 2002 if (c2) { 2003 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2004 } else { 2005 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2006 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2007 } 2008 break; 2009 2010 case INDEX_op_clz_i32: 2011 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2012 break; 2013 case INDEX_op_clz_i64: 2014 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2015 break; 2016 2017 case INDEX_op_deposit_i32: 2018 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2019 break; 2020 case INDEX_op_deposit_i64: 2021 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2022 args[3] + args[4] - 1, args[3]); 2023 break; 2024 2025 case INDEX_op_extract_i32: 2026 if (a2 == 0 && args[3] <= 16) { 2027 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2028 } else { 2029 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2030 } 2031 break; 2032 case INDEX_op_extract_i64: 2033 if (a2 == 0 && args[3] <= 16) { 2034 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2035 } else { 2036 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2037 a0, a1, args[3] - 1, a2); 2038 } 2039 break; 2040 2041 case INDEX_op_sextract_i64: 2042 if (a2 == 0 && args[3] == 32) { 2043 tcg_out_ext32s(s, a0, a1); 2044 break; 2045 } 2046 /* FALLTHRU */ 2047 case INDEX_op_sextract_i32: 2048 if (a2 == 0 && args[3] == 8) { 2049 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 2050 } else if (a2 == 0 && args[3] == 16) { 2051 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 2052 } else { 2053 g_assert_not_reached(); 2054 } 2055 break; 2056 2057 case INDEX_op_brcond_i32: 2058 case INDEX_op_brcond_i64: 2059 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2060 break; 2061 case INDEX_op_brcond2_i32: 2062 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2063 break; 2064 2065 case INDEX_op_movcond_i32: 2066 case INDEX_op_movcond_i64: 2067 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2068 break; 2069 2070 case INDEX_op_setcond_i32: 2071 case INDEX_op_setcond_i64: 2072 tcg_out_setcond(s, args[3], a0, a1, a2); 2073 break; 2074 case INDEX_op_setcond2_i32: 2075 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2076 break; 2077 2078 case INDEX_op_qemu_ld_i32: 2079 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2080 break; 2081 case INDEX_op_qemu_ld_i64: 2082 if (TCG_TARGET_REG_BITS == 64) { 2083 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2084 } else { 2085 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2086 } 2087 break; 2088 2089 case INDEX_op_qemu_st_i32: 2090 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2091 break; 2092 case INDEX_op_qemu_st_i64: 2093 if (TCG_TARGET_REG_BITS == 64) { 2094 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2095 } else { 2096 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2097 } 2098 break; 2099 2100 case INDEX_op_add2_i32: 2101 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2102 const_args[4], const_args[5], false); 2103 break; 2104 case INDEX_op_sub2_i32: 2105 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2106 const_args[4], const_args[5], true); 2107 break; 2108 2109 case INDEX_op_mb: 2110 tcg_out_mb(s, a0); 2111 break; 2112 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2113 case INDEX_op_mov_i64: 2114 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2115 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2116 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2117 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2118 case INDEX_op_ext8s_i64: 2119 case INDEX_op_ext8u_i32: 2120 case INDEX_op_ext8u_i64: 2121 case INDEX_op_ext16s_i32: 2122 case INDEX_op_ext16s_i64: 2123 case INDEX_op_ext32s_i64: 2124 case INDEX_op_ext32u_i64: 2125 case INDEX_op_ext_i32_i64: 2126 case INDEX_op_extu_i32_i64: 2127 case INDEX_op_extrl_i64_i32: 2128 default: 2129 g_assert_not_reached(); 2130 } 2131} 2132 2133static TCGConstraintSetIndex 2134tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2135{ 2136 switch (op) { 2137 case INDEX_op_goto_ptr: 2138 return C_O0_I1(r); 2139 2140 case INDEX_op_ld8u_i32: 2141 case INDEX_op_ld8s_i32: 2142 case INDEX_op_ld16u_i32: 2143 case INDEX_op_ld16s_i32: 2144 case INDEX_op_ld_i32: 2145 case INDEX_op_neg_i32: 2146 case INDEX_op_not_i32: 2147 case INDEX_op_bswap16_i32: 2148 case INDEX_op_bswap32_i32: 2149 case INDEX_op_ext8s_i32: 2150 case INDEX_op_ext16s_i32: 2151 case INDEX_op_extract_i32: 2152 case INDEX_op_sextract_i32: 2153 case INDEX_op_ld8u_i64: 2154 case INDEX_op_ld8s_i64: 2155 case INDEX_op_ld16u_i64: 2156 case INDEX_op_ld16s_i64: 2157 case INDEX_op_ld32s_i64: 2158 case INDEX_op_ld32u_i64: 2159 case INDEX_op_ld_i64: 2160 case INDEX_op_neg_i64: 2161 case INDEX_op_not_i64: 2162 case INDEX_op_bswap16_i64: 2163 case INDEX_op_bswap32_i64: 2164 case INDEX_op_bswap64_i64: 2165 case INDEX_op_ext8s_i64: 2166 case INDEX_op_ext16s_i64: 2167 case INDEX_op_ext32s_i64: 2168 case INDEX_op_ext32u_i64: 2169 case INDEX_op_ext_i32_i64: 2170 case INDEX_op_extu_i32_i64: 2171 case INDEX_op_extrl_i64_i32: 2172 case INDEX_op_extrh_i64_i32: 2173 case INDEX_op_extract_i64: 2174 case INDEX_op_sextract_i64: 2175 return C_O1_I1(r, r); 2176 2177 case INDEX_op_st8_i32: 2178 case INDEX_op_st16_i32: 2179 case INDEX_op_st_i32: 2180 case INDEX_op_st8_i64: 2181 case INDEX_op_st16_i64: 2182 case INDEX_op_st32_i64: 2183 case INDEX_op_st_i64: 2184 return C_O0_I2(rZ, r); 2185 2186 case INDEX_op_add_i32: 2187 case INDEX_op_add_i64: 2188 return C_O1_I2(r, r, rJ); 2189 case INDEX_op_sub_i32: 2190 case INDEX_op_sub_i64: 2191 return C_O1_I2(r, rZ, rN); 2192 case INDEX_op_mul_i32: 2193 case INDEX_op_mulsh_i32: 2194 case INDEX_op_muluh_i32: 2195 case INDEX_op_div_i32: 2196 case INDEX_op_divu_i32: 2197 case INDEX_op_rem_i32: 2198 case INDEX_op_remu_i32: 2199 case INDEX_op_nor_i32: 2200 case INDEX_op_setcond_i32: 2201 case INDEX_op_mul_i64: 2202 case INDEX_op_mulsh_i64: 2203 case INDEX_op_muluh_i64: 2204 case INDEX_op_div_i64: 2205 case INDEX_op_divu_i64: 2206 case INDEX_op_rem_i64: 2207 case INDEX_op_remu_i64: 2208 case INDEX_op_nor_i64: 2209 case INDEX_op_setcond_i64: 2210 return C_O1_I2(r, rZ, rZ); 2211 case INDEX_op_muls2_i32: 2212 case INDEX_op_mulu2_i32: 2213 case INDEX_op_muls2_i64: 2214 case INDEX_op_mulu2_i64: 2215 return C_O2_I2(r, r, r, r); 2216 case INDEX_op_and_i32: 2217 case INDEX_op_and_i64: 2218 return C_O1_I2(r, r, rIK); 2219 case INDEX_op_or_i32: 2220 case INDEX_op_xor_i32: 2221 case INDEX_op_or_i64: 2222 case INDEX_op_xor_i64: 2223 return C_O1_I2(r, r, rI); 2224 case INDEX_op_shl_i32: 2225 case INDEX_op_shr_i32: 2226 case INDEX_op_sar_i32: 2227 case INDEX_op_rotr_i32: 2228 case INDEX_op_rotl_i32: 2229 case INDEX_op_shl_i64: 2230 case INDEX_op_shr_i64: 2231 case INDEX_op_sar_i64: 2232 case INDEX_op_rotr_i64: 2233 case INDEX_op_rotl_i64: 2234 return C_O1_I2(r, r, ri); 2235 case INDEX_op_clz_i32: 2236 case INDEX_op_clz_i64: 2237 return C_O1_I2(r, r, rWZ); 2238 2239 case INDEX_op_deposit_i32: 2240 case INDEX_op_deposit_i64: 2241 return C_O1_I2(r, 0, rZ); 2242 case INDEX_op_brcond_i32: 2243 case INDEX_op_brcond_i64: 2244 return C_O0_I2(rZ, rZ); 2245 case INDEX_op_movcond_i32: 2246 case INDEX_op_movcond_i64: 2247 return (use_mips32r6_instructions 2248 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2249 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2250 case INDEX_op_add2_i32: 2251 case INDEX_op_sub2_i32: 2252 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2253 case INDEX_op_setcond2_i32: 2254 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2255 case INDEX_op_brcond2_i32: 2256 return C_O0_I4(rZ, rZ, rZ, rZ); 2257 2258 case INDEX_op_qemu_ld_i32: 2259 return C_O1_I1(r, r); 2260 case INDEX_op_qemu_st_i32: 2261 return C_O0_I2(rZ, r); 2262 case INDEX_op_qemu_ld_i64: 2263 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2264 case INDEX_op_qemu_st_i64: 2265 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r); 2266 2267 default: 2268 return C_NotImplemented; 2269 } 2270} 2271 2272static const int tcg_target_callee_save_regs[] = { 2273 TCG_REG_S0, 2274 TCG_REG_S1, 2275 TCG_REG_S2, 2276 TCG_REG_S3, 2277 TCG_REG_S4, 2278 TCG_REG_S5, 2279 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2280 TCG_REG_S7, /* used for guest_base */ 2281 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2282 TCG_REG_RA, /* should be last for ABI compliance */ 2283}; 2284 2285/* The Linux kernel doesn't provide any information about the available 2286 instruction set. Probe it using a signal handler. */ 2287 2288 2289#ifndef use_movnz_instructions 2290bool use_movnz_instructions = false; 2291#endif 2292 2293#ifndef use_mips32_instructions 2294bool use_mips32_instructions = false; 2295#endif 2296 2297#ifndef use_mips32r2_instructions 2298bool use_mips32r2_instructions = false; 2299#endif 2300 2301static volatile sig_atomic_t got_sigill; 2302 2303static void sigill_handler(int signo, siginfo_t *si, void *data) 2304{ 2305 /* Skip the faulty instruction */ 2306 ucontext_t *uc = (ucontext_t *)data; 2307 uc->uc_mcontext.pc += 4; 2308 2309 got_sigill = 1; 2310} 2311 2312static void tcg_target_detect_isa(void) 2313{ 2314 struct sigaction sa_old, sa_new; 2315 2316 memset(&sa_new, 0, sizeof(sa_new)); 2317 sa_new.sa_flags = SA_SIGINFO; 2318 sa_new.sa_sigaction = sigill_handler; 2319 sigaction(SIGILL, &sa_new, &sa_old); 2320 2321 /* Probe for movn/movz, necessary to implement movcond. */ 2322#ifndef use_movnz_instructions 2323 got_sigill = 0; 2324 asm volatile(".set push\n" 2325 ".set mips32\n" 2326 "movn $zero, $zero, $zero\n" 2327 "movz $zero, $zero, $zero\n" 2328 ".set pop\n" 2329 : : : ); 2330 use_movnz_instructions = !got_sigill; 2331#endif 2332 2333 /* Probe for MIPS32 instructions. As no subsetting is allowed 2334 by the specification, it is only necessary to probe for one 2335 of the instructions. */ 2336#ifndef use_mips32_instructions 2337 got_sigill = 0; 2338 asm volatile(".set push\n" 2339 ".set mips32\n" 2340 "mul $zero, $zero\n" 2341 ".set pop\n" 2342 : : : ); 2343 use_mips32_instructions = !got_sigill; 2344#endif 2345 2346 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2347 available. As no subsetting is allowed by the specification, 2348 it is only necessary to probe for one of the instructions. */ 2349#ifndef use_mips32r2_instructions 2350 if (use_mips32_instructions) { 2351 got_sigill = 0; 2352 asm volatile(".set push\n" 2353 ".set mips32r2\n" 2354 "seb $zero, $zero\n" 2355 ".set pop\n" 2356 : : : ); 2357 use_mips32r2_instructions = !got_sigill; 2358 } 2359#endif 2360 2361 sigaction(SIGILL, &sa_old, NULL); 2362} 2363 2364static tcg_insn_unit *align_code_ptr(TCGContext *s) 2365{ 2366 uintptr_t p = (uintptr_t)s->code_ptr; 2367 if (p & 15) { 2368 p = (p + 15) & -16; 2369 s->code_ptr = (void *)p; 2370 } 2371 return s->code_ptr; 2372} 2373 2374/* Stack frame parameters. */ 2375#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2376#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2377#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2378 2379#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2380 + TCG_TARGET_STACK_ALIGN - 1) \ 2381 & -TCG_TARGET_STACK_ALIGN) 2382#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2383 2384/* We're expecting to be able to use an immediate for frame allocation. */ 2385QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2386 2387/* Generate global QEMU prologue and epilogue code */ 2388static void tcg_target_qemu_prologue(TCGContext *s) 2389{ 2390 int i; 2391 2392 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2393 2394 /* TB prologue */ 2395 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2396 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2397 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2398 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2399 } 2400 2401 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2402 /* 2403 * The function call abi for n32 and n64 will have loaded $25 (t9) 2404 * with the address of the prologue, so we can use that instead 2405 * of TCG_REG_TB. 2406 */ 2407#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2408# error "Unknown mips abi" 2409#endif 2410 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2411 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2412 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2413 } 2414 2415 if (TCG_TARGET_REG_BITS == 64) { 2416 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2417 } 2418 2419 /* Call generated code */ 2420 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2421 /* delay slot */ 2422 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2423 2424 /* 2425 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2426 * and fall through to the rest of the epilogue. 2427 */ 2428 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2429 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2430 2431 /* TB epilogue */ 2432 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2433 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2434 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2435 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2436 } 2437 2438 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2439 /* delay slot */ 2440 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2441 2442 if (use_mips32r2_instructions) { 2443 return; 2444 } 2445 2446 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2447 clobbers TCG_TMP1, TCG_TMP2. */ 2448 2449 /* 2450 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2451 */ 2452 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2453 /* t3 = (ssss)d000 */ 2454 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2455 /* t1 = 000a */ 2456 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2457 /* t2 = 00c0 */ 2458 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2459 /* t3 = d00a */ 2460 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2461 /* t1 = 0abc */ 2462 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2463 /* t2 = 0c00 */ 2464 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2465 /* t1 = 00b0 */ 2466 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2467 /* t3 = dc0a */ 2468 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2469 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2470 /* t3 = dcba -- delay slot */ 2471 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2472 2473 if (TCG_TARGET_REG_BITS == 32) { 2474 return; 2475 } 2476 2477 /* 2478 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2479 */ 2480 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2481 /* t1 = (0000)000d */ 2482 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2483 /* t3 = 000a */ 2484 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2485 /* t1 = (0000)d000 */ 2486 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2487 /* t2 = 00c0 */ 2488 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2489 /* t3 = d00a */ 2490 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2491 /* t1 = 0abc */ 2492 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2493 /* t2 = 0c00 */ 2494 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2495 /* t1 = 00b0 */ 2496 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2497 /* t3 = dc0a */ 2498 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2499 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2500 /* t3 = dcba -- delay slot */ 2501 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2502 2503 /* 2504 * bswap64 -- 64-bit swap. a0 = abcdefgh 2505 */ 2506 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2507 /* t3 = h0000000 */ 2508 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2509 /* t1 = 0000000a */ 2510 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2511 2512 /* t2 = 000000g0 */ 2513 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2514 /* t3 = h000000a */ 2515 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2516 /* t1 = 00000abc */ 2517 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2518 /* t2 = 0g000000 */ 2519 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2520 /* t1 = 000000b0 */ 2521 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2522 2523 /* t3 = hg00000a */ 2524 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2525 /* t2 = 0000abcd */ 2526 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2527 /* t3 = hg0000ba */ 2528 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2529 2530 /* t1 = 000000c0 */ 2531 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2532 /* t2 = 0000000d */ 2533 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2534 /* t1 = 00000c00 */ 2535 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2536 /* t2 = 0000d000 */ 2537 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2538 2539 /* t3 = hg000cba */ 2540 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2541 /* t1 = 00abcdef */ 2542 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2543 /* t3 = hg00dcba */ 2544 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2545 2546 /* t2 = 0000000f */ 2547 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2548 /* t1 = 000000e0 */ 2549 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2550 /* t2 = 00f00000 */ 2551 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2552 /* t1 = 000e0000 */ 2553 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2554 2555 /* t3 = hgf0dcba */ 2556 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2557 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2558 /* t3 = hgfedcba -- delay slot */ 2559 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2560} 2561 2562static void tcg_out_tb_start(TCGContext *s) 2563{ 2564 /* nothing to do */ 2565} 2566 2567static void tcg_target_init(TCGContext *s) 2568{ 2569 tcg_target_detect_isa(); 2570 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2571 if (TCG_TARGET_REG_BITS == 64) { 2572 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2573 } 2574 2575 tcg_target_call_clobber_regs = 0; 2576 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2577 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2578 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2579 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2580 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2581 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2582 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2583 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2584 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2585 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2586 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2587 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2588 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2589 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2590 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2591 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2592 2593 s->reserved_regs = 0; 2594 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2595 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2596 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2597 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2598 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2599 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2600 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2601 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2602 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2603 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2604 if (TCG_TARGET_REG_BITS == 64) { 2605 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2606 } 2607} 2608 2609typedef struct { 2610 DebugFrameHeader h; 2611 uint8_t fde_def_cfa[4]; 2612 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2613} DebugFrame; 2614 2615#define ELF_HOST_MACHINE EM_MIPS 2616/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2617 which is good because they're really quite complicated for MIPS. */ 2618 2619static const DebugFrame debug_frame = { 2620 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2621 .h.cie.id = -1, 2622 .h.cie.version = 1, 2623 .h.cie.code_align = 1, 2624 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2625 .h.cie.return_column = TCG_REG_RA, 2626 2627 /* Total FDE size does not include the "len" member. */ 2628 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2629 2630 .fde_def_cfa = { 2631 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2632 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2633 (FRAME_SIZE >> 7) 2634 }, 2635 .fde_reg_ofs = { 2636 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2637 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2638 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2639 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2640 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2641 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2642 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2643 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2644 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2645 } 2646}; 2647 2648void tcg_register_jit(const void *buf, size_t buf_size) 2649{ 2650 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2651} 2652