1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */ 191#define TCG_CT_CONST_WSZ 0x1000 /* word size */ 192 193#define ALL_GENERAL_REGS 0xffffffffu 194 195static bool is_p2m1(tcg_target_long val) 196{ 197 return val && ((val + 1) & val) == 0; 198} 199 200/* test if a constant matches the constraint */ 201static bool tcg_target_const_match(int64_t val, int ct, 202 TCGType type, TCGCond cond, int vece) 203{ 204 if (ct & TCG_CT_CONST) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_P2M1) 213 && use_mips32r2_instructions && is_p2m1(val)) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_WSZ) 216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 217 return 1; 218 } 219 return 0; 220} 221 222/* instruction opcodes */ 223typedef enum { 224 OPC_J = 002 << 26, 225 OPC_JAL = 003 << 26, 226 OPC_BEQ = 004 << 26, 227 OPC_BNE = 005 << 26, 228 OPC_BLEZ = 006 << 26, 229 OPC_BGTZ = 007 << 26, 230 OPC_ADDIU = 011 << 26, 231 OPC_SLTI = 012 << 26, 232 OPC_SLTIU = 013 << 26, 233 OPC_ANDI = 014 << 26, 234 OPC_ORI = 015 << 26, 235 OPC_XORI = 016 << 26, 236 OPC_LUI = 017 << 26, 237 OPC_BNEL = 025 << 26, 238 OPC_BNEZALC_R6 = 030 << 26, 239 OPC_DADDIU = 031 << 26, 240 OPC_LDL = 032 << 26, 241 OPC_LDR = 033 << 26, 242 OPC_LB = 040 << 26, 243 OPC_LH = 041 << 26, 244 OPC_LWL = 042 << 26, 245 OPC_LW = 043 << 26, 246 OPC_LBU = 044 << 26, 247 OPC_LHU = 045 << 26, 248 OPC_LWR = 046 << 26, 249 OPC_LWU = 047 << 26, 250 OPC_SB = 050 << 26, 251 OPC_SH = 051 << 26, 252 OPC_SWL = 052 << 26, 253 OPC_SW = 053 << 26, 254 OPC_SDL = 054 << 26, 255 OPC_SDR = 055 << 26, 256 OPC_SWR = 056 << 26, 257 OPC_LD = 067 << 26, 258 OPC_SD = 077 << 26, 259 260 OPC_SPECIAL = 000 << 26, 261 OPC_SLL = OPC_SPECIAL | 000, 262 OPC_SRL = OPC_SPECIAL | 002, 263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 264 OPC_SRA = OPC_SPECIAL | 003, 265 OPC_SLLV = OPC_SPECIAL | 004, 266 OPC_SRLV = OPC_SPECIAL | 006, 267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 268 OPC_SRAV = OPC_SPECIAL | 007, 269 OPC_JR_R5 = OPC_SPECIAL | 010, 270 OPC_JALR = OPC_SPECIAL | 011, 271 OPC_MOVZ = OPC_SPECIAL | 012, 272 OPC_MOVN = OPC_SPECIAL | 013, 273 OPC_SYNC = OPC_SPECIAL | 017, 274 OPC_MFHI = OPC_SPECIAL | 020, 275 OPC_MFLO = OPC_SPECIAL | 022, 276 OPC_DSLLV = OPC_SPECIAL | 024, 277 OPC_DSRLV = OPC_SPECIAL | 026, 278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 279 OPC_DSRAV = OPC_SPECIAL | 027, 280 OPC_MULT = OPC_SPECIAL | 030, 281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 282 OPC_MUH = OPC_SPECIAL | 030 | 0300, 283 OPC_MULTU = OPC_SPECIAL | 031, 284 OPC_MULU = OPC_SPECIAL | 031 | 0200, 285 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 286 OPC_DIV = OPC_SPECIAL | 032, 287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 288 OPC_MOD = OPC_SPECIAL | 032 | 0300, 289 OPC_DIVU = OPC_SPECIAL | 033, 290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 291 OPC_MODU = OPC_SPECIAL | 033 | 0300, 292 OPC_DMULT = OPC_SPECIAL | 034, 293 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 294 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 295 OPC_DMULTU = OPC_SPECIAL | 035, 296 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 298 OPC_DDIV = OPC_SPECIAL | 036, 299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 300 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 301 OPC_DDIVU = OPC_SPECIAL | 037, 302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 303 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 304 OPC_ADDU = OPC_SPECIAL | 041, 305 OPC_SUBU = OPC_SPECIAL | 043, 306 OPC_AND = OPC_SPECIAL | 044, 307 OPC_OR = OPC_SPECIAL | 045, 308 OPC_XOR = OPC_SPECIAL | 046, 309 OPC_NOR = OPC_SPECIAL | 047, 310 OPC_SLT = OPC_SPECIAL | 052, 311 OPC_SLTU = OPC_SPECIAL | 053, 312 OPC_DADDU = OPC_SPECIAL | 055, 313 OPC_DSUBU = OPC_SPECIAL | 057, 314 OPC_SELEQZ = OPC_SPECIAL | 065, 315 OPC_SELNEZ = OPC_SPECIAL | 067, 316 OPC_DSLL = OPC_SPECIAL | 070, 317 OPC_DSRL = OPC_SPECIAL | 072, 318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 319 OPC_DSRA = OPC_SPECIAL | 073, 320 OPC_DSLL32 = OPC_SPECIAL | 074, 321 OPC_DSRL32 = OPC_SPECIAL | 076, 322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 323 OPC_DSRA32 = OPC_SPECIAL | 077, 324 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 326 327 OPC_REGIMM = 001 << 26, 328 OPC_BLTZ = OPC_REGIMM | (000 << 16), 329 OPC_BGEZ = OPC_REGIMM | (001 << 16), 330 331 OPC_SPECIAL2 = 034 << 26, 332 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 333 OPC_CLZ = OPC_SPECIAL2 | 040, 334 OPC_DCLZ = OPC_SPECIAL2 | 044, 335 336 OPC_SPECIAL3 = 037 << 26, 337 OPC_EXT = OPC_SPECIAL3 | 000, 338 OPC_DEXTM = OPC_SPECIAL3 | 001, 339 OPC_DEXTU = OPC_SPECIAL3 | 002, 340 OPC_DEXT = OPC_SPECIAL3 | 003, 341 OPC_INS = OPC_SPECIAL3 | 004, 342 OPC_DINSM = OPC_SPECIAL3 | 005, 343 OPC_DINSU = OPC_SPECIAL3 | 006, 344 OPC_DINS = OPC_SPECIAL3 | 007, 345 OPC_WSBH = OPC_SPECIAL3 | 00240, 346 OPC_DSBH = OPC_SPECIAL3 | 00244, 347 OPC_DSHD = OPC_SPECIAL3 | 00544, 348 OPC_SEB = OPC_SPECIAL3 | 02040, 349 OPC_SEH = OPC_SPECIAL3 | 03040, 350 351 /* MIPS r6 doesn't have JR, JALR should be used instead */ 352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 353 354 /* 355 * MIPS r6 replaces MUL with an alternative encoding which is 356 * backwards-compatible at the assembly level. 357 */ 358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 359 360 /* MIPS r6 introduced names for weaker variants of SYNC. These are 361 backward compatible to previous architecture revisions. */ 362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 367 368 /* Aliases for convenience. */ 369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 371} MIPSInsn; 372 373/* 374 * Type reg 375 */ 376static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 377 TCGReg rd, TCGReg rs, TCGReg rt) 378{ 379 int32_t inst; 380 381 inst = opc; 382 inst |= (rs & 0x1F) << 21; 383 inst |= (rt & 0x1F) << 16; 384 inst |= (rd & 0x1F) << 11; 385 tcg_out32(s, inst); 386} 387 388/* 389 * Type immediate 390 */ 391static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 392 TCGReg rt, TCGReg rs, TCGArg imm) 393{ 394 int32_t inst; 395 396 inst = opc; 397 inst |= (rs & 0x1F) << 21; 398 inst |= (rt & 0x1F) << 16; 399 inst |= (imm & 0xffff); 400 tcg_out32(s, inst); 401} 402 403/* 404 * Type bitfield 405 */ 406static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 407 TCGReg rs, int msb, int lsb) 408{ 409 int32_t inst; 410 411 inst = opc; 412 inst |= (rs & 0x1F) << 21; 413 inst |= (rt & 0x1F) << 16; 414 inst |= (msb & 0x1F) << 11; 415 inst |= (lsb & 0x1F) << 6; 416 tcg_out32(s, inst); 417} 418 419static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 420 MIPSInsn oph, TCGReg rt, TCGReg rs, 421 int msb, int lsb) 422{ 423 if (lsb >= 32) { 424 opc = oph; 425 msb -= 32; 426 lsb -= 32; 427 } else if (msb >= 32) { 428 opc = opm; 429 msb -= 32; 430 } 431 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 432} 433 434/* 435 * Type branch 436 */ 437static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 438{ 439 tcg_out_opc_imm(s, opc, rt, rs, 0); 440} 441 442/* 443 * Type sa 444 */ 445static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 446 TCGReg rd, TCGReg rt, TCGArg sa) 447{ 448 int32_t inst; 449 450 inst = opc; 451 inst |= (rt & 0x1F) << 16; 452 inst |= (rd & 0x1F) << 11; 453 inst |= (sa & 0x1F) << 6; 454 tcg_out32(s, inst); 455 456} 457 458static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 459 TCGReg rd, TCGReg rt, TCGArg sa) 460{ 461 int32_t inst; 462 463 inst = (sa & 32 ? opc2 : opc1); 464 inst |= (rt & 0x1F) << 16; 465 inst |= (rd & 0x1F) << 11; 466 inst |= (sa & 0x1F) << 6; 467 tcg_out32(s, inst); 468} 469 470/* 471 * Type jump. 472 * Returns true if the branch was in range and the insn was emitted. 473 */ 474static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 475{ 476 uintptr_t dest = (uintptr_t)target; 477 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 478 int32_t inst; 479 480 /* The pc-region branch happens within the 256MB region of 481 the delay slot (thus the +4). */ 482 if ((from ^ dest) & -(1 << 28)) { 483 return false; 484 } 485 tcg_debug_assert((dest & 3) == 0); 486 487 inst = opc; 488 inst |= (dest >> 2) & 0x3ffffff; 489 tcg_out32(s, inst); 490 return true; 491} 492 493static void tcg_out_nop(TCGContext *s) 494{ 495 tcg_out32(s, 0); 496} 497 498static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 499{ 500 memset(p, 0, count * sizeof(tcg_insn_unit)); 501} 502 503static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 504{ 505 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 506} 507 508static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 509{ 510 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 511} 512 513static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 514{ 515 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 516} 517 518static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 519{ 520 /* Simple reg-reg move, optimising out the 'do nothing' case */ 521 if (ret != arg) { 522 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 523 } 524 return true; 525} 526 527static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 528{ 529 if (arg == (int16_t)arg) { 530 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 531 return true; 532 } 533 if (arg == (uint16_t)arg) { 534 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 535 return true; 536 } 537 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 538 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 539 return true; 540 } 541 return false; 542} 543 544static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 545{ 546 /* 547 * All signed 32-bit constants are loadable with two immediates, 548 * and everything else requires more work. 549 */ 550 if (arg == (int32_t)arg) { 551 if (!tcg_out_movi_one(s, ret, arg)) { 552 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 553 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 554 } 555 return true; 556 } 557 return false; 558} 559 560static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 561 tcg_target_long arg, TCGReg tbreg) 562{ 563 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 564 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 565} 566 567static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 568 tcg_target_long arg, TCGReg tbreg) 569{ 570 tcg_target_long tmp; 571 int sh, lo; 572 573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 574 arg = (int32_t)arg; 575 } 576 577 /* Load all 32-bit constants. */ 578 if (tcg_out_movi_two(s, ret, arg)) { 579 return; 580 } 581 assert(TCG_TARGET_REG_BITS == 64); 582 583 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 584 tmp = tcg_tbrel_diff(s, (void *)arg); 585 if (tmp == (int16_t)tmp) { 586 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 587 return; 588 } 589 if (tcg_out_movi_two(s, ret, tmp)) { 590 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 591 return; 592 } 593 594 /* 595 * Load bitmasks with a right-shift. This is good for things 596 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 597 * or similarly using LUI. For this to work, bit 31 must be set. 598 */ 599 if (arg > 0 && (int32_t)arg < 0) { 600 sh = clz64(arg); 601 if (tcg_out_movi_one(s, ret, arg << sh)) { 602 tcg_out_dsrl(s, ret, ret, sh); 603 return; 604 } 605 } 606 607 /* 608 * Load slightly larger constants using left-shift. 609 * Limit this sequence to 3 insns to avoid too much expansion. 610 */ 611 sh = ctz64(arg); 612 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 613 tcg_out_dsll(s, ret, ret, sh); 614 return; 615 } 616 617 /* 618 * Load slightly larger constants using left-shift and add/or. 619 * Prefer addi with a negative immediate when that would produce 620 * a larger shift. For this to work, bits 15 and 16 must be set. 621 */ 622 lo = arg & 0xffff; 623 if (lo) { 624 if ((arg & 0x18000) == 0x18000) { 625 lo = (int16_t)arg; 626 } 627 tmp = arg - lo; 628 sh = ctz64(tmp); 629 tmp >>= sh; 630 if (tcg_out_movi_one(s, ret, tmp)) { 631 tcg_out_dsll(s, ret, ret, sh); 632 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 633 return; 634 } 635 } 636 637 /* Otherwise, put 64-bit constants into the constant pool. */ 638 tcg_out_movi_pool(s, ret, arg, tbreg); 639} 640 641static void tcg_out_movi(TCGContext *s, TCGType type, 642 TCGReg ret, tcg_target_long arg) 643{ 644 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 645 tcg_out_movi_int(s, type, ret, arg, tbreg); 646} 647 648static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 649{ 650 tcg_debug_assert(use_mips32r2_instructions); 651 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 652} 653 654static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 655{ 656 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 657} 658 659static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 660{ 661 tcg_debug_assert(use_mips32r2_instructions); 662 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 663} 664 665static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 666{ 667 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 668} 669 670static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 671{ 672 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 673 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 674} 675 676static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 if (rd != rs) { 679 tcg_out_ext32s(s, rd, rs); 680 } 681} 682 683static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 684{ 685 tcg_out_ext32u(s, rd, rs); 686} 687 688static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 689{ 690 tcg_out_ext32s(s, rd, rs); 691} 692 693static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 694{ 695 return false; 696} 697 698static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 699 tcg_target_long imm) 700{ 701 /* This function is only used for passing structs by reference. */ 702 g_assert_not_reached(); 703} 704 705static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 706{ 707 /* ret and arg can't be register tmp0 */ 708 tcg_debug_assert(ret != TCG_TMP0); 709 tcg_debug_assert(arg != TCG_TMP0); 710 711 /* With arg = abcd: */ 712 if (use_mips32r2_instructions) { 713 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 714 if (flags & TCG_BSWAP_OS) { 715 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 716 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 717 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 718 } 719 return; 720 } 721 722 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 723 if (!(flags & TCG_BSWAP_IZ)) { 724 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 725 } 726 if (flags & TCG_BSWAP_OS) { 727 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 728 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 729 } else { 730 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 731 if (flags & TCG_BSWAP_OZ) { 732 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 733 } 734 } 735 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 736} 737 738static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 739{ 740 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 741 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 742 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 743 } 744} 745 746static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 747{ 748 if (use_mips32r2_instructions) { 749 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 750 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 751 if (flags & TCG_BSWAP_OZ) { 752 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 753 } 754 } else { 755 if (flags & TCG_BSWAP_OZ) { 756 tcg_out_bswap_subr(s, bswap32u_addr); 757 } else { 758 tcg_out_bswap_subr(s, bswap32_addr); 759 } 760 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 761 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 762 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 763 } 764} 765 766static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 767{ 768 if (use_mips32r2_instructions) { 769 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 770 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 771 } else { 772 tcg_out_bswap_subr(s, bswap64_addr); 773 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 774 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 775 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 776 } 777} 778 779static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 780{ 781 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 782 if (use_mips32r2_instructions) { 783 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 784 } else { 785 tcg_out_dsll(s, ret, arg, 32); 786 tcg_out_dsrl(s, ret, ret, 32); 787 } 788} 789 790static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 791 TCGReg addr, intptr_t ofs) 792{ 793 int16_t lo = ofs; 794 if (ofs != lo) { 795 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 796 if (addr != TCG_REG_ZERO) { 797 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 798 } 799 addr = TCG_TMP0; 800 } 801 tcg_out_opc_imm(s, opc, data, addr, lo); 802} 803 804static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 805 TCGReg arg1, intptr_t arg2) 806{ 807 MIPSInsn opc = OPC_LD; 808 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 809 opc = OPC_LW; 810 } 811 tcg_out_ldst(s, opc, arg, arg1, arg2); 812} 813 814static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 815 TCGReg arg1, intptr_t arg2) 816{ 817 MIPSInsn opc = OPC_SD; 818 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 819 opc = OPC_SW; 820 } 821 tcg_out_ldst(s, opc, arg, arg1, arg2); 822} 823 824static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 825 TCGReg base, intptr_t ofs) 826{ 827 if (val == 0) { 828 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 829 return true; 830 } 831 return false; 832} 833 834static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 835 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 836 bool cbh, bool is_sub) 837{ 838 TCGReg th = TCG_TMP1; 839 840 /* If we have a negative constant such that negating it would 841 make the high part zero, we can (usually) eliminate one insn. */ 842 if (cbl && cbh && bh == -1 && bl != 0) { 843 bl = -bl; 844 bh = 0; 845 is_sub = !is_sub; 846 } 847 848 /* By operating on the high part first, we get to use the final 849 carry operation to move back from the temporary. */ 850 if (!cbh) { 851 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 852 } else if (bh != 0 || ah == rl) { 853 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 854 } else { 855 th = ah; 856 } 857 858 /* Note that tcg optimization should eliminate the bl == 0 case. */ 859 if (is_sub) { 860 if (cbl) { 861 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 862 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 863 } else { 864 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 865 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 866 } 867 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 868 } else { 869 if (cbl) { 870 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 871 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 872 } else if (rl == al && rl == bl) { 873 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 874 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 875 } else { 876 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 877 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 878 } 879 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 880 } 881} 882 883#define SETCOND_INV TCG_TARGET_NB_REGS 884#define SETCOND_NEZ (SETCOND_INV << 1) 885#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 886 887static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 888 TCGReg arg1, TCGReg arg2) 889{ 890 int flags = 0; 891 892 switch (cond) { 893 case TCG_COND_EQ: /* -> NE */ 894 case TCG_COND_GE: /* -> LT */ 895 case TCG_COND_GEU: /* -> LTU */ 896 case TCG_COND_LE: /* -> GT */ 897 case TCG_COND_LEU: /* -> GTU */ 898 cond = tcg_invert_cond(cond); 899 flags ^= SETCOND_INV; 900 break; 901 default: 902 break; 903 } 904 905 switch (cond) { 906 case TCG_COND_NE: 907 flags |= SETCOND_NEZ; 908 if (arg2 == 0) { 909 return arg1 | flags; 910 } 911 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 912 break; 913 case TCG_COND_LT: 914 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 915 break; 916 case TCG_COND_LTU: 917 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 918 break; 919 case TCG_COND_GT: 920 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 921 break; 922 case TCG_COND_GTU: 923 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 924 break; 925 default: 926 g_assert_not_reached(); 927 } 928 return ret | flags; 929} 930 931static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 932{ 933 if (tmpflags != ret) { 934 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 935 936 switch (tmpflags & SETCOND_FLAGS) { 937 case SETCOND_INV: 938 /* Intermediate result is boolean: simply invert. */ 939 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 940 break; 941 case SETCOND_NEZ: 942 /* Intermediate result is zero/non-zero: test != 0. */ 943 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 944 break; 945 case SETCOND_NEZ | SETCOND_INV: 946 /* Intermediate result is zero/non-zero: test == 0. */ 947 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 948 break; 949 default: 950 g_assert_not_reached(); 951 } 952 } 953} 954 955static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 956 TCGReg arg1, TCGReg arg2) 957{ 958 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 959 tcg_out_setcond_end(s, ret, tmpflags); 960} 961 962static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 963 TCGReg arg2, TCGLabel *l) 964{ 965 static const MIPSInsn b_zero[16] = { 966 [TCG_COND_LT] = OPC_BLTZ, 967 [TCG_COND_GT] = OPC_BGTZ, 968 [TCG_COND_LE] = OPC_BLEZ, 969 [TCG_COND_GE] = OPC_BGEZ, 970 }; 971 972 MIPSInsn b_opc = 0; 973 974 switch (cond) { 975 case TCG_COND_EQ: 976 b_opc = OPC_BEQ; 977 break; 978 case TCG_COND_NE: 979 b_opc = OPC_BNE; 980 break; 981 case TCG_COND_LT: 982 case TCG_COND_GT: 983 case TCG_COND_LE: 984 case TCG_COND_GE: 985 if (arg2 == 0) { 986 b_opc = b_zero[cond]; 987 arg2 = arg1; 988 arg1 = 0; 989 } 990 break; 991 default: 992 break; 993 } 994 995 if (b_opc == 0) { 996 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 997 998 arg2 = TCG_REG_ZERO; 999 arg1 = tmpflags & ~SETCOND_FLAGS; 1000 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1001 } 1002 1003 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1004 tcg_out_opc_br(s, b_opc, arg1, arg2); 1005 tcg_out_nop(s); 1006} 1007 1008static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 1009 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1010{ 1011 int flags = 0; 1012 1013 switch (cond) { 1014 case TCG_COND_EQ: 1015 flags |= SETCOND_INV; 1016 /* fall through */ 1017 case TCG_COND_NE: 1018 flags |= SETCOND_NEZ; 1019 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 1020 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 1021 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1022 break; 1023 1024 default: 1025 tcg_out_setcond(s, TCG_COND_EQ, TCG_TMP0, ah, bh); 1026 tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_TMP1, al, bl); 1027 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 1028 tcg_out_setcond(s, tcg_high_cond(cond), TCG_TMP0, ah, bh); 1029 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1030 break; 1031 } 1032 return ret | flags; 1033} 1034 1035static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1036 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1037{ 1038 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1039 tcg_out_setcond_end(s, ret, tmpflags); 1040} 1041 1042static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1043 TCGReg bl, TCGReg bh, TCGLabel *l) 1044{ 1045 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1046 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1047 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1048 1049 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1050 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1051 tcg_out_nop(s); 1052} 1053 1054static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1055 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1056{ 1057 int tmpflags; 1058 bool eqz; 1059 1060 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1061 if (use_mips32r6_instructions && v1 == 0) { 1062 v1 = v2; 1063 v2 = 0; 1064 cond = tcg_invert_cond(cond); 1065 } 1066 1067 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1068 c1 = tmpflags & ~SETCOND_FLAGS; 1069 eqz = tmpflags & SETCOND_INV; 1070 1071 if (use_mips32r6_instructions) { 1072 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1073 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1074 1075 if (v2 != 0) { 1076 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1077 } 1078 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1079 if (v2 != 0) { 1080 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1081 } 1082 return; 1083 } 1084 1085 /* This should be guaranteed via constraints */ 1086 tcg_debug_assert(v2 == ret); 1087 1088 if (use_movnz_instructions) { 1089 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1090 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1091 } else { 1092 /* Invert the condition in order to branch over the move. */ 1093 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1094 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1095 tcg_out_nop(s); 1096 /* Open-code tcg_out_mov, without the nop-move check. */ 1097 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1098 } 1099} 1100 1101static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1102{ 1103 /* 1104 * Note that __mips_abicalls requires the called function's address 1105 * to be loaded into $25 (t9), even if a direct branch is in range. 1106 * 1107 * For n64, always drop the pointer into the constant pool. 1108 * We can re-use helper addresses often and do not want any 1109 * of the longer sequences tcg_out_movi may try. 1110 */ 1111 if (sizeof(uintptr_t) == 8) { 1112 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1113 } else { 1114 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1115 } 1116 1117 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1118 if (tail) { 1119 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1120 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1121 } 1122 } else { 1123 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1124 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1125 } 1126 } 1127} 1128 1129static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1130 const TCGHelperInfo *info) 1131{ 1132 tcg_out_call_int(s, arg, false); 1133 tcg_out_nop(s); 1134} 1135 1136/* We have four temps, we might as well expose three of them. */ 1137static const TCGLdstHelperParam ldst_helper_param = { 1138 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1139}; 1140 1141static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1142{ 1143 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1144 MemOp opc = get_memop(l->oi); 1145 1146 /* resolve label address */ 1147 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1148 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1149 return false; 1150 } 1151 1152 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1153 1154 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1155 /* delay slot */ 1156 tcg_out_nop(s); 1157 1158 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1159 1160 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1161 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1162 return false; 1163 } 1164 1165 /* delay slot */ 1166 tcg_out_nop(s); 1167 return true; 1168} 1169 1170static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1171{ 1172 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1173 MemOp opc = get_memop(l->oi); 1174 1175 /* resolve label address */ 1176 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1177 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1178 return false; 1179 } 1180 1181 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1182 1183 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1184 /* delay slot */ 1185 tcg_out_nop(s); 1186 1187 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1188 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1189 return false; 1190 } 1191 1192 /* delay slot */ 1193 tcg_out_nop(s); 1194 return true; 1195} 1196 1197typedef struct { 1198 TCGReg base; 1199 TCGAtomAlign aa; 1200} HostAddress; 1201 1202bool tcg_target_has_memory_bswap(MemOp memop) 1203{ 1204 return false; 1205} 1206 1207/* We expect to use a 16-bit negative offset from ENV. */ 1208#define MIN_TLB_MASK_TABLE_OFS -32768 1209 1210/* 1211 * For system-mode, perform the TLB load and compare. 1212 * For user-mode, perform any required alignment tests. 1213 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1214 * is required and fill in @h with the host address for the fast path. 1215 */ 1216static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1217 TCGReg addr, MemOpIdx oi, bool is_ld) 1218{ 1219 TCGType addr_type = s->addr_type; 1220 TCGLabelQemuLdst *ldst = NULL; 1221 MemOp opc = get_memop(oi); 1222 MemOp a_bits; 1223 unsigned s_bits = opc & MO_SIZE; 1224 unsigned a_mask; 1225 TCGReg base; 1226 1227 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1228 a_bits = h->aa.align; 1229 a_mask = (1 << a_bits) - 1; 1230 1231 if (tcg_use_softmmu) { 1232 unsigned s_mask = (1 << s_bits) - 1; 1233 int mem_index = get_mmuidx(oi); 1234 int fast_off = tlb_mask_table_ofs(s, mem_index); 1235 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1236 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1237 int add_off = offsetof(CPUTLBEntry, addend); 1238 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1239 : offsetof(CPUTLBEntry, addr_write); 1240 1241 ldst = new_ldst_label(s); 1242 ldst->is_ld = is_ld; 1243 ldst->oi = oi; 1244 ldst->addr_reg = addr; 1245 1246 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1247 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1248 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1249 1250 /* Extract the TLB index from the address into TMP3. */ 1251 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1252 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1253 s->page_bits - CPU_TLB_ENTRY_BITS); 1254 } else { 1255 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1256 } 1257 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1258 1259 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1260 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1261 1262 /* Load the tlb comparator. */ 1263 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1264 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1265 cmp_off + HOST_BIG_ENDIAN * 4); 1266 } else { 1267 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1268 } 1269 1270 /* Load the tlb addend for the fast path. */ 1271 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1272 1273 /* 1274 * Mask the page bits, keeping the alignment bits to compare against. 1275 * For unaligned accesses, compare against the end of the access to 1276 * verify that it does not cross a page boundary. 1277 */ 1278 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1279 if (a_mask < s_mask) { 1280 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1281 || addr_type == TCG_TYPE_I32 1282 ? OPC_ADDIU : OPC_DADDIU), 1283 TCG_TMP2, addr, s_mask - a_mask); 1284 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1285 } else { 1286 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1287 } 1288 1289 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1290 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1291 tcg_out_ext32u(s, TCG_TMP2, addr); 1292 addr = TCG_TMP2; 1293 } 1294 1295 ldst->label_ptr[0] = s->code_ptr; 1296 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1297 1298 /* delay slot */ 1299 base = TCG_TMP3; 1300 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1301 } else { 1302 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1303 ldst = new_ldst_label(s); 1304 1305 ldst->is_ld = is_ld; 1306 ldst->oi = oi; 1307 ldst->addr_reg = addr; 1308 1309 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1310 tcg_debug_assert(a_bits < 16); 1311 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1312 1313 ldst->label_ptr[0] = s->code_ptr; 1314 if (use_mips32r6_instructions) { 1315 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1316 } else { 1317 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1318 tcg_out_nop(s); 1319 } 1320 } 1321 1322 base = addr; 1323 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1324 tcg_out_ext32u(s, TCG_REG_A0, base); 1325 base = TCG_REG_A0; 1326 } 1327 if (guest_base) { 1328 if (guest_base == (int16_t)guest_base) { 1329 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1330 } else { 1331 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1332 TCG_GUEST_BASE_REG); 1333 } 1334 base = TCG_REG_A0; 1335 } 1336 } 1337 1338 h->base = base; 1339 return ldst; 1340} 1341 1342static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1343 TCGReg base, MemOp opc, TCGType type) 1344{ 1345 switch (opc & MO_SSIZE) { 1346 case MO_UB: 1347 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1348 break; 1349 case MO_SB: 1350 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1351 break; 1352 case MO_UW: 1353 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1354 break; 1355 case MO_SW: 1356 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1357 break; 1358 case MO_UL: 1359 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1360 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1361 break; 1362 } 1363 /* FALLTHRU */ 1364 case MO_SL: 1365 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1366 break; 1367 case MO_UQ: 1368 /* Prefer to load from offset 0 first, but allow for overlap. */ 1369 if (TCG_TARGET_REG_BITS == 64) { 1370 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1371 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1372 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1373 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1374 } else { 1375 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1376 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1377 } 1378 break; 1379 default: 1380 g_assert_not_reached(); 1381 } 1382} 1383 1384static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1385 TCGReg base, MemOp opc, TCGType type) 1386{ 1387 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1388 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1389 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1390 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1391 bool sgn = opc & MO_SIGN; 1392 1393 switch (opc & MO_SIZE) { 1394 case MO_16: 1395 if (HOST_BIG_ENDIAN) { 1396 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1397 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1398 if (use_mips32r2_instructions) { 1399 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1400 } else { 1401 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1402 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1403 } 1404 } else if (use_mips32r2_instructions && lo != base) { 1405 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1406 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1407 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1408 } else { 1409 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1410 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1411 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1412 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1413 } 1414 break; 1415 1416 case MO_32: 1417 tcg_out_opc_imm(s, lw1, lo, base, 0); 1418 tcg_out_opc_imm(s, lw2, lo, base, 3); 1419 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1420 tcg_out_ext32u(s, lo, lo); 1421 } 1422 break; 1423 1424 case MO_64: 1425 if (TCG_TARGET_REG_BITS == 64) { 1426 tcg_out_opc_imm(s, ld1, lo, base, 0); 1427 tcg_out_opc_imm(s, ld2, lo, base, 7); 1428 } else { 1429 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1430 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1431 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1432 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1433 } 1434 break; 1435 1436 default: 1437 g_assert_not_reached(); 1438 } 1439} 1440 1441static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1442 TCGReg addr, MemOpIdx oi, TCGType data_type) 1443{ 1444 MemOp opc = get_memop(oi); 1445 TCGLabelQemuLdst *ldst; 1446 HostAddress h; 1447 1448 ldst = prepare_host_addr(s, &h, addr, oi, true); 1449 1450 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1451 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1452 } else { 1453 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1454 } 1455 1456 if (ldst) { 1457 ldst->type = data_type; 1458 ldst->datalo_reg = datalo; 1459 ldst->datahi_reg = datahi; 1460 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1461 } 1462} 1463 1464static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1465 TCGReg base, MemOp opc) 1466{ 1467 switch (opc & MO_SIZE) { 1468 case MO_8: 1469 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1470 break; 1471 case MO_16: 1472 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1473 break; 1474 case MO_32: 1475 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1476 break; 1477 case MO_64: 1478 if (TCG_TARGET_REG_BITS == 64) { 1479 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1480 } else { 1481 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1482 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1483 } 1484 break; 1485 default: 1486 g_assert_not_reached(); 1487 } 1488} 1489 1490static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1491 TCGReg base, MemOp opc) 1492{ 1493 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1494 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1495 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1496 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1497 1498 switch (opc & MO_SIZE) { 1499 case MO_16: 1500 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1501 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1502 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1503 break; 1504 1505 case MO_32: 1506 tcg_out_opc_imm(s, sw1, lo, base, 0); 1507 tcg_out_opc_imm(s, sw2, lo, base, 3); 1508 break; 1509 1510 case MO_64: 1511 if (TCG_TARGET_REG_BITS == 64) { 1512 tcg_out_opc_imm(s, sd1, lo, base, 0); 1513 tcg_out_opc_imm(s, sd2, lo, base, 7); 1514 } else { 1515 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1516 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1517 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1518 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1519 } 1520 break; 1521 1522 default: 1523 g_assert_not_reached(); 1524 } 1525} 1526 1527static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1528 TCGReg addr, MemOpIdx oi, TCGType data_type) 1529{ 1530 MemOp opc = get_memop(oi); 1531 TCGLabelQemuLdst *ldst; 1532 HostAddress h; 1533 1534 ldst = prepare_host_addr(s, &h, addr, oi, false); 1535 1536 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1537 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1538 } else { 1539 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1540 } 1541 1542 if (ldst) { 1543 ldst->type = data_type; 1544 ldst->datalo_reg = datalo; 1545 ldst->datahi_reg = datahi; 1546 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1547 } 1548} 1549 1550static void tcg_out_mb(TCGContext *s, TCGArg a0) 1551{ 1552 static const MIPSInsn sync[] = { 1553 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1554 as the former is an ordering barrier and the latter 1555 is a completion barrier. */ 1556 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1557 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1558 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1559 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1560 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1561 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1562 }; 1563 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1564} 1565 1566static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1567 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1568{ 1569 if (use_mips32r6_instructions) { 1570 if (a2 == width) { 1571 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1572 } else { 1573 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1574 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1575 } 1576 } else { 1577 if (a2 == width) { 1578 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1579 } else if (a0 == a2) { 1580 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1581 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1582 } else if (a0 != a1) { 1583 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1584 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1585 } else { 1586 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1587 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1588 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1589 } 1590 } 1591} 1592 1593static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1594{ 1595 TCGReg base = TCG_REG_ZERO; 1596 int16_t lo = 0; 1597 1598 if (a0) { 1599 intptr_t ofs; 1600 if (TCG_TARGET_REG_BITS == 64) { 1601 ofs = tcg_tbrel_diff(s, (void *)a0); 1602 lo = ofs; 1603 if (ofs == lo) { 1604 base = TCG_REG_TB; 1605 } else { 1606 base = TCG_REG_V0; 1607 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1608 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1609 } 1610 } else { 1611 ofs = a0; 1612 lo = ofs; 1613 base = TCG_REG_V0; 1614 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1615 } 1616 } 1617 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1618 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1619 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1620 } 1621 /* delay slot */ 1622 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1623} 1624 1625static void tcg_out_goto_tb(TCGContext *s, int which) 1626{ 1627 intptr_t ofs = get_jmp_target_addr(s, which); 1628 TCGReg base, dest; 1629 1630 /* indirect jump method */ 1631 if (TCG_TARGET_REG_BITS == 64) { 1632 dest = TCG_REG_TB; 1633 base = TCG_REG_TB; 1634 ofs = tcg_tbrel_diff(s, (void *)ofs); 1635 } else { 1636 dest = TCG_TMP0; 1637 base = TCG_REG_ZERO; 1638 } 1639 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1640 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1641 /* delay slot */ 1642 tcg_out_nop(s); 1643 1644 set_jmp_reset_offset(s, which); 1645 if (TCG_TARGET_REG_BITS == 64) { 1646 /* For the unlinked case, need to reset TCG_REG_TB. */ 1647 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1648 -tcg_current_code_size(s)); 1649 } 1650} 1651 1652void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1653 uintptr_t jmp_rx, uintptr_t jmp_rw) 1654{ 1655 /* Always indirect, nothing to do */ 1656} 1657 1658 1659static void tgen_add(TCGContext *s, TCGType type, 1660 TCGReg a0, TCGReg a1, TCGReg a2) 1661{ 1662 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1663 tcg_out_opc_reg(s, insn, a0, a1, a2); 1664} 1665 1666static void tgen_addi(TCGContext *s, TCGType type, 1667 TCGReg a0, TCGReg a1, tcg_target_long a2) 1668{ 1669 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1670 tcg_out_opc_imm(s, insn, a0, a1, a2); 1671} 1672 1673static const TCGOutOpBinary outop_add = { 1674 .base.static_constraint = C_O1_I2(r, r, rJ), 1675 .out_rrr = tgen_add, 1676 .out_rri = tgen_addi, 1677}; 1678 1679static void tgen_and(TCGContext *s, TCGType type, 1680 TCGReg a0, TCGReg a1, TCGReg a2) 1681{ 1682 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1683} 1684 1685static void tgen_andi(TCGContext *s, TCGType type, 1686 TCGReg a0, TCGReg a1, tcg_target_long a2) 1687{ 1688 int msb; 1689 1690 if (a2 == (uint16_t)a2) { 1691 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1692 return; 1693 } 1694 1695 tcg_debug_assert(use_mips32r2_instructions); 1696 tcg_debug_assert(is_p2m1(a2)); 1697 msb = ctz64(~a2) - 1; 1698 if (type == TCG_TYPE_I32) { 1699 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1700 } else { 1701 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1702 } 1703} 1704 1705static const TCGOutOpBinary outop_and = { 1706 .base.static_constraint = C_O1_I2(r, r, rIK), 1707 .out_rrr = tgen_and, 1708 .out_rri = tgen_andi, 1709}; 1710 1711static const TCGOutOpBinary outop_andc = { 1712 .base.static_constraint = C_NotImplemented, 1713}; 1714 1715static void tgen_or(TCGContext *s, TCGType type, 1716 TCGReg a0, TCGReg a1, TCGReg a2) 1717{ 1718 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1719} 1720 1721static void tgen_ori(TCGContext *s, TCGType type, 1722 TCGReg a0, TCGReg a1, tcg_target_long a2) 1723{ 1724 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1725} 1726 1727static const TCGOutOpBinary outop_or = { 1728 .base.static_constraint = C_O1_I2(r, r, rI), 1729 .out_rrr = tgen_or, 1730 .out_rri = tgen_ori, 1731}; 1732 1733static const TCGOutOpBinary outop_orc = { 1734 .base.static_constraint = C_NotImplemented, 1735}; 1736 1737 1738static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1739 const TCGArg args[TCG_MAX_OP_ARGS], 1740 const int const_args[TCG_MAX_OP_ARGS]) 1741{ 1742 MIPSInsn i1, i2; 1743 TCGArg a0, a1, a2; 1744 int c2; 1745 1746 a0 = args[0]; 1747 a1 = args[1]; 1748 a2 = args[2]; 1749 c2 = const_args[2]; 1750 1751 switch (opc) { 1752 case INDEX_op_goto_ptr: 1753 /* jmp to the given host address (could be epilogue) */ 1754 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1755 if (TCG_TARGET_REG_BITS == 64) { 1756 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 1757 } else { 1758 tcg_out_nop(s); 1759 } 1760 break; 1761 case INDEX_op_br: 1762 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1763 arg_label(a0)); 1764 break; 1765 1766 case INDEX_op_ld8u_i32: 1767 case INDEX_op_ld8u_i64: 1768 i1 = OPC_LBU; 1769 goto do_ldst; 1770 case INDEX_op_ld8s_i32: 1771 case INDEX_op_ld8s_i64: 1772 i1 = OPC_LB; 1773 goto do_ldst; 1774 case INDEX_op_ld16u_i32: 1775 case INDEX_op_ld16u_i64: 1776 i1 = OPC_LHU; 1777 goto do_ldst; 1778 case INDEX_op_ld16s_i32: 1779 case INDEX_op_ld16s_i64: 1780 i1 = OPC_LH; 1781 goto do_ldst; 1782 case INDEX_op_ld_i32: 1783 case INDEX_op_ld32s_i64: 1784 i1 = OPC_LW; 1785 goto do_ldst; 1786 case INDEX_op_ld32u_i64: 1787 i1 = OPC_LWU; 1788 goto do_ldst; 1789 case INDEX_op_ld_i64: 1790 i1 = OPC_LD; 1791 goto do_ldst; 1792 case INDEX_op_st8_i32: 1793 case INDEX_op_st8_i64: 1794 i1 = OPC_SB; 1795 goto do_ldst; 1796 case INDEX_op_st16_i32: 1797 case INDEX_op_st16_i64: 1798 i1 = OPC_SH; 1799 goto do_ldst; 1800 case INDEX_op_st_i32: 1801 case INDEX_op_st32_i64: 1802 i1 = OPC_SW; 1803 goto do_ldst; 1804 case INDEX_op_st_i64: 1805 i1 = OPC_SD; 1806 do_ldst: 1807 tcg_out_ldst(s, i1, a0, a1, a2); 1808 break; 1809 1810 case INDEX_op_xor_i32: 1811 case INDEX_op_xor_i64: 1812 i1 = OPC_XOR, i2 = OPC_XORI; 1813 if (c2) { 1814 tcg_out_opc_imm(s, i2, a0, a1, a2); 1815 break; 1816 } 1817 do_binaryv: 1818 tcg_out_opc_reg(s, i1, a0, a1, a2); 1819 break; 1820 1821 case INDEX_op_sub_i32: 1822 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1823 goto do_subtract; 1824 case INDEX_op_sub_i64: 1825 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1826 do_subtract: 1827 if (c2) { 1828 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1829 break; 1830 } 1831 goto do_binaryv; 1832 case INDEX_op_nor_i32: 1833 case INDEX_op_nor_i64: 1834 i1 = OPC_NOR; 1835 goto do_binaryv; 1836 1837 case INDEX_op_mul_i32: 1838 if (use_mips32_instructions) { 1839 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1840 break; 1841 } 1842 i1 = OPC_MULT, i2 = OPC_MFLO; 1843 goto do_hilo1; 1844 case INDEX_op_mulsh_i32: 1845 if (use_mips32r6_instructions) { 1846 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1847 break; 1848 } 1849 i1 = OPC_MULT, i2 = OPC_MFHI; 1850 goto do_hilo1; 1851 case INDEX_op_muluh_i32: 1852 if (use_mips32r6_instructions) { 1853 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1854 break; 1855 } 1856 i1 = OPC_MULTU, i2 = OPC_MFHI; 1857 goto do_hilo1; 1858 case INDEX_op_div_i32: 1859 if (use_mips32r6_instructions) { 1860 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1861 break; 1862 } 1863 i1 = OPC_DIV, i2 = OPC_MFLO; 1864 goto do_hilo1; 1865 case INDEX_op_divu_i32: 1866 if (use_mips32r6_instructions) { 1867 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1868 break; 1869 } 1870 i1 = OPC_DIVU, i2 = OPC_MFLO; 1871 goto do_hilo1; 1872 case INDEX_op_rem_i32: 1873 if (use_mips32r6_instructions) { 1874 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1875 break; 1876 } 1877 i1 = OPC_DIV, i2 = OPC_MFHI; 1878 goto do_hilo1; 1879 case INDEX_op_remu_i32: 1880 if (use_mips32r6_instructions) { 1881 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1882 break; 1883 } 1884 i1 = OPC_DIVU, i2 = OPC_MFHI; 1885 goto do_hilo1; 1886 case INDEX_op_mul_i64: 1887 if (use_mips32r6_instructions) { 1888 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1889 break; 1890 } 1891 i1 = OPC_DMULT, i2 = OPC_MFLO; 1892 goto do_hilo1; 1893 case INDEX_op_mulsh_i64: 1894 if (use_mips32r6_instructions) { 1895 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1896 break; 1897 } 1898 i1 = OPC_DMULT, i2 = OPC_MFHI; 1899 goto do_hilo1; 1900 case INDEX_op_muluh_i64: 1901 if (use_mips32r6_instructions) { 1902 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1903 break; 1904 } 1905 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1906 goto do_hilo1; 1907 case INDEX_op_div_i64: 1908 if (use_mips32r6_instructions) { 1909 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1910 break; 1911 } 1912 i1 = OPC_DDIV, i2 = OPC_MFLO; 1913 goto do_hilo1; 1914 case INDEX_op_divu_i64: 1915 if (use_mips32r6_instructions) { 1916 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1917 break; 1918 } 1919 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1920 goto do_hilo1; 1921 case INDEX_op_rem_i64: 1922 if (use_mips32r6_instructions) { 1923 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1924 break; 1925 } 1926 i1 = OPC_DDIV, i2 = OPC_MFHI; 1927 goto do_hilo1; 1928 case INDEX_op_remu_i64: 1929 if (use_mips32r6_instructions) { 1930 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1931 break; 1932 } 1933 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1934 do_hilo1: 1935 tcg_out_opc_reg(s, i1, 0, a1, a2); 1936 tcg_out_opc_reg(s, i2, a0, 0, 0); 1937 break; 1938 1939 case INDEX_op_muls2_i32: 1940 i1 = OPC_MULT; 1941 goto do_hilo2; 1942 case INDEX_op_mulu2_i32: 1943 i1 = OPC_MULTU; 1944 goto do_hilo2; 1945 case INDEX_op_muls2_i64: 1946 i1 = OPC_DMULT; 1947 goto do_hilo2; 1948 case INDEX_op_mulu2_i64: 1949 i1 = OPC_DMULTU; 1950 do_hilo2: 1951 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1952 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1953 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1954 break; 1955 1956 case INDEX_op_neg_i32: 1957 i1 = OPC_SUBU; 1958 goto do_unary; 1959 case INDEX_op_neg_i64: 1960 i1 = OPC_DSUBU; 1961 goto do_unary; 1962 case INDEX_op_not_i32: 1963 case INDEX_op_not_i64: 1964 i1 = OPC_NOR; 1965 goto do_unary; 1966 do_unary: 1967 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1968 break; 1969 1970 case INDEX_op_bswap16_i32: 1971 case INDEX_op_bswap16_i64: 1972 tcg_out_bswap16(s, a0, a1, a2); 1973 break; 1974 case INDEX_op_bswap32_i32: 1975 tcg_out_bswap32(s, a0, a1, 0); 1976 break; 1977 case INDEX_op_bswap32_i64: 1978 tcg_out_bswap32(s, a0, a1, a2); 1979 break; 1980 case INDEX_op_bswap64_i64: 1981 tcg_out_bswap64(s, a0, a1); 1982 break; 1983 case INDEX_op_extrh_i64_i32: 1984 tcg_out_dsra(s, a0, a1, 32); 1985 break; 1986 1987 case INDEX_op_sar_i32: 1988 i1 = OPC_SRAV, i2 = OPC_SRA; 1989 goto do_shift; 1990 case INDEX_op_shl_i32: 1991 i1 = OPC_SLLV, i2 = OPC_SLL; 1992 goto do_shift; 1993 case INDEX_op_shr_i32: 1994 i1 = OPC_SRLV, i2 = OPC_SRL; 1995 goto do_shift; 1996 case INDEX_op_rotr_i32: 1997 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1998 do_shift: 1999 if (c2) { 2000 tcg_out_opc_sa(s, i2, a0, a1, a2); 2001 break; 2002 } 2003 do_shiftv: 2004 tcg_out_opc_reg(s, i1, a0, a2, a1); 2005 break; 2006 case INDEX_op_rotl_i32: 2007 if (c2) { 2008 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 2009 } else { 2010 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2011 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 2012 } 2013 break; 2014 case INDEX_op_sar_i64: 2015 if (c2) { 2016 tcg_out_dsra(s, a0, a1, a2); 2017 break; 2018 } 2019 i1 = OPC_DSRAV; 2020 goto do_shiftv; 2021 case INDEX_op_shl_i64: 2022 if (c2) { 2023 tcg_out_dsll(s, a0, a1, a2); 2024 break; 2025 } 2026 i1 = OPC_DSLLV; 2027 goto do_shiftv; 2028 case INDEX_op_shr_i64: 2029 if (c2) { 2030 tcg_out_dsrl(s, a0, a1, a2); 2031 break; 2032 } 2033 i1 = OPC_DSRLV; 2034 goto do_shiftv; 2035 case INDEX_op_rotr_i64: 2036 if (c2) { 2037 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2038 break; 2039 } 2040 i1 = OPC_DROTRV; 2041 goto do_shiftv; 2042 case INDEX_op_rotl_i64: 2043 if (c2) { 2044 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2045 } else { 2046 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2047 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2048 } 2049 break; 2050 2051 case INDEX_op_clz_i32: 2052 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2053 break; 2054 case INDEX_op_clz_i64: 2055 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2056 break; 2057 2058 case INDEX_op_deposit_i32: 2059 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2060 break; 2061 case INDEX_op_deposit_i64: 2062 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2063 args[3] + args[4] - 1, args[3]); 2064 break; 2065 2066 case INDEX_op_extract_i32: 2067 if (a2 == 0 && args[3] <= 16) { 2068 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2069 } else { 2070 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2071 } 2072 break; 2073 case INDEX_op_extract_i64: 2074 if (a2 == 0 && args[3] <= 16) { 2075 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2076 } else { 2077 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2078 a0, a1, args[3] - 1, a2); 2079 } 2080 break; 2081 2082 case INDEX_op_sextract_i64: 2083 if (a2 == 0 && args[3] == 32) { 2084 tcg_out_ext32s(s, a0, a1); 2085 break; 2086 } 2087 /* FALLTHRU */ 2088 case INDEX_op_sextract_i32: 2089 if (a2 == 0 && args[3] == 8) { 2090 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 2091 } else if (a2 == 0 && args[3] == 16) { 2092 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 2093 } else { 2094 g_assert_not_reached(); 2095 } 2096 break; 2097 2098 case INDEX_op_brcond_i32: 2099 case INDEX_op_brcond_i64: 2100 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2101 break; 2102 case INDEX_op_brcond2_i32: 2103 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2104 break; 2105 2106 case INDEX_op_movcond_i32: 2107 case INDEX_op_movcond_i64: 2108 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2109 break; 2110 2111 case INDEX_op_setcond_i32: 2112 case INDEX_op_setcond_i64: 2113 tcg_out_setcond(s, args[3], a0, a1, a2); 2114 break; 2115 case INDEX_op_setcond2_i32: 2116 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2117 break; 2118 2119 case INDEX_op_qemu_ld_i32: 2120 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2121 break; 2122 case INDEX_op_qemu_ld_i64: 2123 if (TCG_TARGET_REG_BITS == 64) { 2124 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2125 } else { 2126 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2127 } 2128 break; 2129 2130 case INDEX_op_qemu_st_i32: 2131 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2132 break; 2133 case INDEX_op_qemu_st_i64: 2134 if (TCG_TARGET_REG_BITS == 64) { 2135 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2136 } else { 2137 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2138 } 2139 break; 2140 2141 case INDEX_op_add2_i32: 2142 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2143 const_args[4], const_args[5], false); 2144 break; 2145 case INDEX_op_sub2_i32: 2146 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2147 const_args[4], const_args[5], true); 2148 break; 2149 2150 case INDEX_op_mb: 2151 tcg_out_mb(s, a0); 2152 break; 2153 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2154 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2155 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2156 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2157 case INDEX_op_extu_i32_i64: 2158 case INDEX_op_extrl_i64_i32: 2159 default: 2160 g_assert_not_reached(); 2161 } 2162} 2163 2164static TCGConstraintSetIndex 2165tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2166{ 2167 switch (op) { 2168 case INDEX_op_goto_ptr: 2169 return C_O0_I1(r); 2170 2171 case INDEX_op_ld8u_i32: 2172 case INDEX_op_ld8s_i32: 2173 case INDEX_op_ld16u_i32: 2174 case INDEX_op_ld16s_i32: 2175 case INDEX_op_ld_i32: 2176 case INDEX_op_neg_i32: 2177 case INDEX_op_not_i32: 2178 case INDEX_op_bswap16_i32: 2179 case INDEX_op_bswap32_i32: 2180 case INDEX_op_extract_i32: 2181 case INDEX_op_sextract_i32: 2182 case INDEX_op_ld8u_i64: 2183 case INDEX_op_ld8s_i64: 2184 case INDEX_op_ld16u_i64: 2185 case INDEX_op_ld16s_i64: 2186 case INDEX_op_ld32s_i64: 2187 case INDEX_op_ld32u_i64: 2188 case INDEX_op_ld_i64: 2189 case INDEX_op_neg_i64: 2190 case INDEX_op_not_i64: 2191 case INDEX_op_bswap16_i64: 2192 case INDEX_op_bswap32_i64: 2193 case INDEX_op_bswap64_i64: 2194 case INDEX_op_ext_i32_i64: 2195 case INDEX_op_extu_i32_i64: 2196 case INDEX_op_extrl_i64_i32: 2197 case INDEX_op_extrh_i64_i32: 2198 case INDEX_op_extract_i64: 2199 case INDEX_op_sextract_i64: 2200 return C_O1_I1(r, r); 2201 2202 case INDEX_op_st8_i32: 2203 case INDEX_op_st16_i32: 2204 case INDEX_op_st_i32: 2205 case INDEX_op_st8_i64: 2206 case INDEX_op_st16_i64: 2207 case INDEX_op_st32_i64: 2208 case INDEX_op_st_i64: 2209 return C_O0_I2(rz, r); 2210 2211 case INDEX_op_sub_i32: 2212 case INDEX_op_sub_i64: 2213 return C_O1_I2(r, rz, rN); 2214 case INDEX_op_mul_i32: 2215 case INDEX_op_mulsh_i32: 2216 case INDEX_op_muluh_i32: 2217 case INDEX_op_div_i32: 2218 case INDEX_op_divu_i32: 2219 case INDEX_op_rem_i32: 2220 case INDEX_op_remu_i32: 2221 case INDEX_op_nor_i32: 2222 case INDEX_op_setcond_i32: 2223 case INDEX_op_mul_i64: 2224 case INDEX_op_mulsh_i64: 2225 case INDEX_op_muluh_i64: 2226 case INDEX_op_div_i64: 2227 case INDEX_op_divu_i64: 2228 case INDEX_op_rem_i64: 2229 case INDEX_op_remu_i64: 2230 case INDEX_op_nor_i64: 2231 case INDEX_op_setcond_i64: 2232 return C_O1_I2(r, rz, rz); 2233 case INDEX_op_muls2_i32: 2234 case INDEX_op_mulu2_i32: 2235 case INDEX_op_muls2_i64: 2236 case INDEX_op_mulu2_i64: 2237 return C_O2_I2(r, r, r, r); 2238 case INDEX_op_xor_i32: 2239 case INDEX_op_xor_i64: 2240 return C_O1_I2(r, r, rI); 2241 case INDEX_op_shl_i32: 2242 case INDEX_op_shr_i32: 2243 case INDEX_op_sar_i32: 2244 case INDEX_op_rotr_i32: 2245 case INDEX_op_rotl_i32: 2246 case INDEX_op_shl_i64: 2247 case INDEX_op_shr_i64: 2248 case INDEX_op_sar_i64: 2249 case INDEX_op_rotr_i64: 2250 case INDEX_op_rotl_i64: 2251 return C_O1_I2(r, r, ri); 2252 case INDEX_op_clz_i32: 2253 case INDEX_op_clz_i64: 2254 return C_O1_I2(r, r, rzW); 2255 2256 case INDEX_op_deposit_i32: 2257 case INDEX_op_deposit_i64: 2258 return C_O1_I2(r, 0, rz); 2259 case INDEX_op_brcond_i32: 2260 case INDEX_op_brcond_i64: 2261 return C_O0_I2(rz, rz); 2262 case INDEX_op_movcond_i32: 2263 case INDEX_op_movcond_i64: 2264 return (use_mips32r6_instructions 2265 ? C_O1_I4(r, rz, rz, rz, rz) 2266 : C_O1_I4(r, rz, rz, rz, 0)); 2267 case INDEX_op_add2_i32: 2268 case INDEX_op_sub2_i32: 2269 return C_O2_I4(r, r, rz, rz, rN, rN); 2270 case INDEX_op_setcond2_i32: 2271 return C_O1_I4(r, rz, rz, rz, rz); 2272 case INDEX_op_brcond2_i32: 2273 return C_O0_I4(rz, rz, rz, rz); 2274 2275 case INDEX_op_qemu_ld_i32: 2276 return C_O1_I1(r, r); 2277 case INDEX_op_qemu_st_i32: 2278 return C_O0_I2(rz, r); 2279 case INDEX_op_qemu_ld_i64: 2280 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2281 case INDEX_op_qemu_st_i64: 2282 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2283 2284 default: 2285 return C_NotImplemented; 2286 } 2287} 2288 2289static const int tcg_target_callee_save_regs[] = { 2290 TCG_REG_S0, 2291 TCG_REG_S1, 2292 TCG_REG_S2, 2293 TCG_REG_S3, 2294 TCG_REG_S4, 2295 TCG_REG_S5, 2296 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2297 TCG_REG_S7, /* used for guest_base */ 2298 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2299 TCG_REG_RA, /* should be last for ABI compliance */ 2300}; 2301 2302/* The Linux kernel doesn't provide any information about the available 2303 instruction set. Probe it using a signal handler. */ 2304 2305 2306#ifndef use_movnz_instructions 2307bool use_movnz_instructions = false; 2308#endif 2309 2310#ifndef use_mips32_instructions 2311bool use_mips32_instructions = false; 2312#endif 2313 2314#ifndef use_mips32r2_instructions 2315bool use_mips32r2_instructions = false; 2316#endif 2317 2318static volatile sig_atomic_t got_sigill; 2319 2320static void sigill_handler(int signo, siginfo_t *si, void *data) 2321{ 2322 /* Skip the faulty instruction */ 2323 ucontext_t *uc = (ucontext_t *)data; 2324 uc->uc_mcontext.pc += 4; 2325 2326 got_sigill = 1; 2327} 2328 2329static void tcg_target_detect_isa(void) 2330{ 2331 struct sigaction sa_old, sa_new; 2332 2333 memset(&sa_new, 0, sizeof(sa_new)); 2334 sa_new.sa_flags = SA_SIGINFO; 2335 sa_new.sa_sigaction = sigill_handler; 2336 sigaction(SIGILL, &sa_new, &sa_old); 2337 2338 /* Probe for movn/movz, necessary to implement movcond. */ 2339#ifndef use_movnz_instructions 2340 got_sigill = 0; 2341 asm volatile(".set push\n" 2342 ".set mips32\n" 2343 "movn $zero, $zero, $zero\n" 2344 "movz $zero, $zero, $zero\n" 2345 ".set pop\n" 2346 : : : ); 2347 use_movnz_instructions = !got_sigill; 2348#endif 2349 2350 /* Probe for MIPS32 instructions. As no subsetting is allowed 2351 by the specification, it is only necessary to probe for one 2352 of the instructions. */ 2353#ifndef use_mips32_instructions 2354 got_sigill = 0; 2355 asm volatile(".set push\n" 2356 ".set mips32\n" 2357 "mul $zero, $zero\n" 2358 ".set pop\n" 2359 : : : ); 2360 use_mips32_instructions = !got_sigill; 2361#endif 2362 2363 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2364 available. As no subsetting is allowed by the specification, 2365 it is only necessary to probe for one of the instructions. */ 2366#ifndef use_mips32r2_instructions 2367 if (use_mips32_instructions) { 2368 got_sigill = 0; 2369 asm volatile(".set push\n" 2370 ".set mips32r2\n" 2371 "seb $zero, $zero\n" 2372 ".set pop\n" 2373 : : : ); 2374 use_mips32r2_instructions = !got_sigill; 2375 } 2376#endif 2377 2378 sigaction(SIGILL, &sa_old, NULL); 2379} 2380 2381static tcg_insn_unit *align_code_ptr(TCGContext *s) 2382{ 2383 uintptr_t p = (uintptr_t)s->code_ptr; 2384 if (p & 15) { 2385 p = (p + 15) & -16; 2386 s->code_ptr = (void *)p; 2387 } 2388 return s->code_ptr; 2389} 2390 2391/* Stack frame parameters. */ 2392#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2393#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2394#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2395 2396#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2397 + TCG_TARGET_STACK_ALIGN - 1) \ 2398 & -TCG_TARGET_STACK_ALIGN) 2399#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2400 2401/* We're expecting to be able to use an immediate for frame allocation. */ 2402QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2403 2404/* Generate global QEMU prologue and epilogue code */ 2405static void tcg_target_qemu_prologue(TCGContext *s) 2406{ 2407 int i; 2408 2409 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2410 2411 /* TB prologue */ 2412 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2413 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2414 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2415 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2416 } 2417 2418 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2419 /* 2420 * The function call abi for n32 and n64 will have loaded $25 (t9) 2421 * with the address of the prologue, so we can use that instead 2422 * of TCG_REG_TB. 2423 */ 2424#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2425# error "Unknown mips abi" 2426#endif 2427 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2428 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2429 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2430 } 2431 2432 if (TCG_TARGET_REG_BITS == 64) { 2433 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2434 } 2435 2436 /* Call generated code */ 2437 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2438 /* delay slot */ 2439 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2440 2441 /* 2442 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2443 * and fall through to the rest of the epilogue. 2444 */ 2445 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2446 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2447 2448 /* TB epilogue */ 2449 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2450 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2451 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2452 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2453 } 2454 2455 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2456 /* delay slot */ 2457 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2458 2459 if (use_mips32r2_instructions) { 2460 return; 2461 } 2462 2463 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2464 clobbers TCG_TMP1, TCG_TMP2. */ 2465 2466 /* 2467 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2468 */ 2469 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2470 /* t3 = (ssss)d000 */ 2471 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2472 /* t1 = 000a */ 2473 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2474 /* t2 = 00c0 */ 2475 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2476 /* t3 = d00a */ 2477 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2478 /* t1 = 0abc */ 2479 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2480 /* t2 = 0c00 */ 2481 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2482 /* t1 = 00b0 */ 2483 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2484 /* t3 = dc0a */ 2485 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2486 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2487 /* t3 = dcba -- delay slot */ 2488 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2489 2490 if (TCG_TARGET_REG_BITS == 32) { 2491 return; 2492 } 2493 2494 /* 2495 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2496 */ 2497 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2498 /* t1 = (0000)000d */ 2499 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2500 /* t3 = 000a */ 2501 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2502 /* t1 = (0000)d000 */ 2503 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2504 /* t2 = 00c0 */ 2505 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2506 /* t3 = d00a */ 2507 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2508 /* t1 = 0abc */ 2509 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2510 /* t2 = 0c00 */ 2511 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2512 /* t1 = 00b0 */ 2513 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2514 /* t3 = dc0a */ 2515 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2516 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2517 /* t3 = dcba -- delay slot */ 2518 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2519 2520 /* 2521 * bswap64 -- 64-bit swap. a0 = abcdefgh 2522 */ 2523 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2524 /* t3 = h0000000 */ 2525 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2526 /* t1 = 0000000a */ 2527 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2528 2529 /* t2 = 000000g0 */ 2530 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2531 /* t3 = h000000a */ 2532 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2533 /* t1 = 00000abc */ 2534 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2535 /* t2 = 0g000000 */ 2536 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2537 /* t1 = 000000b0 */ 2538 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2539 2540 /* t3 = hg00000a */ 2541 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2542 /* t2 = 0000abcd */ 2543 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2544 /* t3 = hg0000ba */ 2545 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2546 2547 /* t1 = 000000c0 */ 2548 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2549 /* t2 = 0000000d */ 2550 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2551 /* t1 = 00000c00 */ 2552 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2553 /* t2 = 0000d000 */ 2554 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2555 2556 /* t3 = hg000cba */ 2557 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2558 /* t1 = 00abcdef */ 2559 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2560 /* t3 = hg00dcba */ 2561 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2562 2563 /* t2 = 0000000f */ 2564 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2565 /* t1 = 000000e0 */ 2566 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2567 /* t2 = 00f00000 */ 2568 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2569 /* t1 = 000e0000 */ 2570 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2571 2572 /* t3 = hgf0dcba */ 2573 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2574 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2575 /* t3 = hgfedcba -- delay slot */ 2576 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2577} 2578 2579static void tcg_out_tb_start(TCGContext *s) 2580{ 2581 /* nothing to do */ 2582} 2583 2584static void tcg_target_init(TCGContext *s) 2585{ 2586 tcg_target_detect_isa(); 2587 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2588 if (TCG_TARGET_REG_BITS == 64) { 2589 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2590 } 2591 2592 tcg_target_call_clobber_regs = 0; 2593 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2594 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2595 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2596 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2597 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2598 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2599 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2600 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2601 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2602 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2603 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2604 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2605 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2606 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2607 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2608 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2609 2610 s->reserved_regs = 0; 2611 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2612 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2613 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2614 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2615 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2616 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2617 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2618 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2619 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2620 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2621 if (TCG_TARGET_REG_BITS == 64) { 2622 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2623 } 2624} 2625 2626typedef struct { 2627 DebugFrameHeader h; 2628 uint8_t fde_def_cfa[4]; 2629 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2630} DebugFrame; 2631 2632#define ELF_HOST_MACHINE EM_MIPS 2633/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2634 which is good because they're really quite complicated for MIPS. */ 2635 2636static const DebugFrame debug_frame = { 2637 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2638 .h.cie.id = -1, 2639 .h.cie.version = 1, 2640 .h.cie.code_align = 1, 2641 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2642 .h.cie.return_column = TCG_REG_RA, 2643 2644 /* Total FDE size does not include the "len" member. */ 2645 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2646 2647 .fde_def_cfa = { 2648 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2649 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2650 (FRAME_SIZE >> 7) 2651 }, 2652 .fde_reg_ofs = { 2653 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2654 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2655 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2656 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2657 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2658 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2659 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2660 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2661 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2662 } 2663}; 2664 2665void tcg_register_jit(const void *buf, size_t buf_size) 2666{ 2667 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2668} 2669