1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#ifdef HOST_WORDS_BIGENDIAN 28# define MIPS_BE 1 29#else 30# define MIPS_BE 0 31#endif 32 33#if TCG_TARGET_REG_BITS == 32 34# define LO_OFF (MIPS_BE * 4) 35# define HI_OFF (4 - LO_OFF) 36#else 37/* To assert at compile-time that these values are never used 38 for TCG_TARGET_REG_BITS == 64. */ 39int link_error(void); 40# define LO_OFF link_error() 41# define HI_OFF link_error() 42#endif 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "zero", 47 "at", 48 "v0", 49 "v1", 50 "a0", 51 "a1", 52 "a2", 53 "a3", 54 "t0", 55 "t1", 56 "t2", 57 "t3", 58 "t4", 59 "t5", 60 "t6", 61 "t7", 62 "s0", 63 "s1", 64 "s2", 65 "s3", 66 "s4", 67 "s5", 68 "s6", 69 "s7", 70 "t8", 71 "t9", 72 "k0", 73 "k1", 74 "gp", 75 "sp", 76 "s8", 77 "ra", 78}; 79#endif 80 81#define TCG_TMP0 TCG_REG_AT 82#define TCG_TMP1 TCG_REG_T9 83#define TCG_TMP2 TCG_REG_T8 84#define TCG_TMP3 TCG_REG_T7 85 86#ifndef CONFIG_SOFTMMU 87#define TCG_GUEST_BASE_REG TCG_REG_S1 88#endif 89 90/* check if we really need so many registers :P */ 91static const int tcg_target_reg_alloc_order[] = { 92 /* Call saved registers. */ 93 TCG_REG_S0, 94 TCG_REG_S1, 95 TCG_REG_S2, 96 TCG_REG_S3, 97 TCG_REG_S4, 98 TCG_REG_S5, 99 TCG_REG_S6, 100 TCG_REG_S7, 101 TCG_REG_S8, 102 103 /* Call clobbered registers. */ 104 TCG_REG_T4, 105 TCG_REG_T5, 106 TCG_REG_T6, 107 TCG_REG_T7, 108 TCG_REG_T8, 109 TCG_REG_T9, 110 TCG_REG_V1, 111 TCG_REG_V0, 112 113 /* Argument registers, opposite order of allocation. */ 114 TCG_REG_T3, 115 TCG_REG_T2, 116 TCG_REG_T1, 117 TCG_REG_T0, 118 TCG_REG_A3, 119 TCG_REG_A2, 120 TCG_REG_A1, 121 TCG_REG_A0, 122}; 123 124static const TCGReg tcg_target_call_iarg_regs[] = { 125 TCG_REG_A0, 126 TCG_REG_A1, 127 TCG_REG_A2, 128 TCG_REG_A3, 129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 130 TCG_REG_T0, 131 TCG_REG_T1, 132 TCG_REG_T2, 133 TCG_REG_T3, 134#endif 135}; 136 137static const TCGReg tcg_target_call_oarg_regs[2] = { 138 TCG_REG_V0, 139 TCG_REG_V1 140}; 141 142static const tcg_insn_unit *tb_ret_addr; 143static const tcg_insn_unit *bswap32_addr; 144static const tcg_insn_unit *bswap32u_addr; 145static const tcg_insn_unit *bswap64_addr; 146 147static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 148{ 149 /* Let the compiler perform the right-shift as part of the arithmetic. */ 150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 151 ptrdiff_t disp = target - (src_rx + 1); 152 if (disp == (int16_t)disp) { 153 *src_rw = deposit32(*src_rw, 0, 16, disp); 154 return true; 155 } 156 return false; 157} 158 159static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 160 intptr_t value, intptr_t addend) 161{ 162 tcg_debug_assert(type == R_MIPS_PC16); 163 tcg_debug_assert(addend == 0); 164 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 165} 166 167#define TCG_CT_CONST_ZERO 0x100 168#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 169#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 170#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 171#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 172#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 173 174#define ALL_GENERAL_REGS 0xffffffffu 175#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) 176 177#ifdef CONFIG_SOFTMMU 178#define ALL_QLOAD_REGS \ 179 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) 180#define ALL_QSTORE_REGS \ 181 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ 182 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ 183 : (1 << TCG_REG_A1))) 184#else 185#define ALL_QLOAD_REGS NOA0_REGS 186#define ALL_QSTORE_REGS NOA0_REGS 187#endif 188 189 190static inline bool is_p2m1(tcg_target_long val) 191{ 192 return val && ((val + 1) & val) == 0; 193} 194 195/* test if a constant matches the constraint */ 196static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 197{ 198 if (ct & TCG_CT_CONST) { 199 return 1; 200 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 201 return 1; 202 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 203 return 1; 204 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_P2M1) 209 && use_mips32r2_instructions && is_p2m1(val)) { 210 return 1; 211 } else if ((ct & TCG_CT_CONST_WSZ) 212 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 213 return 1; 214 } 215 return 0; 216} 217 218/* instruction opcodes */ 219typedef enum { 220 OPC_J = 002 << 26, 221 OPC_JAL = 003 << 26, 222 OPC_BEQ = 004 << 26, 223 OPC_BNE = 005 << 26, 224 OPC_BLEZ = 006 << 26, 225 OPC_BGTZ = 007 << 26, 226 OPC_ADDIU = 011 << 26, 227 OPC_SLTI = 012 << 26, 228 OPC_SLTIU = 013 << 26, 229 OPC_ANDI = 014 << 26, 230 OPC_ORI = 015 << 26, 231 OPC_XORI = 016 << 26, 232 OPC_LUI = 017 << 26, 233 OPC_DADDIU = 031 << 26, 234 OPC_LB = 040 << 26, 235 OPC_LH = 041 << 26, 236 OPC_LW = 043 << 26, 237 OPC_LBU = 044 << 26, 238 OPC_LHU = 045 << 26, 239 OPC_LWU = 047 << 26, 240 OPC_SB = 050 << 26, 241 OPC_SH = 051 << 26, 242 OPC_SW = 053 << 26, 243 OPC_LD = 067 << 26, 244 OPC_SD = 077 << 26, 245 246 OPC_SPECIAL = 000 << 26, 247 OPC_SLL = OPC_SPECIAL | 000, 248 OPC_SRL = OPC_SPECIAL | 002, 249 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 250 OPC_SRA = OPC_SPECIAL | 003, 251 OPC_SLLV = OPC_SPECIAL | 004, 252 OPC_SRLV = OPC_SPECIAL | 006, 253 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 254 OPC_SRAV = OPC_SPECIAL | 007, 255 OPC_JR_R5 = OPC_SPECIAL | 010, 256 OPC_JALR = OPC_SPECIAL | 011, 257 OPC_MOVZ = OPC_SPECIAL | 012, 258 OPC_MOVN = OPC_SPECIAL | 013, 259 OPC_SYNC = OPC_SPECIAL | 017, 260 OPC_MFHI = OPC_SPECIAL | 020, 261 OPC_MFLO = OPC_SPECIAL | 022, 262 OPC_DSLLV = OPC_SPECIAL | 024, 263 OPC_DSRLV = OPC_SPECIAL | 026, 264 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 265 OPC_DSRAV = OPC_SPECIAL | 027, 266 OPC_MULT = OPC_SPECIAL | 030, 267 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 268 OPC_MUH = OPC_SPECIAL | 030 | 0300, 269 OPC_MULTU = OPC_SPECIAL | 031, 270 OPC_MULU = OPC_SPECIAL | 031 | 0200, 271 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 272 OPC_DIV = OPC_SPECIAL | 032, 273 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 274 OPC_MOD = OPC_SPECIAL | 032 | 0300, 275 OPC_DIVU = OPC_SPECIAL | 033, 276 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 277 OPC_MODU = OPC_SPECIAL | 033 | 0300, 278 OPC_DMULT = OPC_SPECIAL | 034, 279 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 280 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 281 OPC_DMULTU = OPC_SPECIAL | 035, 282 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 283 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 284 OPC_DDIV = OPC_SPECIAL | 036, 285 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 286 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 287 OPC_DDIVU = OPC_SPECIAL | 037, 288 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 289 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 290 OPC_ADDU = OPC_SPECIAL | 041, 291 OPC_SUBU = OPC_SPECIAL | 043, 292 OPC_AND = OPC_SPECIAL | 044, 293 OPC_OR = OPC_SPECIAL | 045, 294 OPC_XOR = OPC_SPECIAL | 046, 295 OPC_NOR = OPC_SPECIAL | 047, 296 OPC_SLT = OPC_SPECIAL | 052, 297 OPC_SLTU = OPC_SPECIAL | 053, 298 OPC_DADDU = OPC_SPECIAL | 055, 299 OPC_DSUBU = OPC_SPECIAL | 057, 300 OPC_SELEQZ = OPC_SPECIAL | 065, 301 OPC_SELNEZ = OPC_SPECIAL | 067, 302 OPC_DSLL = OPC_SPECIAL | 070, 303 OPC_DSRL = OPC_SPECIAL | 072, 304 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 305 OPC_DSRA = OPC_SPECIAL | 073, 306 OPC_DSLL32 = OPC_SPECIAL | 074, 307 OPC_DSRL32 = OPC_SPECIAL | 076, 308 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 309 OPC_DSRA32 = OPC_SPECIAL | 077, 310 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 311 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 312 313 OPC_REGIMM = 001 << 26, 314 OPC_BLTZ = OPC_REGIMM | (000 << 16), 315 OPC_BGEZ = OPC_REGIMM | (001 << 16), 316 317 OPC_SPECIAL2 = 034 << 26, 318 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 319 OPC_CLZ = OPC_SPECIAL2 | 040, 320 OPC_DCLZ = OPC_SPECIAL2 | 044, 321 322 OPC_SPECIAL3 = 037 << 26, 323 OPC_EXT = OPC_SPECIAL3 | 000, 324 OPC_DEXTM = OPC_SPECIAL3 | 001, 325 OPC_DEXTU = OPC_SPECIAL3 | 002, 326 OPC_DEXT = OPC_SPECIAL3 | 003, 327 OPC_INS = OPC_SPECIAL3 | 004, 328 OPC_DINSM = OPC_SPECIAL3 | 005, 329 OPC_DINSU = OPC_SPECIAL3 | 006, 330 OPC_DINS = OPC_SPECIAL3 | 007, 331 OPC_WSBH = OPC_SPECIAL3 | 00240, 332 OPC_DSBH = OPC_SPECIAL3 | 00244, 333 OPC_DSHD = OPC_SPECIAL3 | 00544, 334 OPC_SEB = OPC_SPECIAL3 | 02040, 335 OPC_SEH = OPC_SPECIAL3 | 03040, 336 337 /* MIPS r6 doesn't have JR, JALR should be used instead */ 338 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 339 340 /* 341 * MIPS r6 replaces MUL with an alternative encoding which is 342 * backwards-compatible at the assembly level. 343 */ 344 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 345 346 /* MIPS r6 introduced names for weaker variants of SYNC. These are 347 backward compatible to previous architecture revisions. */ 348 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 349 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 350 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 351 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 352 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 353 354 /* Aliases for convenience. */ 355 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 356 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 357 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 358 ? OPC_SRL : OPC_DSRL, 359} MIPSInsn; 360 361/* 362 * Type reg 363 */ 364static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 365 TCGReg rd, TCGReg rs, TCGReg rt) 366{ 367 int32_t inst; 368 369 inst = opc; 370 inst |= (rs & 0x1F) << 21; 371 inst |= (rt & 0x1F) << 16; 372 inst |= (rd & 0x1F) << 11; 373 tcg_out32(s, inst); 374} 375 376/* 377 * Type immediate 378 */ 379static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 380 TCGReg rt, TCGReg rs, TCGArg imm) 381{ 382 int32_t inst; 383 384 inst = opc; 385 inst |= (rs & 0x1F) << 21; 386 inst |= (rt & 0x1F) << 16; 387 inst |= (imm & 0xffff); 388 tcg_out32(s, inst); 389} 390 391/* 392 * Type bitfield 393 */ 394static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 395 TCGReg rs, int msb, int lsb) 396{ 397 int32_t inst; 398 399 inst = opc; 400 inst |= (rs & 0x1F) << 21; 401 inst |= (rt & 0x1F) << 16; 402 inst |= (msb & 0x1F) << 11; 403 inst |= (lsb & 0x1F) << 6; 404 tcg_out32(s, inst); 405} 406 407static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 408 MIPSInsn oph, TCGReg rt, TCGReg rs, 409 int msb, int lsb) 410{ 411 if (lsb >= 32) { 412 opc = oph; 413 msb -= 32; 414 lsb -= 32; 415 } else if (msb >= 32) { 416 opc = opm; 417 msb -= 32; 418 } 419 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 420} 421 422/* 423 * Type branch 424 */ 425static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, 426 TCGReg rt, TCGReg rs) 427{ 428 tcg_out_opc_imm(s, opc, rt, rs, 0); 429} 430 431/* 432 * Type sa 433 */ 434static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 435 TCGReg rd, TCGReg rt, TCGArg sa) 436{ 437 int32_t inst; 438 439 inst = opc; 440 inst |= (rt & 0x1F) << 16; 441 inst |= (rd & 0x1F) << 11; 442 inst |= (sa & 0x1F) << 6; 443 tcg_out32(s, inst); 444 445} 446 447static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 448 TCGReg rd, TCGReg rt, TCGArg sa) 449{ 450 int32_t inst; 451 452 inst = (sa & 32 ? opc2 : opc1); 453 inst |= (rt & 0x1F) << 16; 454 inst |= (rd & 0x1F) << 11; 455 inst |= (sa & 0x1F) << 6; 456 tcg_out32(s, inst); 457} 458 459/* 460 * Type jump. 461 * Returns true if the branch was in range and the insn was emitted. 462 */ 463static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 464{ 465 uintptr_t dest = (uintptr_t)target; 466 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 467 int32_t inst; 468 469 /* The pc-region branch happens within the 256MB region of 470 the delay slot (thus the +4). */ 471 if ((from ^ dest) & -(1 << 28)) { 472 return false; 473 } 474 tcg_debug_assert((dest & 3) == 0); 475 476 inst = opc; 477 inst |= (dest >> 2) & 0x3ffffff; 478 tcg_out32(s, inst); 479 return true; 480} 481 482static inline void tcg_out_nop(TCGContext *s) 483{ 484 tcg_out32(s, 0); 485} 486 487static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 488{ 489 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 490} 491 492static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 493{ 494 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 495} 496 497static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 498{ 499 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 500} 501 502static inline bool tcg_out_mov(TCGContext *s, TCGType type, 503 TCGReg ret, TCGReg arg) 504{ 505 /* Simple reg-reg move, optimising out the 'do nothing' case */ 506 if (ret != arg) { 507 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 508 } 509 return true; 510} 511 512static void tcg_out_movi(TCGContext *s, TCGType type, 513 TCGReg ret, tcg_target_long arg) 514{ 515 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 516 arg = (int32_t)arg; 517 } 518 if (arg == (int16_t)arg) { 519 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 520 return; 521 } 522 if (arg == (uint16_t)arg) { 523 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 524 return; 525 } 526 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 527 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 528 } else { 529 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 530 if (arg & 0xffff0000ull) { 531 tcg_out_dsll(s, ret, ret, 16); 532 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 533 tcg_out_dsll(s, ret, ret, 16); 534 } else { 535 tcg_out_dsll(s, ret, ret, 32); 536 } 537 } 538 if (arg & 0xffff) { 539 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 540 } 541} 542 543static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) 544{ 545 if (use_mips32r2_instructions) { 546 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 547 } else { 548 /* ret and arg can't be register at */ 549 if (ret == TCG_TMP0 || arg == TCG_TMP0) { 550 tcg_abort(); 551 } 552 553 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); 554 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); 555 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); 556 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); 557 } 558} 559 560static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) 561{ 562 if (use_mips32r2_instructions) { 563 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 564 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); 565 } else { 566 /* ret and arg can't be register at */ 567 if (ret == TCG_TMP0 || arg == TCG_TMP0) { 568 tcg_abort(); 569 } 570 571 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); 572 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 573 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 574 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); 575 } 576} 577 578static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 579{ 580 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); 581 tcg_debug_assert(ok); 582} 583 584static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) 585{ 586 if (use_mips32r2_instructions) { 587 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 588 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 589 } else { 590 tcg_out_bswap_subr(s, bswap32_addr); 591 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 592 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 593 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 594 } 595} 596 597static void tcg_out_bswap32u(TCGContext *s, TCGReg ret, TCGReg arg) 598{ 599 if (use_mips32r2_instructions) { 600 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 601 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 602 tcg_out_dsrl(s, ret, ret, 32); 603 } else { 604 tcg_out_bswap_subr(s, bswap32u_addr); 605 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 606 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 607 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 608 } 609} 610 611static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 612{ 613 if (use_mips32r2_instructions) { 614 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 615 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 616 } else { 617 tcg_out_bswap_subr(s, bswap64_addr); 618 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 619 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 620 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 621 } 622} 623 624static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) 625{ 626 if (use_mips32r2_instructions) { 627 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); 628 } else { 629 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 630 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); 631 } 632} 633 634static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) 635{ 636 if (use_mips32r2_instructions) { 637 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); 638 } else { 639 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); 640 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 641 } 642} 643 644static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 645{ 646 if (use_mips32r2_instructions) { 647 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 648 } else { 649 tcg_out_dsll(s, ret, arg, 32); 650 tcg_out_dsrl(s, ret, ret, 32); 651 } 652} 653 654static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 655 TCGReg addr, intptr_t ofs) 656{ 657 int16_t lo = ofs; 658 if (ofs != lo) { 659 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 660 if (addr != TCG_REG_ZERO) { 661 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 662 } 663 addr = TCG_TMP0; 664 } 665 tcg_out_opc_imm(s, opc, data, addr, lo); 666} 667 668static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 669 TCGReg arg1, intptr_t arg2) 670{ 671 MIPSInsn opc = OPC_LD; 672 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 673 opc = OPC_LW; 674 } 675 tcg_out_ldst(s, opc, arg, arg1, arg2); 676} 677 678static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 679 TCGReg arg1, intptr_t arg2) 680{ 681 MIPSInsn opc = OPC_SD; 682 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 683 opc = OPC_SW; 684 } 685 tcg_out_ldst(s, opc, arg, arg1, arg2); 686} 687 688static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 689 TCGReg base, intptr_t ofs) 690{ 691 if (val == 0) { 692 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 693 return true; 694 } 695 return false; 696} 697 698static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 699 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 700 bool cbh, bool is_sub) 701{ 702 TCGReg th = TCG_TMP1; 703 704 /* If we have a negative constant such that negating it would 705 make the high part zero, we can (usually) eliminate one insn. */ 706 if (cbl && cbh && bh == -1 && bl != 0) { 707 bl = -bl; 708 bh = 0; 709 is_sub = !is_sub; 710 } 711 712 /* By operating on the high part first, we get to use the final 713 carry operation to move back from the temporary. */ 714 if (!cbh) { 715 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 716 } else if (bh != 0 || ah == rl) { 717 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 718 } else { 719 th = ah; 720 } 721 722 /* Note that tcg optimization should eliminate the bl == 0 case. */ 723 if (is_sub) { 724 if (cbl) { 725 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 726 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 727 } else { 728 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 729 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 730 } 731 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 732 } else { 733 if (cbl) { 734 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 735 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 736 } else if (rl == al && rl == bl) { 737 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 738 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 739 } else { 740 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 741 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 742 } 743 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 744 } 745} 746 747/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 748#define MIPS_CMP_INV 1 749#define MIPS_CMP_SWAP 2 750 751static const uint8_t mips_cmp_map[16] = { 752 [TCG_COND_LT] = 0, 753 [TCG_COND_LTU] = 0, 754 [TCG_COND_GE] = MIPS_CMP_INV, 755 [TCG_COND_GEU] = MIPS_CMP_INV, 756 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 757 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 758 [TCG_COND_GT] = MIPS_CMP_SWAP, 759 [TCG_COND_GTU] = MIPS_CMP_SWAP, 760}; 761 762static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 763 TCGReg arg1, TCGReg arg2) 764{ 765 MIPSInsn s_opc = OPC_SLTU; 766 int cmp_map; 767 768 switch (cond) { 769 case TCG_COND_EQ: 770 if (arg2 != 0) { 771 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 772 arg1 = ret; 773 } 774 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 775 break; 776 777 case TCG_COND_NE: 778 if (arg2 != 0) { 779 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 780 arg1 = ret; 781 } 782 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 783 break; 784 785 case TCG_COND_LT: 786 case TCG_COND_GE: 787 case TCG_COND_LE: 788 case TCG_COND_GT: 789 s_opc = OPC_SLT; 790 /* FALLTHRU */ 791 792 case TCG_COND_LTU: 793 case TCG_COND_GEU: 794 case TCG_COND_LEU: 795 case TCG_COND_GTU: 796 cmp_map = mips_cmp_map[cond]; 797 if (cmp_map & MIPS_CMP_SWAP) { 798 TCGReg t = arg1; 799 arg1 = arg2; 800 arg2 = t; 801 } 802 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 803 if (cmp_map & MIPS_CMP_INV) { 804 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 805 } 806 break; 807 808 default: 809 tcg_abort(); 810 break; 811 } 812} 813 814static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 815 TCGReg arg2, TCGLabel *l) 816{ 817 static const MIPSInsn b_zero[16] = { 818 [TCG_COND_LT] = OPC_BLTZ, 819 [TCG_COND_GT] = OPC_BGTZ, 820 [TCG_COND_LE] = OPC_BLEZ, 821 [TCG_COND_GE] = OPC_BGEZ, 822 }; 823 824 MIPSInsn s_opc = OPC_SLTU; 825 MIPSInsn b_opc; 826 int cmp_map; 827 828 switch (cond) { 829 case TCG_COND_EQ: 830 b_opc = OPC_BEQ; 831 break; 832 case TCG_COND_NE: 833 b_opc = OPC_BNE; 834 break; 835 836 case TCG_COND_LT: 837 case TCG_COND_GT: 838 case TCG_COND_LE: 839 case TCG_COND_GE: 840 if (arg2 == 0) { 841 b_opc = b_zero[cond]; 842 arg2 = arg1; 843 arg1 = 0; 844 break; 845 } 846 s_opc = OPC_SLT; 847 /* FALLTHRU */ 848 849 case TCG_COND_LTU: 850 case TCG_COND_GTU: 851 case TCG_COND_LEU: 852 case TCG_COND_GEU: 853 cmp_map = mips_cmp_map[cond]; 854 if (cmp_map & MIPS_CMP_SWAP) { 855 TCGReg t = arg1; 856 arg1 = arg2; 857 arg2 = t; 858 } 859 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 860 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 861 arg1 = TCG_TMP0; 862 arg2 = TCG_REG_ZERO; 863 break; 864 865 default: 866 tcg_abort(); 867 break; 868 } 869 870 tcg_out_opc_br(s, b_opc, arg1, arg2); 871 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 872 tcg_out_nop(s); 873} 874 875static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 876 TCGReg al, TCGReg ah, 877 TCGReg bl, TCGReg bh) 878{ 879 /* Merge highpart comparison into AH. */ 880 if (bh != 0) { 881 if (ah != 0) { 882 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 883 ah = tmp0; 884 } else { 885 ah = bh; 886 } 887 } 888 /* Merge lowpart comparison into AL. */ 889 if (bl != 0) { 890 if (al != 0) { 891 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 892 al = tmp1; 893 } else { 894 al = bl; 895 } 896 } 897 /* Merge high and low part comparisons into AL. */ 898 if (ah != 0) { 899 if (al != 0) { 900 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 901 al = tmp0; 902 } else { 903 al = ah; 904 } 905 } 906 return al; 907} 908 909static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 910 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 911{ 912 TCGReg tmp0 = TCG_TMP0; 913 TCGReg tmp1 = ret; 914 915 tcg_debug_assert(ret != TCG_TMP0); 916 if (ret == ah || ret == bh) { 917 tcg_debug_assert(ret != TCG_TMP1); 918 tmp1 = TCG_TMP1; 919 } 920 921 switch (cond) { 922 case TCG_COND_EQ: 923 case TCG_COND_NE: 924 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 925 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 926 break; 927 928 default: 929 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 930 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 931 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 932 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 933 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 934 break; 935 } 936} 937 938static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 939 TCGReg bl, TCGReg bh, TCGLabel *l) 940{ 941 TCGCond b_cond = TCG_COND_NE; 942 TCGReg tmp = TCG_TMP1; 943 944 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 945 With setcond, we emit between 3 and 10 insns and only 1 branch, 946 which ought to get better branch prediction. */ 947 switch (cond) { 948 case TCG_COND_EQ: 949 case TCG_COND_NE: 950 b_cond = cond; 951 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 952 break; 953 954 default: 955 /* Minimize code size by preferring a compare not requiring INV. */ 956 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 957 cond = tcg_invert_cond(cond); 958 b_cond = TCG_COND_EQ; 959 } 960 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 961 break; 962 } 963 964 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 965} 966 967static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 968 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 969{ 970 bool eqz = false; 971 972 /* If one of the values is zero, put it last to match SEL*Z instructions */ 973 if (use_mips32r6_instructions && v1 == 0) { 974 v1 = v2; 975 v2 = 0; 976 cond = tcg_invert_cond(cond); 977 } 978 979 switch (cond) { 980 case TCG_COND_EQ: 981 eqz = true; 982 /* FALLTHRU */ 983 case TCG_COND_NE: 984 if (c2 != 0) { 985 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 986 c1 = TCG_TMP0; 987 } 988 break; 989 990 default: 991 /* Minimize code size by preferring a compare not requiring INV. */ 992 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 993 cond = tcg_invert_cond(cond); 994 eqz = true; 995 } 996 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 997 c1 = TCG_TMP0; 998 break; 999 } 1000 1001 if (use_mips32r6_instructions) { 1002 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1003 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1004 1005 if (v2 != 0) { 1006 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1007 } 1008 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1009 if (v2 != 0) { 1010 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1011 } 1012 } else { 1013 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1014 1015 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1016 1017 /* This should be guaranteed via constraints */ 1018 tcg_debug_assert(v2 == ret); 1019 } 1020} 1021 1022static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1023{ 1024 /* Note that the ABI requires the called function's address to be 1025 loaded into T9, even if a direct branch is in range. */ 1026 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1027 1028 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1029 if (tail) { 1030 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1031 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1032 } 1033 } else { 1034 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1035 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1036 } 1037 } 1038} 1039 1040static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) 1041{ 1042 tcg_out_call_int(s, arg, false); 1043 tcg_out_nop(s); 1044} 1045 1046#if defined(CONFIG_SOFTMMU) 1047#include "../tcg-ldst.c.inc" 1048 1049static void * const qemu_ld_helpers[16] = { 1050 [MO_UB] = helper_ret_ldub_mmu, 1051 [MO_SB] = helper_ret_ldsb_mmu, 1052 [MO_LEUW] = helper_le_lduw_mmu, 1053 [MO_LESW] = helper_le_ldsw_mmu, 1054 [MO_LEUL] = helper_le_ldul_mmu, 1055 [MO_LEQ] = helper_le_ldq_mmu, 1056 [MO_BEUW] = helper_be_lduw_mmu, 1057 [MO_BESW] = helper_be_ldsw_mmu, 1058 [MO_BEUL] = helper_be_ldul_mmu, 1059 [MO_BEQ] = helper_be_ldq_mmu, 1060#if TCG_TARGET_REG_BITS == 64 1061 [MO_LESL] = helper_le_ldsl_mmu, 1062 [MO_BESL] = helper_be_ldsl_mmu, 1063#endif 1064}; 1065 1066static void * const qemu_st_helpers[16] = { 1067 [MO_UB] = helper_ret_stb_mmu, 1068 [MO_LEUW] = helper_le_stw_mmu, 1069 [MO_LEUL] = helper_le_stl_mmu, 1070 [MO_LEQ] = helper_le_stq_mmu, 1071 [MO_BEUW] = helper_be_stw_mmu, 1072 [MO_BEUL] = helper_be_stl_mmu, 1073 [MO_BEQ] = helper_be_stq_mmu, 1074}; 1075 1076/* Helper routines for marshalling helper function arguments into 1077 * the correct registers and stack. 1078 * I is where we want to put this argument, and is updated and returned 1079 * for the next call. ARG is the argument itself. 1080 * 1081 * We provide routines for arguments which are: immediate, 32 bit 1082 * value in register, 16 and 8 bit values in register (which must be zero 1083 * extended before use) and 64 bit value in a lo:hi register pair. 1084 */ 1085 1086static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) 1087{ 1088 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1089 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); 1090 } else { 1091 /* For N32 and N64, the initial offset is different. But there 1092 we also have 8 argument register so we don't run out here. */ 1093 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1094 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); 1095 } 1096 return i + 1; 1097} 1098 1099static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) 1100{ 1101 TCGReg tmp = TCG_TMP0; 1102 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1103 tmp = tcg_target_call_iarg_regs[i]; 1104 } 1105 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); 1106 return tcg_out_call_iarg_reg(s, i, tmp); 1107} 1108 1109static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) 1110{ 1111 TCGReg tmp = TCG_TMP0; 1112 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1113 tmp = tcg_target_call_iarg_regs[i]; 1114 } 1115 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); 1116 return tcg_out_call_iarg_reg(s, i, tmp); 1117} 1118 1119static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) 1120{ 1121 TCGReg tmp = TCG_TMP0; 1122 if (arg == 0) { 1123 tmp = TCG_REG_ZERO; 1124 } else { 1125 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1126 tmp = tcg_target_call_iarg_regs[i]; 1127 } 1128 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); 1129 } 1130 return tcg_out_call_iarg_reg(s, i, tmp); 1131} 1132 1133static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) 1134{ 1135 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1136 i = (i + 1) & ~1; 1137 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); 1138 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); 1139 return i; 1140} 1141 1142/* We expect to use a 16-bit negative offset from ENV. */ 1143QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1144QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1145 1146/* 1147 * Perform the tlb comparison operation. 1148 * The complete host address is placed in BASE. 1149 * Clobbers TMP0, TMP1, TMP2, TMP3. 1150 */ 1151static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, 1152 TCGReg addrh, TCGMemOpIdx oi, 1153 tcg_insn_unit *label_ptr[2], bool is_load) 1154{ 1155 MemOp opc = get_memop(oi); 1156 unsigned s_bits = opc & MO_SIZE; 1157 unsigned a_bits = get_alignment_bits(opc); 1158 int mem_index = get_mmuidx(oi); 1159 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1160 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1161 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1162 int add_off = offsetof(CPUTLBEntry, addend); 1163 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) 1164 : offsetof(CPUTLBEntry, addr_write)); 1165 target_ulong mask; 1166 1167 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1168 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1169 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1170 1171 /* Extract the TLB index from the address into TMP3. */ 1172 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, 1173 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1174 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1175 1176 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1177 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1178 1179 /* We don't currently support unaligned accesses. 1180 We could do so with mips32r6. */ 1181 if (a_bits < s_bits) { 1182 a_bits = s_bits; 1183 } 1184 1185 /* Mask the page bits, keeping the alignment bits to compare against. */ 1186 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 1187 1188 /* Load the (low-half) tlb comparator. */ 1189 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1190 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1191 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); 1192 } else { 1193 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD 1194 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), 1195 TCG_TMP0, TCG_TMP3, cmp_off); 1196 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); 1197 /* No second compare is required here; 1198 load the tlb addend for the fast path. */ 1199 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1200 } 1201 1202 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1203 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1204 tcg_out_ext32u(s, base, addrl); 1205 addrl = base; 1206 } 1207 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); 1208 1209 label_ptr[0] = s->code_ptr; 1210 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1211 1212 /* Load and test the high half tlb comparator. */ 1213 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1214 /* delay slot */ 1215 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1216 1217 /* Load the tlb addend for the fast path. */ 1218 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1219 1220 label_ptr[1] = s->code_ptr; 1221 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); 1222 } 1223 1224 /* delay slot */ 1225 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); 1226} 1227 1228static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, 1229 TCGType ext, 1230 TCGReg datalo, TCGReg datahi, 1231 TCGReg addrlo, TCGReg addrhi, 1232 void *raddr, tcg_insn_unit *label_ptr[2]) 1233{ 1234 TCGLabelQemuLdst *label = new_ldst_label(s); 1235 1236 label->is_ld = is_ld; 1237 label->oi = oi; 1238 label->type = ext; 1239 label->datalo_reg = datalo; 1240 label->datahi_reg = datahi; 1241 label->addrlo_reg = addrlo; 1242 label->addrhi_reg = addrhi; 1243 label->raddr = tcg_splitwx_to_rx(raddr); 1244 label->label_ptr[0] = label_ptr[0]; 1245 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1246 label->label_ptr[1] = label_ptr[1]; 1247 } 1248} 1249 1250static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1251{ 1252 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1253 TCGMemOpIdx oi = l->oi; 1254 MemOp opc = get_memop(oi); 1255 TCGReg v0; 1256 int i; 1257 1258 /* resolve label address */ 1259 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1260 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1261 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1262 return false; 1263 } 1264 1265 i = 1; 1266 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1267 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1268 } else { 1269 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1270 } 1271 i = tcg_out_call_iarg_imm(s, i, oi); 1272 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); 1273 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); 1274 /* delay slot */ 1275 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1276 1277 v0 = l->datalo_reg; 1278 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 1279 /* We eliminated V0 from the possible output registers, so it 1280 cannot be clobbered here. So we must move V1 first. */ 1281 if (MIPS_BE) { 1282 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); 1283 v0 = l->datahi_reg; 1284 } else { 1285 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); 1286 } 1287 } 1288 1289 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1290 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1291 return false; 1292 } 1293 1294 /* delay slot */ 1295 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { 1296 /* we always sign-extend 32-bit loads */ 1297 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); 1298 } else { 1299 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); 1300 } 1301 return true; 1302} 1303 1304static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1305{ 1306 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1307 TCGMemOpIdx oi = l->oi; 1308 MemOp opc = get_memop(oi); 1309 MemOp s_bits = opc & MO_SIZE; 1310 int i; 1311 1312 /* resolve label address */ 1313 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1314 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1315 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1316 return false; 1317 } 1318 1319 i = 1; 1320 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1321 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1322 } else { 1323 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1324 } 1325 switch (s_bits) { 1326 case MO_8: 1327 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); 1328 break; 1329 case MO_16: 1330 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); 1331 break; 1332 case MO_32: 1333 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1334 break; 1335 case MO_64: 1336 if (TCG_TARGET_REG_BITS == 32) { 1337 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); 1338 } else { 1339 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1340 } 1341 break; 1342 default: 1343 tcg_abort(); 1344 } 1345 i = tcg_out_call_iarg_imm(s, i, oi); 1346 1347 /* Tail call to the store helper. Thus force the return address 1348 computation to take place in the return address register. */ 1349 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); 1350 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); 1351 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); 1352 /* delay slot */ 1353 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1354 return true; 1355} 1356#endif 1357 1358static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1359 TCGReg base, MemOp opc, bool is_64) 1360{ 1361 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1362 case MO_UB: 1363 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1364 break; 1365 case MO_SB: 1366 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1367 break; 1368 case MO_UW | MO_BSWAP: 1369 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1370 tcg_out_bswap16(s, lo, TCG_TMP1); 1371 break; 1372 case MO_UW: 1373 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1374 break; 1375 case MO_SW | MO_BSWAP: 1376 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1377 tcg_out_bswap16s(s, lo, TCG_TMP1); 1378 break; 1379 case MO_SW: 1380 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1381 break; 1382 case MO_UL | MO_BSWAP: 1383 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1384 if (use_mips32r2_instructions) { 1385 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1386 tcg_out_bswap32u(s, lo, lo); 1387 } else { 1388 tcg_out_bswap_subr(s, bswap32u_addr); 1389 /* delay slot */ 1390 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); 1391 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1392 } 1393 break; 1394 } 1395 /* FALLTHRU */ 1396 case MO_SL | MO_BSWAP: 1397 if (use_mips32r2_instructions) { 1398 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1399 tcg_out_bswap32(s, lo, lo); 1400 } else { 1401 tcg_out_bswap_subr(s, bswap32_addr); 1402 /* delay slot */ 1403 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1404 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); 1405 } 1406 break; 1407 case MO_UL: 1408 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1409 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1410 break; 1411 } 1412 /* FALLTHRU */ 1413 case MO_SL: 1414 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1415 break; 1416 case MO_Q | MO_BSWAP: 1417 if (TCG_TARGET_REG_BITS == 64) { 1418 if (use_mips32r2_instructions) { 1419 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1420 tcg_out_bswap64(s, lo, lo); 1421 } else { 1422 tcg_out_bswap_subr(s, bswap64_addr); 1423 /* delay slot */ 1424 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); 1425 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1426 } 1427 } else if (use_mips32r2_instructions) { 1428 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1429 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); 1430 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1431 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1432 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1433 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1434 } else { 1435 tcg_out_bswap_subr(s, bswap32_addr); 1436 /* delay slot */ 1437 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1438 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); 1439 tcg_out_bswap_subr(s, bswap32_addr); 1440 /* delay slot */ 1441 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1442 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1443 } 1444 break; 1445 case MO_Q: 1446 /* Prefer to load from offset 0 first, but allow for overlap. */ 1447 if (TCG_TARGET_REG_BITS == 64) { 1448 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1449 } else if (MIPS_BE ? hi != base : lo == base) { 1450 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1451 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1452 } else { 1453 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1454 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1455 } 1456 break; 1457 default: 1458 tcg_abort(); 1459 } 1460} 1461 1462static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1463{ 1464 TCGReg addr_regl, addr_regh __attribute__((unused)); 1465 TCGReg data_regl, data_regh; 1466 TCGMemOpIdx oi; 1467 MemOp opc; 1468#if defined(CONFIG_SOFTMMU) 1469 tcg_insn_unit *label_ptr[2]; 1470#endif 1471 TCGReg base = TCG_REG_A0; 1472 1473 data_regl = *args++; 1474 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1475 addr_regl = *args++; 1476 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1477 oi = *args++; 1478 opc = get_memop(oi); 1479 1480#if defined(CONFIG_SOFTMMU) 1481 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); 1482 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1483 add_qemu_ldst_label(s, 1, oi, 1484 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1485 data_regl, data_regh, addr_regl, addr_regh, 1486 s->code_ptr, label_ptr); 1487#else 1488 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1489 tcg_out_ext32u(s, base, addr_regl); 1490 addr_regl = base; 1491 } 1492 if (guest_base == 0 && data_regl != addr_regl) { 1493 base = addr_regl; 1494 } else if (guest_base == (int16_t)guest_base) { 1495 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1496 } else { 1497 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1498 } 1499 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1500#endif 1501} 1502 1503static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1504 TCGReg base, MemOp opc) 1505{ 1506 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1507 if ((lo | hi) == 0) { 1508 opc &= ~MO_BSWAP; 1509 } 1510 1511 switch (opc & (MO_SIZE | MO_BSWAP)) { 1512 case MO_8: 1513 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1514 break; 1515 1516 case MO_16 | MO_BSWAP: 1517 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, lo, 0xffff); 1518 tcg_out_bswap16(s, TCG_TMP1, TCG_TMP1); 1519 lo = TCG_TMP1; 1520 /* FALLTHRU */ 1521 case MO_16: 1522 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1523 break; 1524 1525 case MO_32 | MO_BSWAP: 1526 tcg_out_bswap32(s, TCG_TMP3, lo); 1527 lo = TCG_TMP3; 1528 /* FALLTHRU */ 1529 case MO_32: 1530 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1531 break; 1532 1533 case MO_64 | MO_BSWAP: 1534 if (TCG_TARGET_REG_BITS == 64) { 1535 tcg_out_bswap64(s, TCG_TMP3, lo); 1536 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); 1537 } else if (use_mips32r2_instructions) { 1538 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); 1539 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); 1540 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1541 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1542 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); 1543 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); 1544 } else { 1545 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi); 1546 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); 1547 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo); 1548 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); 1549 } 1550 break; 1551 case MO_64: 1552 if (TCG_TARGET_REG_BITS == 64) { 1553 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1554 } else { 1555 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1556 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1557 } 1558 break; 1559 1560 default: 1561 tcg_abort(); 1562 } 1563} 1564 1565static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1566{ 1567 TCGReg addr_regl, addr_regh __attribute__((unused)); 1568 TCGReg data_regl, data_regh; 1569 TCGMemOpIdx oi; 1570 MemOp opc; 1571#if defined(CONFIG_SOFTMMU) 1572 tcg_insn_unit *label_ptr[2]; 1573#endif 1574 TCGReg base = TCG_REG_A0; 1575 1576 data_regl = *args++; 1577 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1578 addr_regl = *args++; 1579 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1580 oi = *args++; 1581 opc = get_memop(oi); 1582 1583#if defined(CONFIG_SOFTMMU) 1584 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); 1585 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1586 add_qemu_ldst_label(s, 0, oi, 1587 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1588 data_regl, data_regh, addr_regl, addr_regh, 1589 s->code_ptr, label_ptr); 1590#else 1591 base = TCG_REG_A0; 1592 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1593 tcg_out_ext32u(s, base, addr_regl); 1594 addr_regl = base; 1595 } 1596 if (guest_base == 0) { 1597 base = addr_regl; 1598 } else if (guest_base == (int16_t)guest_base) { 1599 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1600 } else { 1601 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1602 } 1603 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1604#endif 1605} 1606 1607static void tcg_out_mb(TCGContext *s, TCGArg a0) 1608{ 1609 static const MIPSInsn sync[] = { 1610 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1611 as the former is an ordering barrier and the latter 1612 is a completion barrier. */ 1613 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1614 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1615 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1616 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1617 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1618 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1619 }; 1620 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1621} 1622 1623static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1624 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1625{ 1626 if (use_mips32r6_instructions) { 1627 if (a2 == width) { 1628 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1629 } else { 1630 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1631 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1632 } 1633 } else { 1634 if (a2 == width) { 1635 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1636 } else if (a0 == a2) { 1637 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1638 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1639 } else if (a0 != a1) { 1640 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1641 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1642 } else { 1643 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1644 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1645 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1646 } 1647 } 1648} 1649 1650static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 1651 const TCGArg args[TCG_MAX_OP_ARGS], 1652 const int const_args[TCG_MAX_OP_ARGS]) 1653{ 1654 MIPSInsn i1, i2; 1655 TCGArg a0, a1, a2; 1656 int c2; 1657 1658 /* 1659 * Note that many operands use the constraint set "rZ". 1660 * We make use of the fact that 0 is the ZERO register, 1661 * and hence such cases need not check for const_args. 1662 */ 1663 a0 = args[0]; 1664 a1 = args[1]; 1665 a2 = args[2]; 1666 c2 = const_args[2]; 1667 1668 switch (opc) { 1669 case INDEX_op_exit_tb: 1670 { 1671 TCGReg b0 = TCG_REG_ZERO; 1672 1673 a0 = (intptr_t)a0; 1674 if (a0 & ~0xffff) { 1675 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 1676 b0 = TCG_REG_V0; 1677 } 1678 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1679 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, 1680 (uintptr_t)tb_ret_addr); 1681 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1682 } 1683 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 1684 } 1685 break; 1686 case INDEX_op_goto_tb: 1687 if (s->tb_jmp_insn_offset) { 1688 /* direct jump method */ 1689 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); 1690 /* Avoid clobbering the address during retranslation. */ 1691 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); 1692 } else { 1693 /* indirect jump method */ 1694 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 1695 (uintptr_t)(s->tb_jmp_target_addr + a0)); 1696 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1697 } 1698 tcg_out_nop(s); 1699 set_jmp_reset_offset(s, a0); 1700 break; 1701 case INDEX_op_goto_ptr: 1702 /* jmp to the given host address (could be epilogue) */ 1703 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1704 tcg_out_nop(s); 1705 break; 1706 case INDEX_op_br: 1707 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1708 arg_label(a0)); 1709 break; 1710 1711 case INDEX_op_ld8u_i32: 1712 case INDEX_op_ld8u_i64: 1713 i1 = OPC_LBU; 1714 goto do_ldst; 1715 case INDEX_op_ld8s_i32: 1716 case INDEX_op_ld8s_i64: 1717 i1 = OPC_LB; 1718 goto do_ldst; 1719 case INDEX_op_ld16u_i32: 1720 case INDEX_op_ld16u_i64: 1721 i1 = OPC_LHU; 1722 goto do_ldst; 1723 case INDEX_op_ld16s_i32: 1724 case INDEX_op_ld16s_i64: 1725 i1 = OPC_LH; 1726 goto do_ldst; 1727 case INDEX_op_ld_i32: 1728 case INDEX_op_ld32s_i64: 1729 i1 = OPC_LW; 1730 goto do_ldst; 1731 case INDEX_op_ld32u_i64: 1732 i1 = OPC_LWU; 1733 goto do_ldst; 1734 case INDEX_op_ld_i64: 1735 i1 = OPC_LD; 1736 goto do_ldst; 1737 case INDEX_op_st8_i32: 1738 case INDEX_op_st8_i64: 1739 i1 = OPC_SB; 1740 goto do_ldst; 1741 case INDEX_op_st16_i32: 1742 case INDEX_op_st16_i64: 1743 i1 = OPC_SH; 1744 goto do_ldst; 1745 case INDEX_op_st_i32: 1746 case INDEX_op_st32_i64: 1747 i1 = OPC_SW; 1748 goto do_ldst; 1749 case INDEX_op_st_i64: 1750 i1 = OPC_SD; 1751 do_ldst: 1752 tcg_out_ldst(s, i1, a0, a1, a2); 1753 break; 1754 1755 case INDEX_op_add_i32: 1756 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1757 goto do_binary; 1758 case INDEX_op_add_i64: 1759 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1760 goto do_binary; 1761 case INDEX_op_or_i32: 1762 case INDEX_op_or_i64: 1763 i1 = OPC_OR, i2 = OPC_ORI; 1764 goto do_binary; 1765 case INDEX_op_xor_i32: 1766 case INDEX_op_xor_i64: 1767 i1 = OPC_XOR, i2 = OPC_XORI; 1768 do_binary: 1769 if (c2) { 1770 tcg_out_opc_imm(s, i2, a0, a1, a2); 1771 break; 1772 } 1773 do_binaryv: 1774 tcg_out_opc_reg(s, i1, a0, a1, a2); 1775 break; 1776 1777 case INDEX_op_sub_i32: 1778 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1779 goto do_subtract; 1780 case INDEX_op_sub_i64: 1781 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1782 do_subtract: 1783 if (c2) { 1784 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1785 break; 1786 } 1787 goto do_binaryv; 1788 case INDEX_op_and_i32: 1789 if (c2 && a2 != (uint16_t)a2) { 1790 int msb = ctz32(~a2) - 1; 1791 tcg_debug_assert(use_mips32r2_instructions); 1792 tcg_debug_assert(is_p2m1(a2)); 1793 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1794 break; 1795 } 1796 i1 = OPC_AND, i2 = OPC_ANDI; 1797 goto do_binary; 1798 case INDEX_op_and_i64: 1799 if (c2 && a2 != (uint16_t)a2) { 1800 int msb = ctz64(~a2) - 1; 1801 tcg_debug_assert(use_mips32r2_instructions); 1802 tcg_debug_assert(is_p2m1(a2)); 1803 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1804 break; 1805 } 1806 i1 = OPC_AND, i2 = OPC_ANDI; 1807 goto do_binary; 1808 case INDEX_op_nor_i32: 1809 case INDEX_op_nor_i64: 1810 i1 = OPC_NOR; 1811 goto do_binaryv; 1812 1813 case INDEX_op_mul_i32: 1814 if (use_mips32_instructions) { 1815 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1816 break; 1817 } 1818 i1 = OPC_MULT, i2 = OPC_MFLO; 1819 goto do_hilo1; 1820 case INDEX_op_mulsh_i32: 1821 if (use_mips32r6_instructions) { 1822 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1823 break; 1824 } 1825 i1 = OPC_MULT, i2 = OPC_MFHI; 1826 goto do_hilo1; 1827 case INDEX_op_muluh_i32: 1828 if (use_mips32r6_instructions) { 1829 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1830 break; 1831 } 1832 i1 = OPC_MULTU, i2 = OPC_MFHI; 1833 goto do_hilo1; 1834 case INDEX_op_div_i32: 1835 if (use_mips32r6_instructions) { 1836 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1837 break; 1838 } 1839 i1 = OPC_DIV, i2 = OPC_MFLO; 1840 goto do_hilo1; 1841 case INDEX_op_divu_i32: 1842 if (use_mips32r6_instructions) { 1843 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1844 break; 1845 } 1846 i1 = OPC_DIVU, i2 = OPC_MFLO; 1847 goto do_hilo1; 1848 case INDEX_op_rem_i32: 1849 if (use_mips32r6_instructions) { 1850 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1851 break; 1852 } 1853 i1 = OPC_DIV, i2 = OPC_MFHI; 1854 goto do_hilo1; 1855 case INDEX_op_remu_i32: 1856 if (use_mips32r6_instructions) { 1857 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1858 break; 1859 } 1860 i1 = OPC_DIVU, i2 = OPC_MFHI; 1861 goto do_hilo1; 1862 case INDEX_op_mul_i64: 1863 if (use_mips32r6_instructions) { 1864 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1865 break; 1866 } 1867 i1 = OPC_DMULT, i2 = OPC_MFLO; 1868 goto do_hilo1; 1869 case INDEX_op_mulsh_i64: 1870 if (use_mips32r6_instructions) { 1871 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1872 break; 1873 } 1874 i1 = OPC_DMULT, i2 = OPC_MFHI; 1875 goto do_hilo1; 1876 case INDEX_op_muluh_i64: 1877 if (use_mips32r6_instructions) { 1878 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1879 break; 1880 } 1881 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1882 goto do_hilo1; 1883 case INDEX_op_div_i64: 1884 if (use_mips32r6_instructions) { 1885 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1886 break; 1887 } 1888 i1 = OPC_DDIV, i2 = OPC_MFLO; 1889 goto do_hilo1; 1890 case INDEX_op_divu_i64: 1891 if (use_mips32r6_instructions) { 1892 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1893 break; 1894 } 1895 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1896 goto do_hilo1; 1897 case INDEX_op_rem_i64: 1898 if (use_mips32r6_instructions) { 1899 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1900 break; 1901 } 1902 i1 = OPC_DDIV, i2 = OPC_MFHI; 1903 goto do_hilo1; 1904 case INDEX_op_remu_i64: 1905 if (use_mips32r6_instructions) { 1906 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1907 break; 1908 } 1909 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1910 do_hilo1: 1911 tcg_out_opc_reg(s, i1, 0, a1, a2); 1912 tcg_out_opc_reg(s, i2, a0, 0, 0); 1913 break; 1914 1915 case INDEX_op_muls2_i32: 1916 i1 = OPC_MULT; 1917 goto do_hilo2; 1918 case INDEX_op_mulu2_i32: 1919 i1 = OPC_MULTU; 1920 goto do_hilo2; 1921 case INDEX_op_muls2_i64: 1922 i1 = OPC_DMULT; 1923 goto do_hilo2; 1924 case INDEX_op_mulu2_i64: 1925 i1 = OPC_DMULTU; 1926 do_hilo2: 1927 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1928 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1929 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1930 break; 1931 1932 case INDEX_op_not_i32: 1933 case INDEX_op_not_i64: 1934 i1 = OPC_NOR; 1935 goto do_unary; 1936 case INDEX_op_bswap16_i32: 1937 case INDEX_op_bswap16_i64: 1938 i1 = OPC_WSBH; 1939 goto do_unary; 1940 case INDEX_op_ext8s_i32: 1941 case INDEX_op_ext8s_i64: 1942 i1 = OPC_SEB; 1943 goto do_unary; 1944 case INDEX_op_ext16s_i32: 1945 case INDEX_op_ext16s_i64: 1946 i1 = OPC_SEH; 1947 do_unary: 1948 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1949 break; 1950 1951 case INDEX_op_bswap32_i32: 1952 tcg_out_bswap32(s, a0, a1); 1953 break; 1954 case INDEX_op_bswap32_i64: 1955 tcg_out_bswap32u(s, a0, a1); 1956 break; 1957 case INDEX_op_bswap64_i64: 1958 tcg_out_bswap64(s, a0, a1); 1959 break; 1960 case INDEX_op_extrh_i64_i32: 1961 tcg_out_dsra(s, a0, a1, 32); 1962 break; 1963 case INDEX_op_ext32s_i64: 1964 case INDEX_op_ext_i32_i64: 1965 case INDEX_op_extrl_i64_i32: 1966 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); 1967 break; 1968 case INDEX_op_ext32u_i64: 1969 case INDEX_op_extu_i32_i64: 1970 tcg_out_ext32u(s, a0, a1); 1971 break; 1972 1973 case INDEX_op_sar_i32: 1974 i1 = OPC_SRAV, i2 = OPC_SRA; 1975 goto do_shift; 1976 case INDEX_op_shl_i32: 1977 i1 = OPC_SLLV, i2 = OPC_SLL; 1978 goto do_shift; 1979 case INDEX_op_shr_i32: 1980 i1 = OPC_SRLV, i2 = OPC_SRL; 1981 goto do_shift; 1982 case INDEX_op_rotr_i32: 1983 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1984 do_shift: 1985 if (c2) { 1986 tcg_out_opc_sa(s, i2, a0, a1, a2); 1987 break; 1988 } 1989 do_shiftv: 1990 tcg_out_opc_reg(s, i1, a0, a2, a1); 1991 break; 1992 case INDEX_op_rotl_i32: 1993 if (c2) { 1994 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 1995 } else { 1996 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1997 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 1998 } 1999 break; 2000 case INDEX_op_sar_i64: 2001 if (c2) { 2002 tcg_out_dsra(s, a0, a1, a2); 2003 break; 2004 } 2005 i1 = OPC_DSRAV; 2006 goto do_shiftv; 2007 case INDEX_op_shl_i64: 2008 if (c2) { 2009 tcg_out_dsll(s, a0, a1, a2); 2010 break; 2011 } 2012 i1 = OPC_DSLLV; 2013 goto do_shiftv; 2014 case INDEX_op_shr_i64: 2015 if (c2) { 2016 tcg_out_dsrl(s, a0, a1, a2); 2017 break; 2018 } 2019 i1 = OPC_DSRLV; 2020 goto do_shiftv; 2021 case INDEX_op_rotr_i64: 2022 if (c2) { 2023 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2024 break; 2025 } 2026 i1 = OPC_DROTRV; 2027 goto do_shiftv; 2028 case INDEX_op_rotl_i64: 2029 if (c2) { 2030 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2031 } else { 2032 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2033 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2034 } 2035 break; 2036 2037 case INDEX_op_clz_i32: 2038 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2039 break; 2040 case INDEX_op_clz_i64: 2041 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2042 break; 2043 2044 case INDEX_op_deposit_i32: 2045 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2046 break; 2047 case INDEX_op_deposit_i64: 2048 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2049 args[3] + args[4] - 1, args[3]); 2050 break; 2051 case INDEX_op_extract_i32: 2052 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2053 break; 2054 case INDEX_op_extract_i64: 2055 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2056 args[3] - 1, a2); 2057 break; 2058 2059 case INDEX_op_brcond_i32: 2060 case INDEX_op_brcond_i64: 2061 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2062 break; 2063 case INDEX_op_brcond2_i32: 2064 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2065 break; 2066 2067 case INDEX_op_movcond_i32: 2068 case INDEX_op_movcond_i64: 2069 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2070 break; 2071 2072 case INDEX_op_setcond_i32: 2073 case INDEX_op_setcond_i64: 2074 tcg_out_setcond(s, args[3], a0, a1, a2); 2075 break; 2076 case INDEX_op_setcond2_i32: 2077 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2078 break; 2079 2080 case INDEX_op_qemu_ld_i32: 2081 tcg_out_qemu_ld(s, args, false); 2082 break; 2083 case INDEX_op_qemu_ld_i64: 2084 tcg_out_qemu_ld(s, args, true); 2085 break; 2086 case INDEX_op_qemu_st_i32: 2087 tcg_out_qemu_st(s, args, false); 2088 break; 2089 case INDEX_op_qemu_st_i64: 2090 tcg_out_qemu_st(s, args, true); 2091 break; 2092 2093 case INDEX_op_add2_i32: 2094 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2095 const_args[4], const_args[5], false); 2096 break; 2097 case INDEX_op_sub2_i32: 2098 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2099 const_args[4], const_args[5], true); 2100 break; 2101 2102 case INDEX_op_mb: 2103 tcg_out_mb(s, a0); 2104 break; 2105 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2106 case INDEX_op_mov_i64: 2107 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2108 default: 2109 tcg_abort(); 2110 } 2111} 2112 2113static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2114{ 2115 switch (op) { 2116 case INDEX_op_goto_ptr: 2117 return C_O0_I1(r); 2118 2119 case INDEX_op_ld8u_i32: 2120 case INDEX_op_ld8s_i32: 2121 case INDEX_op_ld16u_i32: 2122 case INDEX_op_ld16s_i32: 2123 case INDEX_op_ld_i32: 2124 case INDEX_op_not_i32: 2125 case INDEX_op_bswap16_i32: 2126 case INDEX_op_bswap32_i32: 2127 case INDEX_op_ext8s_i32: 2128 case INDEX_op_ext16s_i32: 2129 case INDEX_op_extract_i32: 2130 case INDEX_op_ld8u_i64: 2131 case INDEX_op_ld8s_i64: 2132 case INDEX_op_ld16u_i64: 2133 case INDEX_op_ld16s_i64: 2134 case INDEX_op_ld32s_i64: 2135 case INDEX_op_ld32u_i64: 2136 case INDEX_op_ld_i64: 2137 case INDEX_op_not_i64: 2138 case INDEX_op_bswap16_i64: 2139 case INDEX_op_bswap32_i64: 2140 case INDEX_op_bswap64_i64: 2141 case INDEX_op_ext8s_i64: 2142 case INDEX_op_ext16s_i64: 2143 case INDEX_op_ext32s_i64: 2144 case INDEX_op_ext32u_i64: 2145 case INDEX_op_ext_i32_i64: 2146 case INDEX_op_extu_i32_i64: 2147 case INDEX_op_extrl_i64_i32: 2148 case INDEX_op_extrh_i64_i32: 2149 case INDEX_op_extract_i64: 2150 return C_O1_I1(r, r); 2151 2152 case INDEX_op_st8_i32: 2153 case INDEX_op_st16_i32: 2154 case INDEX_op_st_i32: 2155 case INDEX_op_st8_i64: 2156 case INDEX_op_st16_i64: 2157 case INDEX_op_st32_i64: 2158 case INDEX_op_st_i64: 2159 return C_O0_I2(rZ, r); 2160 2161 case INDEX_op_add_i32: 2162 case INDEX_op_add_i64: 2163 return C_O1_I2(r, r, rJ); 2164 case INDEX_op_sub_i32: 2165 case INDEX_op_sub_i64: 2166 return C_O1_I2(r, rZ, rN); 2167 case INDEX_op_mul_i32: 2168 case INDEX_op_mulsh_i32: 2169 case INDEX_op_muluh_i32: 2170 case INDEX_op_div_i32: 2171 case INDEX_op_divu_i32: 2172 case INDEX_op_rem_i32: 2173 case INDEX_op_remu_i32: 2174 case INDEX_op_nor_i32: 2175 case INDEX_op_setcond_i32: 2176 case INDEX_op_mul_i64: 2177 case INDEX_op_mulsh_i64: 2178 case INDEX_op_muluh_i64: 2179 case INDEX_op_div_i64: 2180 case INDEX_op_divu_i64: 2181 case INDEX_op_rem_i64: 2182 case INDEX_op_remu_i64: 2183 case INDEX_op_nor_i64: 2184 case INDEX_op_setcond_i64: 2185 return C_O1_I2(r, rZ, rZ); 2186 case INDEX_op_muls2_i32: 2187 case INDEX_op_mulu2_i32: 2188 case INDEX_op_muls2_i64: 2189 case INDEX_op_mulu2_i64: 2190 return C_O2_I2(r, r, r, r); 2191 case INDEX_op_and_i32: 2192 case INDEX_op_and_i64: 2193 return C_O1_I2(r, r, rIK); 2194 case INDEX_op_or_i32: 2195 case INDEX_op_xor_i32: 2196 case INDEX_op_or_i64: 2197 case INDEX_op_xor_i64: 2198 return C_O1_I2(r, r, rI); 2199 case INDEX_op_shl_i32: 2200 case INDEX_op_shr_i32: 2201 case INDEX_op_sar_i32: 2202 case INDEX_op_rotr_i32: 2203 case INDEX_op_rotl_i32: 2204 case INDEX_op_shl_i64: 2205 case INDEX_op_shr_i64: 2206 case INDEX_op_sar_i64: 2207 case INDEX_op_rotr_i64: 2208 case INDEX_op_rotl_i64: 2209 return C_O1_I2(r, r, ri); 2210 case INDEX_op_clz_i32: 2211 case INDEX_op_clz_i64: 2212 return C_O1_I2(r, r, rWZ); 2213 2214 case INDEX_op_deposit_i32: 2215 case INDEX_op_deposit_i64: 2216 return C_O1_I2(r, 0, rZ); 2217 case INDEX_op_brcond_i32: 2218 case INDEX_op_brcond_i64: 2219 return C_O0_I2(rZ, rZ); 2220 case INDEX_op_movcond_i32: 2221 case INDEX_op_movcond_i64: 2222 return (use_mips32r6_instructions 2223 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2224 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2225 case INDEX_op_add2_i32: 2226 case INDEX_op_sub2_i32: 2227 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2228 case INDEX_op_setcond2_i32: 2229 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2230 case INDEX_op_brcond2_i32: 2231 return C_O0_I4(rZ, rZ, rZ, rZ); 2232 2233 case INDEX_op_qemu_ld_i32: 2234 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2235 ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); 2236 case INDEX_op_qemu_st_i32: 2237 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2238 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); 2239 case INDEX_op_qemu_ld_i64: 2240 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) 2241 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) 2242 : C_O2_I2(r, r, L, L)); 2243 case INDEX_op_qemu_st_i64: 2244 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) 2245 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) 2246 : C_O0_I4(SZ, SZ, S, S)); 2247 2248 default: 2249 g_assert_not_reached(); 2250 } 2251} 2252 2253static const int tcg_target_callee_save_regs[] = { 2254 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2255 TCG_REG_S1, 2256 TCG_REG_S2, 2257 TCG_REG_S3, 2258 TCG_REG_S4, 2259 TCG_REG_S5, 2260 TCG_REG_S6, 2261 TCG_REG_S7, 2262 TCG_REG_S8, 2263 TCG_REG_RA, /* should be last for ABI compliance */ 2264}; 2265 2266/* The Linux kernel doesn't provide any information about the available 2267 instruction set. Probe it using a signal handler. */ 2268 2269 2270#ifndef use_movnz_instructions 2271bool use_movnz_instructions = false; 2272#endif 2273 2274#ifndef use_mips32_instructions 2275bool use_mips32_instructions = false; 2276#endif 2277 2278#ifndef use_mips32r2_instructions 2279bool use_mips32r2_instructions = false; 2280#endif 2281 2282static volatile sig_atomic_t got_sigill; 2283 2284static void sigill_handler(int signo, siginfo_t *si, void *data) 2285{ 2286 /* Skip the faulty instruction */ 2287 ucontext_t *uc = (ucontext_t *)data; 2288 uc->uc_mcontext.pc += 4; 2289 2290 got_sigill = 1; 2291} 2292 2293static void tcg_target_detect_isa(void) 2294{ 2295 struct sigaction sa_old, sa_new; 2296 2297 memset(&sa_new, 0, sizeof(sa_new)); 2298 sa_new.sa_flags = SA_SIGINFO; 2299 sa_new.sa_sigaction = sigill_handler; 2300 sigaction(SIGILL, &sa_new, &sa_old); 2301 2302 /* Probe for movn/movz, necessary to implement movcond. */ 2303#ifndef use_movnz_instructions 2304 got_sigill = 0; 2305 asm volatile(".set push\n" 2306 ".set mips32\n" 2307 "movn $zero, $zero, $zero\n" 2308 "movz $zero, $zero, $zero\n" 2309 ".set pop\n" 2310 : : : ); 2311 use_movnz_instructions = !got_sigill; 2312#endif 2313 2314 /* Probe for MIPS32 instructions. As no subsetting is allowed 2315 by the specification, it is only necessary to probe for one 2316 of the instructions. */ 2317#ifndef use_mips32_instructions 2318 got_sigill = 0; 2319 asm volatile(".set push\n" 2320 ".set mips32\n" 2321 "mul $zero, $zero\n" 2322 ".set pop\n" 2323 : : : ); 2324 use_mips32_instructions = !got_sigill; 2325#endif 2326 2327 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2328 available. As no subsetting is allowed by the specification, 2329 it is only necessary to probe for one of the instructions. */ 2330#ifndef use_mips32r2_instructions 2331 if (use_mips32_instructions) { 2332 got_sigill = 0; 2333 asm volatile(".set push\n" 2334 ".set mips32r2\n" 2335 "seb $zero, $zero\n" 2336 ".set pop\n" 2337 : : : ); 2338 use_mips32r2_instructions = !got_sigill; 2339 } 2340#endif 2341 2342 sigaction(SIGILL, &sa_old, NULL); 2343} 2344 2345static tcg_insn_unit *align_code_ptr(TCGContext *s) 2346{ 2347 uintptr_t p = (uintptr_t)s->code_ptr; 2348 if (p & 15) { 2349 p = (p + 15) & -16; 2350 s->code_ptr = (void *)p; 2351 } 2352 return s->code_ptr; 2353} 2354 2355/* Stack frame parameters. */ 2356#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2357#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2358#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2359 2360#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2361 + TCG_TARGET_STACK_ALIGN - 1) \ 2362 & -TCG_TARGET_STACK_ALIGN) 2363#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2364 2365/* We're expecting to be able to use an immediate for frame allocation. */ 2366QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2367 2368/* Generate global QEMU prologue and epilogue code */ 2369static void tcg_target_qemu_prologue(TCGContext *s) 2370{ 2371 int i; 2372 2373 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2374 2375 /* TB prologue */ 2376 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2377 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2378 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2379 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2380 } 2381 2382#ifndef CONFIG_SOFTMMU 2383 if (guest_base) { 2384 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2385 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2386 } 2387#endif 2388 2389 /* Call generated code */ 2390 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2391 /* delay slot */ 2392 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2393 2394 /* 2395 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2396 * and fall through to the rest of the epilogue. 2397 */ 2398 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2399 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2400 2401 /* TB epilogue */ 2402 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2403 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2404 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2405 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2406 } 2407 2408 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2409 /* delay slot */ 2410 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2411 2412 if (use_mips32r2_instructions) { 2413 return; 2414 } 2415 2416 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2417 clobbers TCG_TMP1, TCG_TMP2. */ 2418 2419 /* 2420 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2421 */ 2422 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2423 /* t3 = (ssss)d000 */ 2424 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2425 /* t1 = 000a */ 2426 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2427 /* t2 = 00c0 */ 2428 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2429 /* t3 = d00a */ 2430 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2431 /* t1 = 0abc */ 2432 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2433 /* t2 = 0c00 */ 2434 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2435 /* t1 = 00b0 */ 2436 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2437 /* t3 = dc0a */ 2438 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2439 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2440 /* t3 = dcba -- delay slot */ 2441 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2442 2443 if (TCG_TARGET_REG_BITS == 32) { 2444 return; 2445 } 2446 2447 /* 2448 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2449 */ 2450 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2451 /* t1 = (0000)000d */ 2452 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2453 /* t3 = 000a */ 2454 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2455 /* t1 = (0000)d000 */ 2456 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2457 /* t2 = 00c0 */ 2458 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2459 /* t3 = d00a */ 2460 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2461 /* t1 = 0abc */ 2462 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2463 /* t2 = 0c00 */ 2464 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2465 /* t1 = 00b0 */ 2466 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2467 /* t3 = dc0a */ 2468 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2469 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2470 /* t3 = dcba -- delay slot */ 2471 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2472 2473 /* 2474 * bswap64 -- 64-bit swap. a0 = abcdefgh 2475 */ 2476 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2477 /* t3 = h0000000 */ 2478 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2479 /* t1 = 0000000a */ 2480 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2481 2482 /* t2 = 000000g0 */ 2483 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2484 /* t3 = h000000a */ 2485 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2486 /* t1 = 00000abc */ 2487 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2488 /* t2 = 0g000000 */ 2489 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2490 /* t1 = 000000b0 */ 2491 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2492 2493 /* t3 = hg00000a */ 2494 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2495 /* t2 = 0000abcd */ 2496 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2497 /* t3 = hg0000ba */ 2498 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2499 2500 /* t1 = 000000c0 */ 2501 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2502 /* t2 = 0000000d */ 2503 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2504 /* t1 = 00000c00 */ 2505 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2506 /* t2 = 0000d000 */ 2507 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2508 2509 /* t3 = hg000cba */ 2510 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2511 /* t1 = 00abcdef */ 2512 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2513 /* t3 = hg00dcba */ 2514 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2515 2516 /* t2 = 0000000f */ 2517 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2518 /* t1 = 000000e0 */ 2519 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2520 /* t2 = 00f00000 */ 2521 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2522 /* t1 = 000e0000 */ 2523 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2524 2525 /* t3 = hgf0dcba */ 2526 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2527 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2528 /* t3 = hgfedcba -- delay slot */ 2529 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2530} 2531 2532static void tcg_target_init(TCGContext *s) 2533{ 2534 tcg_target_detect_isa(); 2535 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2536 if (TCG_TARGET_REG_BITS == 64) { 2537 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2538 } 2539 2540 tcg_target_call_clobber_regs = 0; 2541 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2542 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2543 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2544 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2545 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2546 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2547 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2548 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2549 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2550 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2551 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2552 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2553 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2554 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2555 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2556 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2557 2558 s->reserved_regs = 0; 2559 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2560 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2561 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2562 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2563 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2564 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2565 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2566 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2567 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2568 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2569} 2570 2571void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, 2572 uintptr_t jmp_rw, uintptr_t addr) 2573{ 2574 qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); 2575 flush_idcache_range(jmp_rx, jmp_rw, 4); 2576} 2577 2578typedef struct { 2579 DebugFrameHeader h; 2580 uint8_t fde_def_cfa[4]; 2581 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2582} DebugFrame; 2583 2584#define ELF_HOST_MACHINE EM_MIPS 2585/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2586 which is good because they're really quite complicated for MIPS. */ 2587 2588static const DebugFrame debug_frame = { 2589 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2590 .h.cie.id = -1, 2591 .h.cie.version = 1, 2592 .h.cie.code_align = 1, 2593 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2594 .h.cie.return_column = TCG_REG_RA, 2595 2596 /* Total FDE size does not include the "len" member. */ 2597 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2598 2599 .fde_def_cfa = { 2600 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2601 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2602 (FRAME_SIZE >> 7) 2603 }, 2604 .fde_reg_ofs = { 2605 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2606 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2607 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2608 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2609 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2610 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2611 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2612 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2613 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2614 } 2615}; 2616 2617void tcg_register_jit(const void *buf, size_t buf_size) 2618{ 2619 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2620} 2621