1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28#include "../tcg-pool.c.inc" 29 30/* used for function call generation */ 31#define TCG_TARGET_STACK_ALIGN 16 32#if _MIPS_SIM == _ABIO32 33# define TCG_TARGET_CALL_STACK_OFFSET 16 34# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 35# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 36#else 37# define TCG_TARGET_CALL_STACK_OFFSET 0 38# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 39# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 40#endif 41#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 42#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 43 44#if TCG_TARGET_REG_BITS == 32 45# define LO_OFF (HOST_BIG_ENDIAN * 4) 46# define HI_OFF (4 - LO_OFF) 47#else 48/* Assert at compile-time that these values are never used for 64-bit. */ 49# define LO_OFF ({ qemu_build_not_reached(); 0; }) 50# define HI_OFF ({ qemu_build_not_reached(); 0; }) 51#endif 52 53#ifdef CONFIG_DEBUG_TCG 54static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 55 "zero", 56 "at", 57 "v0", 58 "v1", 59 "a0", 60 "a1", 61 "a2", 62 "a3", 63 "t0", 64 "t1", 65 "t2", 66 "t3", 67 "t4", 68 "t5", 69 "t6", 70 "t7", 71 "s0", 72 "s1", 73 "s2", 74 "s3", 75 "s4", 76 "s5", 77 "s6", 78 "s7", 79 "t8", 80 "t9", 81 "k0", 82 "k1", 83 "gp", 84 "sp", 85 "s8", 86 "ra", 87}; 88#endif 89 90#define TCG_TMP0 TCG_REG_AT 91#define TCG_TMP1 TCG_REG_T9 92#define TCG_TMP2 TCG_REG_T8 93#define TCG_TMP3 TCG_REG_T7 94 95#define TCG_GUEST_BASE_REG TCG_REG_S7 96#if TCG_TARGET_REG_BITS == 64 97#define TCG_REG_TB TCG_REG_S6 98#else 99#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 100#endif 101 102/* check if we really need so many registers :P */ 103static const int tcg_target_reg_alloc_order[] = { 104 /* Call saved registers. */ 105 TCG_REG_S0, 106 TCG_REG_S1, 107 TCG_REG_S2, 108 TCG_REG_S3, 109 TCG_REG_S4, 110 TCG_REG_S5, 111 TCG_REG_S6, 112 TCG_REG_S7, 113 TCG_REG_S8, 114 115 /* Call clobbered registers. */ 116 TCG_REG_T4, 117 TCG_REG_T5, 118 TCG_REG_T6, 119 TCG_REG_T7, 120 TCG_REG_T8, 121 TCG_REG_T9, 122 TCG_REG_V1, 123 TCG_REG_V0, 124 125 /* Argument registers, opposite order of allocation. */ 126 TCG_REG_T3, 127 TCG_REG_T2, 128 TCG_REG_T1, 129 TCG_REG_T0, 130 TCG_REG_A3, 131 TCG_REG_A2, 132 TCG_REG_A1, 133 TCG_REG_A0, 134}; 135 136static const TCGReg tcg_target_call_iarg_regs[] = { 137 TCG_REG_A0, 138 TCG_REG_A1, 139 TCG_REG_A2, 140 TCG_REG_A3, 141#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 142 TCG_REG_T0, 143 TCG_REG_T1, 144 TCG_REG_T2, 145 TCG_REG_T3, 146#endif 147}; 148 149static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 150{ 151 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 152 tcg_debug_assert(slot >= 0 && slot <= 1); 153 return TCG_REG_V0 + slot; 154} 155 156static const tcg_insn_unit *tb_ret_addr; 157static const tcg_insn_unit *bswap32_addr; 158static const tcg_insn_unit *bswap32u_addr; 159static const tcg_insn_unit *bswap64_addr; 160 161static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 162{ 163 /* Let the compiler perform the right-shift as part of the arithmetic. */ 164 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 165 ptrdiff_t disp = target - (src_rx + 1); 166 if (disp == (int16_t)disp) { 167 *src_rw = deposit32(*src_rw, 0, 16, disp); 168 return true; 169 } 170 return false; 171} 172 173static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 174 intptr_t value, intptr_t addend) 175{ 176 value += addend; 177 switch (type) { 178 case R_MIPS_PC16: 179 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 180 case R_MIPS_16: 181 if (value != (int16_t)value) { 182 return false; 183 } 184 *code_ptr = deposit32(*code_ptr, 0, 16, value); 185 return true; 186 } 187 g_assert_not_reached(); 188} 189 190#define TCG_CT_CONST_ZERO 0x100 191#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 192#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 193#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 194#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 195#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 196 197#define ALL_GENERAL_REGS 0xffffffffu 198 199static bool is_p2m1(tcg_target_long val) 200{ 201 return val && ((val + 1) & val) == 0; 202} 203 204/* test if a constant matches the constraint */ 205static bool tcg_target_const_match(int64_t val, int ct, 206 TCGType type, TCGCond cond, int vece) 207{ 208 if (ct & TCG_CT_CONST) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 213 return 1; 214 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 215 return 1; 216 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 217 return 1; 218 } else if ((ct & TCG_CT_CONST_P2M1) 219 && use_mips32r2_instructions && is_p2m1(val)) { 220 return 1; 221 } else if ((ct & TCG_CT_CONST_WSZ) 222 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 223 return 1; 224 } 225 return 0; 226} 227 228/* instruction opcodes */ 229typedef enum { 230 OPC_J = 002 << 26, 231 OPC_JAL = 003 << 26, 232 OPC_BEQ = 004 << 26, 233 OPC_BNE = 005 << 26, 234 OPC_BLEZ = 006 << 26, 235 OPC_BGTZ = 007 << 26, 236 OPC_ADDIU = 011 << 26, 237 OPC_SLTI = 012 << 26, 238 OPC_SLTIU = 013 << 26, 239 OPC_ANDI = 014 << 26, 240 OPC_ORI = 015 << 26, 241 OPC_XORI = 016 << 26, 242 OPC_LUI = 017 << 26, 243 OPC_BNEL = 025 << 26, 244 OPC_BNEZALC_R6 = 030 << 26, 245 OPC_DADDIU = 031 << 26, 246 OPC_LDL = 032 << 26, 247 OPC_LDR = 033 << 26, 248 OPC_LB = 040 << 26, 249 OPC_LH = 041 << 26, 250 OPC_LWL = 042 << 26, 251 OPC_LW = 043 << 26, 252 OPC_LBU = 044 << 26, 253 OPC_LHU = 045 << 26, 254 OPC_LWR = 046 << 26, 255 OPC_LWU = 047 << 26, 256 OPC_SB = 050 << 26, 257 OPC_SH = 051 << 26, 258 OPC_SWL = 052 << 26, 259 OPC_SW = 053 << 26, 260 OPC_SDL = 054 << 26, 261 OPC_SDR = 055 << 26, 262 OPC_SWR = 056 << 26, 263 OPC_LD = 067 << 26, 264 OPC_SD = 077 << 26, 265 266 OPC_SPECIAL = 000 << 26, 267 OPC_SLL = OPC_SPECIAL | 000, 268 OPC_SRL = OPC_SPECIAL | 002, 269 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 270 OPC_SRA = OPC_SPECIAL | 003, 271 OPC_SLLV = OPC_SPECIAL | 004, 272 OPC_SRLV = OPC_SPECIAL | 006, 273 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 274 OPC_SRAV = OPC_SPECIAL | 007, 275 OPC_JR_R5 = OPC_SPECIAL | 010, 276 OPC_JALR = OPC_SPECIAL | 011, 277 OPC_MOVZ = OPC_SPECIAL | 012, 278 OPC_MOVN = OPC_SPECIAL | 013, 279 OPC_SYNC = OPC_SPECIAL | 017, 280 OPC_MFHI = OPC_SPECIAL | 020, 281 OPC_MFLO = OPC_SPECIAL | 022, 282 OPC_DSLLV = OPC_SPECIAL | 024, 283 OPC_DSRLV = OPC_SPECIAL | 026, 284 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 285 OPC_DSRAV = OPC_SPECIAL | 027, 286 OPC_MULT = OPC_SPECIAL | 030, 287 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 288 OPC_MUH = OPC_SPECIAL | 030 | 0300, 289 OPC_MULTU = OPC_SPECIAL | 031, 290 OPC_MULU = OPC_SPECIAL | 031 | 0200, 291 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 292 OPC_DIV = OPC_SPECIAL | 032, 293 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 294 OPC_MOD = OPC_SPECIAL | 032 | 0300, 295 OPC_DIVU = OPC_SPECIAL | 033, 296 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 297 OPC_MODU = OPC_SPECIAL | 033 | 0300, 298 OPC_DMULT = OPC_SPECIAL | 034, 299 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 300 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 301 OPC_DMULTU = OPC_SPECIAL | 035, 302 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 303 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 304 OPC_DDIV = OPC_SPECIAL | 036, 305 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 306 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 307 OPC_DDIVU = OPC_SPECIAL | 037, 308 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 309 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 310 OPC_ADDU = OPC_SPECIAL | 041, 311 OPC_SUBU = OPC_SPECIAL | 043, 312 OPC_AND = OPC_SPECIAL | 044, 313 OPC_OR = OPC_SPECIAL | 045, 314 OPC_XOR = OPC_SPECIAL | 046, 315 OPC_NOR = OPC_SPECIAL | 047, 316 OPC_SLT = OPC_SPECIAL | 052, 317 OPC_SLTU = OPC_SPECIAL | 053, 318 OPC_DADDU = OPC_SPECIAL | 055, 319 OPC_DSUBU = OPC_SPECIAL | 057, 320 OPC_SELEQZ = OPC_SPECIAL | 065, 321 OPC_SELNEZ = OPC_SPECIAL | 067, 322 OPC_DSLL = OPC_SPECIAL | 070, 323 OPC_DSRL = OPC_SPECIAL | 072, 324 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 325 OPC_DSRA = OPC_SPECIAL | 073, 326 OPC_DSLL32 = OPC_SPECIAL | 074, 327 OPC_DSRL32 = OPC_SPECIAL | 076, 328 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 329 OPC_DSRA32 = OPC_SPECIAL | 077, 330 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 331 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 332 333 OPC_REGIMM = 001 << 26, 334 OPC_BLTZ = OPC_REGIMM | (000 << 16), 335 OPC_BGEZ = OPC_REGIMM | (001 << 16), 336 337 OPC_SPECIAL2 = 034 << 26, 338 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 339 OPC_CLZ = OPC_SPECIAL2 | 040, 340 OPC_DCLZ = OPC_SPECIAL2 | 044, 341 342 OPC_SPECIAL3 = 037 << 26, 343 OPC_EXT = OPC_SPECIAL3 | 000, 344 OPC_DEXTM = OPC_SPECIAL3 | 001, 345 OPC_DEXTU = OPC_SPECIAL3 | 002, 346 OPC_DEXT = OPC_SPECIAL3 | 003, 347 OPC_INS = OPC_SPECIAL3 | 004, 348 OPC_DINSM = OPC_SPECIAL3 | 005, 349 OPC_DINSU = OPC_SPECIAL3 | 006, 350 OPC_DINS = OPC_SPECIAL3 | 007, 351 OPC_WSBH = OPC_SPECIAL3 | 00240, 352 OPC_DSBH = OPC_SPECIAL3 | 00244, 353 OPC_DSHD = OPC_SPECIAL3 | 00544, 354 OPC_SEB = OPC_SPECIAL3 | 02040, 355 OPC_SEH = OPC_SPECIAL3 | 03040, 356 357 /* MIPS r6 doesn't have JR, JALR should be used instead */ 358 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 359 360 /* 361 * MIPS r6 replaces MUL with an alternative encoding which is 362 * backwards-compatible at the assembly level. 363 */ 364 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 365 366 /* MIPS r6 introduced names for weaker variants of SYNC. These are 367 backward compatible to previous architecture revisions. */ 368 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 369 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 370 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 371 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 372 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 373 374 /* Aliases for convenience. */ 375 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 376 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 377} MIPSInsn; 378 379/* 380 * Type reg 381 */ 382static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 383 TCGReg rd, TCGReg rs, TCGReg rt) 384{ 385 int32_t inst; 386 387 inst = opc; 388 inst |= (rs & 0x1F) << 21; 389 inst |= (rt & 0x1F) << 16; 390 inst |= (rd & 0x1F) << 11; 391 tcg_out32(s, inst); 392} 393 394/* 395 * Type immediate 396 */ 397static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 398 TCGReg rt, TCGReg rs, TCGArg imm) 399{ 400 int32_t inst; 401 402 inst = opc; 403 inst |= (rs & 0x1F) << 21; 404 inst |= (rt & 0x1F) << 16; 405 inst |= (imm & 0xffff); 406 tcg_out32(s, inst); 407} 408 409/* 410 * Type bitfield 411 */ 412static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 413 TCGReg rs, int msb, int lsb) 414{ 415 int32_t inst; 416 417 inst = opc; 418 inst |= (rs & 0x1F) << 21; 419 inst |= (rt & 0x1F) << 16; 420 inst |= (msb & 0x1F) << 11; 421 inst |= (lsb & 0x1F) << 6; 422 tcg_out32(s, inst); 423} 424 425static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 426 MIPSInsn oph, TCGReg rt, TCGReg rs, 427 int msb, int lsb) 428{ 429 if (lsb >= 32) { 430 opc = oph; 431 msb -= 32; 432 lsb -= 32; 433 } else if (msb >= 32) { 434 opc = opm; 435 msb -= 32; 436 } 437 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 438} 439 440/* 441 * Type branch 442 */ 443static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 444{ 445 tcg_out_opc_imm(s, opc, rt, rs, 0); 446} 447 448/* 449 * Type sa 450 */ 451static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 452 TCGReg rd, TCGReg rt, TCGArg sa) 453{ 454 int32_t inst; 455 456 inst = opc; 457 inst |= (rt & 0x1F) << 16; 458 inst |= (rd & 0x1F) << 11; 459 inst |= (sa & 0x1F) << 6; 460 tcg_out32(s, inst); 461 462} 463 464static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 465 TCGReg rd, TCGReg rt, TCGArg sa) 466{ 467 int32_t inst; 468 469 inst = (sa & 32 ? opc2 : opc1); 470 inst |= (rt & 0x1F) << 16; 471 inst |= (rd & 0x1F) << 11; 472 inst |= (sa & 0x1F) << 6; 473 tcg_out32(s, inst); 474} 475 476/* 477 * Type jump. 478 * Returns true if the branch was in range and the insn was emitted. 479 */ 480static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 481{ 482 uintptr_t dest = (uintptr_t)target; 483 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 484 int32_t inst; 485 486 /* The pc-region branch happens within the 256MB region of 487 the delay slot (thus the +4). */ 488 if ((from ^ dest) & -(1 << 28)) { 489 return false; 490 } 491 tcg_debug_assert((dest & 3) == 0); 492 493 inst = opc; 494 inst |= (dest >> 2) & 0x3ffffff; 495 tcg_out32(s, inst); 496 return true; 497} 498 499static void tcg_out_nop(TCGContext *s) 500{ 501 tcg_out32(s, 0); 502} 503 504static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 505{ 506 memset(p, 0, count * sizeof(tcg_insn_unit)); 507} 508 509static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 510{ 511 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 512} 513 514static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 515{ 516 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 517} 518 519static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 520{ 521 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 522} 523 524static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 525{ 526 /* Simple reg-reg move, optimising out the 'do nothing' case */ 527 if (ret != arg) { 528 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 529 } 530 return true; 531} 532 533static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 534{ 535 if (arg == (int16_t)arg) { 536 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 537 return true; 538 } 539 if (arg == (uint16_t)arg) { 540 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 541 return true; 542 } 543 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 544 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 545 return true; 546 } 547 return false; 548} 549 550static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 551{ 552 /* 553 * All signed 32-bit constants are loadable with two immediates, 554 * and everything else requires more work. 555 */ 556 if (arg == (int32_t)arg) { 557 if (!tcg_out_movi_one(s, ret, arg)) { 558 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 559 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 560 } 561 return true; 562 } 563 return false; 564} 565 566static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 567 tcg_target_long arg, TCGReg tbreg) 568{ 569 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 570 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 571} 572 573static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 574 tcg_target_long arg, TCGReg tbreg) 575{ 576 tcg_target_long tmp; 577 int sh, lo; 578 579 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 580 arg = (int32_t)arg; 581 } 582 583 /* Load all 32-bit constants. */ 584 if (tcg_out_movi_two(s, ret, arg)) { 585 return; 586 } 587 assert(TCG_TARGET_REG_BITS == 64); 588 589 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 590 tmp = tcg_tbrel_diff(s, (void *)arg); 591 if (tmp == (int16_t)tmp) { 592 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 593 return; 594 } 595 if (tcg_out_movi_two(s, ret, tmp)) { 596 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 597 return; 598 } 599 600 /* 601 * Load bitmasks with a right-shift. This is good for things 602 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 603 * or similarly using LUI. For this to work, bit 31 must be set. 604 */ 605 if (arg > 0 && (int32_t)arg < 0) { 606 sh = clz64(arg); 607 if (tcg_out_movi_one(s, ret, arg << sh)) { 608 tcg_out_dsrl(s, ret, ret, sh); 609 return; 610 } 611 } 612 613 /* 614 * Load slightly larger constants using left-shift. 615 * Limit this sequence to 3 insns to avoid too much expansion. 616 */ 617 sh = ctz64(arg); 618 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 619 tcg_out_dsll(s, ret, ret, sh); 620 return; 621 } 622 623 /* 624 * Load slightly larger constants using left-shift and add/or. 625 * Prefer addi with a negative immediate when that would produce 626 * a larger shift. For this to work, bits 15 and 16 must be set. 627 */ 628 lo = arg & 0xffff; 629 if (lo) { 630 if ((arg & 0x18000) == 0x18000) { 631 lo = (int16_t)arg; 632 } 633 tmp = arg - lo; 634 sh = ctz64(tmp); 635 tmp >>= sh; 636 if (tcg_out_movi_one(s, ret, tmp)) { 637 tcg_out_dsll(s, ret, ret, sh); 638 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 639 return; 640 } 641 } 642 643 /* Otherwise, put 64-bit constants into the constant pool. */ 644 tcg_out_movi_pool(s, ret, arg, tbreg); 645} 646 647static void tcg_out_movi(TCGContext *s, TCGType type, 648 TCGReg ret, tcg_target_long arg) 649{ 650 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 651 tcg_out_movi_int(s, type, ret, arg, tbreg); 652} 653 654static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 655{ 656 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); 657 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 658} 659 660static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 661{ 662 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 663} 664 665static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 666{ 667 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); 668 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 669} 670 671static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 672{ 673 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 674} 675 676static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 679 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 680} 681 682static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 683{ 684 if (rd != rs) { 685 tcg_out_ext32s(s, rd, rs); 686 } 687} 688 689static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 690{ 691 tcg_out_ext32u(s, rd, rs); 692} 693 694static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 695{ 696 tcg_out_ext32s(s, rd, rs); 697} 698 699static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 700{ 701 return false; 702} 703 704static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 705 tcg_target_long imm) 706{ 707 /* This function is only used for passing structs by reference. */ 708 g_assert_not_reached(); 709} 710 711static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 712{ 713 /* ret and arg can't be register tmp0 */ 714 tcg_debug_assert(ret != TCG_TMP0); 715 tcg_debug_assert(arg != TCG_TMP0); 716 717 /* With arg = abcd: */ 718 if (use_mips32r2_instructions) { 719 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 720 if (flags & TCG_BSWAP_OS) { 721 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 722 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 723 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 724 } 725 return; 726 } 727 728 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 729 if (!(flags & TCG_BSWAP_IZ)) { 730 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 731 } 732 if (flags & TCG_BSWAP_OS) { 733 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 734 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 735 } else { 736 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 737 if (flags & TCG_BSWAP_OZ) { 738 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 739 } 740 } 741 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 742} 743 744static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 745{ 746 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 747 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 748 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 749 } 750} 751 752static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 753{ 754 if (use_mips32r2_instructions) { 755 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 756 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 757 if (flags & TCG_BSWAP_OZ) { 758 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 759 } 760 } else { 761 if (flags & TCG_BSWAP_OZ) { 762 tcg_out_bswap_subr(s, bswap32u_addr); 763 } else { 764 tcg_out_bswap_subr(s, bswap32_addr); 765 } 766 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 767 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 768 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 769 } 770} 771 772static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 773{ 774 if (use_mips32r2_instructions) { 775 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 776 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 777 } else { 778 tcg_out_bswap_subr(s, bswap64_addr); 779 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 780 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 781 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 782 } 783} 784 785static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 786{ 787 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 788 if (use_mips32r2_instructions) { 789 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 790 } else { 791 tcg_out_dsll(s, ret, arg, 32); 792 tcg_out_dsrl(s, ret, ret, 32); 793 } 794} 795 796static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 797 TCGReg addr, intptr_t ofs) 798{ 799 int16_t lo = ofs; 800 if (ofs != lo) { 801 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 802 if (addr != TCG_REG_ZERO) { 803 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 804 } 805 addr = TCG_TMP0; 806 } 807 tcg_out_opc_imm(s, opc, data, addr, lo); 808} 809 810static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 811 TCGReg arg1, intptr_t arg2) 812{ 813 MIPSInsn opc = OPC_LD; 814 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 815 opc = OPC_LW; 816 } 817 tcg_out_ldst(s, opc, arg, arg1, arg2); 818} 819 820static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 821 TCGReg arg1, intptr_t arg2) 822{ 823 MIPSInsn opc = OPC_SD; 824 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 825 opc = OPC_SW; 826 } 827 tcg_out_ldst(s, opc, arg, arg1, arg2); 828} 829 830static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 831 TCGReg base, intptr_t ofs) 832{ 833 if (val == 0) { 834 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 835 return true; 836 } 837 return false; 838} 839 840static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 841 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 842 bool cbh, bool is_sub) 843{ 844 TCGReg th = TCG_TMP1; 845 846 /* If we have a negative constant such that negating it would 847 make the high part zero, we can (usually) eliminate one insn. */ 848 if (cbl && cbh && bh == -1 && bl != 0) { 849 bl = -bl; 850 bh = 0; 851 is_sub = !is_sub; 852 } 853 854 /* By operating on the high part first, we get to use the final 855 carry operation to move back from the temporary. */ 856 if (!cbh) { 857 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 858 } else if (bh != 0 || ah == rl) { 859 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 860 } else { 861 th = ah; 862 } 863 864 /* Note that tcg optimization should eliminate the bl == 0 case. */ 865 if (is_sub) { 866 if (cbl) { 867 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 868 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 869 } else { 870 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 871 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 872 } 873 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 874 } else { 875 if (cbl) { 876 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 877 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 878 } else if (rl == al && rl == bl) { 879 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 880 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 881 } else { 882 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 883 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 884 } 885 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 886 } 887} 888 889#define SETCOND_INV TCG_TARGET_NB_REGS 890#define SETCOND_NEZ (SETCOND_INV << 1) 891#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 892 893static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 894 TCGReg arg1, TCGReg arg2) 895{ 896 int flags = 0; 897 898 switch (cond) { 899 case TCG_COND_EQ: /* -> NE */ 900 case TCG_COND_GE: /* -> LT */ 901 case TCG_COND_GEU: /* -> LTU */ 902 case TCG_COND_LE: /* -> GT */ 903 case TCG_COND_LEU: /* -> GTU */ 904 cond = tcg_invert_cond(cond); 905 flags ^= SETCOND_INV; 906 break; 907 default: 908 break; 909 } 910 911 switch (cond) { 912 case TCG_COND_NE: 913 flags |= SETCOND_NEZ; 914 if (arg2 == 0) { 915 return arg1 | flags; 916 } 917 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 918 break; 919 case TCG_COND_LT: 920 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 921 break; 922 case TCG_COND_LTU: 923 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 924 break; 925 case TCG_COND_GT: 926 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 927 break; 928 case TCG_COND_GTU: 929 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 930 break; 931 default: 932 g_assert_not_reached(); 933 } 934 return ret | flags; 935} 936 937static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 938{ 939 if (tmpflags != ret) { 940 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 941 942 switch (tmpflags & SETCOND_FLAGS) { 943 case SETCOND_INV: 944 /* Intermediate result is boolean: simply invert. */ 945 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 946 break; 947 case SETCOND_NEZ: 948 /* Intermediate result is zero/non-zero: test != 0. */ 949 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 950 break; 951 case SETCOND_NEZ | SETCOND_INV: 952 /* Intermediate result is zero/non-zero: test == 0. */ 953 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 954 break; 955 default: 956 g_assert_not_reached(); 957 } 958 } 959} 960 961static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 962 TCGReg arg1, TCGReg arg2) 963{ 964 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 965 tcg_out_setcond_end(s, ret, tmpflags); 966} 967 968static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 969 TCGReg arg2, TCGLabel *l) 970{ 971 static const MIPSInsn b_zero[16] = { 972 [TCG_COND_LT] = OPC_BLTZ, 973 [TCG_COND_GT] = OPC_BGTZ, 974 [TCG_COND_LE] = OPC_BLEZ, 975 [TCG_COND_GE] = OPC_BGEZ, 976 }; 977 978 MIPSInsn b_opc = 0; 979 980 switch (cond) { 981 case TCG_COND_EQ: 982 b_opc = OPC_BEQ; 983 break; 984 case TCG_COND_NE: 985 b_opc = OPC_BNE; 986 break; 987 case TCG_COND_LT: 988 case TCG_COND_GT: 989 case TCG_COND_LE: 990 case TCG_COND_GE: 991 if (arg2 == 0) { 992 b_opc = b_zero[cond]; 993 arg2 = arg1; 994 arg1 = 0; 995 } 996 break; 997 default: 998 break; 999 } 1000 1001 if (b_opc == 0) { 1002 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 1003 1004 arg2 = TCG_REG_ZERO; 1005 arg1 = tmpflags & ~SETCOND_FLAGS; 1006 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1007 } 1008 1009 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1010 tcg_out_opc_br(s, b_opc, arg1, arg2); 1011 tcg_out_nop(s); 1012} 1013 1014static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 1015 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1016{ 1017 int flags = 0; 1018 1019 switch (cond) { 1020 case TCG_COND_EQ: 1021 flags |= SETCOND_INV; 1022 /* fall through */ 1023 case TCG_COND_NE: 1024 flags |= SETCOND_NEZ; 1025 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 1026 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 1027 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1028 break; 1029 1030 default: 1031 tcg_out_setcond(s, TCG_COND_EQ, TCG_TMP0, ah, bh); 1032 tcg_out_setcond(s, tcg_unsigned_cond(cond), TCG_TMP1, al, bl); 1033 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 1034 tcg_out_setcond(s, tcg_high_cond(cond), TCG_TMP0, ah, bh); 1035 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1036 break; 1037 } 1038 return ret | flags; 1039} 1040 1041static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1042 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1043{ 1044 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1045 tcg_out_setcond_end(s, ret, tmpflags); 1046} 1047 1048static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1049 TCGReg bl, TCGReg bh, TCGLabel *l) 1050{ 1051 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1052 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1053 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1054 1055 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1056 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1057 tcg_out_nop(s); 1058} 1059 1060static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1061 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1062{ 1063 int tmpflags; 1064 bool eqz; 1065 1066 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1067 if (use_mips32r6_instructions && v1 == 0) { 1068 v1 = v2; 1069 v2 = 0; 1070 cond = tcg_invert_cond(cond); 1071 } 1072 1073 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1074 c1 = tmpflags & ~SETCOND_FLAGS; 1075 eqz = tmpflags & SETCOND_INV; 1076 1077 if (use_mips32r6_instructions) { 1078 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1079 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1080 1081 if (v2 != 0) { 1082 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1083 } 1084 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1085 if (v2 != 0) { 1086 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1087 } 1088 return; 1089 } 1090 1091 /* This should be guaranteed via constraints */ 1092 tcg_debug_assert(v2 == ret); 1093 1094 if (use_movnz_instructions) { 1095 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1096 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1097 } else { 1098 /* Invert the condition in order to branch over the move. */ 1099 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1100 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1101 tcg_out_nop(s); 1102 /* Open-code tcg_out_mov, without the nop-move check. */ 1103 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1104 } 1105} 1106 1107static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1108{ 1109 /* 1110 * Note that __mips_abicalls requires the called function's address 1111 * to be loaded into $25 (t9), even if a direct branch is in range. 1112 * 1113 * For n64, always drop the pointer into the constant pool. 1114 * We can re-use helper addresses often and do not want any 1115 * of the longer sequences tcg_out_movi may try. 1116 */ 1117 if (sizeof(uintptr_t) == 8) { 1118 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1119 } else { 1120 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1121 } 1122 1123 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1124 if (tail) { 1125 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1126 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1127 } 1128 } else { 1129 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1130 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1131 } 1132 } 1133} 1134 1135static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1136 const TCGHelperInfo *info) 1137{ 1138 tcg_out_call_int(s, arg, false); 1139 tcg_out_nop(s); 1140} 1141 1142/* We have four temps, we might as well expose three of them. */ 1143static const TCGLdstHelperParam ldst_helper_param = { 1144 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1145}; 1146 1147static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1148{ 1149 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1150 MemOp opc = get_memop(l->oi); 1151 1152 /* resolve label address */ 1153 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1154 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1155 return false; 1156 } 1157 1158 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1159 1160 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1161 /* delay slot */ 1162 tcg_out_nop(s); 1163 1164 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1165 1166 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1167 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1168 return false; 1169 } 1170 1171 /* delay slot */ 1172 tcg_out_nop(s); 1173 return true; 1174} 1175 1176static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1177{ 1178 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1179 MemOp opc = get_memop(l->oi); 1180 1181 /* resolve label address */ 1182 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1183 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1184 return false; 1185 } 1186 1187 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1188 1189 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1190 /* delay slot */ 1191 tcg_out_nop(s); 1192 1193 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1194 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1195 return false; 1196 } 1197 1198 /* delay slot */ 1199 tcg_out_nop(s); 1200 return true; 1201} 1202 1203typedef struct { 1204 TCGReg base; 1205 TCGAtomAlign aa; 1206} HostAddress; 1207 1208bool tcg_target_has_memory_bswap(MemOp memop) 1209{ 1210 return false; 1211} 1212 1213/* We expect to use a 16-bit negative offset from ENV. */ 1214#define MIN_TLB_MASK_TABLE_OFS -32768 1215 1216/* 1217 * For system-mode, perform the TLB load and compare. 1218 * For user-mode, perform any required alignment tests. 1219 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1220 * is required and fill in @h with the host address for the fast path. 1221 */ 1222static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1223 TCGReg addrlo, TCGReg addrhi, 1224 MemOpIdx oi, bool is_ld) 1225{ 1226 TCGType addr_type = s->addr_type; 1227 TCGLabelQemuLdst *ldst = NULL; 1228 MemOp opc = get_memop(oi); 1229 MemOp a_bits; 1230 unsigned s_bits = opc & MO_SIZE; 1231 unsigned a_mask; 1232 TCGReg base; 1233 1234 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1235 a_bits = h->aa.align; 1236 a_mask = (1 << a_bits) - 1; 1237 1238 if (tcg_use_softmmu) { 1239 unsigned s_mask = (1 << s_bits) - 1; 1240 int mem_index = get_mmuidx(oi); 1241 int fast_off = tlb_mask_table_ofs(s, mem_index); 1242 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1243 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1244 int add_off = offsetof(CPUTLBEntry, addend); 1245 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1246 : offsetof(CPUTLBEntry, addr_write); 1247 1248 ldst = new_ldst_label(s); 1249 ldst->is_ld = is_ld; 1250 ldst->oi = oi; 1251 ldst->addrlo_reg = addrlo; 1252 ldst->addrhi_reg = addrhi; 1253 1254 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1255 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1256 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1257 1258 /* Extract the TLB index from the address into TMP3. */ 1259 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1260 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, 1261 s->page_bits - CPU_TLB_ENTRY_BITS); 1262 } else { 1263 tcg_out_dsrl(s, TCG_TMP3, addrlo, 1264 s->page_bits - CPU_TLB_ENTRY_BITS); 1265 } 1266 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1267 1268 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1269 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1270 1271 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1272 /* Load the (low half) tlb comparator. */ 1273 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1274 cmp_off + HOST_BIG_ENDIAN * 4); 1275 } else { 1276 tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off); 1277 } 1278 1279 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { 1280 /* Load the tlb addend for the fast path. */ 1281 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1282 } 1283 1284 /* 1285 * Mask the page bits, keeping the alignment bits to compare against. 1286 * For unaligned accesses, compare against the end of the access to 1287 * verify that it does not cross a page boundary. 1288 */ 1289 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1290 if (a_mask < s_mask) { 1291 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1292 || addr_type == TCG_TYPE_I32 1293 ? OPC_ADDIU : OPC_DADDIU), 1294 TCG_TMP2, addrlo, s_mask - a_mask); 1295 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1296 } else { 1297 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); 1298 } 1299 1300 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1301 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1302 tcg_out_ext32u(s, TCG_TMP2, addrlo); 1303 addrlo = TCG_TMP2; 1304 } 1305 1306 ldst->label_ptr[0] = s->code_ptr; 1307 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1308 1309 /* Load and test the high half tlb comparator. */ 1310 if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { 1311 /* delay slot */ 1312 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1313 1314 /* Load the tlb addend for the fast path. */ 1315 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1316 1317 ldst->label_ptr[1] = s->code_ptr; 1318 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); 1319 } 1320 1321 /* delay slot */ 1322 base = TCG_TMP3; 1323 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); 1324 } else { 1325 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1326 ldst = new_ldst_label(s); 1327 1328 ldst->is_ld = is_ld; 1329 ldst->oi = oi; 1330 ldst->addrlo_reg = addrlo; 1331 ldst->addrhi_reg = addrhi; 1332 1333 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1334 tcg_debug_assert(a_bits < 16); 1335 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); 1336 1337 ldst->label_ptr[0] = s->code_ptr; 1338 if (use_mips32r6_instructions) { 1339 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1340 } else { 1341 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1342 tcg_out_nop(s); 1343 } 1344 } 1345 1346 base = addrlo; 1347 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1348 tcg_out_ext32u(s, TCG_REG_A0, base); 1349 base = TCG_REG_A0; 1350 } 1351 if (guest_base) { 1352 if (guest_base == (int16_t)guest_base) { 1353 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1354 } else { 1355 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1356 TCG_GUEST_BASE_REG); 1357 } 1358 base = TCG_REG_A0; 1359 } 1360 } 1361 1362 h->base = base; 1363 return ldst; 1364} 1365 1366static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1367 TCGReg base, MemOp opc, TCGType type) 1368{ 1369 switch (opc & MO_SSIZE) { 1370 case MO_UB: 1371 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1372 break; 1373 case MO_SB: 1374 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1375 break; 1376 case MO_UW: 1377 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1378 break; 1379 case MO_SW: 1380 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1381 break; 1382 case MO_UL: 1383 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1384 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1385 break; 1386 } 1387 /* FALLTHRU */ 1388 case MO_SL: 1389 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1390 break; 1391 case MO_UQ: 1392 /* Prefer to load from offset 0 first, but allow for overlap. */ 1393 if (TCG_TARGET_REG_BITS == 64) { 1394 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1395 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1396 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1397 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1398 } else { 1399 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1400 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1401 } 1402 break; 1403 default: 1404 g_assert_not_reached(); 1405 } 1406} 1407 1408static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1409 TCGReg base, MemOp opc, TCGType type) 1410{ 1411 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1412 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1413 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1414 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1415 bool sgn = opc & MO_SIGN; 1416 1417 switch (opc & MO_SIZE) { 1418 case MO_16: 1419 if (HOST_BIG_ENDIAN) { 1420 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1421 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1422 if (use_mips32r2_instructions) { 1423 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1424 } else { 1425 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1426 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1427 } 1428 } else if (use_mips32r2_instructions && lo != base) { 1429 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1430 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1431 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1432 } else { 1433 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1434 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1435 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1436 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1437 } 1438 break; 1439 1440 case MO_32: 1441 tcg_out_opc_imm(s, lw1, lo, base, 0); 1442 tcg_out_opc_imm(s, lw2, lo, base, 3); 1443 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1444 tcg_out_ext32u(s, lo, lo); 1445 } 1446 break; 1447 1448 case MO_64: 1449 if (TCG_TARGET_REG_BITS == 64) { 1450 tcg_out_opc_imm(s, ld1, lo, base, 0); 1451 tcg_out_opc_imm(s, ld2, lo, base, 7); 1452 } else { 1453 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1454 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1455 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1456 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1457 } 1458 break; 1459 1460 default: 1461 g_assert_not_reached(); 1462 } 1463} 1464 1465static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1466 TCGReg addrlo, TCGReg addrhi, 1467 MemOpIdx oi, TCGType data_type) 1468{ 1469 MemOp opc = get_memop(oi); 1470 TCGLabelQemuLdst *ldst; 1471 HostAddress h; 1472 1473 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 1474 1475 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1476 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1477 } else { 1478 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1479 } 1480 1481 if (ldst) { 1482 ldst->type = data_type; 1483 ldst->datalo_reg = datalo; 1484 ldst->datahi_reg = datahi; 1485 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1486 } 1487} 1488 1489static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1490 TCGReg base, MemOp opc) 1491{ 1492 switch (opc & MO_SIZE) { 1493 case MO_8: 1494 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1495 break; 1496 case MO_16: 1497 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1498 break; 1499 case MO_32: 1500 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1501 break; 1502 case MO_64: 1503 if (TCG_TARGET_REG_BITS == 64) { 1504 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1505 } else { 1506 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1507 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1508 } 1509 break; 1510 default: 1511 g_assert_not_reached(); 1512 } 1513} 1514 1515static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1516 TCGReg base, MemOp opc) 1517{ 1518 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1519 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1520 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1521 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1522 1523 switch (opc & MO_SIZE) { 1524 case MO_16: 1525 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1526 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1527 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1528 break; 1529 1530 case MO_32: 1531 tcg_out_opc_imm(s, sw1, lo, base, 0); 1532 tcg_out_opc_imm(s, sw2, lo, base, 3); 1533 break; 1534 1535 case MO_64: 1536 if (TCG_TARGET_REG_BITS == 64) { 1537 tcg_out_opc_imm(s, sd1, lo, base, 0); 1538 tcg_out_opc_imm(s, sd2, lo, base, 7); 1539 } else { 1540 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1541 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1542 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1543 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1544 } 1545 break; 1546 1547 default: 1548 g_assert_not_reached(); 1549 } 1550} 1551 1552static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1553 TCGReg addrlo, TCGReg addrhi, 1554 MemOpIdx oi, TCGType data_type) 1555{ 1556 MemOp opc = get_memop(oi); 1557 TCGLabelQemuLdst *ldst; 1558 HostAddress h; 1559 1560 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 1561 1562 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1563 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1564 } else { 1565 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1566 } 1567 1568 if (ldst) { 1569 ldst->type = data_type; 1570 ldst->datalo_reg = datalo; 1571 ldst->datahi_reg = datahi; 1572 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1573 } 1574} 1575 1576static void tcg_out_mb(TCGContext *s, TCGArg a0) 1577{ 1578 static const MIPSInsn sync[] = { 1579 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1580 as the former is an ordering barrier and the latter 1581 is a completion barrier. */ 1582 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1583 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1584 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1585 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1586 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1587 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1588 }; 1589 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1590} 1591 1592static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1593 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1594{ 1595 if (use_mips32r6_instructions) { 1596 if (a2 == width) { 1597 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1598 } else { 1599 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1600 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1601 } 1602 } else { 1603 if (a2 == width) { 1604 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1605 } else if (a0 == a2) { 1606 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1607 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1608 } else if (a0 != a1) { 1609 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1610 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1611 } else { 1612 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1613 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1614 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1615 } 1616 } 1617} 1618 1619static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1620{ 1621 TCGReg base = TCG_REG_ZERO; 1622 int16_t lo = 0; 1623 1624 if (a0) { 1625 intptr_t ofs; 1626 if (TCG_TARGET_REG_BITS == 64) { 1627 ofs = tcg_tbrel_diff(s, (void *)a0); 1628 lo = ofs; 1629 if (ofs == lo) { 1630 base = TCG_REG_TB; 1631 } else { 1632 base = TCG_REG_V0; 1633 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1634 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1635 } 1636 } else { 1637 ofs = a0; 1638 lo = ofs; 1639 base = TCG_REG_V0; 1640 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1641 } 1642 } 1643 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1644 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1645 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1646 } 1647 /* delay slot */ 1648 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1649} 1650 1651static void tcg_out_goto_tb(TCGContext *s, int which) 1652{ 1653 intptr_t ofs = get_jmp_target_addr(s, which); 1654 TCGReg base, dest; 1655 1656 /* indirect jump method */ 1657 if (TCG_TARGET_REG_BITS == 64) { 1658 dest = TCG_REG_TB; 1659 base = TCG_REG_TB; 1660 ofs = tcg_tbrel_diff(s, (void *)ofs); 1661 } else { 1662 dest = TCG_TMP0; 1663 base = TCG_REG_ZERO; 1664 } 1665 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1666 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1667 /* delay slot */ 1668 tcg_out_nop(s); 1669 1670 set_jmp_reset_offset(s, which); 1671 if (TCG_TARGET_REG_BITS == 64) { 1672 /* For the unlinked case, need to reset TCG_REG_TB. */ 1673 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1674 -tcg_current_code_size(s)); 1675 } 1676} 1677 1678void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1679 uintptr_t jmp_rx, uintptr_t jmp_rw) 1680{ 1681 /* Always indirect, nothing to do */ 1682} 1683 1684static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1685 const TCGArg args[TCG_MAX_OP_ARGS], 1686 const int const_args[TCG_MAX_OP_ARGS]) 1687{ 1688 MIPSInsn i1, i2; 1689 TCGArg a0, a1, a2; 1690 int c2; 1691 1692 /* 1693 * Note that many operands use the constraint set "rZ". 1694 * We make use of the fact that 0 is the ZERO register, 1695 * and hence such cases need not check for const_args. 1696 */ 1697 a0 = args[0]; 1698 a1 = args[1]; 1699 a2 = args[2]; 1700 c2 = const_args[2]; 1701 1702 switch (opc) { 1703 case INDEX_op_goto_ptr: 1704 /* jmp to the given host address (could be epilogue) */ 1705 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1706 if (TCG_TARGET_REG_BITS == 64) { 1707 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 1708 } else { 1709 tcg_out_nop(s); 1710 } 1711 break; 1712 case INDEX_op_br: 1713 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1714 arg_label(a0)); 1715 break; 1716 1717 case INDEX_op_ld8u_i32: 1718 case INDEX_op_ld8u_i64: 1719 i1 = OPC_LBU; 1720 goto do_ldst; 1721 case INDEX_op_ld8s_i32: 1722 case INDEX_op_ld8s_i64: 1723 i1 = OPC_LB; 1724 goto do_ldst; 1725 case INDEX_op_ld16u_i32: 1726 case INDEX_op_ld16u_i64: 1727 i1 = OPC_LHU; 1728 goto do_ldst; 1729 case INDEX_op_ld16s_i32: 1730 case INDEX_op_ld16s_i64: 1731 i1 = OPC_LH; 1732 goto do_ldst; 1733 case INDEX_op_ld_i32: 1734 case INDEX_op_ld32s_i64: 1735 i1 = OPC_LW; 1736 goto do_ldst; 1737 case INDEX_op_ld32u_i64: 1738 i1 = OPC_LWU; 1739 goto do_ldst; 1740 case INDEX_op_ld_i64: 1741 i1 = OPC_LD; 1742 goto do_ldst; 1743 case INDEX_op_st8_i32: 1744 case INDEX_op_st8_i64: 1745 i1 = OPC_SB; 1746 goto do_ldst; 1747 case INDEX_op_st16_i32: 1748 case INDEX_op_st16_i64: 1749 i1 = OPC_SH; 1750 goto do_ldst; 1751 case INDEX_op_st_i32: 1752 case INDEX_op_st32_i64: 1753 i1 = OPC_SW; 1754 goto do_ldst; 1755 case INDEX_op_st_i64: 1756 i1 = OPC_SD; 1757 do_ldst: 1758 tcg_out_ldst(s, i1, a0, a1, a2); 1759 break; 1760 1761 case INDEX_op_add_i32: 1762 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1763 goto do_binary; 1764 case INDEX_op_add_i64: 1765 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1766 goto do_binary; 1767 case INDEX_op_or_i32: 1768 case INDEX_op_or_i64: 1769 i1 = OPC_OR, i2 = OPC_ORI; 1770 goto do_binary; 1771 case INDEX_op_xor_i32: 1772 case INDEX_op_xor_i64: 1773 i1 = OPC_XOR, i2 = OPC_XORI; 1774 do_binary: 1775 if (c2) { 1776 tcg_out_opc_imm(s, i2, a0, a1, a2); 1777 break; 1778 } 1779 do_binaryv: 1780 tcg_out_opc_reg(s, i1, a0, a1, a2); 1781 break; 1782 1783 case INDEX_op_sub_i32: 1784 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1785 goto do_subtract; 1786 case INDEX_op_sub_i64: 1787 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1788 do_subtract: 1789 if (c2) { 1790 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1791 break; 1792 } 1793 goto do_binaryv; 1794 case INDEX_op_and_i32: 1795 if (c2 && a2 != (uint16_t)a2) { 1796 int msb = ctz32(~a2) - 1; 1797 tcg_debug_assert(use_mips32r2_instructions); 1798 tcg_debug_assert(is_p2m1(a2)); 1799 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1800 break; 1801 } 1802 i1 = OPC_AND, i2 = OPC_ANDI; 1803 goto do_binary; 1804 case INDEX_op_and_i64: 1805 if (c2 && a2 != (uint16_t)a2) { 1806 int msb = ctz64(~a2) - 1; 1807 tcg_debug_assert(use_mips32r2_instructions); 1808 tcg_debug_assert(is_p2m1(a2)); 1809 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1810 break; 1811 } 1812 i1 = OPC_AND, i2 = OPC_ANDI; 1813 goto do_binary; 1814 case INDEX_op_nor_i32: 1815 case INDEX_op_nor_i64: 1816 i1 = OPC_NOR; 1817 goto do_binaryv; 1818 1819 case INDEX_op_mul_i32: 1820 if (use_mips32_instructions) { 1821 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1822 break; 1823 } 1824 i1 = OPC_MULT, i2 = OPC_MFLO; 1825 goto do_hilo1; 1826 case INDEX_op_mulsh_i32: 1827 if (use_mips32r6_instructions) { 1828 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1829 break; 1830 } 1831 i1 = OPC_MULT, i2 = OPC_MFHI; 1832 goto do_hilo1; 1833 case INDEX_op_muluh_i32: 1834 if (use_mips32r6_instructions) { 1835 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1836 break; 1837 } 1838 i1 = OPC_MULTU, i2 = OPC_MFHI; 1839 goto do_hilo1; 1840 case INDEX_op_div_i32: 1841 if (use_mips32r6_instructions) { 1842 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1843 break; 1844 } 1845 i1 = OPC_DIV, i2 = OPC_MFLO; 1846 goto do_hilo1; 1847 case INDEX_op_divu_i32: 1848 if (use_mips32r6_instructions) { 1849 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1850 break; 1851 } 1852 i1 = OPC_DIVU, i2 = OPC_MFLO; 1853 goto do_hilo1; 1854 case INDEX_op_rem_i32: 1855 if (use_mips32r6_instructions) { 1856 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1857 break; 1858 } 1859 i1 = OPC_DIV, i2 = OPC_MFHI; 1860 goto do_hilo1; 1861 case INDEX_op_remu_i32: 1862 if (use_mips32r6_instructions) { 1863 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1864 break; 1865 } 1866 i1 = OPC_DIVU, i2 = OPC_MFHI; 1867 goto do_hilo1; 1868 case INDEX_op_mul_i64: 1869 if (use_mips32r6_instructions) { 1870 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1871 break; 1872 } 1873 i1 = OPC_DMULT, i2 = OPC_MFLO; 1874 goto do_hilo1; 1875 case INDEX_op_mulsh_i64: 1876 if (use_mips32r6_instructions) { 1877 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1878 break; 1879 } 1880 i1 = OPC_DMULT, i2 = OPC_MFHI; 1881 goto do_hilo1; 1882 case INDEX_op_muluh_i64: 1883 if (use_mips32r6_instructions) { 1884 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1885 break; 1886 } 1887 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1888 goto do_hilo1; 1889 case INDEX_op_div_i64: 1890 if (use_mips32r6_instructions) { 1891 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1892 break; 1893 } 1894 i1 = OPC_DDIV, i2 = OPC_MFLO; 1895 goto do_hilo1; 1896 case INDEX_op_divu_i64: 1897 if (use_mips32r6_instructions) { 1898 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1899 break; 1900 } 1901 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1902 goto do_hilo1; 1903 case INDEX_op_rem_i64: 1904 if (use_mips32r6_instructions) { 1905 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1906 break; 1907 } 1908 i1 = OPC_DDIV, i2 = OPC_MFHI; 1909 goto do_hilo1; 1910 case INDEX_op_remu_i64: 1911 if (use_mips32r6_instructions) { 1912 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1913 break; 1914 } 1915 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1916 do_hilo1: 1917 tcg_out_opc_reg(s, i1, 0, a1, a2); 1918 tcg_out_opc_reg(s, i2, a0, 0, 0); 1919 break; 1920 1921 case INDEX_op_muls2_i32: 1922 i1 = OPC_MULT; 1923 goto do_hilo2; 1924 case INDEX_op_mulu2_i32: 1925 i1 = OPC_MULTU; 1926 goto do_hilo2; 1927 case INDEX_op_muls2_i64: 1928 i1 = OPC_DMULT; 1929 goto do_hilo2; 1930 case INDEX_op_mulu2_i64: 1931 i1 = OPC_DMULTU; 1932 do_hilo2: 1933 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1934 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1935 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1936 break; 1937 1938 case INDEX_op_neg_i32: 1939 i1 = OPC_SUBU; 1940 goto do_unary; 1941 case INDEX_op_neg_i64: 1942 i1 = OPC_DSUBU; 1943 goto do_unary; 1944 case INDEX_op_not_i32: 1945 case INDEX_op_not_i64: 1946 i1 = OPC_NOR; 1947 goto do_unary; 1948 do_unary: 1949 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1950 break; 1951 1952 case INDEX_op_bswap16_i32: 1953 case INDEX_op_bswap16_i64: 1954 tcg_out_bswap16(s, a0, a1, a2); 1955 break; 1956 case INDEX_op_bswap32_i32: 1957 tcg_out_bswap32(s, a0, a1, 0); 1958 break; 1959 case INDEX_op_bswap32_i64: 1960 tcg_out_bswap32(s, a0, a1, a2); 1961 break; 1962 case INDEX_op_bswap64_i64: 1963 tcg_out_bswap64(s, a0, a1); 1964 break; 1965 case INDEX_op_extrh_i64_i32: 1966 tcg_out_dsra(s, a0, a1, 32); 1967 break; 1968 1969 case INDEX_op_sar_i32: 1970 i1 = OPC_SRAV, i2 = OPC_SRA; 1971 goto do_shift; 1972 case INDEX_op_shl_i32: 1973 i1 = OPC_SLLV, i2 = OPC_SLL; 1974 goto do_shift; 1975 case INDEX_op_shr_i32: 1976 i1 = OPC_SRLV, i2 = OPC_SRL; 1977 goto do_shift; 1978 case INDEX_op_rotr_i32: 1979 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1980 do_shift: 1981 if (c2) { 1982 tcg_out_opc_sa(s, i2, a0, a1, a2); 1983 break; 1984 } 1985 do_shiftv: 1986 tcg_out_opc_reg(s, i1, a0, a2, a1); 1987 break; 1988 case INDEX_op_rotl_i32: 1989 if (c2) { 1990 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 1991 } else { 1992 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1993 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 1994 } 1995 break; 1996 case INDEX_op_sar_i64: 1997 if (c2) { 1998 tcg_out_dsra(s, a0, a1, a2); 1999 break; 2000 } 2001 i1 = OPC_DSRAV; 2002 goto do_shiftv; 2003 case INDEX_op_shl_i64: 2004 if (c2) { 2005 tcg_out_dsll(s, a0, a1, a2); 2006 break; 2007 } 2008 i1 = OPC_DSLLV; 2009 goto do_shiftv; 2010 case INDEX_op_shr_i64: 2011 if (c2) { 2012 tcg_out_dsrl(s, a0, a1, a2); 2013 break; 2014 } 2015 i1 = OPC_DSRLV; 2016 goto do_shiftv; 2017 case INDEX_op_rotr_i64: 2018 if (c2) { 2019 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2020 break; 2021 } 2022 i1 = OPC_DROTRV; 2023 goto do_shiftv; 2024 case INDEX_op_rotl_i64: 2025 if (c2) { 2026 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2027 } else { 2028 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2029 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2030 } 2031 break; 2032 2033 case INDEX_op_clz_i32: 2034 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2035 break; 2036 case INDEX_op_clz_i64: 2037 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2038 break; 2039 2040 case INDEX_op_deposit_i32: 2041 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2042 break; 2043 case INDEX_op_deposit_i64: 2044 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2045 args[3] + args[4] - 1, args[3]); 2046 break; 2047 case INDEX_op_extract_i32: 2048 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2049 break; 2050 case INDEX_op_extract_i64: 2051 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2052 args[3] - 1, a2); 2053 break; 2054 2055 case INDEX_op_brcond_i32: 2056 case INDEX_op_brcond_i64: 2057 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2058 break; 2059 case INDEX_op_brcond2_i32: 2060 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2061 break; 2062 2063 case INDEX_op_movcond_i32: 2064 case INDEX_op_movcond_i64: 2065 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2066 break; 2067 2068 case INDEX_op_setcond_i32: 2069 case INDEX_op_setcond_i64: 2070 tcg_out_setcond(s, args[3], a0, a1, a2); 2071 break; 2072 case INDEX_op_setcond2_i32: 2073 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2074 break; 2075 2076 case INDEX_op_qemu_ld_a64_i32: 2077 if (TCG_TARGET_REG_BITS == 32) { 2078 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 2079 break; 2080 } 2081 /* fall through */ 2082 case INDEX_op_qemu_ld_a32_i32: 2083 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 2084 break; 2085 case INDEX_op_qemu_ld_a32_i64: 2086 if (TCG_TARGET_REG_BITS == 64) { 2087 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2088 } else { 2089 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 2090 } 2091 break; 2092 case INDEX_op_qemu_ld_a64_i64: 2093 if (TCG_TARGET_REG_BITS == 64) { 2094 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2095 } else { 2096 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2097 } 2098 break; 2099 2100 case INDEX_op_qemu_st_a64_i32: 2101 if (TCG_TARGET_REG_BITS == 32) { 2102 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 2103 break; 2104 } 2105 /* fall through */ 2106 case INDEX_op_qemu_st_a32_i32: 2107 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 2108 break; 2109 case INDEX_op_qemu_st_a32_i64: 2110 if (TCG_TARGET_REG_BITS == 64) { 2111 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2112 } else { 2113 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 2114 } 2115 break; 2116 case INDEX_op_qemu_st_a64_i64: 2117 if (TCG_TARGET_REG_BITS == 64) { 2118 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2119 } else { 2120 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2121 } 2122 break; 2123 2124 case INDEX_op_add2_i32: 2125 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2126 const_args[4], const_args[5], false); 2127 break; 2128 case INDEX_op_sub2_i32: 2129 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2130 const_args[4], const_args[5], true); 2131 break; 2132 2133 case INDEX_op_mb: 2134 tcg_out_mb(s, a0); 2135 break; 2136 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2137 case INDEX_op_mov_i64: 2138 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2139 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2140 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2141 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2142 case INDEX_op_ext8s_i64: 2143 case INDEX_op_ext8u_i32: 2144 case INDEX_op_ext8u_i64: 2145 case INDEX_op_ext16s_i32: 2146 case INDEX_op_ext16s_i64: 2147 case INDEX_op_ext32s_i64: 2148 case INDEX_op_ext32u_i64: 2149 case INDEX_op_ext_i32_i64: 2150 case INDEX_op_extu_i32_i64: 2151 case INDEX_op_extrl_i64_i32: 2152 default: 2153 g_assert_not_reached(); 2154 } 2155} 2156 2157static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2158{ 2159 switch (op) { 2160 case INDEX_op_goto_ptr: 2161 return C_O0_I1(r); 2162 2163 case INDEX_op_ld8u_i32: 2164 case INDEX_op_ld8s_i32: 2165 case INDEX_op_ld16u_i32: 2166 case INDEX_op_ld16s_i32: 2167 case INDEX_op_ld_i32: 2168 case INDEX_op_neg_i32: 2169 case INDEX_op_not_i32: 2170 case INDEX_op_bswap16_i32: 2171 case INDEX_op_bswap32_i32: 2172 case INDEX_op_ext8s_i32: 2173 case INDEX_op_ext16s_i32: 2174 case INDEX_op_extract_i32: 2175 case INDEX_op_ld8u_i64: 2176 case INDEX_op_ld8s_i64: 2177 case INDEX_op_ld16u_i64: 2178 case INDEX_op_ld16s_i64: 2179 case INDEX_op_ld32s_i64: 2180 case INDEX_op_ld32u_i64: 2181 case INDEX_op_ld_i64: 2182 case INDEX_op_neg_i64: 2183 case INDEX_op_not_i64: 2184 case INDEX_op_bswap16_i64: 2185 case INDEX_op_bswap32_i64: 2186 case INDEX_op_bswap64_i64: 2187 case INDEX_op_ext8s_i64: 2188 case INDEX_op_ext16s_i64: 2189 case INDEX_op_ext32s_i64: 2190 case INDEX_op_ext32u_i64: 2191 case INDEX_op_ext_i32_i64: 2192 case INDEX_op_extu_i32_i64: 2193 case INDEX_op_extrl_i64_i32: 2194 case INDEX_op_extrh_i64_i32: 2195 case INDEX_op_extract_i64: 2196 return C_O1_I1(r, r); 2197 2198 case INDEX_op_st8_i32: 2199 case INDEX_op_st16_i32: 2200 case INDEX_op_st_i32: 2201 case INDEX_op_st8_i64: 2202 case INDEX_op_st16_i64: 2203 case INDEX_op_st32_i64: 2204 case INDEX_op_st_i64: 2205 return C_O0_I2(rZ, r); 2206 2207 case INDEX_op_add_i32: 2208 case INDEX_op_add_i64: 2209 return C_O1_I2(r, r, rJ); 2210 case INDEX_op_sub_i32: 2211 case INDEX_op_sub_i64: 2212 return C_O1_I2(r, rZ, rN); 2213 case INDEX_op_mul_i32: 2214 case INDEX_op_mulsh_i32: 2215 case INDEX_op_muluh_i32: 2216 case INDEX_op_div_i32: 2217 case INDEX_op_divu_i32: 2218 case INDEX_op_rem_i32: 2219 case INDEX_op_remu_i32: 2220 case INDEX_op_nor_i32: 2221 case INDEX_op_setcond_i32: 2222 case INDEX_op_mul_i64: 2223 case INDEX_op_mulsh_i64: 2224 case INDEX_op_muluh_i64: 2225 case INDEX_op_div_i64: 2226 case INDEX_op_divu_i64: 2227 case INDEX_op_rem_i64: 2228 case INDEX_op_remu_i64: 2229 case INDEX_op_nor_i64: 2230 case INDEX_op_setcond_i64: 2231 return C_O1_I2(r, rZ, rZ); 2232 case INDEX_op_muls2_i32: 2233 case INDEX_op_mulu2_i32: 2234 case INDEX_op_muls2_i64: 2235 case INDEX_op_mulu2_i64: 2236 return C_O2_I2(r, r, r, r); 2237 case INDEX_op_and_i32: 2238 case INDEX_op_and_i64: 2239 return C_O1_I2(r, r, rIK); 2240 case INDEX_op_or_i32: 2241 case INDEX_op_xor_i32: 2242 case INDEX_op_or_i64: 2243 case INDEX_op_xor_i64: 2244 return C_O1_I2(r, r, rI); 2245 case INDEX_op_shl_i32: 2246 case INDEX_op_shr_i32: 2247 case INDEX_op_sar_i32: 2248 case INDEX_op_rotr_i32: 2249 case INDEX_op_rotl_i32: 2250 case INDEX_op_shl_i64: 2251 case INDEX_op_shr_i64: 2252 case INDEX_op_sar_i64: 2253 case INDEX_op_rotr_i64: 2254 case INDEX_op_rotl_i64: 2255 return C_O1_I2(r, r, ri); 2256 case INDEX_op_clz_i32: 2257 case INDEX_op_clz_i64: 2258 return C_O1_I2(r, r, rWZ); 2259 2260 case INDEX_op_deposit_i32: 2261 case INDEX_op_deposit_i64: 2262 return C_O1_I2(r, 0, rZ); 2263 case INDEX_op_brcond_i32: 2264 case INDEX_op_brcond_i64: 2265 return C_O0_I2(rZ, rZ); 2266 case INDEX_op_movcond_i32: 2267 case INDEX_op_movcond_i64: 2268 return (use_mips32r6_instructions 2269 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2270 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2271 case INDEX_op_add2_i32: 2272 case INDEX_op_sub2_i32: 2273 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2274 case INDEX_op_setcond2_i32: 2275 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2276 case INDEX_op_brcond2_i32: 2277 return C_O0_I4(rZ, rZ, rZ, rZ); 2278 2279 case INDEX_op_qemu_ld_a32_i32: 2280 return C_O1_I1(r, r); 2281 case INDEX_op_qemu_ld_a64_i32: 2282 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r); 2283 case INDEX_op_qemu_st_a32_i32: 2284 return C_O0_I2(rZ, r); 2285 case INDEX_op_qemu_st_a64_i32: 2286 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r); 2287 case INDEX_op_qemu_ld_a32_i64: 2288 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2289 case INDEX_op_qemu_ld_a64_i64: 2290 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r); 2291 case INDEX_op_qemu_st_a32_i64: 2292 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r); 2293 case INDEX_op_qemu_st_a64_i64: 2294 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) 2295 : C_O0_I4(rZ, rZ, r, r)); 2296 2297 default: 2298 g_assert_not_reached(); 2299 } 2300} 2301 2302static const int tcg_target_callee_save_regs[] = { 2303 TCG_REG_S0, 2304 TCG_REG_S1, 2305 TCG_REG_S2, 2306 TCG_REG_S3, 2307 TCG_REG_S4, 2308 TCG_REG_S5, 2309 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2310 TCG_REG_S7, /* used for guest_base */ 2311 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2312 TCG_REG_RA, /* should be last for ABI compliance */ 2313}; 2314 2315/* The Linux kernel doesn't provide any information about the available 2316 instruction set. Probe it using a signal handler. */ 2317 2318 2319#ifndef use_movnz_instructions 2320bool use_movnz_instructions = false; 2321#endif 2322 2323#ifndef use_mips32_instructions 2324bool use_mips32_instructions = false; 2325#endif 2326 2327#ifndef use_mips32r2_instructions 2328bool use_mips32r2_instructions = false; 2329#endif 2330 2331static volatile sig_atomic_t got_sigill; 2332 2333static void sigill_handler(int signo, siginfo_t *si, void *data) 2334{ 2335 /* Skip the faulty instruction */ 2336 ucontext_t *uc = (ucontext_t *)data; 2337 uc->uc_mcontext.pc += 4; 2338 2339 got_sigill = 1; 2340} 2341 2342static void tcg_target_detect_isa(void) 2343{ 2344 struct sigaction sa_old, sa_new; 2345 2346 memset(&sa_new, 0, sizeof(sa_new)); 2347 sa_new.sa_flags = SA_SIGINFO; 2348 sa_new.sa_sigaction = sigill_handler; 2349 sigaction(SIGILL, &sa_new, &sa_old); 2350 2351 /* Probe for movn/movz, necessary to implement movcond. */ 2352#ifndef use_movnz_instructions 2353 got_sigill = 0; 2354 asm volatile(".set push\n" 2355 ".set mips32\n" 2356 "movn $zero, $zero, $zero\n" 2357 "movz $zero, $zero, $zero\n" 2358 ".set pop\n" 2359 : : : ); 2360 use_movnz_instructions = !got_sigill; 2361#endif 2362 2363 /* Probe for MIPS32 instructions. As no subsetting is allowed 2364 by the specification, it is only necessary to probe for one 2365 of the instructions. */ 2366#ifndef use_mips32_instructions 2367 got_sigill = 0; 2368 asm volatile(".set push\n" 2369 ".set mips32\n" 2370 "mul $zero, $zero\n" 2371 ".set pop\n" 2372 : : : ); 2373 use_mips32_instructions = !got_sigill; 2374#endif 2375 2376 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2377 available. As no subsetting is allowed by the specification, 2378 it is only necessary to probe for one of the instructions. */ 2379#ifndef use_mips32r2_instructions 2380 if (use_mips32_instructions) { 2381 got_sigill = 0; 2382 asm volatile(".set push\n" 2383 ".set mips32r2\n" 2384 "seb $zero, $zero\n" 2385 ".set pop\n" 2386 : : : ); 2387 use_mips32r2_instructions = !got_sigill; 2388 } 2389#endif 2390 2391 sigaction(SIGILL, &sa_old, NULL); 2392} 2393 2394static tcg_insn_unit *align_code_ptr(TCGContext *s) 2395{ 2396 uintptr_t p = (uintptr_t)s->code_ptr; 2397 if (p & 15) { 2398 p = (p + 15) & -16; 2399 s->code_ptr = (void *)p; 2400 } 2401 return s->code_ptr; 2402} 2403 2404/* Stack frame parameters. */ 2405#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2406#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2407#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2408 2409#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2410 + TCG_TARGET_STACK_ALIGN - 1) \ 2411 & -TCG_TARGET_STACK_ALIGN) 2412#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2413 2414/* We're expecting to be able to use an immediate for frame allocation. */ 2415QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2416 2417/* Generate global QEMU prologue and epilogue code */ 2418static void tcg_target_qemu_prologue(TCGContext *s) 2419{ 2420 int i; 2421 2422 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2423 2424 /* TB prologue */ 2425 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2426 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2427 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2428 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2429 } 2430 2431 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2432 /* 2433 * The function call abi for n32 and n64 will have loaded $25 (t9) 2434 * with the address of the prologue, so we can use that instead 2435 * of TCG_REG_TB. 2436 */ 2437#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2438# error "Unknown mips abi" 2439#endif 2440 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2441 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2442 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2443 } 2444 2445 if (TCG_TARGET_REG_BITS == 64) { 2446 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2447 } 2448 2449 /* Call generated code */ 2450 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2451 /* delay slot */ 2452 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2453 2454 /* 2455 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2456 * and fall through to the rest of the epilogue. 2457 */ 2458 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2459 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2460 2461 /* TB epilogue */ 2462 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2463 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2464 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2465 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2466 } 2467 2468 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2469 /* delay slot */ 2470 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2471 2472 if (use_mips32r2_instructions) { 2473 return; 2474 } 2475 2476 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2477 clobbers TCG_TMP1, TCG_TMP2. */ 2478 2479 /* 2480 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2481 */ 2482 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2483 /* t3 = (ssss)d000 */ 2484 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2485 /* t1 = 000a */ 2486 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2487 /* t2 = 00c0 */ 2488 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2489 /* t3 = d00a */ 2490 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2491 /* t1 = 0abc */ 2492 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2493 /* t2 = 0c00 */ 2494 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2495 /* t1 = 00b0 */ 2496 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2497 /* t3 = dc0a */ 2498 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2499 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2500 /* t3 = dcba -- delay slot */ 2501 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2502 2503 if (TCG_TARGET_REG_BITS == 32) { 2504 return; 2505 } 2506 2507 /* 2508 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2509 */ 2510 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2511 /* t1 = (0000)000d */ 2512 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2513 /* t3 = 000a */ 2514 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2515 /* t1 = (0000)d000 */ 2516 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2517 /* t2 = 00c0 */ 2518 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2519 /* t3 = d00a */ 2520 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2521 /* t1 = 0abc */ 2522 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2523 /* t2 = 0c00 */ 2524 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2525 /* t1 = 00b0 */ 2526 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2527 /* t3 = dc0a */ 2528 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2529 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2530 /* t3 = dcba -- delay slot */ 2531 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2532 2533 /* 2534 * bswap64 -- 64-bit swap. a0 = abcdefgh 2535 */ 2536 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2537 /* t3 = h0000000 */ 2538 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2539 /* t1 = 0000000a */ 2540 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2541 2542 /* t2 = 000000g0 */ 2543 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2544 /* t3 = h000000a */ 2545 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2546 /* t1 = 00000abc */ 2547 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2548 /* t2 = 0g000000 */ 2549 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2550 /* t1 = 000000b0 */ 2551 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2552 2553 /* t3 = hg00000a */ 2554 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2555 /* t2 = 0000abcd */ 2556 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2557 /* t3 = hg0000ba */ 2558 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2559 2560 /* t1 = 000000c0 */ 2561 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2562 /* t2 = 0000000d */ 2563 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2564 /* t1 = 00000c00 */ 2565 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2566 /* t2 = 0000d000 */ 2567 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2568 2569 /* t3 = hg000cba */ 2570 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2571 /* t1 = 00abcdef */ 2572 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2573 /* t3 = hg00dcba */ 2574 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2575 2576 /* t2 = 0000000f */ 2577 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2578 /* t1 = 000000e0 */ 2579 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2580 /* t2 = 00f00000 */ 2581 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2582 /* t1 = 000e0000 */ 2583 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2584 2585 /* t3 = hgf0dcba */ 2586 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2587 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2588 /* t3 = hgfedcba -- delay slot */ 2589 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2590} 2591 2592static void tcg_out_tb_start(TCGContext *s) 2593{ 2594 /* nothing to do */ 2595} 2596 2597static void tcg_target_init(TCGContext *s) 2598{ 2599 tcg_target_detect_isa(); 2600 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2601 if (TCG_TARGET_REG_BITS == 64) { 2602 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2603 } 2604 2605 tcg_target_call_clobber_regs = 0; 2606 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2607 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2608 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2609 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2610 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2611 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2612 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2613 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2614 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2615 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2616 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2617 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2618 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2619 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2620 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2621 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2622 2623 s->reserved_regs = 0; 2624 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2625 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2626 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2627 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2628 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2629 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2630 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2631 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2632 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2633 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2634 if (TCG_TARGET_REG_BITS == 64) { 2635 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2636 } 2637} 2638 2639typedef struct { 2640 DebugFrameHeader h; 2641 uint8_t fde_def_cfa[4]; 2642 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2643} DebugFrame; 2644 2645#define ELF_HOST_MACHINE EM_MIPS 2646/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2647 which is good because they're really quite complicated for MIPS. */ 2648 2649static const DebugFrame debug_frame = { 2650 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2651 .h.cie.id = -1, 2652 .h.cie.version = 1, 2653 .h.cie.code_align = 1, 2654 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2655 .h.cie.return_column = TCG_REG_RA, 2656 2657 /* Total FDE size does not include the "len" member. */ 2658 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2659 2660 .fde_def_cfa = { 2661 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2662 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2663 (FRAME_SIZE >> 7) 2664 }, 2665 .fde_reg_ofs = { 2666 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2667 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2668 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2669 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2670 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2671 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2672 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2673 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2674 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2675 } 2676}; 2677 2678void tcg_register_jit(const void *buf, size_t buf_size) 2679{ 2680 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2681} 2682