1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */ 191#define TCG_CT_CONST_WSZ 0x1000 /* word size */ 192 193#define ALL_GENERAL_REGS 0xffffffffu 194 195static bool is_p2m1(tcg_target_long val) 196{ 197 return val && ((val + 1) & val) == 0; 198} 199 200/* test if a constant matches the constraint */ 201static bool tcg_target_const_match(int64_t val, int ct, 202 TCGType type, TCGCond cond, int vece) 203{ 204 if (ct & TCG_CT_CONST) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_P2M1) 213 && use_mips32r2_instructions && is_p2m1(val)) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_WSZ) 216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 217 return 1; 218 } 219 return 0; 220} 221 222/* instruction opcodes */ 223typedef enum { 224 OPC_J = 002 << 26, 225 OPC_JAL = 003 << 26, 226 OPC_BEQ = 004 << 26, 227 OPC_BNE = 005 << 26, 228 OPC_BLEZ = 006 << 26, 229 OPC_BGTZ = 007 << 26, 230 OPC_ADDIU = 011 << 26, 231 OPC_SLTI = 012 << 26, 232 OPC_SLTIU = 013 << 26, 233 OPC_ANDI = 014 << 26, 234 OPC_ORI = 015 << 26, 235 OPC_XORI = 016 << 26, 236 OPC_LUI = 017 << 26, 237 OPC_BNEL = 025 << 26, 238 OPC_BNEZALC_R6 = 030 << 26, 239 OPC_DADDIU = 031 << 26, 240 OPC_LDL = 032 << 26, 241 OPC_LDR = 033 << 26, 242 OPC_LB = 040 << 26, 243 OPC_LH = 041 << 26, 244 OPC_LWL = 042 << 26, 245 OPC_LW = 043 << 26, 246 OPC_LBU = 044 << 26, 247 OPC_LHU = 045 << 26, 248 OPC_LWR = 046 << 26, 249 OPC_LWU = 047 << 26, 250 OPC_SB = 050 << 26, 251 OPC_SH = 051 << 26, 252 OPC_SWL = 052 << 26, 253 OPC_SW = 053 << 26, 254 OPC_SDL = 054 << 26, 255 OPC_SDR = 055 << 26, 256 OPC_SWR = 056 << 26, 257 OPC_LD = 067 << 26, 258 OPC_SD = 077 << 26, 259 260 OPC_SPECIAL = 000 << 26, 261 OPC_SLL = OPC_SPECIAL | 000, 262 OPC_SRL = OPC_SPECIAL | 002, 263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 264 OPC_SRA = OPC_SPECIAL | 003, 265 OPC_SLLV = OPC_SPECIAL | 004, 266 OPC_SRLV = OPC_SPECIAL | 006, 267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 268 OPC_SRAV = OPC_SPECIAL | 007, 269 OPC_JR_R5 = OPC_SPECIAL | 010, 270 OPC_JALR = OPC_SPECIAL | 011, 271 OPC_MOVZ = OPC_SPECIAL | 012, 272 OPC_MOVN = OPC_SPECIAL | 013, 273 OPC_SYNC = OPC_SPECIAL | 017, 274 OPC_MFHI = OPC_SPECIAL | 020, 275 OPC_MFLO = OPC_SPECIAL | 022, 276 OPC_DSLLV = OPC_SPECIAL | 024, 277 OPC_DSRLV = OPC_SPECIAL | 026, 278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 279 OPC_DSRAV = OPC_SPECIAL | 027, 280 OPC_MULT = OPC_SPECIAL | 030, 281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 282 OPC_MUH = OPC_SPECIAL | 030 | 0300, 283 OPC_MULTU = OPC_SPECIAL | 031, 284 OPC_MULU = OPC_SPECIAL | 031 | 0200, 285 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 286 OPC_DIV = OPC_SPECIAL | 032, 287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 288 OPC_MOD = OPC_SPECIAL | 032 | 0300, 289 OPC_DIVU = OPC_SPECIAL | 033, 290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 291 OPC_MODU = OPC_SPECIAL | 033 | 0300, 292 OPC_DMULT = OPC_SPECIAL | 034, 293 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 294 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 295 OPC_DMULTU = OPC_SPECIAL | 035, 296 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 298 OPC_DDIV = OPC_SPECIAL | 036, 299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 300 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 301 OPC_DDIVU = OPC_SPECIAL | 037, 302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 303 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 304 OPC_ADDU = OPC_SPECIAL | 041, 305 OPC_SUBU = OPC_SPECIAL | 043, 306 OPC_AND = OPC_SPECIAL | 044, 307 OPC_OR = OPC_SPECIAL | 045, 308 OPC_XOR = OPC_SPECIAL | 046, 309 OPC_NOR = OPC_SPECIAL | 047, 310 OPC_SLT = OPC_SPECIAL | 052, 311 OPC_SLTU = OPC_SPECIAL | 053, 312 OPC_DADDU = OPC_SPECIAL | 055, 313 OPC_DSUBU = OPC_SPECIAL | 057, 314 OPC_SELEQZ = OPC_SPECIAL | 065, 315 OPC_SELNEZ = OPC_SPECIAL | 067, 316 OPC_DSLL = OPC_SPECIAL | 070, 317 OPC_DSRL = OPC_SPECIAL | 072, 318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 319 OPC_DSRA = OPC_SPECIAL | 073, 320 OPC_DSLL32 = OPC_SPECIAL | 074, 321 OPC_DSRL32 = OPC_SPECIAL | 076, 322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 323 OPC_DSRA32 = OPC_SPECIAL | 077, 324 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 326 327 OPC_REGIMM = 001 << 26, 328 OPC_BLTZ = OPC_REGIMM | (000 << 16), 329 OPC_BGEZ = OPC_REGIMM | (001 << 16), 330 331 OPC_SPECIAL2 = 034 << 26, 332 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 333 OPC_CLZ = OPC_SPECIAL2 | 040, 334 OPC_DCLZ = OPC_SPECIAL2 | 044, 335 336 OPC_SPECIAL3 = 037 << 26, 337 OPC_EXT = OPC_SPECIAL3 | 000, 338 OPC_DEXTM = OPC_SPECIAL3 | 001, 339 OPC_DEXTU = OPC_SPECIAL3 | 002, 340 OPC_DEXT = OPC_SPECIAL3 | 003, 341 OPC_INS = OPC_SPECIAL3 | 004, 342 OPC_DINSM = OPC_SPECIAL3 | 005, 343 OPC_DINSU = OPC_SPECIAL3 | 006, 344 OPC_DINS = OPC_SPECIAL3 | 007, 345 OPC_WSBH = OPC_SPECIAL3 | 00240, 346 OPC_DSBH = OPC_SPECIAL3 | 00244, 347 OPC_DSHD = OPC_SPECIAL3 | 00544, 348 OPC_SEB = OPC_SPECIAL3 | 02040, 349 OPC_SEH = OPC_SPECIAL3 | 03040, 350 351 /* MIPS r6 doesn't have JR, JALR should be used instead */ 352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 353 354 /* 355 * MIPS r6 replaces MUL with an alternative encoding which is 356 * backwards-compatible at the assembly level. 357 */ 358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 359 360 /* MIPS r6 introduced names for weaker variants of SYNC. These are 361 backward compatible to previous architecture revisions. */ 362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 367 368 /* Aliases for convenience. */ 369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 371} MIPSInsn; 372 373/* 374 * Type reg 375 */ 376static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 377 TCGReg rd, TCGReg rs, TCGReg rt) 378{ 379 int32_t inst; 380 381 inst = opc; 382 inst |= (rs & 0x1F) << 21; 383 inst |= (rt & 0x1F) << 16; 384 inst |= (rd & 0x1F) << 11; 385 tcg_out32(s, inst); 386} 387 388/* 389 * Type immediate 390 */ 391static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 392 TCGReg rt, TCGReg rs, TCGArg imm) 393{ 394 int32_t inst; 395 396 inst = opc; 397 inst |= (rs & 0x1F) << 21; 398 inst |= (rt & 0x1F) << 16; 399 inst |= (imm & 0xffff); 400 tcg_out32(s, inst); 401} 402 403/* 404 * Type bitfield 405 */ 406static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 407 TCGReg rs, int msb, int lsb) 408{ 409 int32_t inst; 410 411 inst = opc; 412 inst |= (rs & 0x1F) << 21; 413 inst |= (rt & 0x1F) << 16; 414 inst |= (msb & 0x1F) << 11; 415 inst |= (lsb & 0x1F) << 6; 416 tcg_out32(s, inst); 417} 418 419static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 420 MIPSInsn oph, TCGReg rt, TCGReg rs, 421 int msb, int lsb) 422{ 423 if (lsb >= 32) { 424 opc = oph; 425 msb -= 32; 426 lsb -= 32; 427 } else if (msb >= 32) { 428 opc = opm; 429 msb -= 32; 430 } 431 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 432} 433 434/* 435 * Type branch 436 */ 437static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 438{ 439 tcg_out_opc_imm(s, opc, rt, rs, 0); 440} 441 442/* 443 * Type sa 444 */ 445static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 446 TCGReg rd, TCGReg rt, TCGArg sa) 447{ 448 int32_t inst; 449 450 inst = opc; 451 inst |= (rt & 0x1F) << 16; 452 inst |= (rd & 0x1F) << 11; 453 inst |= (sa & 0x1F) << 6; 454 tcg_out32(s, inst); 455 456} 457 458static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 459 TCGReg rd, TCGReg rt, TCGArg sa) 460{ 461 int32_t inst; 462 463 inst = (sa & 32 ? opc2 : opc1); 464 inst |= (rt & 0x1F) << 16; 465 inst |= (rd & 0x1F) << 11; 466 inst |= (sa & 0x1F) << 6; 467 tcg_out32(s, inst); 468} 469 470/* 471 * Type jump. 472 * Returns true if the branch was in range and the insn was emitted. 473 */ 474static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 475{ 476 uintptr_t dest = (uintptr_t)target; 477 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 478 int32_t inst; 479 480 /* The pc-region branch happens within the 256MB region of 481 the delay slot (thus the +4). */ 482 if ((from ^ dest) & -(1 << 28)) { 483 return false; 484 } 485 tcg_debug_assert((dest & 3) == 0); 486 487 inst = opc; 488 inst |= (dest >> 2) & 0x3ffffff; 489 tcg_out32(s, inst); 490 return true; 491} 492 493static void tcg_out_nop(TCGContext *s) 494{ 495 tcg_out32(s, 0); 496} 497 498static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 499{ 500 memset(p, 0, count * sizeof(tcg_insn_unit)); 501} 502 503static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 504{ 505 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 506} 507 508static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 509{ 510 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 511} 512 513static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 514{ 515 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 516} 517 518static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 519{ 520 /* Simple reg-reg move, optimising out the 'do nothing' case */ 521 if (ret != arg) { 522 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 523 } 524 return true; 525} 526 527static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 528{ 529 if (arg == (int16_t)arg) { 530 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 531 return true; 532 } 533 if (arg == (uint16_t)arg) { 534 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 535 return true; 536 } 537 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 538 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 539 return true; 540 } 541 return false; 542} 543 544static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 545{ 546 /* 547 * All signed 32-bit constants are loadable with two immediates, 548 * and everything else requires more work. 549 */ 550 if (arg == (int32_t)arg) { 551 if (!tcg_out_movi_one(s, ret, arg)) { 552 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 553 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 554 } 555 return true; 556 } 557 return false; 558} 559 560static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 561 tcg_target_long arg, TCGReg tbreg) 562{ 563 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 564 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 565} 566 567static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 568 tcg_target_long arg, TCGReg tbreg) 569{ 570 tcg_target_long tmp; 571 int sh, lo; 572 573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 574 arg = (int32_t)arg; 575 } 576 577 /* Load all 32-bit constants. */ 578 if (tcg_out_movi_two(s, ret, arg)) { 579 return; 580 } 581 assert(TCG_TARGET_REG_BITS == 64); 582 583 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 584 tmp = tcg_tbrel_diff(s, (void *)arg); 585 if (tmp == (int16_t)tmp) { 586 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 587 return; 588 } 589 if (tcg_out_movi_two(s, ret, tmp)) { 590 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 591 return; 592 } 593 594 /* 595 * Load bitmasks with a right-shift. This is good for things 596 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 597 * or similarly using LUI. For this to work, bit 31 must be set. 598 */ 599 if (arg > 0 && (int32_t)arg < 0) { 600 sh = clz64(arg); 601 if (tcg_out_movi_one(s, ret, arg << sh)) { 602 tcg_out_dsrl(s, ret, ret, sh); 603 return; 604 } 605 } 606 607 /* 608 * Load slightly larger constants using left-shift. 609 * Limit this sequence to 3 insns to avoid too much expansion. 610 */ 611 sh = ctz64(arg); 612 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 613 tcg_out_dsll(s, ret, ret, sh); 614 return; 615 } 616 617 /* 618 * Load slightly larger constants using left-shift and add/or. 619 * Prefer addi with a negative immediate when that would produce 620 * a larger shift. For this to work, bits 15 and 16 must be set. 621 */ 622 lo = arg & 0xffff; 623 if (lo) { 624 if ((arg & 0x18000) == 0x18000) { 625 lo = (int16_t)arg; 626 } 627 tmp = arg - lo; 628 sh = ctz64(tmp); 629 tmp >>= sh; 630 if (tcg_out_movi_one(s, ret, tmp)) { 631 tcg_out_dsll(s, ret, ret, sh); 632 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 633 return; 634 } 635 } 636 637 /* Otherwise, put 64-bit constants into the constant pool. */ 638 tcg_out_movi_pool(s, ret, arg, tbreg); 639} 640 641static void tcg_out_movi(TCGContext *s, TCGType type, 642 TCGReg ret, tcg_target_long arg) 643{ 644 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 645 tcg_out_movi_int(s, type, ret, arg, tbreg); 646} 647 648static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 649{ 650 tcg_debug_assert(use_mips32r2_instructions); 651 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 652} 653 654static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 655{ 656 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 657} 658 659static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 660{ 661 tcg_debug_assert(use_mips32r2_instructions); 662 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 663} 664 665static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 666{ 667 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 668} 669 670static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 671{ 672 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 673 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 674} 675 676static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 if (rd != rs) { 679 tcg_out_ext32s(s, rd, rs); 680 } 681} 682 683static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 684{ 685 tcg_out_ext32u(s, rd, rs); 686} 687 688static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 689{ 690 tcg_out_ext32s(s, rd, rs); 691} 692 693static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 694{ 695 return false; 696} 697 698static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 699 tcg_target_long imm) 700{ 701 /* This function is only used for passing structs by reference. */ 702 g_assert_not_reached(); 703} 704 705static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 706{ 707 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 708 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 709 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 710 } 711} 712 713static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 714{ 715 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 716 if (use_mips32r2_instructions) { 717 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 718 } else { 719 tcg_out_dsll(s, ret, arg, 32); 720 tcg_out_dsrl(s, ret, ret, 32); 721 } 722} 723 724static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 725 TCGReg addr, intptr_t ofs) 726{ 727 int16_t lo = ofs; 728 if (ofs != lo) { 729 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 730 if (addr != TCG_REG_ZERO) { 731 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 732 } 733 addr = TCG_TMP0; 734 } 735 tcg_out_opc_imm(s, opc, data, addr, lo); 736} 737 738static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 739 TCGReg arg1, intptr_t arg2) 740{ 741 MIPSInsn opc = OPC_LD; 742 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 743 opc = OPC_LW; 744 } 745 tcg_out_ldst(s, opc, arg, arg1, arg2); 746} 747 748static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 749 TCGReg arg1, intptr_t arg2) 750{ 751 MIPSInsn opc = OPC_SD; 752 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 753 opc = OPC_SW; 754 } 755 tcg_out_ldst(s, opc, arg, arg1, arg2); 756} 757 758static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 759 TCGReg base, intptr_t ofs) 760{ 761 if (val == 0) { 762 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 763 return true; 764 } 765 return false; 766} 767 768static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 769 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 770 bool cbh, bool is_sub) 771{ 772 TCGReg th = TCG_TMP1; 773 774 /* If we have a negative constant such that negating it would 775 make the high part zero, we can (usually) eliminate one insn. */ 776 if (cbl && cbh && bh == -1 && bl != 0) { 777 bl = -bl; 778 bh = 0; 779 is_sub = !is_sub; 780 } 781 782 /* By operating on the high part first, we get to use the final 783 carry operation to move back from the temporary. */ 784 if (!cbh) { 785 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 786 } else if (bh != 0 || ah == rl) { 787 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 788 } else { 789 th = ah; 790 } 791 792 /* Note that tcg optimization should eliminate the bl == 0 case. */ 793 if (is_sub) { 794 if (cbl) { 795 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 796 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 797 } else { 798 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 799 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 800 } 801 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 802 } else { 803 if (cbl) { 804 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 805 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 806 } else if (rl == al && rl == bl) { 807 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 808 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 809 } else { 810 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 811 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 812 } 813 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 814 } 815} 816 817#define SETCOND_INV TCG_TARGET_NB_REGS 818#define SETCOND_NEZ (SETCOND_INV << 1) 819#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 820 821static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 822 TCGReg arg1, TCGReg arg2) 823{ 824 int flags = 0; 825 826 switch (cond) { 827 case TCG_COND_EQ: /* -> NE */ 828 case TCG_COND_GE: /* -> LT */ 829 case TCG_COND_GEU: /* -> LTU */ 830 case TCG_COND_LE: /* -> GT */ 831 case TCG_COND_LEU: /* -> GTU */ 832 cond = tcg_invert_cond(cond); 833 flags ^= SETCOND_INV; 834 break; 835 default: 836 break; 837 } 838 839 switch (cond) { 840 case TCG_COND_NE: 841 flags |= SETCOND_NEZ; 842 if (arg2 == 0) { 843 return arg1 | flags; 844 } 845 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 846 break; 847 case TCG_COND_LT: 848 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 849 break; 850 case TCG_COND_LTU: 851 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 852 break; 853 case TCG_COND_GT: 854 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 855 break; 856 case TCG_COND_GTU: 857 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 858 break; 859 default: 860 g_assert_not_reached(); 861 } 862 return ret | flags; 863} 864 865static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 866{ 867 if (tmpflags != ret) { 868 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 869 870 switch (tmpflags & SETCOND_FLAGS) { 871 case SETCOND_INV: 872 /* Intermediate result is boolean: simply invert. */ 873 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 874 break; 875 case SETCOND_NEZ: 876 /* Intermediate result is zero/non-zero: test != 0. */ 877 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 878 break; 879 case SETCOND_NEZ | SETCOND_INV: 880 /* Intermediate result is zero/non-zero: test == 0. */ 881 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 882 break; 883 default: 884 g_assert_not_reached(); 885 } 886 } 887} 888 889static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 890 TCGReg ret, TCGReg arg1, TCGReg arg2) 891{ 892 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 893 tcg_out_setcond_end(s, ret, tmpflags); 894} 895 896static const TCGOutOpSetcond outop_setcond = { 897 .base.static_constraint = C_O1_I2(r, r, rz), 898 .out_rrr = tgen_setcond, 899}; 900 901static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 902 TCGReg ret, TCGReg arg1, TCGReg arg2) 903{ 904 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 905 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 906 907 /* If intermediate result is zero/non-zero: test != 0. */ 908 if (tmpflags & SETCOND_NEZ) { 909 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 910 tmp = ret; 911 } 912 /* Produce the 0/-1 result. */ 913 if (tmpflags & SETCOND_INV) { 914 tcg_out_opc_imm(s, OPC_ADDIU, ret, tmp, -1); 915 } else { 916 tcg_out_opc_reg(s, OPC_SUBU, ret, TCG_REG_ZERO, tmp); 917 } 918} 919 920static const TCGOutOpSetcond outop_negsetcond = { 921 .base.static_constraint = C_O1_I2(r, r, rz), 922 .out_rrr = tgen_negsetcond, 923}; 924 925static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 926 TCGReg arg1, TCGReg arg2, TCGLabel *l) 927{ 928 static const MIPSInsn b_zero[16] = { 929 [TCG_COND_LT] = OPC_BLTZ, 930 [TCG_COND_GT] = OPC_BGTZ, 931 [TCG_COND_LE] = OPC_BLEZ, 932 [TCG_COND_GE] = OPC_BGEZ, 933 }; 934 935 MIPSInsn b_opc = 0; 936 937 switch (cond) { 938 case TCG_COND_EQ: 939 b_opc = OPC_BEQ; 940 break; 941 case TCG_COND_NE: 942 b_opc = OPC_BNE; 943 break; 944 case TCG_COND_LT: 945 case TCG_COND_GT: 946 case TCG_COND_LE: 947 case TCG_COND_GE: 948 if (arg2 == 0) { 949 b_opc = b_zero[cond]; 950 arg2 = arg1; 951 arg1 = 0; 952 } 953 break; 954 default: 955 break; 956 } 957 958 if (b_opc == 0) { 959 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 960 961 arg2 = TCG_REG_ZERO; 962 arg1 = tmpflags & ~SETCOND_FLAGS; 963 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 964 } 965 966 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 967 tcg_out_opc_br(s, b_opc, arg1, arg2); 968 tcg_out_nop(s); 969} 970 971static const TCGOutOpBrcond outop_brcond = { 972 .base.static_constraint = C_O0_I2(r, rz), 973 .out_rr = tgen_brcond, 974}; 975 976static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 977 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 978{ 979 int flags = 0; 980 981 switch (cond) { 982 case TCG_COND_EQ: 983 flags |= SETCOND_INV; 984 /* fall through */ 985 case TCG_COND_NE: 986 flags |= SETCOND_NEZ; 987 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 988 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 989 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 990 break; 991 992 default: 993 tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); 994 tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), 995 TCG_TMP1, al, bl); 996 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 997 tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); 998 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 999 break; 1000 } 1001 return ret | flags; 1002} 1003 1004static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1005 TCGReg al, TCGReg ah, 1006 TCGArg bl, bool const_bl, 1007 TCGArg bh, bool const_bh) 1008{ 1009 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1010 tcg_out_setcond_end(s, ret, tmpflags); 1011} 1012 1013#if TCG_TARGET_REG_BITS != 32 1014__attribute__((unused)) 1015#endif 1016static const TCGOutOpSetcond2 outop_setcond2 = { 1017 .base.static_constraint = C_O1_I4(r, r, r, rz, rz), 1018 .out = tgen_setcond2, 1019}; 1020 1021static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1022 TCGArg bl, bool const_bl, 1023 TCGArg bh, bool const_bh, TCGLabel *l) 1024{ 1025 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1026 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1027 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1028 1029 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1030 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1031 tcg_out_nop(s); 1032} 1033 1034#if TCG_TARGET_REG_BITS != 32 1035__attribute__((unused)) 1036#endif 1037static const TCGOutOpBrcond2 outop_brcond2 = { 1038 .base.static_constraint = C_O0_I4(r, r, rz, rz), 1039 .out = tgen_brcond2, 1040}; 1041 1042static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 1043 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 1044 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 1045{ 1046 int tmpflags; 1047 bool eqz; 1048 1049 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1050 if (use_mips32r6_instructions && v1 == 0) { 1051 v1 = v2; 1052 v2 = 0; 1053 cond = tcg_invert_cond(cond); 1054 } 1055 1056 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1057 c1 = tmpflags & ~SETCOND_FLAGS; 1058 eqz = tmpflags & SETCOND_INV; 1059 1060 if (use_mips32r6_instructions) { 1061 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1062 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1063 1064 if (v2 != 0) { 1065 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1066 } 1067 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1068 if (v2 != 0) { 1069 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1070 } 1071 return; 1072 } 1073 1074 /* This should be guaranteed via constraints */ 1075 tcg_debug_assert(v2 == ret); 1076 1077 if (use_movnz_instructions) { 1078 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1079 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1080 } else { 1081 /* Invert the condition in order to branch over the move. */ 1082 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1083 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1084 tcg_out_nop(s); 1085 /* Open-code tcg_out_mov, without the nop-move check. */ 1086 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1087 } 1088} 1089 1090static const TCGOutOpMovcond outop_movcond = { 1091 .base.static_constraint = (use_mips32r6_instructions 1092 ? C_O1_I4(r, r, rz, rz, rz) 1093 : C_O1_I4(r, r, rz, rz, 0)), 1094 .out = tgen_movcond, 1095}; 1096 1097static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1098{ 1099 /* 1100 * Note that __mips_abicalls requires the called function's address 1101 * to be loaded into $25 (t9), even if a direct branch is in range. 1102 * 1103 * For n64, always drop the pointer into the constant pool. 1104 * We can re-use helper addresses often and do not want any 1105 * of the longer sequences tcg_out_movi may try. 1106 */ 1107 if (sizeof(uintptr_t) == 8) { 1108 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1109 } else { 1110 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1111 } 1112 1113 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1114 if (tail) { 1115 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1116 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1117 } 1118 } else { 1119 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1120 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1121 } 1122 } 1123} 1124 1125static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1126 const TCGHelperInfo *info) 1127{ 1128 tcg_out_call_int(s, arg, false); 1129 tcg_out_nop(s); 1130} 1131 1132/* We have four temps, we might as well expose three of them. */ 1133static const TCGLdstHelperParam ldst_helper_param = { 1134 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1135}; 1136 1137static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1138{ 1139 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1140 MemOp opc = get_memop(l->oi); 1141 1142 /* resolve label address */ 1143 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1144 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1145 return false; 1146 } 1147 1148 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1149 1150 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1151 /* delay slot */ 1152 tcg_out_nop(s); 1153 1154 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1155 1156 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1157 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1158 return false; 1159 } 1160 1161 /* delay slot */ 1162 tcg_out_nop(s); 1163 return true; 1164} 1165 1166static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1167{ 1168 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1169 MemOp opc = get_memop(l->oi); 1170 1171 /* resolve label address */ 1172 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1173 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1174 return false; 1175 } 1176 1177 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1178 1179 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1180 /* delay slot */ 1181 tcg_out_nop(s); 1182 1183 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1184 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1185 return false; 1186 } 1187 1188 /* delay slot */ 1189 tcg_out_nop(s); 1190 return true; 1191} 1192 1193typedef struct { 1194 TCGReg base; 1195 TCGAtomAlign aa; 1196} HostAddress; 1197 1198bool tcg_target_has_memory_bswap(MemOp memop) 1199{ 1200 return false; 1201} 1202 1203/* We expect to use a 16-bit negative offset from ENV. */ 1204#define MIN_TLB_MASK_TABLE_OFS -32768 1205 1206/* 1207 * For system-mode, perform the TLB load and compare. 1208 * For user-mode, perform any required alignment tests. 1209 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1210 * is required and fill in @h with the host address for the fast path. 1211 */ 1212static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1213 TCGReg addr, MemOpIdx oi, bool is_ld) 1214{ 1215 TCGType addr_type = s->addr_type; 1216 TCGLabelQemuLdst *ldst = NULL; 1217 MemOp opc = get_memop(oi); 1218 MemOp a_bits; 1219 unsigned s_bits = opc & MO_SIZE; 1220 unsigned a_mask; 1221 TCGReg base; 1222 1223 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1224 a_bits = h->aa.align; 1225 a_mask = (1 << a_bits) - 1; 1226 1227 if (tcg_use_softmmu) { 1228 unsigned s_mask = (1 << s_bits) - 1; 1229 int mem_index = get_mmuidx(oi); 1230 int fast_off = tlb_mask_table_ofs(s, mem_index); 1231 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1232 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1233 int add_off = offsetof(CPUTLBEntry, addend); 1234 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1235 : offsetof(CPUTLBEntry, addr_write); 1236 1237 ldst = new_ldst_label(s); 1238 ldst->is_ld = is_ld; 1239 ldst->oi = oi; 1240 ldst->addr_reg = addr; 1241 1242 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1243 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1244 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1245 1246 /* Extract the TLB index from the address into TMP3. */ 1247 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1248 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1249 s->page_bits - CPU_TLB_ENTRY_BITS); 1250 } else { 1251 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1252 } 1253 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1254 1255 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1256 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1257 1258 /* Load the tlb comparator. */ 1259 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1260 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1261 cmp_off + HOST_BIG_ENDIAN * 4); 1262 } else { 1263 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1264 } 1265 1266 /* Load the tlb addend for the fast path. */ 1267 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1268 1269 /* 1270 * Mask the page bits, keeping the alignment bits to compare against. 1271 * For unaligned accesses, compare against the end of the access to 1272 * verify that it does not cross a page boundary. 1273 */ 1274 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1275 if (a_mask < s_mask) { 1276 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1277 || addr_type == TCG_TYPE_I32 1278 ? OPC_ADDIU : OPC_DADDIU), 1279 TCG_TMP2, addr, s_mask - a_mask); 1280 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1281 } else { 1282 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1283 } 1284 1285 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1286 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1287 tcg_out_ext32u(s, TCG_TMP2, addr); 1288 addr = TCG_TMP2; 1289 } 1290 1291 ldst->label_ptr[0] = s->code_ptr; 1292 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1293 1294 /* delay slot */ 1295 base = TCG_TMP3; 1296 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1297 } else { 1298 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1299 ldst = new_ldst_label(s); 1300 1301 ldst->is_ld = is_ld; 1302 ldst->oi = oi; 1303 ldst->addr_reg = addr; 1304 1305 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1306 tcg_debug_assert(a_bits < 16); 1307 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1308 1309 ldst->label_ptr[0] = s->code_ptr; 1310 if (use_mips32r6_instructions) { 1311 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1312 } else { 1313 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1314 tcg_out_nop(s); 1315 } 1316 } 1317 1318 base = addr; 1319 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1320 tcg_out_ext32u(s, TCG_REG_A0, base); 1321 base = TCG_REG_A0; 1322 } 1323 if (guest_base) { 1324 if (guest_base == (int16_t)guest_base) { 1325 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1326 } else { 1327 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1328 TCG_GUEST_BASE_REG); 1329 } 1330 base = TCG_REG_A0; 1331 } 1332 } 1333 1334 h->base = base; 1335 return ldst; 1336} 1337 1338static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1339 TCGReg base, MemOp opc, TCGType type) 1340{ 1341 switch (opc & MO_SSIZE) { 1342 case MO_UB: 1343 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1344 break; 1345 case MO_SB: 1346 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1347 break; 1348 case MO_UW: 1349 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1350 break; 1351 case MO_SW: 1352 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1353 break; 1354 case MO_UL: 1355 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1356 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1357 break; 1358 } 1359 /* FALLTHRU */ 1360 case MO_SL: 1361 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1362 break; 1363 case MO_UQ: 1364 /* Prefer to load from offset 0 first, but allow for overlap. */ 1365 if (TCG_TARGET_REG_BITS == 64) { 1366 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1367 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1368 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1369 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1370 } else { 1371 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1372 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1373 } 1374 break; 1375 default: 1376 g_assert_not_reached(); 1377 } 1378} 1379 1380static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1381 TCGReg base, MemOp opc, TCGType type) 1382{ 1383 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1384 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1385 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1386 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1387 bool sgn = opc & MO_SIGN; 1388 1389 switch (opc & MO_SIZE) { 1390 case MO_16: 1391 if (HOST_BIG_ENDIAN) { 1392 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1393 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1394 if (use_mips32r2_instructions) { 1395 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1396 } else { 1397 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1398 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1399 } 1400 } else if (use_mips32r2_instructions && lo != base) { 1401 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1402 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1403 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1404 } else { 1405 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1406 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1407 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1408 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1409 } 1410 break; 1411 1412 case MO_32: 1413 tcg_out_opc_imm(s, lw1, lo, base, 0); 1414 tcg_out_opc_imm(s, lw2, lo, base, 3); 1415 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1416 tcg_out_ext32u(s, lo, lo); 1417 } 1418 break; 1419 1420 case MO_64: 1421 if (TCG_TARGET_REG_BITS == 64) { 1422 tcg_out_opc_imm(s, ld1, lo, base, 0); 1423 tcg_out_opc_imm(s, ld2, lo, base, 7); 1424 } else { 1425 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1426 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1427 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1428 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1429 } 1430 break; 1431 1432 default: 1433 g_assert_not_reached(); 1434 } 1435} 1436 1437static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1438 TCGReg addr, MemOpIdx oi, TCGType data_type) 1439{ 1440 MemOp opc = get_memop(oi); 1441 TCGLabelQemuLdst *ldst; 1442 HostAddress h; 1443 1444 ldst = prepare_host_addr(s, &h, addr, oi, true); 1445 1446 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1447 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1448 } else { 1449 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1450 } 1451 1452 if (ldst) { 1453 ldst->type = data_type; 1454 ldst->datalo_reg = datalo; 1455 ldst->datahi_reg = datahi; 1456 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1457 } 1458} 1459 1460static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1461 TCGReg base, MemOp opc) 1462{ 1463 switch (opc & MO_SIZE) { 1464 case MO_8: 1465 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1466 break; 1467 case MO_16: 1468 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1469 break; 1470 case MO_32: 1471 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1472 break; 1473 case MO_64: 1474 if (TCG_TARGET_REG_BITS == 64) { 1475 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1476 } else { 1477 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1478 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1479 } 1480 break; 1481 default: 1482 g_assert_not_reached(); 1483 } 1484} 1485 1486static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1487 TCGReg base, MemOp opc) 1488{ 1489 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1490 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1491 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1492 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1493 1494 switch (opc & MO_SIZE) { 1495 case MO_16: 1496 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1497 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1498 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1499 break; 1500 1501 case MO_32: 1502 tcg_out_opc_imm(s, sw1, lo, base, 0); 1503 tcg_out_opc_imm(s, sw2, lo, base, 3); 1504 break; 1505 1506 case MO_64: 1507 if (TCG_TARGET_REG_BITS == 64) { 1508 tcg_out_opc_imm(s, sd1, lo, base, 0); 1509 tcg_out_opc_imm(s, sd2, lo, base, 7); 1510 } else { 1511 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1512 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1513 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1514 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1515 } 1516 break; 1517 1518 default: 1519 g_assert_not_reached(); 1520 } 1521} 1522 1523static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1524 TCGReg addr, MemOpIdx oi, TCGType data_type) 1525{ 1526 MemOp opc = get_memop(oi); 1527 TCGLabelQemuLdst *ldst; 1528 HostAddress h; 1529 1530 ldst = prepare_host_addr(s, &h, addr, oi, false); 1531 1532 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1533 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1534 } else { 1535 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1536 } 1537 1538 if (ldst) { 1539 ldst->type = data_type; 1540 ldst->datalo_reg = datalo; 1541 ldst->datahi_reg = datahi; 1542 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1543 } 1544} 1545 1546static void tcg_out_mb(TCGContext *s, TCGArg a0) 1547{ 1548 static const MIPSInsn sync[] = { 1549 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1550 as the former is an ordering barrier and the latter 1551 is a completion barrier. */ 1552 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1553 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1554 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1555 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1556 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1557 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1558 }; 1559 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1560} 1561 1562static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1563{ 1564 TCGReg base = TCG_REG_ZERO; 1565 int16_t lo = 0; 1566 1567 if (a0) { 1568 intptr_t ofs; 1569 if (TCG_TARGET_REG_BITS == 64) { 1570 ofs = tcg_tbrel_diff(s, (void *)a0); 1571 lo = ofs; 1572 if (ofs == lo) { 1573 base = TCG_REG_TB; 1574 } else { 1575 base = TCG_REG_V0; 1576 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1577 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1578 } 1579 } else { 1580 ofs = a0; 1581 lo = ofs; 1582 base = TCG_REG_V0; 1583 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1584 } 1585 } 1586 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1587 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1588 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1589 } 1590 /* delay slot */ 1591 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1592} 1593 1594static void tcg_out_goto_tb(TCGContext *s, int which) 1595{ 1596 intptr_t ofs = get_jmp_target_addr(s, which); 1597 TCGReg base, dest; 1598 1599 /* indirect jump method */ 1600 if (TCG_TARGET_REG_BITS == 64) { 1601 dest = TCG_REG_TB; 1602 base = TCG_REG_TB; 1603 ofs = tcg_tbrel_diff(s, (void *)ofs); 1604 } else { 1605 dest = TCG_TMP0; 1606 base = TCG_REG_ZERO; 1607 } 1608 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1609 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1610 /* delay slot */ 1611 tcg_out_nop(s); 1612 1613 set_jmp_reset_offset(s, which); 1614 if (TCG_TARGET_REG_BITS == 64) { 1615 /* For the unlinked case, need to reset TCG_REG_TB. */ 1616 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1617 -tcg_current_code_size(s)); 1618 } 1619} 1620 1621void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1622 uintptr_t jmp_rx, uintptr_t jmp_rw) 1623{ 1624 /* Always indirect, nothing to do */ 1625} 1626 1627 1628static void tgen_add(TCGContext *s, TCGType type, 1629 TCGReg a0, TCGReg a1, TCGReg a2) 1630{ 1631 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1632 tcg_out_opc_reg(s, insn, a0, a1, a2); 1633} 1634 1635static void tgen_addi(TCGContext *s, TCGType type, 1636 TCGReg a0, TCGReg a1, tcg_target_long a2) 1637{ 1638 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1639 tcg_out_opc_imm(s, insn, a0, a1, a2); 1640} 1641 1642static const TCGOutOpBinary outop_add = { 1643 .base.static_constraint = C_O1_I2(r, r, rJ), 1644 .out_rrr = tgen_add, 1645 .out_rri = tgen_addi, 1646}; 1647 1648static void tgen_and(TCGContext *s, TCGType type, 1649 TCGReg a0, TCGReg a1, TCGReg a2) 1650{ 1651 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1652} 1653 1654static void tgen_andi(TCGContext *s, TCGType type, 1655 TCGReg a0, TCGReg a1, tcg_target_long a2) 1656{ 1657 int msb; 1658 1659 if (a2 == (uint16_t)a2) { 1660 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1661 return; 1662 } 1663 1664 tcg_debug_assert(use_mips32r2_instructions); 1665 tcg_debug_assert(is_p2m1(a2)); 1666 msb = ctz64(~a2) - 1; 1667 if (type == TCG_TYPE_I32) { 1668 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1669 } else { 1670 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1671 } 1672} 1673 1674static const TCGOutOpBinary outop_and = { 1675 .base.static_constraint = C_O1_I2(r, r, rIK), 1676 .out_rrr = tgen_and, 1677 .out_rri = tgen_andi, 1678}; 1679 1680static const TCGOutOpBinary outop_andc = { 1681 .base.static_constraint = C_NotImplemented, 1682}; 1683 1684static void tgen_clz(TCGContext *s, TCGType type, 1685 TCGReg a0, TCGReg a1, TCGReg a2) 1686{ 1687 if (use_mips32r6_instructions) { 1688 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1689 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1690 tgen_movcond(s, TCG_TYPE_REG, TCG_COND_EQ, a0, a1, a2, false, 1691 TCG_TMP0, false, TCG_REG_ZERO, false); 1692 } else { 1693 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1694 if (a0 == a2) { 1695 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1696 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1697 } else if (a0 != a1) { 1698 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1699 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1700 } else { 1701 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1702 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1703 tcg_out_mov(s, type, a0, TCG_TMP0); 1704 } 1705 } 1706} 1707 1708static void tgen_clzi(TCGContext *s, TCGType type, 1709 TCGReg a0, TCGReg a1, tcg_target_long a2) 1710{ 1711 if (a2 == 0) { 1712 tgen_clz(s, type, a0, a1, TCG_REG_ZERO); 1713 } else if (use_mips32r6_instructions) { 1714 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1715 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1716 } else { 1717 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1718 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1719 } 1720} 1721 1722static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 1723{ 1724 return use_mips32r2_instructions ? C_O1_I2(r, r, rzW) : C_NotImplemented; 1725} 1726 1727static const TCGOutOpBinary outop_clz = { 1728 .base.static_constraint = C_Dynamic, 1729 .base.dynamic_constraint = cset_clz, 1730 .out_rrr = tgen_clz, 1731 .out_rri = tgen_clzi, 1732}; 1733 1734static const TCGOutOpUnary outop_ctpop = { 1735 .base.static_constraint = C_NotImplemented, 1736}; 1737 1738static const TCGOutOpBinary outop_ctz = { 1739 .base.static_constraint = C_NotImplemented, 1740}; 1741 1742static void tgen_divs(TCGContext *s, TCGType type, 1743 TCGReg a0, TCGReg a1, TCGReg a2) 1744{ 1745 if (use_mips32r6_instructions) { 1746 if (type == TCG_TYPE_I32) { 1747 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1748 } else { 1749 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1750 } 1751 } else { 1752 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1753 tcg_out_opc_reg(s, insn, 0, a1, a2); 1754 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1755 } 1756} 1757 1758static const TCGOutOpBinary outop_divs = { 1759 .base.static_constraint = C_O1_I2(r, r, r), 1760 .out_rrr = tgen_divs, 1761}; 1762 1763static const TCGOutOpDivRem outop_divs2 = { 1764 .base.static_constraint = C_NotImplemented, 1765}; 1766 1767static void tgen_divu(TCGContext *s, TCGType type, 1768 TCGReg a0, TCGReg a1, TCGReg a2) 1769{ 1770 if (use_mips32r6_instructions) { 1771 if (type == TCG_TYPE_I32) { 1772 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1773 } else { 1774 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1775 } 1776 } else { 1777 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1778 tcg_out_opc_reg(s, insn, 0, a1, a2); 1779 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1780 } 1781} 1782 1783static const TCGOutOpBinary outop_divu = { 1784 .base.static_constraint = C_O1_I2(r, r, r), 1785 .out_rrr = tgen_divu, 1786}; 1787 1788static const TCGOutOpDivRem outop_divu2 = { 1789 .base.static_constraint = C_NotImplemented, 1790}; 1791 1792static const TCGOutOpBinary outop_eqv = { 1793 .base.static_constraint = C_NotImplemented, 1794}; 1795 1796#if TCG_TARGET_REG_BITS == 64 1797static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 1798{ 1799 tcg_out_dsra(s, a0, a1, 32); 1800} 1801 1802static const TCGOutOpUnary outop_extrh_i64_i32 = { 1803 .base.static_constraint = C_O1_I1(r, r), 1804 .out_rr = tgen_extrh_i64_i32, 1805}; 1806#endif 1807 1808static void tgen_mul(TCGContext *s, TCGType type, 1809 TCGReg a0, TCGReg a1, TCGReg a2) 1810{ 1811 MIPSInsn insn; 1812 1813 if (type == TCG_TYPE_I32) { 1814 if (use_mips32_instructions) { 1815 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1816 return; 1817 } 1818 insn = OPC_MULT; 1819 } else { 1820 if (use_mips32r6_instructions) { 1821 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1822 return; 1823 } 1824 insn = OPC_DMULT; 1825 } 1826 tcg_out_opc_reg(s, insn, 0, a1, a2); 1827 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1828} 1829 1830static const TCGOutOpBinary outop_mul = { 1831 .base.static_constraint = C_O1_I2(r, r, r), 1832 .out_rrr = tgen_mul, 1833}; 1834 1835static void tgen_muls2(TCGContext *s, TCGType type, 1836 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1837{ 1838 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1839 tcg_out_opc_reg(s, insn, 0, a2, a3); 1840 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1841 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1842} 1843 1844static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1845{ 1846 return use_mips32r6_instructions ? C_NotImplemented : C_O2_I2(r, r, r, r); 1847} 1848 1849static const TCGOutOpMul2 outop_muls2 = { 1850 .base.static_constraint = C_Dynamic, 1851 .base.dynamic_constraint = cset_mul2, 1852 .out_rrrr = tgen_muls2, 1853}; 1854 1855static void tgen_mulsh(TCGContext *s, TCGType type, 1856 TCGReg a0, TCGReg a1, TCGReg a2) 1857{ 1858 if (use_mips32r6_instructions) { 1859 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH; 1860 tcg_out_opc_reg(s, insn, a0, a1, a2); 1861 } else { 1862 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1863 tcg_out_opc_reg(s, insn, 0, a1, a2); 1864 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1865 } 1866} 1867 1868static const TCGOutOpBinary outop_mulsh = { 1869 .base.static_constraint = C_O1_I2(r, r, r), 1870 .out_rrr = tgen_mulsh, 1871}; 1872 1873static void tgen_mulu2(TCGContext *s, TCGType type, 1874 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1875{ 1876 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1877 tcg_out_opc_reg(s, insn, 0, a2, a3); 1878 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1879 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1880} 1881 1882static const TCGOutOpMul2 outop_mulu2 = { 1883 .base.static_constraint = C_Dynamic, 1884 .base.dynamic_constraint = cset_mul2, 1885 .out_rrrr = tgen_mulu2, 1886}; 1887 1888static void tgen_muluh(TCGContext *s, TCGType type, 1889 TCGReg a0, TCGReg a1, TCGReg a2) 1890{ 1891 if (use_mips32r6_instructions) { 1892 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; 1893 tcg_out_opc_reg(s, insn, a0, a1, a2); 1894 } else { 1895 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1896 tcg_out_opc_reg(s, insn, 0, a1, a2); 1897 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1898 } 1899} 1900 1901static const TCGOutOpBinary outop_muluh = { 1902 .base.static_constraint = C_O1_I2(r, r, r), 1903 .out_rrr = tgen_muluh, 1904}; 1905 1906static const TCGOutOpBinary outop_nand = { 1907 .base.static_constraint = C_NotImplemented, 1908}; 1909 1910static void tgen_nor(TCGContext *s, TCGType type, 1911 TCGReg a0, TCGReg a1, TCGReg a2) 1912{ 1913 tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); 1914} 1915 1916static const TCGOutOpBinary outop_nor = { 1917 .base.static_constraint = C_O1_I2(r, r, r), 1918 .out_rrr = tgen_nor, 1919}; 1920 1921static void tgen_or(TCGContext *s, TCGType type, 1922 TCGReg a0, TCGReg a1, TCGReg a2) 1923{ 1924 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1925} 1926 1927static void tgen_ori(TCGContext *s, TCGType type, 1928 TCGReg a0, TCGReg a1, tcg_target_long a2) 1929{ 1930 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1931} 1932 1933static const TCGOutOpBinary outop_or = { 1934 .base.static_constraint = C_O1_I2(r, r, rI), 1935 .out_rrr = tgen_or, 1936 .out_rri = tgen_ori, 1937}; 1938 1939static const TCGOutOpBinary outop_orc = { 1940 .base.static_constraint = C_NotImplemented, 1941}; 1942 1943static void tgen_rems(TCGContext *s, TCGType type, 1944 TCGReg a0, TCGReg a1, TCGReg a2) 1945{ 1946 if (use_mips32r6_instructions) { 1947 if (type == TCG_TYPE_I32) { 1948 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1949 } else { 1950 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1951 } 1952 } else { 1953 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1954 tcg_out_opc_reg(s, insn, 0, a1, a2); 1955 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1956 } 1957} 1958 1959static const TCGOutOpBinary outop_rems = { 1960 .base.static_constraint = C_O1_I2(r, r, r), 1961 .out_rrr = tgen_rems, 1962}; 1963 1964static void tgen_remu(TCGContext *s, TCGType type, 1965 TCGReg a0, TCGReg a1, TCGReg a2) 1966{ 1967 if (use_mips32r6_instructions) { 1968 if (type == TCG_TYPE_I32) { 1969 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1970 } else { 1971 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1972 } 1973 } else { 1974 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1975 tcg_out_opc_reg(s, insn, 0, a1, a2); 1976 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1977 } 1978} 1979 1980static const TCGOutOpBinary outop_remu = { 1981 .base.static_constraint = C_O1_I2(r, r, r), 1982 .out_rrr = tgen_remu, 1983}; 1984 1985static const TCGOutOpBinary outop_rotl = { 1986 .base.static_constraint = C_NotImplemented, 1987}; 1988 1989static TCGConstraintSetIndex cset_rotr(TCGType type, unsigned flags) 1990{ 1991 return use_mips32r2_instructions ? C_O1_I2(r, r, ri) : C_NotImplemented; 1992} 1993 1994static void tgen_rotr(TCGContext *s, TCGType type, 1995 TCGReg a0, TCGReg a1, TCGReg a2) 1996{ 1997 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; 1998 tcg_out_opc_reg(s, insn, a0, a1, a2); 1999} 2000 2001static void tgen_rotri(TCGContext *s, TCGType type, 2002 TCGReg a0, TCGReg a1, tcg_target_long a2) 2003{ 2004 if (type == TCG_TYPE_I32) { 2005 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); 2006 } else { 2007 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2008 } 2009} 2010 2011static const TCGOutOpBinary outop_rotr = { 2012 .base.static_constraint = C_Dynamic, 2013 .base.dynamic_constraint = cset_rotr, 2014 .out_rrr = tgen_rotr, 2015 .out_rri = tgen_rotri, 2016}; 2017 2018static void tgen_sar(TCGContext *s, TCGType type, 2019 TCGReg a0, TCGReg a1, TCGReg a2) 2020{ 2021 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; 2022 tcg_out_opc_reg(s, insn, a0, a1, a2); 2023} 2024 2025static void tgen_sari(TCGContext *s, TCGType type, 2026 TCGReg a0, TCGReg a1, tcg_target_long a2) 2027{ 2028 if (type == TCG_TYPE_I32) { 2029 tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); 2030 } else { 2031 tcg_out_dsra(s, a0, a1, a2); 2032 } 2033} 2034 2035static const TCGOutOpBinary outop_sar = { 2036 .base.static_constraint = C_O1_I2(r, r, ri), 2037 .out_rrr = tgen_sar, 2038 .out_rri = tgen_sari, 2039}; 2040 2041static void tgen_shl(TCGContext *s, TCGType type, 2042 TCGReg a0, TCGReg a1, TCGReg a2) 2043{ 2044 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; 2045 tcg_out_opc_reg(s, insn, a0, a1, a2); 2046} 2047 2048static void tgen_shli(TCGContext *s, TCGType type, 2049 TCGReg a0, TCGReg a1, tcg_target_long a2) 2050{ 2051 if (type == TCG_TYPE_I32) { 2052 tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); 2053 } else { 2054 tcg_out_dsll(s, a0, a1, a2); 2055 } 2056} 2057 2058static const TCGOutOpBinary outop_shl = { 2059 .base.static_constraint = C_O1_I2(r, r, ri), 2060 .out_rrr = tgen_shl, 2061 .out_rri = tgen_shli, 2062}; 2063 2064static void tgen_shr(TCGContext *s, TCGType type, 2065 TCGReg a0, TCGReg a1, TCGReg a2) 2066{ 2067 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; 2068 tcg_out_opc_reg(s, insn, a0, a1, a2); 2069} 2070 2071static void tgen_shri(TCGContext *s, TCGType type, 2072 TCGReg a0, TCGReg a1, tcg_target_long a2) 2073{ 2074 if (type == TCG_TYPE_I32) { 2075 tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); 2076 } else { 2077 tcg_out_dsrl(s, a0, a1, a2); 2078 } 2079} 2080 2081static const TCGOutOpBinary outop_shr = { 2082 .base.static_constraint = C_O1_I2(r, r, ri), 2083 .out_rrr = tgen_shr, 2084 .out_rri = tgen_shri, 2085}; 2086 2087static void tgen_sub(TCGContext *s, TCGType type, 2088 TCGReg a0, TCGReg a1, TCGReg a2) 2089{ 2090 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU; 2091 tcg_out_opc_reg(s, insn, a0, a1, a2); 2092} 2093 2094static const TCGOutOpSubtract outop_sub = { 2095 .base.static_constraint = C_O1_I2(r, r, r), 2096 .out_rrr = tgen_sub, 2097}; 2098 2099static void tgen_xor(TCGContext *s, TCGType type, 2100 TCGReg a0, TCGReg a1, TCGReg a2) 2101{ 2102 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2103} 2104 2105static void tgen_xori(TCGContext *s, TCGType type, 2106 TCGReg a0, TCGReg a1, tcg_target_long a2) 2107{ 2108 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2109} 2110 2111static const TCGOutOpBinary outop_xor = { 2112 .base.static_constraint = C_O1_I2(r, r, rI), 2113 .out_rrr = tgen_xor, 2114 .out_rri = tgen_xori, 2115}; 2116 2117static void tgen_bswap16(TCGContext *s, TCGType type, 2118 TCGReg ret, TCGReg arg, unsigned flags) 2119{ 2120 /* With arg = abcd: */ 2121 if (use_mips32r2_instructions) { 2122 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 2123 if (flags & TCG_BSWAP_OS) { 2124 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 2125 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2126 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 2127 } 2128 return; 2129 } 2130 2131 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 2132 if (!(flags & TCG_BSWAP_IZ)) { 2133 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 2134 } 2135 if (flags & TCG_BSWAP_OS) { 2136 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 2137 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 2138 } else { 2139 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 2140 if (flags & TCG_BSWAP_OZ) { 2141 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 2142 } 2143 } 2144 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 2145} 2146 2147static const TCGOutOpBswap outop_bswap16 = { 2148 .base.static_constraint = C_O1_I1(r, r), 2149 .out_rr = tgen_bswap16, 2150}; 2151 2152static void tgen_bswap32(TCGContext *s, TCGType type, 2153 TCGReg ret, TCGReg arg, unsigned flags) 2154{ 2155 if (use_mips32r2_instructions) { 2156 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 2157 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 2158 if (flags & TCG_BSWAP_OZ) { 2159 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 2160 } 2161 } else { 2162 if (flags & TCG_BSWAP_OZ) { 2163 tcg_out_bswap_subr(s, bswap32u_addr); 2164 } else { 2165 tcg_out_bswap_subr(s, bswap32_addr); 2166 } 2167 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2168 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2169 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2170 } 2171} 2172 2173static const TCGOutOpBswap outop_bswap32 = { 2174 .base.static_constraint = C_O1_I1(r, r), 2175 .out_rr = tgen_bswap32, 2176}; 2177 2178#if TCG_TARGET_REG_BITS == 64 2179static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2180{ 2181 if (use_mips32r2_instructions) { 2182 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 2183 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 2184 } else { 2185 tcg_out_bswap_subr(s, bswap64_addr); 2186 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2187 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2188 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2189 } 2190} 2191 2192static const TCGOutOpUnary outop_bswap64 = { 2193 .base.static_constraint = C_O1_I1(r, r), 2194 .out_rr = tgen_bswap64, 2195}; 2196#endif /* TCG_TARGET_REG_BITS == 64 */ 2197 2198static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2199{ 2200 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2201} 2202 2203static const TCGOutOpUnary outop_neg = { 2204 .base.static_constraint = C_O1_I1(r, r), 2205 .out_rr = tgen_neg, 2206}; 2207 2208static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2209{ 2210 tgen_nor(s, type, a0, TCG_REG_ZERO, a1); 2211} 2212 2213static const TCGOutOpUnary outop_not = { 2214 .base.static_constraint = C_O1_I1(r, r), 2215 .out_rr = tgen_not, 2216}; 2217 2218static void tgen_deposit(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2219 TCGReg a2, unsigned ofs, unsigned len) 2220{ 2221 if (type == TCG_TYPE_I32) { 2222 tcg_out_opc_bf(s, OPC_INS, a0, a2, ofs + len - 1, ofs); 2223 } else { 2224 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2225 ofs + len - 1, ofs); 2226 } 2227} 2228 2229static const TCGOutOpDeposit outop_deposit = { 2230 .base.static_constraint = C_O1_I2(r, 0, rz), 2231 .out_rrr = tgen_deposit, 2232}; 2233 2234static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2235 unsigned ofs, unsigned len) 2236{ 2237 if (ofs == 0 && len <= 16) { 2238 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << len) - 1); 2239 } else if (type == TCG_TYPE_I32) { 2240 tcg_out_opc_bf(s, OPC_EXT, a0, a1, len - 1, ofs); 2241 } else { 2242 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2243 a0, a1, len - 1, ofs); 2244 } 2245} 2246 2247static const TCGOutOpExtract outop_extract = { 2248 .base.static_constraint = C_O1_I1(r, r), 2249 .out_rr = tgen_extract, 2250}; 2251 2252static void tgen_sextract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2253 unsigned ofs, unsigned len) 2254{ 2255 if (ofs == 0) { 2256 switch (len) { 2257 case 8: 2258 tcg_out_ext8s(s, type, a0, a1); 2259 return; 2260 case 16: 2261 tcg_out_ext16s(s, type, a0, a1); 2262 return; 2263 case 32: 2264 tcg_out_ext32s(s, a0, a1); 2265 return; 2266 } 2267 } 2268 g_assert_not_reached(); 2269} 2270 2271static const TCGOutOpExtract outop_sextract = { 2272 .base.static_constraint = C_O1_I1(r, r), 2273 .out_rr = tgen_sextract, 2274}; 2275 2276static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2277 const TCGArg args[TCG_MAX_OP_ARGS], 2278 const int const_args[TCG_MAX_OP_ARGS]) 2279{ 2280 MIPSInsn i1; 2281 TCGArg a0, a1, a2; 2282 2283 a0 = args[0]; 2284 a1 = args[1]; 2285 a2 = args[2]; 2286 2287 switch (opc) { 2288 case INDEX_op_goto_ptr: 2289 /* jmp to the given host address (could be epilogue) */ 2290 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2291 if (TCG_TARGET_REG_BITS == 64) { 2292 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 2293 } else { 2294 tcg_out_nop(s); 2295 } 2296 break; 2297 case INDEX_op_br: 2298 tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, 2299 TCG_REG_ZERO, TCG_REG_ZERO, arg_label(a0)); 2300 break; 2301 2302 case INDEX_op_ld8u_i32: 2303 case INDEX_op_ld8u_i64: 2304 i1 = OPC_LBU; 2305 goto do_ldst; 2306 case INDEX_op_ld8s_i32: 2307 case INDEX_op_ld8s_i64: 2308 i1 = OPC_LB; 2309 goto do_ldst; 2310 case INDEX_op_ld16u_i32: 2311 case INDEX_op_ld16u_i64: 2312 i1 = OPC_LHU; 2313 goto do_ldst; 2314 case INDEX_op_ld16s_i32: 2315 case INDEX_op_ld16s_i64: 2316 i1 = OPC_LH; 2317 goto do_ldst; 2318 case INDEX_op_ld_i32: 2319 case INDEX_op_ld32s_i64: 2320 i1 = OPC_LW; 2321 goto do_ldst; 2322 case INDEX_op_ld32u_i64: 2323 i1 = OPC_LWU; 2324 goto do_ldst; 2325 case INDEX_op_ld_i64: 2326 i1 = OPC_LD; 2327 goto do_ldst; 2328 case INDEX_op_st8_i32: 2329 case INDEX_op_st8_i64: 2330 i1 = OPC_SB; 2331 goto do_ldst; 2332 case INDEX_op_st16_i32: 2333 case INDEX_op_st16_i64: 2334 i1 = OPC_SH; 2335 goto do_ldst; 2336 case INDEX_op_st_i32: 2337 case INDEX_op_st32_i64: 2338 i1 = OPC_SW; 2339 goto do_ldst; 2340 case INDEX_op_st_i64: 2341 i1 = OPC_SD; 2342 do_ldst: 2343 tcg_out_ldst(s, i1, a0, a1, a2); 2344 break; 2345 2346 case INDEX_op_qemu_ld_i32: 2347 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2348 break; 2349 case INDEX_op_qemu_ld_i64: 2350 if (TCG_TARGET_REG_BITS == 64) { 2351 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2352 } else { 2353 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2354 } 2355 break; 2356 2357 case INDEX_op_qemu_st_i32: 2358 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2359 break; 2360 case INDEX_op_qemu_st_i64: 2361 if (TCG_TARGET_REG_BITS == 64) { 2362 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2363 } else { 2364 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2365 } 2366 break; 2367 2368 case INDEX_op_add2_i32: 2369 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2370 const_args[4], const_args[5], false); 2371 break; 2372 case INDEX_op_sub2_i32: 2373 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2374 const_args[4], const_args[5], true); 2375 break; 2376 2377 case INDEX_op_mb: 2378 tcg_out_mb(s, a0); 2379 break; 2380 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2381 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2382 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2383 default: 2384 g_assert_not_reached(); 2385 } 2386} 2387 2388static TCGConstraintSetIndex 2389tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2390{ 2391 switch (op) { 2392 case INDEX_op_goto_ptr: 2393 return C_O0_I1(r); 2394 2395 case INDEX_op_ld8u_i32: 2396 case INDEX_op_ld8s_i32: 2397 case INDEX_op_ld16u_i32: 2398 case INDEX_op_ld16s_i32: 2399 case INDEX_op_ld_i32: 2400 case INDEX_op_ld8u_i64: 2401 case INDEX_op_ld8s_i64: 2402 case INDEX_op_ld16u_i64: 2403 case INDEX_op_ld16s_i64: 2404 case INDEX_op_ld32s_i64: 2405 case INDEX_op_ld32u_i64: 2406 case INDEX_op_ld_i64: 2407 return C_O1_I1(r, r); 2408 2409 case INDEX_op_st8_i32: 2410 case INDEX_op_st16_i32: 2411 case INDEX_op_st_i32: 2412 case INDEX_op_st8_i64: 2413 case INDEX_op_st16_i64: 2414 case INDEX_op_st32_i64: 2415 case INDEX_op_st_i64: 2416 return C_O0_I2(rz, r); 2417 2418 case INDEX_op_add2_i32: 2419 case INDEX_op_sub2_i32: 2420 return C_O2_I4(r, r, rz, rz, rN, rN); 2421 2422 case INDEX_op_qemu_ld_i32: 2423 return C_O1_I1(r, r); 2424 case INDEX_op_qemu_st_i32: 2425 return C_O0_I2(rz, r); 2426 case INDEX_op_qemu_ld_i64: 2427 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2428 case INDEX_op_qemu_st_i64: 2429 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2430 2431 default: 2432 return C_NotImplemented; 2433 } 2434} 2435 2436static const int tcg_target_callee_save_regs[] = { 2437 TCG_REG_S0, 2438 TCG_REG_S1, 2439 TCG_REG_S2, 2440 TCG_REG_S3, 2441 TCG_REG_S4, 2442 TCG_REG_S5, 2443 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2444 TCG_REG_S7, /* used for guest_base */ 2445 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2446 TCG_REG_RA, /* should be last for ABI compliance */ 2447}; 2448 2449/* The Linux kernel doesn't provide any information about the available 2450 instruction set. Probe it using a signal handler. */ 2451 2452 2453#ifndef use_movnz_instructions 2454bool use_movnz_instructions = false; 2455#endif 2456 2457#ifndef use_mips32_instructions 2458bool use_mips32_instructions = false; 2459#endif 2460 2461#ifndef use_mips32r2_instructions 2462bool use_mips32r2_instructions = false; 2463#endif 2464 2465static volatile sig_atomic_t got_sigill; 2466 2467static void sigill_handler(int signo, siginfo_t *si, void *data) 2468{ 2469 /* Skip the faulty instruction */ 2470 ucontext_t *uc = (ucontext_t *)data; 2471 uc->uc_mcontext.pc += 4; 2472 2473 got_sigill = 1; 2474} 2475 2476static void tcg_target_detect_isa(void) 2477{ 2478 struct sigaction sa_old, sa_new; 2479 2480 memset(&sa_new, 0, sizeof(sa_new)); 2481 sa_new.sa_flags = SA_SIGINFO; 2482 sa_new.sa_sigaction = sigill_handler; 2483 sigaction(SIGILL, &sa_new, &sa_old); 2484 2485 /* Probe for movn/movz, necessary to implement movcond. */ 2486#ifndef use_movnz_instructions 2487 got_sigill = 0; 2488 asm volatile(".set push\n" 2489 ".set mips32\n" 2490 "movn $zero, $zero, $zero\n" 2491 "movz $zero, $zero, $zero\n" 2492 ".set pop\n" 2493 : : : ); 2494 use_movnz_instructions = !got_sigill; 2495#endif 2496 2497 /* Probe for MIPS32 instructions. As no subsetting is allowed 2498 by the specification, it is only necessary to probe for one 2499 of the instructions. */ 2500#ifndef use_mips32_instructions 2501 got_sigill = 0; 2502 asm volatile(".set push\n" 2503 ".set mips32\n" 2504 "mul $zero, $zero\n" 2505 ".set pop\n" 2506 : : : ); 2507 use_mips32_instructions = !got_sigill; 2508#endif 2509 2510 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2511 available. As no subsetting is allowed by the specification, 2512 it is only necessary to probe for one of the instructions. */ 2513#ifndef use_mips32r2_instructions 2514 if (use_mips32_instructions) { 2515 got_sigill = 0; 2516 asm volatile(".set push\n" 2517 ".set mips32r2\n" 2518 "seb $zero, $zero\n" 2519 ".set pop\n" 2520 : : : ); 2521 use_mips32r2_instructions = !got_sigill; 2522 } 2523#endif 2524 2525 sigaction(SIGILL, &sa_old, NULL); 2526} 2527 2528static tcg_insn_unit *align_code_ptr(TCGContext *s) 2529{ 2530 uintptr_t p = (uintptr_t)s->code_ptr; 2531 if (p & 15) { 2532 p = (p + 15) & -16; 2533 s->code_ptr = (void *)p; 2534 } 2535 return s->code_ptr; 2536} 2537 2538/* Stack frame parameters. */ 2539#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2540#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2541#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2542 2543#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2544 + TCG_TARGET_STACK_ALIGN - 1) \ 2545 & -TCG_TARGET_STACK_ALIGN) 2546#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2547 2548/* We're expecting to be able to use an immediate for frame allocation. */ 2549QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2550 2551/* Generate global QEMU prologue and epilogue code */ 2552static void tcg_target_qemu_prologue(TCGContext *s) 2553{ 2554 int i; 2555 2556 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2557 2558 /* TB prologue */ 2559 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2560 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2561 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2562 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2563 } 2564 2565 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2566 /* 2567 * The function call abi for n32 and n64 will have loaded $25 (t9) 2568 * with the address of the prologue, so we can use that instead 2569 * of TCG_REG_TB. 2570 */ 2571#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2572# error "Unknown mips abi" 2573#endif 2574 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2575 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2576 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2577 } 2578 2579 if (TCG_TARGET_REG_BITS == 64) { 2580 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2581 } 2582 2583 /* Call generated code */ 2584 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2585 /* delay slot */ 2586 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2587 2588 /* 2589 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2590 * and fall through to the rest of the epilogue. 2591 */ 2592 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2593 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2594 2595 /* TB epilogue */ 2596 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2597 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2598 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2599 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2600 } 2601 2602 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2603 /* delay slot */ 2604 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2605 2606 if (use_mips32r2_instructions) { 2607 return; 2608 } 2609 2610 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2611 clobbers TCG_TMP1, TCG_TMP2. */ 2612 2613 /* 2614 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2615 */ 2616 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2617 /* t3 = (ssss)d000 */ 2618 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2619 /* t1 = 000a */ 2620 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2621 /* t2 = 00c0 */ 2622 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2623 /* t3 = d00a */ 2624 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2625 /* t1 = 0abc */ 2626 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2627 /* t2 = 0c00 */ 2628 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2629 /* t1 = 00b0 */ 2630 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2631 /* t3 = dc0a */ 2632 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2633 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2634 /* t3 = dcba -- delay slot */ 2635 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2636 2637 if (TCG_TARGET_REG_BITS == 32) { 2638 return; 2639 } 2640 2641 /* 2642 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2643 */ 2644 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2645 /* t1 = (0000)000d */ 2646 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2647 /* t3 = 000a */ 2648 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2649 /* t1 = (0000)d000 */ 2650 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2651 /* t2 = 00c0 */ 2652 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2653 /* t3 = d00a */ 2654 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2655 /* t1 = 0abc */ 2656 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2657 /* t2 = 0c00 */ 2658 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2659 /* t1 = 00b0 */ 2660 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2661 /* t3 = dc0a */ 2662 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2663 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2664 /* t3 = dcba -- delay slot */ 2665 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2666 2667 /* 2668 * bswap64 -- 64-bit swap. a0 = abcdefgh 2669 */ 2670 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2671 /* t3 = h0000000 */ 2672 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2673 /* t1 = 0000000a */ 2674 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2675 2676 /* t2 = 000000g0 */ 2677 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2678 /* t3 = h000000a */ 2679 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2680 /* t1 = 00000abc */ 2681 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2682 /* t2 = 0g000000 */ 2683 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2684 /* t1 = 000000b0 */ 2685 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2686 2687 /* t3 = hg00000a */ 2688 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2689 /* t2 = 0000abcd */ 2690 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2691 /* t3 = hg0000ba */ 2692 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2693 2694 /* t1 = 000000c0 */ 2695 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2696 /* t2 = 0000000d */ 2697 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2698 /* t1 = 00000c00 */ 2699 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2700 /* t2 = 0000d000 */ 2701 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2702 2703 /* t3 = hg000cba */ 2704 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2705 /* t1 = 00abcdef */ 2706 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2707 /* t3 = hg00dcba */ 2708 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2709 2710 /* t2 = 0000000f */ 2711 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2712 /* t1 = 000000e0 */ 2713 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2714 /* t2 = 00f00000 */ 2715 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2716 /* t1 = 000e0000 */ 2717 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2718 2719 /* t3 = hgf0dcba */ 2720 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2721 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2722 /* t3 = hgfedcba -- delay slot */ 2723 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2724} 2725 2726static void tcg_out_tb_start(TCGContext *s) 2727{ 2728 /* nothing to do */ 2729} 2730 2731static void tcg_target_init(TCGContext *s) 2732{ 2733 tcg_target_detect_isa(); 2734 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2735 if (TCG_TARGET_REG_BITS == 64) { 2736 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2737 } 2738 2739 tcg_target_call_clobber_regs = 0; 2740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2741 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2742 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2743 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2744 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2745 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2746 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2747 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2748 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2749 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2750 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2751 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2752 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2753 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2754 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2755 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2756 2757 s->reserved_regs = 0; 2758 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2759 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2760 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2761 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2762 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2763 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2764 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2765 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2766 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2767 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2768 if (TCG_TARGET_REG_BITS == 64) { 2769 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2770 } 2771} 2772 2773typedef struct { 2774 DebugFrameHeader h; 2775 uint8_t fde_def_cfa[4]; 2776 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2777} DebugFrame; 2778 2779#define ELF_HOST_MACHINE EM_MIPS 2780/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2781 which is good because they're really quite complicated for MIPS. */ 2782 2783static const DebugFrame debug_frame = { 2784 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2785 .h.cie.id = -1, 2786 .h.cie.version = 1, 2787 .h.cie.code_align = 1, 2788 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2789 .h.cie.return_column = TCG_REG_RA, 2790 2791 /* Total FDE size does not include the "len" member. */ 2792 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2793 2794 .fde_def_cfa = { 2795 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2796 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2797 (FRAME_SIZE >> 7) 2798 }, 2799 .fde_reg_ofs = { 2800 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2801 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2802 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2803 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2804 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2805 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2806 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2807 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2808 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2809 } 2810}; 2811 2812void tcg_register_jit(const void *buf, size_t buf_size) 2813{ 2814 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2815} 2816