1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */ 191#define TCG_CT_CONST_WSZ 0x1000 /* word size */ 192 193#define ALL_GENERAL_REGS 0xffffffffu 194 195static bool is_p2m1(tcg_target_long val) 196{ 197 return val && ((val + 1) & val) == 0; 198} 199 200/* test if a constant matches the constraint */ 201static bool tcg_target_const_match(int64_t val, int ct, 202 TCGType type, TCGCond cond, int vece) 203{ 204 if (ct & TCG_CT_CONST) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_P2M1) 213 && use_mips32r2_instructions && is_p2m1(val)) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_WSZ) 216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 217 return 1; 218 } 219 return 0; 220} 221 222/* instruction opcodes */ 223typedef enum { 224 OPC_J = 002 << 26, 225 OPC_JAL = 003 << 26, 226 OPC_BEQ = 004 << 26, 227 OPC_BNE = 005 << 26, 228 OPC_BLEZ = 006 << 26, 229 OPC_BGTZ = 007 << 26, 230 OPC_ADDIU = 011 << 26, 231 OPC_SLTI = 012 << 26, 232 OPC_SLTIU = 013 << 26, 233 OPC_ANDI = 014 << 26, 234 OPC_ORI = 015 << 26, 235 OPC_XORI = 016 << 26, 236 OPC_LUI = 017 << 26, 237 OPC_BNEL = 025 << 26, 238 OPC_BNEZALC_R6 = 030 << 26, 239 OPC_DADDIU = 031 << 26, 240 OPC_LDL = 032 << 26, 241 OPC_LDR = 033 << 26, 242 OPC_LB = 040 << 26, 243 OPC_LH = 041 << 26, 244 OPC_LWL = 042 << 26, 245 OPC_LW = 043 << 26, 246 OPC_LBU = 044 << 26, 247 OPC_LHU = 045 << 26, 248 OPC_LWR = 046 << 26, 249 OPC_LWU = 047 << 26, 250 OPC_SB = 050 << 26, 251 OPC_SH = 051 << 26, 252 OPC_SWL = 052 << 26, 253 OPC_SW = 053 << 26, 254 OPC_SDL = 054 << 26, 255 OPC_SDR = 055 << 26, 256 OPC_SWR = 056 << 26, 257 OPC_LD = 067 << 26, 258 OPC_SD = 077 << 26, 259 260 OPC_SPECIAL = 000 << 26, 261 OPC_SLL = OPC_SPECIAL | 000, 262 OPC_SRL = OPC_SPECIAL | 002, 263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 264 OPC_SRA = OPC_SPECIAL | 003, 265 OPC_SLLV = OPC_SPECIAL | 004, 266 OPC_SRLV = OPC_SPECIAL | 006, 267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 268 OPC_SRAV = OPC_SPECIAL | 007, 269 OPC_JR_R5 = OPC_SPECIAL | 010, 270 OPC_JALR = OPC_SPECIAL | 011, 271 OPC_MOVZ = OPC_SPECIAL | 012, 272 OPC_MOVN = OPC_SPECIAL | 013, 273 OPC_SYNC = OPC_SPECIAL | 017, 274 OPC_MFHI = OPC_SPECIAL | 020, 275 OPC_MFLO = OPC_SPECIAL | 022, 276 OPC_DSLLV = OPC_SPECIAL | 024, 277 OPC_DSRLV = OPC_SPECIAL | 026, 278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 279 OPC_DSRAV = OPC_SPECIAL | 027, 280 OPC_MULT = OPC_SPECIAL | 030, 281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 282 OPC_MUH = OPC_SPECIAL | 030 | 0300, 283 OPC_MULTU = OPC_SPECIAL | 031, 284 OPC_MULU = OPC_SPECIAL | 031 | 0200, 285 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 286 OPC_DIV = OPC_SPECIAL | 032, 287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 288 OPC_MOD = OPC_SPECIAL | 032 | 0300, 289 OPC_DIVU = OPC_SPECIAL | 033, 290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 291 OPC_MODU = OPC_SPECIAL | 033 | 0300, 292 OPC_DMULT = OPC_SPECIAL | 034, 293 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 294 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 295 OPC_DMULTU = OPC_SPECIAL | 035, 296 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 298 OPC_DDIV = OPC_SPECIAL | 036, 299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 300 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 301 OPC_DDIVU = OPC_SPECIAL | 037, 302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 303 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 304 OPC_ADDU = OPC_SPECIAL | 041, 305 OPC_SUBU = OPC_SPECIAL | 043, 306 OPC_AND = OPC_SPECIAL | 044, 307 OPC_OR = OPC_SPECIAL | 045, 308 OPC_XOR = OPC_SPECIAL | 046, 309 OPC_NOR = OPC_SPECIAL | 047, 310 OPC_SLT = OPC_SPECIAL | 052, 311 OPC_SLTU = OPC_SPECIAL | 053, 312 OPC_DADDU = OPC_SPECIAL | 055, 313 OPC_DSUBU = OPC_SPECIAL | 057, 314 OPC_SELEQZ = OPC_SPECIAL | 065, 315 OPC_SELNEZ = OPC_SPECIAL | 067, 316 OPC_DSLL = OPC_SPECIAL | 070, 317 OPC_DSRL = OPC_SPECIAL | 072, 318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 319 OPC_DSRA = OPC_SPECIAL | 073, 320 OPC_DSLL32 = OPC_SPECIAL | 074, 321 OPC_DSRL32 = OPC_SPECIAL | 076, 322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 323 OPC_DSRA32 = OPC_SPECIAL | 077, 324 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 326 327 OPC_REGIMM = 001 << 26, 328 OPC_BLTZ = OPC_REGIMM | (000 << 16), 329 OPC_BGEZ = OPC_REGIMM | (001 << 16), 330 331 OPC_SPECIAL2 = 034 << 26, 332 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 333 OPC_CLZ = OPC_SPECIAL2 | 040, 334 OPC_DCLZ = OPC_SPECIAL2 | 044, 335 336 OPC_SPECIAL3 = 037 << 26, 337 OPC_EXT = OPC_SPECIAL3 | 000, 338 OPC_DEXTM = OPC_SPECIAL3 | 001, 339 OPC_DEXTU = OPC_SPECIAL3 | 002, 340 OPC_DEXT = OPC_SPECIAL3 | 003, 341 OPC_INS = OPC_SPECIAL3 | 004, 342 OPC_DINSM = OPC_SPECIAL3 | 005, 343 OPC_DINSU = OPC_SPECIAL3 | 006, 344 OPC_DINS = OPC_SPECIAL3 | 007, 345 OPC_WSBH = OPC_SPECIAL3 | 00240, 346 OPC_DSBH = OPC_SPECIAL3 | 00244, 347 OPC_DSHD = OPC_SPECIAL3 | 00544, 348 OPC_SEB = OPC_SPECIAL3 | 02040, 349 OPC_SEH = OPC_SPECIAL3 | 03040, 350 351 /* MIPS r6 doesn't have JR, JALR should be used instead */ 352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 353 354 /* 355 * MIPS r6 replaces MUL with an alternative encoding which is 356 * backwards-compatible at the assembly level. 357 */ 358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 359 360 /* MIPS r6 introduced names for weaker variants of SYNC. These are 361 backward compatible to previous architecture revisions. */ 362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 367 368 /* Aliases for convenience. */ 369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 371} MIPSInsn; 372 373/* 374 * Type reg 375 */ 376static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 377 TCGReg rd, TCGReg rs, TCGReg rt) 378{ 379 int32_t inst; 380 381 inst = opc; 382 inst |= (rs & 0x1F) << 21; 383 inst |= (rt & 0x1F) << 16; 384 inst |= (rd & 0x1F) << 11; 385 tcg_out32(s, inst); 386} 387 388/* 389 * Type immediate 390 */ 391static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 392 TCGReg rt, TCGReg rs, TCGArg imm) 393{ 394 int32_t inst; 395 396 inst = opc; 397 inst |= (rs & 0x1F) << 21; 398 inst |= (rt & 0x1F) << 16; 399 inst |= (imm & 0xffff); 400 tcg_out32(s, inst); 401} 402 403/* 404 * Type bitfield 405 */ 406static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 407 TCGReg rs, int msb, int lsb) 408{ 409 int32_t inst; 410 411 inst = opc; 412 inst |= (rs & 0x1F) << 21; 413 inst |= (rt & 0x1F) << 16; 414 inst |= (msb & 0x1F) << 11; 415 inst |= (lsb & 0x1F) << 6; 416 tcg_out32(s, inst); 417} 418 419static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 420 MIPSInsn oph, TCGReg rt, TCGReg rs, 421 int msb, int lsb) 422{ 423 if (lsb >= 32) { 424 opc = oph; 425 msb -= 32; 426 lsb -= 32; 427 } else if (msb >= 32) { 428 opc = opm; 429 msb -= 32; 430 } 431 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 432} 433 434/* 435 * Type branch 436 */ 437static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 438{ 439 tcg_out_opc_imm(s, opc, rt, rs, 0); 440} 441 442/* 443 * Type sa 444 */ 445static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 446 TCGReg rd, TCGReg rt, TCGArg sa) 447{ 448 int32_t inst; 449 450 inst = opc; 451 inst |= (rt & 0x1F) << 16; 452 inst |= (rd & 0x1F) << 11; 453 inst |= (sa & 0x1F) << 6; 454 tcg_out32(s, inst); 455 456} 457 458static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 459 TCGReg rd, TCGReg rt, TCGArg sa) 460{ 461 int32_t inst; 462 463 inst = (sa & 32 ? opc2 : opc1); 464 inst |= (rt & 0x1F) << 16; 465 inst |= (rd & 0x1F) << 11; 466 inst |= (sa & 0x1F) << 6; 467 tcg_out32(s, inst); 468} 469 470/* 471 * Type jump. 472 * Returns true if the branch was in range and the insn was emitted. 473 */ 474static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 475{ 476 uintptr_t dest = (uintptr_t)target; 477 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 478 int32_t inst; 479 480 /* The pc-region branch happens within the 256MB region of 481 the delay slot (thus the +4). */ 482 if ((from ^ dest) & -(1 << 28)) { 483 return false; 484 } 485 tcg_debug_assert((dest & 3) == 0); 486 487 inst = opc; 488 inst |= (dest >> 2) & 0x3ffffff; 489 tcg_out32(s, inst); 490 return true; 491} 492 493static void tcg_out_nop(TCGContext *s) 494{ 495 tcg_out32(s, 0); 496} 497 498static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 499{ 500 memset(p, 0, count * sizeof(tcg_insn_unit)); 501} 502 503static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 504{ 505 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 506} 507 508static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 509{ 510 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 511} 512 513static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 514{ 515 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 516} 517 518static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 519{ 520 /* Simple reg-reg move, optimising out the 'do nothing' case */ 521 if (ret != arg) { 522 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 523 } 524 return true; 525} 526 527static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 528{ 529 if (arg == (int16_t)arg) { 530 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 531 return true; 532 } 533 if (arg == (uint16_t)arg) { 534 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 535 return true; 536 } 537 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 538 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 539 return true; 540 } 541 return false; 542} 543 544static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 545{ 546 /* 547 * All signed 32-bit constants are loadable with two immediates, 548 * and everything else requires more work. 549 */ 550 if (arg == (int32_t)arg) { 551 if (!tcg_out_movi_one(s, ret, arg)) { 552 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 553 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 554 } 555 return true; 556 } 557 return false; 558} 559 560static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 561 tcg_target_long arg, TCGReg tbreg) 562{ 563 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 564 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 565} 566 567static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 568 tcg_target_long arg, TCGReg tbreg) 569{ 570 tcg_target_long tmp; 571 int sh, lo; 572 573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 574 arg = (int32_t)arg; 575 } 576 577 /* Load all 32-bit constants. */ 578 if (tcg_out_movi_two(s, ret, arg)) { 579 return; 580 } 581 assert(TCG_TARGET_REG_BITS == 64); 582 583 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 584 tmp = tcg_tbrel_diff(s, (void *)arg); 585 if (tmp == (int16_t)tmp) { 586 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 587 return; 588 } 589 if (tcg_out_movi_two(s, ret, tmp)) { 590 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 591 return; 592 } 593 594 /* 595 * Load bitmasks with a right-shift. This is good for things 596 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 597 * or similarly using LUI. For this to work, bit 31 must be set. 598 */ 599 if (arg > 0 && (int32_t)arg < 0) { 600 sh = clz64(arg); 601 if (tcg_out_movi_one(s, ret, arg << sh)) { 602 tcg_out_dsrl(s, ret, ret, sh); 603 return; 604 } 605 } 606 607 /* 608 * Load slightly larger constants using left-shift. 609 * Limit this sequence to 3 insns to avoid too much expansion. 610 */ 611 sh = ctz64(arg); 612 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 613 tcg_out_dsll(s, ret, ret, sh); 614 return; 615 } 616 617 /* 618 * Load slightly larger constants using left-shift and add/or. 619 * Prefer addi with a negative immediate when that would produce 620 * a larger shift. For this to work, bits 15 and 16 must be set. 621 */ 622 lo = arg & 0xffff; 623 if (lo) { 624 if ((arg & 0x18000) == 0x18000) { 625 lo = (int16_t)arg; 626 } 627 tmp = arg - lo; 628 sh = ctz64(tmp); 629 tmp >>= sh; 630 if (tcg_out_movi_one(s, ret, tmp)) { 631 tcg_out_dsll(s, ret, ret, sh); 632 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 633 return; 634 } 635 } 636 637 /* Otherwise, put 64-bit constants into the constant pool. */ 638 tcg_out_movi_pool(s, ret, arg, tbreg); 639} 640 641static void tcg_out_movi(TCGContext *s, TCGType type, 642 TCGReg ret, tcg_target_long arg) 643{ 644 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 645 tcg_out_movi_int(s, type, ret, arg, tbreg); 646} 647 648static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 649{ 650 tcg_debug_assert(use_mips32r2_instructions); 651 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 652} 653 654static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 655{ 656 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 657} 658 659static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 660{ 661 tcg_debug_assert(use_mips32r2_instructions); 662 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 663} 664 665static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 666{ 667 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 668} 669 670static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 671{ 672 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 673 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 674} 675 676static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 if (rd != rs) { 679 tcg_out_ext32s(s, rd, rs); 680 } 681} 682 683static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 684{ 685 tcg_out_ext32u(s, rd, rs); 686} 687 688static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 689{ 690 tcg_out_ext32s(s, rd, rs); 691} 692 693static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 694{ 695 return false; 696} 697 698static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 699 tcg_target_long imm) 700{ 701 /* This function is only used for passing structs by reference. */ 702 g_assert_not_reached(); 703} 704 705static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 706{ 707 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 708 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 709 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 710 } 711} 712 713static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 714{ 715 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 716 if (use_mips32r2_instructions) { 717 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 718 } else { 719 tcg_out_dsll(s, ret, arg, 32); 720 tcg_out_dsrl(s, ret, ret, 32); 721 } 722} 723 724static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 725 TCGReg addr, intptr_t ofs) 726{ 727 int16_t lo = ofs; 728 if (ofs != lo) { 729 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 730 if (addr != TCG_REG_ZERO) { 731 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 732 } 733 addr = TCG_TMP0; 734 } 735 tcg_out_opc_imm(s, opc, data, addr, lo); 736} 737 738static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 739 TCGReg arg1, intptr_t arg2) 740{ 741 MIPSInsn opc = OPC_LD; 742 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 743 opc = OPC_LW; 744 } 745 tcg_out_ldst(s, opc, arg, arg1, arg2); 746} 747 748static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 749 TCGReg arg1, intptr_t arg2) 750{ 751 MIPSInsn opc = OPC_SD; 752 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 753 opc = OPC_SW; 754 } 755 tcg_out_ldst(s, opc, arg, arg1, arg2); 756} 757 758static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 759 TCGReg base, intptr_t ofs) 760{ 761 if (val == 0) { 762 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 763 return true; 764 } 765 return false; 766} 767 768static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 769 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 770 bool cbh, bool is_sub) 771{ 772 TCGReg th = TCG_TMP1; 773 774 /* If we have a negative constant such that negating it would 775 make the high part zero, we can (usually) eliminate one insn. */ 776 if (cbl && cbh && bh == -1 && bl != 0) { 777 bl = -bl; 778 bh = 0; 779 is_sub = !is_sub; 780 } 781 782 /* By operating on the high part first, we get to use the final 783 carry operation to move back from the temporary. */ 784 if (!cbh) { 785 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 786 } else if (bh != 0 || ah == rl) { 787 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 788 } else { 789 th = ah; 790 } 791 792 /* Note that tcg optimization should eliminate the bl == 0 case. */ 793 if (is_sub) { 794 if (cbl) { 795 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 796 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 797 } else { 798 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 799 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 800 } 801 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 802 } else { 803 if (cbl) { 804 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 805 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 806 } else if (rl == al && rl == bl) { 807 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 808 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 809 } else { 810 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 811 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 812 } 813 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 814 } 815} 816 817#define SETCOND_INV TCG_TARGET_NB_REGS 818#define SETCOND_NEZ (SETCOND_INV << 1) 819#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 820 821static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 822 TCGReg arg1, TCGReg arg2) 823{ 824 int flags = 0; 825 826 switch (cond) { 827 case TCG_COND_EQ: /* -> NE */ 828 case TCG_COND_GE: /* -> LT */ 829 case TCG_COND_GEU: /* -> LTU */ 830 case TCG_COND_LE: /* -> GT */ 831 case TCG_COND_LEU: /* -> GTU */ 832 cond = tcg_invert_cond(cond); 833 flags ^= SETCOND_INV; 834 break; 835 default: 836 break; 837 } 838 839 switch (cond) { 840 case TCG_COND_NE: 841 flags |= SETCOND_NEZ; 842 if (arg2 == 0) { 843 return arg1 | flags; 844 } 845 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 846 break; 847 case TCG_COND_LT: 848 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 849 break; 850 case TCG_COND_LTU: 851 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 852 break; 853 case TCG_COND_GT: 854 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 855 break; 856 case TCG_COND_GTU: 857 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 858 break; 859 default: 860 g_assert_not_reached(); 861 } 862 return ret | flags; 863} 864 865static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 866{ 867 if (tmpflags != ret) { 868 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 869 870 switch (tmpflags & SETCOND_FLAGS) { 871 case SETCOND_INV: 872 /* Intermediate result is boolean: simply invert. */ 873 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 874 break; 875 case SETCOND_NEZ: 876 /* Intermediate result is zero/non-zero: test != 0. */ 877 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 878 break; 879 case SETCOND_NEZ | SETCOND_INV: 880 /* Intermediate result is zero/non-zero: test == 0. */ 881 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 882 break; 883 default: 884 g_assert_not_reached(); 885 } 886 } 887} 888 889static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 890 TCGReg ret, TCGReg arg1, TCGReg arg2) 891{ 892 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 893 tcg_out_setcond_end(s, ret, tmpflags); 894} 895 896static const TCGOutOpSetcond outop_setcond = { 897 .base.static_constraint = C_O1_I2(r, r, rz), 898 .out_rrr = tgen_setcond, 899}; 900 901static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 902 TCGReg ret, TCGReg arg1, TCGReg arg2) 903{ 904 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 905 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 906 907 /* If intermediate result is zero/non-zero: test != 0. */ 908 if (tmpflags & SETCOND_NEZ) { 909 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 910 tmp = ret; 911 } 912 /* Produce the 0/-1 result. */ 913 if (tmpflags & SETCOND_INV) { 914 tcg_out_opc_imm(s, OPC_ADDIU, ret, tmp, -1); 915 } else { 916 tcg_out_opc_reg(s, OPC_SUBU, ret, TCG_REG_ZERO, tmp); 917 } 918} 919 920static const TCGOutOpSetcond outop_negsetcond = { 921 .base.static_constraint = C_O1_I2(r, r, rz), 922 .out_rrr = tgen_negsetcond, 923}; 924 925static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 926 TCGReg arg1, TCGReg arg2, TCGLabel *l) 927{ 928 static const MIPSInsn b_zero[16] = { 929 [TCG_COND_LT] = OPC_BLTZ, 930 [TCG_COND_GT] = OPC_BGTZ, 931 [TCG_COND_LE] = OPC_BLEZ, 932 [TCG_COND_GE] = OPC_BGEZ, 933 }; 934 935 MIPSInsn b_opc = 0; 936 937 switch (cond) { 938 case TCG_COND_EQ: 939 b_opc = OPC_BEQ; 940 break; 941 case TCG_COND_NE: 942 b_opc = OPC_BNE; 943 break; 944 case TCG_COND_LT: 945 case TCG_COND_GT: 946 case TCG_COND_LE: 947 case TCG_COND_GE: 948 if (arg2 == 0) { 949 b_opc = b_zero[cond]; 950 arg2 = arg1; 951 arg1 = 0; 952 } 953 break; 954 default: 955 break; 956 } 957 958 if (b_opc == 0) { 959 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 960 961 arg2 = TCG_REG_ZERO; 962 arg1 = tmpflags & ~SETCOND_FLAGS; 963 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 964 } 965 966 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 967 tcg_out_opc_br(s, b_opc, arg1, arg2); 968 tcg_out_nop(s); 969} 970 971static const TCGOutOpBrcond outop_brcond = { 972 .base.static_constraint = C_O0_I2(r, rz), 973 .out_rr = tgen_brcond, 974}; 975 976static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 977 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 978{ 979 int flags = 0; 980 981 switch (cond) { 982 case TCG_COND_EQ: 983 flags |= SETCOND_INV; 984 /* fall through */ 985 case TCG_COND_NE: 986 flags |= SETCOND_NEZ; 987 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 988 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 989 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 990 break; 991 992 default: 993 tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); 994 tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), 995 TCG_TMP1, al, bl); 996 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 997 tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); 998 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 999 break; 1000 } 1001 return ret | flags; 1002} 1003 1004static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1005 TCGReg al, TCGReg ah, 1006 TCGArg bl, bool const_bl, 1007 TCGArg bh, bool const_bh) 1008{ 1009 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1010 tcg_out_setcond_end(s, ret, tmpflags); 1011} 1012 1013#if TCG_TARGET_REG_BITS != 32 1014__attribute__((unused)) 1015#endif 1016static const TCGOutOpSetcond2 outop_setcond2 = { 1017 .base.static_constraint = C_O1_I4(r, r, r, rz, rz), 1018 .out = tgen_setcond2, 1019}; 1020 1021static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1022 TCGArg bl, bool const_bl, 1023 TCGArg bh, bool const_bh, TCGLabel *l) 1024{ 1025 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1026 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1027 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1028 1029 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1030 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1031 tcg_out_nop(s); 1032} 1033 1034#if TCG_TARGET_REG_BITS != 32 1035__attribute__((unused)) 1036#endif 1037static const TCGOutOpBrcond2 outop_brcond2 = { 1038 .base.static_constraint = C_O0_I4(r, r, rz, rz), 1039 .out = tgen_brcond2, 1040}; 1041 1042static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 1043 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 1044 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 1045{ 1046 int tmpflags; 1047 bool eqz; 1048 1049 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1050 if (use_mips32r6_instructions && v1 == 0) { 1051 v1 = v2; 1052 v2 = 0; 1053 cond = tcg_invert_cond(cond); 1054 } 1055 1056 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1057 c1 = tmpflags & ~SETCOND_FLAGS; 1058 eqz = tmpflags & SETCOND_INV; 1059 1060 if (use_mips32r6_instructions) { 1061 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1062 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1063 1064 if (v2 != 0) { 1065 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1066 } 1067 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1068 if (v2 != 0) { 1069 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1070 } 1071 return; 1072 } 1073 1074 /* This should be guaranteed via constraints */ 1075 tcg_debug_assert(v2 == ret); 1076 1077 if (use_movnz_instructions) { 1078 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1079 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1080 } else { 1081 /* Invert the condition in order to branch over the move. */ 1082 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1083 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1084 tcg_out_nop(s); 1085 /* Open-code tcg_out_mov, without the nop-move check. */ 1086 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1087 } 1088} 1089 1090static const TCGOutOpMovcond outop_movcond = { 1091 .base.static_constraint = (use_mips32r6_instructions 1092 ? C_O1_I4(r, r, rz, rz, rz) 1093 : C_O1_I4(r, r, rz, rz, 0)), 1094 .out = tgen_movcond, 1095}; 1096 1097static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1098{ 1099 /* 1100 * Note that __mips_abicalls requires the called function's address 1101 * to be loaded into $25 (t9), even if a direct branch is in range. 1102 * 1103 * For n64, always drop the pointer into the constant pool. 1104 * We can re-use helper addresses often and do not want any 1105 * of the longer sequences tcg_out_movi may try. 1106 */ 1107 if (sizeof(uintptr_t) == 8) { 1108 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1109 } else { 1110 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1111 } 1112 1113 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1114 if (tail) { 1115 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1116 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1117 } 1118 } else { 1119 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1120 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1121 } 1122 } 1123} 1124 1125static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1126 const TCGHelperInfo *info) 1127{ 1128 tcg_out_call_int(s, arg, false); 1129 tcg_out_nop(s); 1130} 1131 1132/* We have four temps, we might as well expose three of them. */ 1133static const TCGLdstHelperParam ldst_helper_param = { 1134 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1135}; 1136 1137static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1138{ 1139 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1140 MemOp opc = get_memop(l->oi); 1141 1142 /* resolve label address */ 1143 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1144 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1145 return false; 1146 } 1147 1148 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1149 1150 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1151 /* delay slot */ 1152 tcg_out_nop(s); 1153 1154 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1155 1156 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1157 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1158 return false; 1159 } 1160 1161 /* delay slot */ 1162 tcg_out_nop(s); 1163 return true; 1164} 1165 1166static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1167{ 1168 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1169 MemOp opc = get_memop(l->oi); 1170 1171 /* resolve label address */ 1172 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1173 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1174 return false; 1175 } 1176 1177 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1178 1179 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1180 /* delay slot */ 1181 tcg_out_nop(s); 1182 1183 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1184 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1185 return false; 1186 } 1187 1188 /* delay slot */ 1189 tcg_out_nop(s); 1190 return true; 1191} 1192 1193typedef struct { 1194 TCGReg base; 1195 TCGAtomAlign aa; 1196} HostAddress; 1197 1198bool tcg_target_has_memory_bswap(MemOp memop) 1199{ 1200 return false; 1201} 1202 1203/* We expect to use a 16-bit negative offset from ENV. */ 1204#define MIN_TLB_MASK_TABLE_OFS -32768 1205 1206/* 1207 * For system-mode, perform the TLB load and compare. 1208 * For user-mode, perform any required alignment tests. 1209 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1210 * is required and fill in @h with the host address for the fast path. 1211 */ 1212static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1213 TCGReg addr, MemOpIdx oi, bool is_ld) 1214{ 1215 TCGType addr_type = s->addr_type; 1216 TCGLabelQemuLdst *ldst = NULL; 1217 MemOp opc = get_memop(oi); 1218 MemOp a_bits; 1219 unsigned s_bits = opc & MO_SIZE; 1220 unsigned a_mask; 1221 TCGReg base; 1222 1223 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1224 a_bits = h->aa.align; 1225 a_mask = (1 << a_bits) - 1; 1226 1227 if (tcg_use_softmmu) { 1228 unsigned s_mask = (1 << s_bits) - 1; 1229 int mem_index = get_mmuidx(oi); 1230 int fast_off = tlb_mask_table_ofs(s, mem_index); 1231 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1232 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1233 int add_off = offsetof(CPUTLBEntry, addend); 1234 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1235 : offsetof(CPUTLBEntry, addr_write); 1236 1237 ldst = new_ldst_label(s); 1238 ldst->is_ld = is_ld; 1239 ldst->oi = oi; 1240 ldst->addr_reg = addr; 1241 1242 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1243 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1244 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1245 1246 /* Extract the TLB index from the address into TMP3. */ 1247 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1248 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1249 s->page_bits - CPU_TLB_ENTRY_BITS); 1250 } else { 1251 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1252 } 1253 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1254 1255 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1256 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1257 1258 /* Load the tlb comparator. */ 1259 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1260 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1261 cmp_off + HOST_BIG_ENDIAN * 4); 1262 } else { 1263 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1264 } 1265 1266 /* Load the tlb addend for the fast path. */ 1267 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1268 1269 /* 1270 * Mask the page bits, keeping the alignment bits to compare against. 1271 * For unaligned accesses, compare against the end of the access to 1272 * verify that it does not cross a page boundary. 1273 */ 1274 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1275 if (a_mask < s_mask) { 1276 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1277 || addr_type == TCG_TYPE_I32 1278 ? OPC_ADDIU : OPC_DADDIU), 1279 TCG_TMP2, addr, s_mask - a_mask); 1280 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1281 } else { 1282 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1283 } 1284 1285 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1286 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1287 tcg_out_ext32u(s, TCG_TMP2, addr); 1288 addr = TCG_TMP2; 1289 } 1290 1291 ldst->label_ptr[0] = s->code_ptr; 1292 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1293 1294 /* delay slot */ 1295 base = TCG_TMP3; 1296 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1297 } else { 1298 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1299 ldst = new_ldst_label(s); 1300 1301 ldst->is_ld = is_ld; 1302 ldst->oi = oi; 1303 ldst->addr_reg = addr; 1304 1305 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1306 tcg_debug_assert(a_bits < 16); 1307 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1308 1309 ldst->label_ptr[0] = s->code_ptr; 1310 if (use_mips32r6_instructions) { 1311 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1312 } else { 1313 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1314 tcg_out_nop(s); 1315 } 1316 } 1317 1318 base = addr; 1319 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1320 tcg_out_ext32u(s, TCG_REG_A0, base); 1321 base = TCG_REG_A0; 1322 } 1323 if (guest_base) { 1324 if (guest_base == (int16_t)guest_base) { 1325 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1326 } else { 1327 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1328 TCG_GUEST_BASE_REG); 1329 } 1330 base = TCG_REG_A0; 1331 } 1332 } 1333 1334 h->base = base; 1335 return ldst; 1336} 1337 1338static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1339 TCGReg base, MemOp opc, TCGType type) 1340{ 1341 switch (opc & MO_SSIZE) { 1342 case MO_UB: 1343 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1344 break; 1345 case MO_SB: 1346 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1347 break; 1348 case MO_UW: 1349 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1350 break; 1351 case MO_SW: 1352 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1353 break; 1354 case MO_UL: 1355 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1356 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1357 break; 1358 } 1359 /* FALLTHRU */ 1360 case MO_SL: 1361 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1362 break; 1363 case MO_UQ: 1364 /* Prefer to load from offset 0 first, but allow for overlap. */ 1365 if (TCG_TARGET_REG_BITS == 64) { 1366 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1367 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1368 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1369 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1370 } else { 1371 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1372 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1373 } 1374 break; 1375 default: 1376 g_assert_not_reached(); 1377 } 1378} 1379 1380static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1381 TCGReg base, MemOp opc, TCGType type) 1382{ 1383 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1384 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1385 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1386 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1387 bool sgn = opc & MO_SIGN; 1388 1389 switch (opc & MO_SIZE) { 1390 case MO_16: 1391 if (HOST_BIG_ENDIAN) { 1392 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1393 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1394 if (use_mips32r2_instructions) { 1395 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1396 } else { 1397 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1398 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1399 } 1400 } else if (use_mips32r2_instructions && lo != base) { 1401 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1402 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1403 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1404 } else { 1405 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1406 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1407 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1408 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1409 } 1410 break; 1411 1412 case MO_32: 1413 tcg_out_opc_imm(s, lw1, lo, base, 0); 1414 tcg_out_opc_imm(s, lw2, lo, base, 3); 1415 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1416 tcg_out_ext32u(s, lo, lo); 1417 } 1418 break; 1419 1420 case MO_64: 1421 if (TCG_TARGET_REG_BITS == 64) { 1422 tcg_out_opc_imm(s, ld1, lo, base, 0); 1423 tcg_out_opc_imm(s, ld2, lo, base, 7); 1424 } else { 1425 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1426 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1427 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1428 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1429 } 1430 break; 1431 1432 default: 1433 g_assert_not_reached(); 1434 } 1435} 1436 1437static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1438 TCGReg addr, MemOpIdx oi, TCGType data_type) 1439{ 1440 MemOp opc = get_memop(oi); 1441 TCGLabelQemuLdst *ldst; 1442 HostAddress h; 1443 1444 ldst = prepare_host_addr(s, &h, addr, oi, true); 1445 1446 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1447 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1448 } else { 1449 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1450 } 1451 1452 if (ldst) { 1453 ldst->type = data_type; 1454 ldst->datalo_reg = datalo; 1455 ldst->datahi_reg = datahi; 1456 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1457 } 1458} 1459 1460static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1461 TCGReg base, MemOp opc) 1462{ 1463 switch (opc & MO_SIZE) { 1464 case MO_8: 1465 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1466 break; 1467 case MO_16: 1468 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1469 break; 1470 case MO_32: 1471 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1472 break; 1473 case MO_64: 1474 if (TCG_TARGET_REG_BITS == 64) { 1475 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1476 } else { 1477 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1478 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1479 } 1480 break; 1481 default: 1482 g_assert_not_reached(); 1483 } 1484} 1485 1486static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1487 TCGReg base, MemOp opc) 1488{ 1489 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1490 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1491 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1492 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1493 1494 switch (opc & MO_SIZE) { 1495 case MO_16: 1496 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1497 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1498 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1499 break; 1500 1501 case MO_32: 1502 tcg_out_opc_imm(s, sw1, lo, base, 0); 1503 tcg_out_opc_imm(s, sw2, lo, base, 3); 1504 break; 1505 1506 case MO_64: 1507 if (TCG_TARGET_REG_BITS == 64) { 1508 tcg_out_opc_imm(s, sd1, lo, base, 0); 1509 tcg_out_opc_imm(s, sd2, lo, base, 7); 1510 } else { 1511 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1512 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1513 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1514 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1515 } 1516 break; 1517 1518 default: 1519 g_assert_not_reached(); 1520 } 1521} 1522 1523static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1524 TCGReg addr, MemOpIdx oi, TCGType data_type) 1525{ 1526 MemOp opc = get_memop(oi); 1527 TCGLabelQemuLdst *ldst; 1528 HostAddress h; 1529 1530 ldst = prepare_host_addr(s, &h, addr, oi, false); 1531 1532 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1533 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1534 } else { 1535 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1536 } 1537 1538 if (ldst) { 1539 ldst->type = data_type; 1540 ldst->datalo_reg = datalo; 1541 ldst->datahi_reg = datahi; 1542 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1543 } 1544} 1545 1546static void tcg_out_mb(TCGContext *s, TCGArg a0) 1547{ 1548 static const MIPSInsn sync[] = { 1549 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1550 as the former is an ordering barrier and the latter 1551 is a completion barrier. */ 1552 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1553 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1554 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1555 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1556 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1557 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1558 }; 1559 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1560} 1561 1562static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1563{ 1564 TCGReg base = TCG_REG_ZERO; 1565 int16_t lo = 0; 1566 1567 if (a0) { 1568 intptr_t ofs; 1569 if (TCG_TARGET_REG_BITS == 64) { 1570 ofs = tcg_tbrel_diff(s, (void *)a0); 1571 lo = ofs; 1572 if (ofs == lo) { 1573 base = TCG_REG_TB; 1574 } else { 1575 base = TCG_REG_V0; 1576 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1577 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1578 } 1579 } else { 1580 ofs = a0; 1581 lo = ofs; 1582 base = TCG_REG_V0; 1583 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1584 } 1585 } 1586 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1587 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1588 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1589 } 1590 /* delay slot */ 1591 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1592} 1593 1594static void tcg_out_goto_tb(TCGContext *s, int which) 1595{ 1596 intptr_t ofs = get_jmp_target_addr(s, which); 1597 TCGReg base, dest; 1598 1599 /* indirect jump method */ 1600 if (TCG_TARGET_REG_BITS == 64) { 1601 dest = TCG_REG_TB; 1602 base = TCG_REG_TB; 1603 ofs = tcg_tbrel_diff(s, (void *)ofs); 1604 } else { 1605 dest = TCG_TMP0; 1606 base = TCG_REG_ZERO; 1607 } 1608 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1609 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1610 /* delay slot */ 1611 tcg_out_nop(s); 1612 1613 set_jmp_reset_offset(s, which); 1614 if (TCG_TARGET_REG_BITS == 64) { 1615 /* For the unlinked case, need to reset TCG_REG_TB. */ 1616 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1617 -tcg_current_code_size(s)); 1618 } 1619} 1620 1621void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1622 uintptr_t jmp_rx, uintptr_t jmp_rw) 1623{ 1624 /* Always indirect, nothing to do */ 1625} 1626 1627 1628static void tgen_add(TCGContext *s, TCGType type, 1629 TCGReg a0, TCGReg a1, TCGReg a2) 1630{ 1631 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1632 tcg_out_opc_reg(s, insn, a0, a1, a2); 1633} 1634 1635static void tgen_addi(TCGContext *s, TCGType type, 1636 TCGReg a0, TCGReg a1, tcg_target_long a2) 1637{ 1638 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1639 tcg_out_opc_imm(s, insn, a0, a1, a2); 1640} 1641 1642static const TCGOutOpBinary outop_add = { 1643 .base.static_constraint = C_O1_I2(r, r, rJ), 1644 .out_rrr = tgen_add, 1645 .out_rri = tgen_addi, 1646}; 1647 1648static void tgen_and(TCGContext *s, TCGType type, 1649 TCGReg a0, TCGReg a1, TCGReg a2) 1650{ 1651 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1652} 1653 1654static void tgen_andi(TCGContext *s, TCGType type, 1655 TCGReg a0, TCGReg a1, tcg_target_long a2) 1656{ 1657 int msb; 1658 1659 if (a2 == (uint16_t)a2) { 1660 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1661 return; 1662 } 1663 1664 tcg_debug_assert(use_mips32r2_instructions); 1665 tcg_debug_assert(is_p2m1(a2)); 1666 msb = ctz64(~a2) - 1; 1667 if (type == TCG_TYPE_I32) { 1668 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1669 } else { 1670 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1671 } 1672} 1673 1674static const TCGOutOpBinary outop_and = { 1675 .base.static_constraint = C_O1_I2(r, r, rIK), 1676 .out_rrr = tgen_and, 1677 .out_rri = tgen_andi, 1678}; 1679 1680static const TCGOutOpBinary outop_andc = { 1681 .base.static_constraint = C_NotImplemented, 1682}; 1683 1684static void tgen_clz(TCGContext *s, TCGType type, 1685 TCGReg a0, TCGReg a1, TCGReg a2) 1686{ 1687 if (use_mips32r6_instructions) { 1688 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1689 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1690 tgen_movcond(s, TCG_TYPE_REG, TCG_COND_EQ, a0, a1, a2, false, 1691 TCG_TMP0, false, TCG_REG_ZERO, false); 1692 } else { 1693 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1694 if (a0 == a2) { 1695 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1696 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1697 } else if (a0 != a1) { 1698 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1699 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1700 } else { 1701 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1702 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1703 tcg_out_mov(s, type, a0, TCG_TMP0); 1704 } 1705 } 1706} 1707 1708static void tgen_clzi(TCGContext *s, TCGType type, 1709 TCGReg a0, TCGReg a1, tcg_target_long a2) 1710{ 1711 if (a2 == 0) { 1712 tgen_clz(s, type, a0, a1, TCG_REG_ZERO); 1713 } else if (use_mips32r6_instructions) { 1714 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1715 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1716 } else { 1717 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1718 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1719 } 1720} 1721 1722static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 1723{ 1724 return use_mips32r2_instructions ? C_O1_I2(r, r, rzW) : C_NotImplemented; 1725} 1726 1727static const TCGOutOpBinary outop_clz = { 1728 .base.static_constraint = C_Dynamic, 1729 .base.dynamic_constraint = cset_clz, 1730 .out_rrr = tgen_clz, 1731 .out_rri = tgen_clzi, 1732}; 1733 1734static const TCGOutOpUnary outop_ctpop = { 1735 .base.static_constraint = C_NotImplemented, 1736}; 1737 1738static const TCGOutOpBinary outop_ctz = { 1739 .base.static_constraint = C_NotImplemented, 1740}; 1741 1742static void tgen_divs(TCGContext *s, TCGType type, 1743 TCGReg a0, TCGReg a1, TCGReg a2) 1744{ 1745 if (use_mips32r6_instructions) { 1746 if (type == TCG_TYPE_I32) { 1747 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1748 } else { 1749 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1750 } 1751 } else { 1752 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1753 tcg_out_opc_reg(s, insn, 0, a1, a2); 1754 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1755 } 1756} 1757 1758static const TCGOutOpBinary outop_divs = { 1759 .base.static_constraint = C_O1_I2(r, r, r), 1760 .out_rrr = tgen_divs, 1761}; 1762 1763static const TCGOutOpDivRem outop_divs2 = { 1764 .base.static_constraint = C_NotImplemented, 1765}; 1766 1767static void tgen_divu(TCGContext *s, TCGType type, 1768 TCGReg a0, TCGReg a1, TCGReg a2) 1769{ 1770 if (use_mips32r6_instructions) { 1771 if (type == TCG_TYPE_I32) { 1772 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1773 } else { 1774 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1775 } 1776 } else { 1777 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1778 tcg_out_opc_reg(s, insn, 0, a1, a2); 1779 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1780 } 1781} 1782 1783static const TCGOutOpBinary outop_divu = { 1784 .base.static_constraint = C_O1_I2(r, r, r), 1785 .out_rrr = tgen_divu, 1786}; 1787 1788static const TCGOutOpDivRem outop_divu2 = { 1789 .base.static_constraint = C_NotImplemented, 1790}; 1791 1792static const TCGOutOpBinary outop_eqv = { 1793 .base.static_constraint = C_NotImplemented, 1794}; 1795 1796static void tgen_mul(TCGContext *s, TCGType type, 1797 TCGReg a0, TCGReg a1, TCGReg a2) 1798{ 1799 MIPSInsn insn; 1800 1801 if (type == TCG_TYPE_I32) { 1802 if (use_mips32_instructions) { 1803 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1804 return; 1805 } 1806 insn = OPC_MULT; 1807 } else { 1808 if (use_mips32r6_instructions) { 1809 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1810 return; 1811 } 1812 insn = OPC_DMULT; 1813 } 1814 tcg_out_opc_reg(s, insn, 0, a1, a2); 1815 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1816} 1817 1818static const TCGOutOpBinary outop_mul = { 1819 .base.static_constraint = C_O1_I2(r, r, r), 1820 .out_rrr = tgen_mul, 1821}; 1822 1823static void tgen_muls2(TCGContext *s, TCGType type, 1824 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1825{ 1826 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1827 tcg_out_opc_reg(s, insn, 0, a2, a3); 1828 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1829 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1830} 1831 1832static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1833{ 1834 return use_mips32r6_instructions ? C_NotImplemented : C_O2_I2(r, r, r, r); 1835} 1836 1837static const TCGOutOpMul2 outop_muls2 = { 1838 .base.static_constraint = C_Dynamic, 1839 .base.dynamic_constraint = cset_mul2, 1840 .out_rrrr = tgen_muls2, 1841}; 1842 1843static void tgen_mulsh(TCGContext *s, TCGType type, 1844 TCGReg a0, TCGReg a1, TCGReg a2) 1845{ 1846 if (use_mips32r6_instructions) { 1847 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH; 1848 tcg_out_opc_reg(s, insn, a0, a1, a2); 1849 } else { 1850 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1851 tcg_out_opc_reg(s, insn, 0, a1, a2); 1852 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1853 } 1854} 1855 1856static const TCGOutOpBinary outop_mulsh = { 1857 .base.static_constraint = C_O1_I2(r, r, r), 1858 .out_rrr = tgen_mulsh, 1859}; 1860 1861static void tgen_mulu2(TCGContext *s, TCGType type, 1862 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1863{ 1864 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1865 tcg_out_opc_reg(s, insn, 0, a2, a3); 1866 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1867 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1868} 1869 1870static const TCGOutOpMul2 outop_mulu2 = { 1871 .base.static_constraint = C_Dynamic, 1872 .base.dynamic_constraint = cset_mul2, 1873 .out_rrrr = tgen_mulu2, 1874}; 1875 1876static void tgen_muluh(TCGContext *s, TCGType type, 1877 TCGReg a0, TCGReg a1, TCGReg a2) 1878{ 1879 if (use_mips32r6_instructions) { 1880 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; 1881 tcg_out_opc_reg(s, insn, a0, a1, a2); 1882 } else { 1883 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1884 tcg_out_opc_reg(s, insn, 0, a1, a2); 1885 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1886 } 1887} 1888 1889static const TCGOutOpBinary outop_muluh = { 1890 .base.static_constraint = C_O1_I2(r, r, r), 1891 .out_rrr = tgen_muluh, 1892}; 1893 1894static const TCGOutOpBinary outop_nand = { 1895 .base.static_constraint = C_NotImplemented, 1896}; 1897 1898static void tgen_nor(TCGContext *s, TCGType type, 1899 TCGReg a0, TCGReg a1, TCGReg a2) 1900{ 1901 tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); 1902} 1903 1904static const TCGOutOpBinary outop_nor = { 1905 .base.static_constraint = C_O1_I2(r, r, r), 1906 .out_rrr = tgen_nor, 1907}; 1908 1909static void tgen_or(TCGContext *s, TCGType type, 1910 TCGReg a0, TCGReg a1, TCGReg a2) 1911{ 1912 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1913} 1914 1915static void tgen_ori(TCGContext *s, TCGType type, 1916 TCGReg a0, TCGReg a1, tcg_target_long a2) 1917{ 1918 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1919} 1920 1921static const TCGOutOpBinary outop_or = { 1922 .base.static_constraint = C_O1_I2(r, r, rI), 1923 .out_rrr = tgen_or, 1924 .out_rri = tgen_ori, 1925}; 1926 1927static const TCGOutOpBinary outop_orc = { 1928 .base.static_constraint = C_NotImplemented, 1929}; 1930 1931static void tgen_rems(TCGContext *s, TCGType type, 1932 TCGReg a0, TCGReg a1, TCGReg a2) 1933{ 1934 if (use_mips32r6_instructions) { 1935 if (type == TCG_TYPE_I32) { 1936 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1937 } else { 1938 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1939 } 1940 } else { 1941 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1942 tcg_out_opc_reg(s, insn, 0, a1, a2); 1943 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1944 } 1945} 1946 1947static const TCGOutOpBinary outop_rems = { 1948 .base.static_constraint = C_O1_I2(r, r, r), 1949 .out_rrr = tgen_rems, 1950}; 1951 1952static void tgen_remu(TCGContext *s, TCGType type, 1953 TCGReg a0, TCGReg a1, TCGReg a2) 1954{ 1955 if (use_mips32r6_instructions) { 1956 if (type == TCG_TYPE_I32) { 1957 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1958 } else { 1959 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1960 } 1961 } else { 1962 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1963 tcg_out_opc_reg(s, insn, 0, a1, a2); 1964 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1965 } 1966} 1967 1968static const TCGOutOpBinary outop_remu = { 1969 .base.static_constraint = C_O1_I2(r, r, r), 1970 .out_rrr = tgen_remu, 1971}; 1972 1973static const TCGOutOpBinary outop_rotl = { 1974 .base.static_constraint = C_NotImplemented, 1975}; 1976 1977static TCGConstraintSetIndex cset_rotr(TCGType type, unsigned flags) 1978{ 1979 return use_mips32r2_instructions ? C_O1_I2(r, r, ri) : C_NotImplemented; 1980} 1981 1982static void tgen_rotr(TCGContext *s, TCGType type, 1983 TCGReg a0, TCGReg a1, TCGReg a2) 1984{ 1985 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; 1986 tcg_out_opc_reg(s, insn, a0, a1, a2); 1987} 1988 1989static void tgen_rotri(TCGContext *s, TCGType type, 1990 TCGReg a0, TCGReg a1, tcg_target_long a2) 1991{ 1992 if (type == TCG_TYPE_I32) { 1993 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); 1994 } else { 1995 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 1996 } 1997} 1998 1999static const TCGOutOpBinary outop_rotr = { 2000 .base.static_constraint = C_Dynamic, 2001 .base.dynamic_constraint = cset_rotr, 2002 .out_rrr = tgen_rotr, 2003 .out_rri = tgen_rotri, 2004}; 2005 2006static void tgen_sar(TCGContext *s, TCGType type, 2007 TCGReg a0, TCGReg a1, TCGReg a2) 2008{ 2009 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; 2010 tcg_out_opc_reg(s, insn, a0, a1, a2); 2011} 2012 2013static void tgen_sari(TCGContext *s, TCGType type, 2014 TCGReg a0, TCGReg a1, tcg_target_long a2) 2015{ 2016 if (type == TCG_TYPE_I32) { 2017 tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); 2018 } else { 2019 tcg_out_dsra(s, a0, a1, a2); 2020 } 2021} 2022 2023static const TCGOutOpBinary outop_sar = { 2024 .base.static_constraint = C_O1_I2(r, r, ri), 2025 .out_rrr = tgen_sar, 2026 .out_rri = tgen_sari, 2027}; 2028 2029static void tgen_shl(TCGContext *s, TCGType type, 2030 TCGReg a0, TCGReg a1, TCGReg a2) 2031{ 2032 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; 2033 tcg_out_opc_reg(s, insn, a0, a1, a2); 2034} 2035 2036static void tgen_shli(TCGContext *s, TCGType type, 2037 TCGReg a0, TCGReg a1, tcg_target_long a2) 2038{ 2039 if (type == TCG_TYPE_I32) { 2040 tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); 2041 } else { 2042 tcg_out_dsll(s, a0, a1, a2); 2043 } 2044} 2045 2046static const TCGOutOpBinary outop_shl = { 2047 .base.static_constraint = C_O1_I2(r, r, ri), 2048 .out_rrr = tgen_shl, 2049 .out_rri = tgen_shli, 2050}; 2051 2052static void tgen_shr(TCGContext *s, TCGType type, 2053 TCGReg a0, TCGReg a1, TCGReg a2) 2054{ 2055 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; 2056 tcg_out_opc_reg(s, insn, a0, a1, a2); 2057} 2058 2059static void tgen_shri(TCGContext *s, TCGType type, 2060 TCGReg a0, TCGReg a1, tcg_target_long a2) 2061{ 2062 if (type == TCG_TYPE_I32) { 2063 tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); 2064 } else { 2065 tcg_out_dsrl(s, a0, a1, a2); 2066 } 2067} 2068 2069static const TCGOutOpBinary outop_shr = { 2070 .base.static_constraint = C_O1_I2(r, r, ri), 2071 .out_rrr = tgen_shr, 2072 .out_rri = tgen_shri, 2073}; 2074 2075static void tgen_sub(TCGContext *s, TCGType type, 2076 TCGReg a0, TCGReg a1, TCGReg a2) 2077{ 2078 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU; 2079 tcg_out_opc_reg(s, insn, a0, a1, a2); 2080} 2081 2082static const TCGOutOpSubtract outop_sub = { 2083 .base.static_constraint = C_O1_I2(r, r, r), 2084 .out_rrr = tgen_sub, 2085}; 2086 2087static void tgen_xor(TCGContext *s, TCGType type, 2088 TCGReg a0, TCGReg a1, TCGReg a2) 2089{ 2090 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2091} 2092 2093static void tgen_xori(TCGContext *s, TCGType type, 2094 TCGReg a0, TCGReg a1, tcg_target_long a2) 2095{ 2096 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2097} 2098 2099static const TCGOutOpBinary outop_xor = { 2100 .base.static_constraint = C_O1_I2(r, r, rI), 2101 .out_rrr = tgen_xor, 2102 .out_rri = tgen_xori, 2103}; 2104 2105static void tgen_bswap16(TCGContext *s, TCGType type, 2106 TCGReg ret, TCGReg arg, unsigned flags) 2107{ 2108 /* With arg = abcd: */ 2109 if (use_mips32r2_instructions) { 2110 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 2111 if (flags & TCG_BSWAP_OS) { 2112 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 2113 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2114 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 2115 } 2116 return; 2117 } 2118 2119 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 2120 if (!(flags & TCG_BSWAP_IZ)) { 2121 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 2122 } 2123 if (flags & TCG_BSWAP_OS) { 2124 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 2125 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 2126 } else { 2127 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 2128 if (flags & TCG_BSWAP_OZ) { 2129 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 2130 } 2131 } 2132 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 2133} 2134 2135static const TCGOutOpBswap outop_bswap16 = { 2136 .base.static_constraint = C_O1_I1(r, r), 2137 .out_rr = tgen_bswap16, 2138}; 2139 2140static void tgen_bswap32(TCGContext *s, TCGType type, 2141 TCGReg ret, TCGReg arg, unsigned flags) 2142{ 2143 if (use_mips32r2_instructions) { 2144 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 2145 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 2146 if (flags & TCG_BSWAP_OZ) { 2147 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 2148 } 2149 } else { 2150 if (flags & TCG_BSWAP_OZ) { 2151 tcg_out_bswap_subr(s, bswap32u_addr); 2152 } else { 2153 tcg_out_bswap_subr(s, bswap32_addr); 2154 } 2155 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2156 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2157 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2158 } 2159} 2160 2161static const TCGOutOpBswap outop_bswap32 = { 2162 .base.static_constraint = C_O1_I1(r, r), 2163 .out_rr = tgen_bswap32, 2164}; 2165 2166#if TCG_TARGET_REG_BITS == 64 2167static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2168{ 2169 if (use_mips32r2_instructions) { 2170 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 2171 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 2172 } else { 2173 tcg_out_bswap_subr(s, bswap64_addr); 2174 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2175 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2176 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2177 } 2178} 2179 2180static const TCGOutOpUnary outop_bswap64 = { 2181 .base.static_constraint = C_O1_I1(r, r), 2182 .out_rr = tgen_bswap64, 2183}; 2184#endif /* TCG_TARGET_REG_BITS == 64 */ 2185 2186static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2187{ 2188 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2189} 2190 2191static const TCGOutOpUnary outop_neg = { 2192 .base.static_constraint = C_O1_I1(r, r), 2193 .out_rr = tgen_neg, 2194}; 2195 2196static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2197{ 2198 tgen_nor(s, type, a0, TCG_REG_ZERO, a1); 2199} 2200 2201static const TCGOutOpUnary outop_not = { 2202 .base.static_constraint = C_O1_I1(r, r), 2203 .out_rr = tgen_not, 2204}; 2205 2206 2207static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2208 const TCGArg args[TCG_MAX_OP_ARGS], 2209 const int const_args[TCG_MAX_OP_ARGS]) 2210{ 2211 MIPSInsn i1; 2212 TCGArg a0, a1, a2; 2213 2214 a0 = args[0]; 2215 a1 = args[1]; 2216 a2 = args[2]; 2217 2218 switch (opc) { 2219 case INDEX_op_goto_ptr: 2220 /* jmp to the given host address (could be epilogue) */ 2221 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2222 if (TCG_TARGET_REG_BITS == 64) { 2223 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 2224 } else { 2225 tcg_out_nop(s); 2226 } 2227 break; 2228 case INDEX_op_br: 2229 tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, 2230 TCG_REG_ZERO, TCG_REG_ZERO, arg_label(a0)); 2231 break; 2232 2233 case INDEX_op_ld8u_i32: 2234 case INDEX_op_ld8u_i64: 2235 i1 = OPC_LBU; 2236 goto do_ldst; 2237 case INDEX_op_ld8s_i32: 2238 case INDEX_op_ld8s_i64: 2239 i1 = OPC_LB; 2240 goto do_ldst; 2241 case INDEX_op_ld16u_i32: 2242 case INDEX_op_ld16u_i64: 2243 i1 = OPC_LHU; 2244 goto do_ldst; 2245 case INDEX_op_ld16s_i32: 2246 case INDEX_op_ld16s_i64: 2247 i1 = OPC_LH; 2248 goto do_ldst; 2249 case INDEX_op_ld_i32: 2250 case INDEX_op_ld32s_i64: 2251 i1 = OPC_LW; 2252 goto do_ldst; 2253 case INDEX_op_ld32u_i64: 2254 i1 = OPC_LWU; 2255 goto do_ldst; 2256 case INDEX_op_ld_i64: 2257 i1 = OPC_LD; 2258 goto do_ldst; 2259 case INDEX_op_st8_i32: 2260 case INDEX_op_st8_i64: 2261 i1 = OPC_SB; 2262 goto do_ldst; 2263 case INDEX_op_st16_i32: 2264 case INDEX_op_st16_i64: 2265 i1 = OPC_SH; 2266 goto do_ldst; 2267 case INDEX_op_st_i32: 2268 case INDEX_op_st32_i64: 2269 i1 = OPC_SW; 2270 goto do_ldst; 2271 case INDEX_op_st_i64: 2272 i1 = OPC_SD; 2273 do_ldst: 2274 tcg_out_ldst(s, i1, a0, a1, a2); 2275 break; 2276 2277 case INDEX_op_extrh_i64_i32: 2278 tcg_out_dsra(s, a0, a1, 32); 2279 break; 2280 2281 case INDEX_op_deposit_i32: 2282 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2283 break; 2284 case INDEX_op_deposit_i64: 2285 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2286 args[3] + args[4] - 1, args[3]); 2287 break; 2288 2289 case INDEX_op_extract_i32: 2290 if (a2 == 0 && args[3] <= 16) { 2291 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2292 } else { 2293 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2294 } 2295 break; 2296 case INDEX_op_extract_i64: 2297 if (a2 == 0 && args[3] <= 16) { 2298 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2299 } else { 2300 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2301 a0, a1, args[3] - 1, a2); 2302 } 2303 break; 2304 2305 case INDEX_op_sextract_i64: 2306 if (a2 == 0 && args[3] == 32) { 2307 tcg_out_ext32s(s, a0, a1); 2308 break; 2309 } 2310 /* FALLTHRU */ 2311 case INDEX_op_sextract_i32: 2312 if (a2 == 0 && args[3] == 8) { 2313 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 2314 } else if (a2 == 0 && args[3] == 16) { 2315 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 2316 } else { 2317 g_assert_not_reached(); 2318 } 2319 break; 2320 2321 case INDEX_op_qemu_ld_i32: 2322 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2323 break; 2324 case INDEX_op_qemu_ld_i64: 2325 if (TCG_TARGET_REG_BITS == 64) { 2326 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2327 } else { 2328 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2329 } 2330 break; 2331 2332 case INDEX_op_qemu_st_i32: 2333 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2334 break; 2335 case INDEX_op_qemu_st_i64: 2336 if (TCG_TARGET_REG_BITS == 64) { 2337 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2338 } else { 2339 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2340 } 2341 break; 2342 2343 case INDEX_op_add2_i32: 2344 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2345 const_args[4], const_args[5], false); 2346 break; 2347 case INDEX_op_sub2_i32: 2348 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2349 const_args[4], const_args[5], true); 2350 break; 2351 2352 case INDEX_op_mb: 2353 tcg_out_mb(s, a0); 2354 break; 2355 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2356 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2357 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2358 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2359 case INDEX_op_extu_i32_i64: 2360 case INDEX_op_extrl_i64_i32: 2361 default: 2362 g_assert_not_reached(); 2363 } 2364} 2365 2366static TCGConstraintSetIndex 2367tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2368{ 2369 switch (op) { 2370 case INDEX_op_goto_ptr: 2371 return C_O0_I1(r); 2372 2373 case INDEX_op_ld8u_i32: 2374 case INDEX_op_ld8s_i32: 2375 case INDEX_op_ld16u_i32: 2376 case INDEX_op_ld16s_i32: 2377 case INDEX_op_ld_i32: 2378 case INDEX_op_extract_i32: 2379 case INDEX_op_sextract_i32: 2380 case INDEX_op_ld8u_i64: 2381 case INDEX_op_ld8s_i64: 2382 case INDEX_op_ld16u_i64: 2383 case INDEX_op_ld16s_i64: 2384 case INDEX_op_ld32s_i64: 2385 case INDEX_op_ld32u_i64: 2386 case INDEX_op_ld_i64: 2387 case INDEX_op_ext_i32_i64: 2388 case INDEX_op_extu_i32_i64: 2389 case INDEX_op_extrl_i64_i32: 2390 case INDEX_op_extrh_i64_i32: 2391 case INDEX_op_extract_i64: 2392 case INDEX_op_sextract_i64: 2393 return C_O1_I1(r, r); 2394 2395 case INDEX_op_st8_i32: 2396 case INDEX_op_st16_i32: 2397 case INDEX_op_st_i32: 2398 case INDEX_op_st8_i64: 2399 case INDEX_op_st16_i64: 2400 case INDEX_op_st32_i64: 2401 case INDEX_op_st_i64: 2402 return C_O0_I2(rz, r); 2403 2404 case INDEX_op_deposit_i32: 2405 case INDEX_op_deposit_i64: 2406 return C_O1_I2(r, 0, rz); 2407 case INDEX_op_add2_i32: 2408 case INDEX_op_sub2_i32: 2409 return C_O2_I4(r, r, rz, rz, rN, rN); 2410 2411 case INDEX_op_qemu_ld_i32: 2412 return C_O1_I1(r, r); 2413 case INDEX_op_qemu_st_i32: 2414 return C_O0_I2(rz, r); 2415 case INDEX_op_qemu_ld_i64: 2416 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2417 case INDEX_op_qemu_st_i64: 2418 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2419 2420 default: 2421 return C_NotImplemented; 2422 } 2423} 2424 2425static const int tcg_target_callee_save_regs[] = { 2426 TCG_REG_S0, 2427 TCG_REG_S1, 2428 TCG_REG_S2, 2429 TCG_REG_S3, 2430 TCG_REG_S4, 2431 TCG_REG_S5, 2432 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2433 TCG_REG_S7, /* used for guest_base */ 2434 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2435 TCG_REG_RA, /* should be last for ABI compliance */ 2436}; 2437 2438/* The Linux kernel doesn't provide any information about the available 2439 instruction set. Probe it using a signal handler. */ 2440 2441 2442#ifndef use_movnz_instructions 2443bool use_movnz_instructions = false; 2444#endif 2445 2446#ifndef use_mips32_instructions 2447bool use_mips32_instructions = false; 2448#endif 2449 2450#ifndef use_mips32r2_instructions 2451bool use_mips32r2_instructions = false; 2452#endif 2453 2454static volatile sig_atomic_t got_sigill; 2455 2456static void sigill_handler(int signo, siginfo_t *si, void *data) 2457{ 2458 /* Skip the faulty instruction */ 2459 ucontext_t *uc = (ucontext_t *)data; 2460 uc->uc_mcontext.pc += 4; 2461 2462 got_sigill = 1; 2463} 2464 2465static void tcg_target_detect_isa(void) 2466{ 2467 struct sigaction sa_old, sa_new; 2468 2469 memset(&sa_new, 0, sizeof(sa_new)); 2470 sa_new.sa_flags = SA_SIGINFO; 2471 sa_new.sa_sigaction = sigill_handler; 2472 sigaction(SIGILL, &sa_new, &sa_old); 2473 2474 /* Probe for movn/movz, necessary to implement movcond. */ 2475#ifndef use_movnz_instructions 2476 got_sigill = 0; 2477 asm volatile(".set push\n" 2478 ".set mips32\n" 2479 "movn $zero, $zero, $zero\n" 2480 "movz $zero, $zero, $zero\n" 2481 ".set pop\n" 2482 : : : ); 2483 use_movnz_instructions = !got_sigill; 2484#endif 2485 2486 /* Probe for MIPS32 instructions. As no subsetting is allowed 2487 by the specification, it is only necessary to probe for one 2488 of the instructions. */ 2489#ifndef use_mips32_instructions 2490 got_sigill = 0; 2491 asm volatile(".set push\n" 2492 ".set mips32\n" 2493 "mul $zero, $zero\n" 2494 ".set pop\n" 2495 : : : ); 2496 use_mips32_instructions = !got_sigill; 2497#endif 2498 2499 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2500 available. As no subsetting is allowed by the specification, 2501 it is only necessary to probe for one of the instructions. */ 2502#ifndef use_mips32r2_instructions 2503 if (use_mips32_instructions) { 2504 got_sigill = 0; 2505 asm volatile(".set push\n" 2506 ".set mips32r2\n" 2507 "seb $zero, $zero\n" 2508 ".set pop\n" 2509 : : : ); 2510 use_mips32r2_instructions = !got_sigill; 2511 } 2512#endif 2513 2514 sigaction(SIGILL, &sa_old, NULL); 2515} 2516 2517static tcg_insn_unit *align_code_ptr(TCGContext *s) 2518{ 2519 uintptr_t p = (uintptr_t)s->code_ptr; 2520 if (p & 15) { 2521 p = (p + 15) & -16; 2522 s->code_ptr = (void *)p; 2523 } 2524 return s->code_ptr; 2525} 2526 2527/* Stack frame parameters. */ 2528#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2529#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2530#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2531 2532#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2533 + TCG_TARGET_STACK_ALIGN - 1) \ 2534 & -TCG_TARGET_STACK_ALIGN) 2535#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2536 2537/* We're expecting to be able to use an immediate for frame allocation. */ 2538QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2539 2540/* Generate global QEMU prologue and epilogue code */ 2541static void tcg_target_qemu_prologue(TCGContext *s) 2542{ 2543 int i; 2544 2545 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2546 2547 /* TB prologue */ 2548 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2549 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2550 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2551 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2552 } 2553 2554 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2555 /* 2556 * The function call abi for n32 and n64 will have loaded $25 (t9) 2557 * with the address of the prologue, so we can use that instead 2558 * of TCG_REG_TB. 2559 */ 2560#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2561# error "Unknown mips abi" 2562#endif 2563 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2564 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2565 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2566 } 2567 2568 if (TCG_TARGET_REG_BITS == 64) { 2569 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2570 } 2571 2572 /* Call generated code */ 2573 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2574 /* delay slot */ 2575 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2576 2577 /* 2578 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2579 * and fall through to the rest of the epilogue. 2580 */ 2581 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2582 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2583 2584 /* TB epilogue */ 2585 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2586 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2587 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2588 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2589 } 2590 2591 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2592 /* delay slot */ 2593 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2594 2595 if (use_mips32r2_instructions) { 2596 return; 2597 } 2598 2599 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2600 clobbers TCG_TMP1, TCG_TMP2. */ 2601 2602 /* 2603 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2604 */ 2605 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2606 /* t3 = (ssss)d000 */ 2607 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2608 /* t1 = 000a */ 2609 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2610 /* t2 = 00c0 */ 2611 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2612 /* t3 = d00a */ 2613 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2614 /* t1 = 0abc */ 2615 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2616 /* t2 = 0c00 */ 2617 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2618 /* t1 = 00b0 */ 2619 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2620 /* t3 = dc0a */ 2621 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2622 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2623 /* t3 = dcba -- delay slot */ 2624 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2625 2626 if (TCG_TARGET_REG_BITS == 32) { 2627 return; 2628 } 2629 2630 /* 2631 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2632 */ 2633 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2634 /* t1 = (0000)000d */ 2635 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2636 /* t3 = 000a */ 2637 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2638 /* t1 = (0000)d000 */ 2639 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2640 /* t2 = 00c0 */ 2641 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2642 /* t3 = d00a */ 2643 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2644 /* t1 = 0abc */ 2645 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2646 /* t2 = 0c00 */ 2647 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2648 /* t1 = 00b0 */ 2649 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2650 /* t3 = dc0a */ 2651 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2652 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2653 /* t3 = dcba -- delay slot */ 2654 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2655 2656 /* 2657 * bswap64 -- 64-bit swap. a0 = abcdefgh 2658 */ 2659 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2660 /* t3 = h0000000 */ 2661 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2662 /* t1 = 0000000a */ 2663 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2664 2665 /* t2 = 000000g0 */ 2666 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2667 /* t3 = h000000a */ 2668 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2669 /* t1 = 00000abc */ 2670 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2671 /* t2 = 0g000000 */ 2672 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2673 /* t1 = 000000b0 */ 2674 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2675 2676 /* t3 = hg00000a */ 2677 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2678 /* t2 = 0000abcd */ 2679 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2680 /* t3 = hg0000ba */ 2681 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2682 2683 /* t1 = 000000c0 */ 2684 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2685 /* t2 = 0000000d */ 2686 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2687 /* t1 = 00000c00 */ 2688 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2689 /* t2 = 0000d000 */ 2690 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2691 2692 /* t3 = hg000cba */ 2693 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2694 /* t1 = 00abcdef */ 2695 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2696 /* t3 = hg00dcba */ 2697 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2698 2699 /* t2 = 0000000f */ 2700 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2701 /* t1 = 000000e0 */ 2702 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2703 /* t2 = 00f00000 */ 2704 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2705 /* t1 = 000e0000 */ 2706 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2707 2708 /* t3 = hgf0dcba */ 2709 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2710 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2711 /* t3 = hgfedcba -- delay slot */ 2712 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2713} 2714 2715static void tcg_out_tb_start(TCGContext *s) 2716{ 2717 /* nothing to do */ 2718} 2719 2720static void tcg_target_init(TCGContext *s) 2721{ 2722 tcg_target_detect_isa(); 2723 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2724 if (TCG_TARGET_REG_BITS == 64) { 2725 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2726 } 2727 2728 tcg_target_call_clobber_regs = 0; 2729 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2730 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2731 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2732 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2733 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2734 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2735 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2736 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2737 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2738 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2741 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2742 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2743 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2744 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2745 2746 s->reserved_regs = 0; 2747 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2748 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2749 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2750 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2751 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2752 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2753 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2754 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2755 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2756 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2757 if (TCG_TARGET_REG_BITS == 64) { 2758 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2759 } 2760} 2761 2762typedef struct { 2763 DebugFrameHeader h; 2764 uint8_t fde_def_cfa[4]; 2765 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2766} DebugFrame; 2767 2768#define ELF_HOST_MACHINE EM_MIPS 2769/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2770 which is good because they're really quite complicated for MIPS. */ 2771 2772static const DebugFrame debug_frame = { 2773 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2774 .h.cie.id = -1, 2775 .h.cie.version = 1, 2776 .h.cie.code_align = 1, 2777 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2778 .h.cie.return_column = TCG_REG_RA, 2779 2780 /* Total FDE size does not include the "len" member. */ 2781 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2782 2783 .fde_def_cfa = { 2784 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2785 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2786 (FRAME_SIZE >> 7) 2787 }, 2788 .fde_reg_ofs = { 2789 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2790 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2791 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2792 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2793 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2794 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2795 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2796 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2797 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2798 } 2799}; 2800 2801void tcg_register_jit(const void *buf, size_t buf_size) 2802{ 2803 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2804} 2805