1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#ifdef HOST_WORDS_BIGENDIAN 28# define MIPS_BE 1 29#else 30# define MIPS_BE 0 31#endif 32 33#if TCG_TARGET_REG_BITS == 32 34# define LO_OFF (MIPS_BE * 4) 35# define HI_OFF (4 - LO_OFF) 36#else 37/* To assert at compile-time that these values are never used 38 for TCG_TARGET_REG_BITS == 64. */ 39int link_error(void); 40# define LO_OFF link_error() 41# define HI_OFF link_error() 42#endif 43 44#ifdef CONFIG_DEBUG_TCG 45static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 46 "zero", 47 "at", 48 "v0", 49 "v1", 50 "a0", 51 "a1", 52 "a2", 53 "a3", 54 "t0", 55 "t1", 56 "t2", 57 "t3", 58 "t4", 59 "t5", 60 "t6", 61 "t7", 62 "s0", 63 "s1", 64 "s2", 65 "s3", 66 "s4", 67 "s5", 68 "s6", 69 "s7", 70 "t8", 71 "t9", 72 "k0", 73 "k1", 74 "gp", 75 "sp", 76 "s8", 77 "ra", 78}; 79#endif 80 81#define TCG_TMP0 TCG_REG_AT 82#define TCG_TMP1 TCG_REG_T9 83#define TCG_TMP2 TCG_REG_T8 84#define TCG_TMP3 TCG_REG_T7 85 86#ifndef CONFIG_SOFTMMU 87#define TCG_GUEST_BASE_REG TCG_REG_S1 88#endif 89 90/* check if we really need so many registers :P */ 91static const int tcg_target_reg_alloc_order[] = { 92 /* Call saved registers. */ 93 TCG_REG_S0, 94 TCG_REG_S1, 95 TCG_REG_S2, 96 TCG_REG_S3, 97 TCG_REG_S4, 98 TCG_REG_S5, 99 TCG_REG_S6, 100 TCG_REG_S7, 101 TCG_REG_S8, 102 103 /* Call clobbered registers. */ 104 TCG_REG_T4, 105 TCG_REG_T5, 106 TCG_REG_T6, 107 TCG_REG_T7, 108 TCG_REG_T8, 109 TCG_REG_T9, 110 TCG_REG_V1, 111 TCG_REG_V0, 112 113 /* Argument registers, opposite order of allocation. */ 114 TCG_REG_T3, 115 TCG_REG_T2, 116 TCG_REG_T1, 117 TCG_REG_T0, 118 TCG_REG_A3, 119 TCG_REG_A2, 120 TCG_REG_A1, 121 TCG_REG_A0, 122}; 123 124static const TCGReg tcg_target_call_iarg_regs[] = { 125 TCG_REG_A0, 126 TCG_REG_A1, 127 TCG_REG_A2, 128 TCG_REG_A3, 129#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 130 TCG_REG_T0, 131 TCG_REG_T1, 132 TCG_REG_T2, 133 TCG_REG_T3, 134#endif 135}; 136 137static const TCGReg tcg_target_call_oarg_regs[2] = { 138 TCG_REG_V0, 139 TCG_REG_V1 140}; 141 142static const tcg_insn_unit *tb_ret_addr; 143static const tcg_insn_unit *bswap32_addr; 144static const tcg_insn_unit *bswap32u_addr; 145static const tcg_insn_unit *bswap64_addr; 146 147static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 148{ 149 /* Let the compiler perform the right-shift as part of the arithmetic. */ 150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 151 ptrdiff_t disp = target - (src_rx + 1); 152 if (disp == (int16_t)disp) { 153 *src_rw = deposit32(*src_rw, 0, 16, disp); 154 return true; 155 } 156 return false; 157} 158 159static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 160 intptr_t value, intptr_t addend) 161{ 162 tcg_debug_assert(type == R_MIPS_PC16); 163 tcg_debug_assert(addend == 0); 164 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 165} 166 167#define TCG_CT_CONST_ZERO 0x100 168#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 169#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 170#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 171#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 172#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 173 174#define ALL_GENERAL_REGS 0xffffffffu 175#define NOA0_REGS (ALL_GENERAL_REGS & ~(1 << TCG_REG_A0)) 176 177#ifdef CONFIG_SOFTMMU 178#define ALL_QLOAD_REGS \ 179 (NOA0_REGS & ~((TCG_TARGET_REG_BITS < TARGET_LONG_BITS) << TCG_REG_A2)) 180#define ALL_QSTORE_REGS \ 181 (NOA0_REGS & ~(TCG_TARGET_REG_BITS < TARGET_LONG_BITS \ 182 ? (1 << TCG_REG_A2) | (1 << TCG_REG_A3) \ 183 : (1 << TCG_REG_A1))) 184#else 185#define ALL_QLOAD_REGS NOA0_REGS 186#define ALL_QSTORE_REGS NOA0_REGS 187#endif 188 189 190static inline bool is_p2m1(tcg_target_long val) 191{ 192 return val && ((val + 1) & val) == 0; 193} 194 195/* test if a constant matches the constraint */ 196static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 197{ 198 if (ct & TCG_CT_CONST) { 199 return 1; 200 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 201 return 1; 202 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 203 return 1; 204 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_P2M1) 209 && use_mips32r2_instructions && is_p2m1(val)) { 210 return 1; 211 } else if ((ct & TCG_CT_CONST_WSZ) 212 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 213 return 1; 214 } 215 return 0; 216} 217 218/* instruction opcodes */ 219typedef enum { 220 OPC_J = 002 << 26, 221 OPC_JAL = 003 << 26, 222 OPC_BEQ = 004 << 26, 223 OPC_BNE = 005 << 26, 224 OPC_BLEZ = 006 << 26, 225 OPC_BGTZ = 007 << 26, 226 OPC_ADDIU = 011 << 26, 227 OPC_SLTI = 012 << 26, 228 OPC_SLTIU = 013 << 26, 229 OPC_ANDI = 014 << 26, 230 OPC_ORI = 015 << 26, 231 OPC_XORI = 016 << 26, 232 OPC_LUI = 017 << 26, 233 OPC_DADDIU = 031 << 26, 234 OPC_LB = 040 << 26, 235 OPC_LH = 041 << 26, 236 OPC_LW = 043 << 26, 237 OPC_LBU = 044 << 26, 238 OPC_LHU = 045 << 26, 239 OPC_LWU = 047 << 26, 240 OPC_SB = 050 << 26, 241 OPC_SH = 051 << 26, 242 OPC_SW = 053 << 26, 243 OPC_LD = 067 << 26, 244 OPC_SD = 077 << 26, 245 246 OPC_SPECIAL = 000 << 26, 247 OPC_SLL = OPC_SPECIAL | 000, 248 OPC_SRL = OPC_SPECIAL | 002, 249 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 250 OPC_SRA = OPC_SPECIAL | 003, 251 OPC_SLLV = OPC_SPECIAL | 004, 252 OPC_SRLV = OPC_SPECIAL | 006, 253 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 254 OPC_SRAV = OPC_SPECIAL | 007, 255 OPC_JR_R5 = OPC_SPECIAL | 010, 256 OPC_JALR = OPC_SPECIAL | 011, 257 OPC_MOVZ = OPC_SPECIAL | 012, 258 OPC_MOVN = OPC_SPECIAL | 013, 259 OPC_SYNC = OPC_SPECIAL | 017, 260 OPC_MFHI = OPC_SPECIAL | 020, 261 OPC_MFLO = OPC_SPECIAL | 022, 262 OPC_DSLLV = OPC_SPECIAL | 024, 263 OPC_DSRLV = OPC_SPECIAL | 026, 264 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 265 OPC_DSRAV = OPC_SPECIAL | 027, 266 OPC_MULT = OPC_SPECIAL | 030, 267 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 268 OPC_MUH = OPC_SPECIAL | 030 | 0300, 269 OPC_MULTU = OPC_SPECIAL | 031, 270 OPC_MULU = OPC_SPECIAL | 031 | 0200, 271 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 272 OPC_DIV = OPC_SPECIAL | 032, 273 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 274 OPC_MOD = OPC_SPECIAL | 032 | 0300, 275 OPC_DIVU = OPC_SPECIAL | 033, 276 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 277 OPC_MODU = OPC_SPECIAL | 033 | 0300, 278 OPC_DMULT = OPC_SPECIAL | 034, 279 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 280 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 281 OPC_DMULTU = OPC_SPECIAL | 035, 282 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 283 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 284 OPC_DDIV = OPC_SPECIAL | 036, 285 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 286 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 287 OPC_DDIVU = OPC_SPECIAL | 037, 288 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 289 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 290 OPC_ADDU = OPC_SPECIAL | 041, 291 OPC_SUBU = OPC_SPECIAL | 043, 292 OPC_AND = OPC_SPECIAL | 044, 293 OPC_OR = OPC_SPECIAL | 045, 294 OPC_XOR = OPC_SPECIAL | 046, 295 OPC_NOR = OPC_SPECIAL | 047, 296 OPC_SLT = OPC_SPECIAL | 052, 297 OPC_SLTU = OPC_SPECIAL | 053, 298 OPC_DADDU = OPC_SPECIAL | 055, 299 OPC_DSUBU = OPC_SPECIAL | 057, 300 OPC_SELEQZ = OPC_SPECIAL | 065, 301 OPC_SELNEZ = OPC_SPECIAL | 067, 302 OPC_DSLL = OPC_SPECIAL | 070, 303 OPC_DSRL = OPC_SPECIAL | 072, 304 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 305 OPC_DSRA = OPC_SPECIAL | 073, 306 OPC_DSLL32 = OPC_SPECIAL | 074, 307 OPC_DSRL32 = OPC_SPECIAL | 076, 308 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 309 OPC_DSRA32 = OPC_SPECIAL | 077, 310 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 311 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 312 313 OPC_REGIMM = 001 << 26, 314 OPC_BLTZ = OPC_REGIMM | (000 << 16), 315 OPC_BGEZ = OPC_REGIMM | (001 << 16), 316 317 OPC_SPECIAL2 = 034 << 26, 318 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 319 OPC_CLZ = OPC_SPECIAL2 | 040, 320 OPC_DCLZ = OPC_SPECIAL2 | 044, 321 322 OPC_SPECIAL3 = 037 << 26, 323 OPC_EXT = OPC_SPECIAL3 | 000, 324 OPC_DEXTM = OPC_SPECIAL3 | 001, 325 OPC_DEXTU = OPC_SPECIAL3 | 002, 326 OPC_DEXT = OPC_SPECIAL3 | 003, 327 OPC_INS = OPC_SPECIAL3 | 004, 328 OPC_DINSM = OPC_SPECIAL3 | 005, 329 OPC_DINSU = OPC_SPECIAL3 | 006, 330 OPC_DINS = OPC_SPECIAL3 | 007, 331 OPC_WSBH = OPC_SPECIAL3 | 00240, 332 OPC_DSBH = OPC_SPECIAL3 | 00244, 333 OPC_DSHD = OPC_SPECIAL3 | 00544, 334 OPC_SEB = OPC_SPECIAL3 | 02040, 335 OPC_SEH = OPC_SPECIAL3 | 03040, 336 337 /* MIPS r6 doesn't have JR, JALR should be used instead */ 338 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 339 340 /* 341 * MIPS r6 replaces MUL with an alternative encoding which is 342 * backwards-compatible at the assembly level. 343 */ 344 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 345 346 /* MIPS r6 introduced names for weaker variants of SYNC. These are 347 backward compatible to previous architecture revisions. */ 348 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 349 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 350 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 351 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 352 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 353 354 /* Aliases for convenience. */ 355 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 356 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 357 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 358 ? OPC_SRL : OPC_DSRL, 359} MIPSInsn; 360 361/* 362 * Type reg 363 */ 364static inline void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 365 TCGReg rd, TCGReg rs, TCGReg rt) 366{ 367 int32_t inst; 368 369 inst = opc; 370 inst |= (rs & 0x1F) << 21; 371 inst |= (rt & 0x1F) << 16; 372 inst |= (rd & 0x1F) << 11; 373 tcg_out32(s, inst); 374} 375 376/* 377 * Type immediate 378 */ 379static inline void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 380 TCGReg rt, TCGReg rs, TCGArg imm) 381{ 382 int32_t inst; 383 384 inst = opc; 385 inst |= (rs & 0x1F) << 21; 386 inst |= (rt & 0x1F) << 16; 387 inst |= (imm & 0xffff); 388 tcg_out32(s, inst); 389} 390 391/* 392 * Type bitfield 393 */ 394static inline void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 395 TCGReg rs, int msb, int lsb) 396{ 397 int32_t inst; 398 399 inst = opc; 400 inst |= (rs & 0x1F) << 21; 401 inst |= (rt & 0x1F) << 16; 402 inst |= (msb & 0x1F) << 11; 403 inst |= (lsb & 0x1F) << 6; 404 tcg_out32(s, inst); 405} 406 407static inline void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 408 MIPSInsn oph, TCGReg rt, TCGReg rs, 409 int msb, int lsb) 410{ 411 if (lsb >= 32) { 412 opc = oph; 413 msb -= 32; 414 lsb -= 32; 415 } else if (msb >= 32) { 416 opc = opm; 417 msb -= 32; 418 } 419 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 420} 421 422/* 423 * Type branch 424 */ 425static inline void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, 426 TCGReg rt, TCGReg rs) 427{ 428 tcg_out_opc_imm(s, opc, rt, rs, 0); 429} 430 431/* 432 * Type sa 433 */ 434static inline void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 435 TCGReg rd, TCGReg rt, TCGArg sa) 436{ 437 int32_t inst; 438 439 inst = opc; 440 inst |= (rt & 0x1F) << 16; 441 inst |= (rd & 0x1F) << 11; 442 inst |= (sa & 0x1F) << 6; 443 tcg_out32(s, inst); 444 445} 446 447static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 448 TCGReg rd, TCGReg rt, TCGArg sa) 449{ 450 int32_t inst; 451 452 inst = (sa & 32 ? opc2 : opc1); 453 inst |= (rt & 0x1F) << 16; 454 inst |= (rd & 0x1F) << 11; 455 inst |= (sa & 0x1F) << 6; 456 tcg_out32(s, inst); 457} 458 459/* 460 * Type jump. 461 * Returns true if the branch was in range and the insn was emitted. 462 */ 463static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 464{ 465 uintptr_t dest = (uintptr_t)target; 466 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 467 int32_t inst; 468 469 /* The pc-region branch happens within the 256MB region of 470 the delay slot (thus the +4). */ 471 if ((from ^ dest) & -(1 << 28)) { 472 return false; 473 } 474 tcg_debug_assert((dest & 3) == 0); 475 476 inst = opc; 477 inst |= (dest >> 2) & 0x3ffffff; 478 tcg_out32(s, inst); 479 return true; 480} 481 482static inline void tcg_out_nop(TCGContext *s) 483{ 484 tcg_out32(s, 0); 485} 486 487static inline void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 488{ 489 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 490} 491 492static inline void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 493{ 494 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 495} 496 497static inline void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 498{ 499 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 500} 501 502static inline bool tcg_out_mov(TCGContext *s, TCGType type, 503 TCGReg ret, TCGReg arg) 504{ 505 /* Simple reg-reg move, optimising out the 'do nothing' case */ 506 if (ret != arg) { 507 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 508 } 509 return true; 510} 511 512static void tcg_out_movi(TCGContext *s, TCGType type, 513 TCGReg ret, tcg_target_long arg) 514{ 515 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 516 arg = (int32_t)arg; 517 } 518 if (arg == (int16_t)arg) { 519 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 520 return; 521 } 522 if (arg == (uint16_t)arg) { 523 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 524 return; 525 } 526 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 527 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 528 } else { 529 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 530 if (arg & 0xffff0000ull) { 531 tcg_out_dsll(s, ret, ret, 16); 532 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 533 tcg_out_dsll(s, ret, ret, 16); 534 } else { 535 tcg_out_dsll(s, ret, ret, 32); 536 } 537 } 538 if (arg & 0xffff) { 539 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 540 } 541} 542 543static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 544{ 545 /* ret and arg can't be register tmp0 */ 546 tcg_debug_assert(ret != TCG_TMP0); 547 tcg_debug_assert(arg != TCG_TMP0); 548 549 /* With arg = abcd: */ 550 if (use_mips32r2_instructions) { 551 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 552 if (flags & TCG_BSWAP_OS) { 553 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 554 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 555 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 556 } 557 return; 558 } 559 560 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 561 if (!(flags & TCG_BSWAP_IZ)) { 562 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 563 } 564 if (flags & TCG_BSWAP_OS) { 565 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 566 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 567 } else { 568 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 569 if (flags & TCG_BSWAP_OZ) { 570 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 571 } 572 } 573 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 574} 575 576static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 577{ 578 bool ok = tcg_out_opc_jmp(s, OPC_JAL, sub); 579 tcg_debug_assert(ok); 580} 581 582static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 583{ 584 if (use_mips32r2_instructions) { 585 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 586 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 587 if (flags & TCG_BSWAP_OZ) { 588 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 589 } 590 } else { 591 if (flags & TCG_BSWAP_OZ) { 592 tcg_out_bswap_subr(s, bswap32u_addr); 593 } else { 594 tcg_out_bswap_subr(s, bswap32_addr); 595 } 596 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 597 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 598 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 599 } 600} 601 602static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 603{ 604 if (use_mips32r2_instructions) { 605 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 606 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 607 } else { 608 tcg_out_bswap_subr(s, bswap64_addr); 609 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 610 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 611 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 612 } 613} 614 615static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) 616{ 617 if (use_mips32r2_instructions) { 618 tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); 619 } else { 620 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); 621 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 24); 622 } 623} 624 625static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) 626{ 627 if (use_mips32r2_instructions) { 628 tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); 629 } else { 630 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); 631 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); 632 } 633} 634 635static inline void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 636{ 637 if (use_mips32r2_instructions) { 638 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 639 } else { 640 tcg_out_dsll(s, ret, arg, 32); 641 tcg_out_dsrl(s, ret, ret, 32); 642 } 643} 644 645static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 646 TCGReg addr, intptr_t ofs) 647{ 648 int16_t lo = ofs; 649 if (ofs != lo) { 650 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 651 if (addr != TCG_REG_ZERO) { 652 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 653 } 654 addr = TCG_TMP0; 655 } 656 tcg_out_opc_imm(s, opc, data, addr, lo); 657} 658 659static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 660 TCGReg arg1, intptr_t arg2) 661{ 662 MIPSInsn opc = OPC_LD; 663 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 664 opc = OPC_LW; 665 } 666 tcg_out_ldst(s, opc, arg, arg1, arg2); 667} 668 669static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 670 TCGReg arg1, intptr_t arg2) 671{ 672 MIPSInsn opc = OPC_SD; 673 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 674 opc = OPC_SW; 675 } 676 tcg_out_ldst(s, opc, arg, arg1, arg2); 677} 678 679static inline bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 680 TCGReg base, intptr_t ofs) 681{ 682 if (val == 0) { 683 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 684 return true; 685 } 686 return false; 687} 688 689static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 690 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 691 bool cbh, bool is_sub) 692{ 693 TCGReg th = TCG_TMP1; 694 695 /* If we have a negative constant such that negating it would 696 make the high part zero, we can (usually) eliminate one insn. */ 697 if (cbl && cbh && bh == -1 && bl != 0) { 698 bl = -bl; 699 bh = 0; 700 is_sub = !is_sub; 701 } 702 703 /* By operating on the high part first, we get to use the final 704 carry operation to move back from the temporary. */ 705 if (!cbh) { 706 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 707 } else if (bh != 0 || ah == rl) { 708 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 709 } else { 710 th = ah; 711 } 712 713 /* Note that tcg optimization should eliminate the bl == 0 case. */ 714 if (is_sub) { 715 if (cbl) { 716 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 717 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 718 } else { 719 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 720 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 721 } 722 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 723 } else { 724 if (cbl) { 725 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 726 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 727 } else if (rl == al && rl == bl) { 728 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 729 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 730 } else { 731 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 732 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 733 } 734 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 735 } 736} 737 738/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 739#define MIPS_CMP_INV 1 740#define MIPS_CMP_SWAP 2 741 742static const uint8_t mips_cmp_map[16] = { 743 [TCG_COND_LT] = 0, 744 [TCG_COND_LTU] = 0, 745 [TCG_COND_GE] = MIPS_CMP_INV, 746 [TCG_COND_GEU] = MIPS_CMP_INV, 747 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 748 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 749 [TCG_COND_GT] = MIPS_CMP_SWAP, 750 [TCG_COND_GTU] = MIPS_CMP_SWAP, 751}; 752 753static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 754 TCGReg arg1, TCGReg arg2) 755{ 756 MIPSInsn s_opc = OPC_SLTU; 757 int cmp_map; 758 759 switch (cond) { 760 case TCG_COND_EQ: 761 if (arg2 != 0) { 762 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 763 arg1 = ret; 764 } 765 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 766 break; 767 768 case TCG_COND_NE: 769 if (arg2 != 0) { 770 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 771 arg1 = ret; 772 } 773 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 774 break; 775 776 case TCG_COND_LT: 777 case TCG_COND_GE: 778 case TCG_COND_LE: 779 case TCG_COND_GT: 780 s_opc = OPC_SLT; 781 /* FALLTHRU */ 782 783 case TCG_COND_LTU: 784 case TCG_COND_GEU: 785 case TCG_COND_LEU: 786 case TCG_COND_GTU: 787 cmp_map = mips_cmp_map[cond]; 788 if (cmp_map & MIPS_CMP_SWAP) { 789 TCGReg t = arg1; 790 arg1 = arg2; 791 arg2 = t; 792 } 793 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 794 if (cmp_map & MIPS_CMP_INV) { 795 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 796 } 797 break; 798 799 default: 800 tcg_abort(); 801 break; 802 } 803} 804 805static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 806 TCGReg arg2, TCGLabel *l) 807{ 808 static const MIPSInsn b_zero[16] = { 809 [TCG_COND_LT] = OPC_BLTZ, 810 [TCG_COND_GT] = OPC_BGTZ, 811 [TCG_COND_LE] = OPC_BLEZ, 812 [TCG_COND_GE] = OPC_BGEZ, 813 }; 814 815 MIPSInsn s_opc = OPC_SLTU; 816 MIPSInsn b_opc; 817 int cmp_map; 818 819 switch (cond) { 820 case TCG_COND_EQ: 821 b_opc = OPC_BEQ; 822 break; 823 case TCG_COND_NE: 824 b_opc = OPC_BNE; 825 break; 826 827 case TCG_COND_LT: 828 case TCG_COND_GT: 829 case TCG_COND_LE: 830 case TCG_COND_GE: 831 if (arg2 == 0) { 832 b_opc = b_zero[cond]; 833 arg2 = arg1; 834 arg1 = 0; 835 break; 836 } 837 s_opc = OPC_SLT; 838 /* FALLTHRU */ 839 840 case TCG_COND_LTU: 841 case TCG_COND_GTU: 842 case TCG_COND_LEU: 843 case TCG_COND_GEU: 844 cmp_map = mips_cmp_map[cond]; 845 if (cmp_map & MIPS_CMP_SWAP) { 846 TCGReg t = arg1; 847 arg1 = arg2; 848 arg2 = t; 849 } 850 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 851 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 852 arg1 = TCG_TMP0; 853 arg2 = TCG_REG_ZERO; 854 break; 855 856 default: 857 tcg_abort(); 858 break; 859 } 860 861 tcg_out_opc_br(s, b_opc, arg1, arg2); 862 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 863 tcg_out_nop(s); 864} 865 866static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 867 TCGReg al, TCGReg ah, 868 TCGReg bl, TCGReg bh) 869{ 870 /* Merge highpart comparison into AH. */ 871 if (bh != 0) { 872 if (ah != 0) { 873 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 874 ah = tmp0; 875 } else { 876 ah = bh; 877 } 878 } 879 /* Merge lowpart comparison into AL. */ 880 if (bl != 0) { 881 if (al != 0) { 882 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 883 al = tmp1; 884 } else { 885 al = bl; 886 } 887 } 888 /* Merge high and low part comparisons into AL. */ 889 if (ah != 0) { 890 if (al != 0) { 891 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 892 al = tmp0; 893 } else { 894 al = ah; 895 } 896 } 897 return al; 898} 899 900static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 901 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 902{ 903 TCGReg tmp0 = TCG_TMP0; 904 TCGReg tmp1 = ret; 905 906 tcg_debug_assert(ret != TCG_TMP0); 907 if (ret == ah || ret == bh) { 908 tcg_debug_assert(ret != TCG_TMP1); 909 tmp1 = TCG_TMP1; 910 } 911 912 switch (cond) { 913 case TCG_COND_EQ: 914 case TCG_COND_NE: 915 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 916 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 917 break; 918 919 default: 920 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 921 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 922 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 923 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 924 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 925 break; 926 } 927} 928 929static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 930 TCGReg bl, TCGReg bh, TCGLabel *l) 931{ 932 TCGCond b_cond = TCG_COND_NE; 933 TCGReg tmp = TCG_TMP1; 934 935 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 936 With setcond, we emit between 3 and 10 insns and only 1 branch, 937 which ought to get better branch prediction. */ 938 switch (cond) { 939 case TCG_COND_EQ: 940 case TCG_COND_NE: 941 b_cond = cond; 942 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 943 break; 944 945 default: 946 /* Minimize code size by preferring a compare not requiring INV. */ 947 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 948 cond = tcg_invert_cond(cond); 949 b_cond = TCG_COND_EQ; 950 } 951 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 952 break; 953 } 954 955 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 956} 957 958static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 959 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 960{ 961 bool eqz = false; 962 963 /* If one of the values is zero, put it last to match SEL*Z instructions */ 964 if (use_mips32r6_instructions && v1 == 0) { 965 v1 = v2; 966 v2 = 0; 967 cond = tcg_invert_cond(cond); 968 } 969 970 switch (cond) { 971 case TCG_COND_EQ: 972 eqz = true; 973 /* FALLTHRU */ 974 case TCG_COND_NE: 975 if (c2 != 0) { 976 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 977 c1 = TCG_TMP0; 978 } 979 break; 980 981 default: 982 /* Minimize code size by preferring a compare not requiring INV. */ 983 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 984 cond = tcg_invert_cond(cond); 985 eqz = true; 986 } 987 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 988 c1 = TCG_TMP0; 989 break; 990 } 991 992 if (use_mips32r6_instructions) { 993 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 994 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 995 996 if (v2 != 0) { 997 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 998 } 999 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1000 if (v2 != 0) { 1001 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1002 } 1003 } else { 1004 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1005 1006 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1007 1008 /* This should be guaranteed via constraints */ 1009 tcg_debug_assert(v2 == ret); 1010 } 1011} 1012 1013static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1014{ 1015 /* Note that the ABI requires the called function's address to be 1016 loaded into T9, even if a direct branch is in range. */ 1017 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1018 1019 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1020 if (tail) { 1021 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1022 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1023 } 1024 } else { 1025 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1026 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1027 } 1028 } 1029} 1030 1031static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg) 1032{ 1033 tcg_out_call_int(s, arg, false); 1034 tcg_out_nop(s); 1035} 1036 1037#if defined(CONFIG_SOFTMMU) 1038#include "../tcg-ldst.c.inc" 1039 1040static void * const qemu_ld_helpers[16] = { 1041 [MO_UB] = helper_ret_ldub_mmu, 1042 [MO_SB] = helper_ret_ldsb_mmu, 1043 [MO_LEUW] = helper_le_lduw_mmu, 1044 [MO_LESW] = helper_le_ldsw_mmu, 1045 [MO_LEUL] = helper_le_ldul_mmu, 1046 [MO_LEQ] = helper_le_ldq_mmu, 1047 [MO_BEUW] = helper_be_lduw_mmu, 1048 [MO_BESW] = helper_be_ldsw_mmu, 1049 [MO_BEUL] = helper_be_ldul_mmu, 1050 [MO_BEQ] = helper_be_ldq_mmu, 1051#if TCG_TARGET_REG_BITS == 64 1052 [MO_LESL] = helper_le_ldsl_mmu, 1053 [MO_BESL] = helper_be_ldsl_mmu, 1054#endif 1055}; 1056 1057static void * const qemu_st_helpers[16] = { 1058 [MO_UB] = helper_ret_stb_mmu, 1059 [MO_LEUW] = helper_le_stw_mmu, 1060 [MO_LEUL] = helper_le_stl_mmu, 1061 [MO_LEQ] = helper_le_stq_mmu, 1062 [MO_BEUW] = helper_be_stw_mmu, 1063 [MO_BEUL] = helper_be_stl_mmu, 1064 [MO_BEQ] = helper_be_stq_mmu, 1065}; 1066 1067/* Helper routines for marshalling helper function arguments into 1068 * the correct registers and stack. 1069 * I is where we want to put this argument, and is updated and returned 1070 * for the next call. ARG is the argument itself. 1071 * 1072 * We provide routines for arguments which are: immediate, 32 bit 1073 * value in register, 16 and 8 bit values in register (which must be zero 1074 * extended before use) and 64 bit value in a lo:hi register pair. 1075 */ 1076 1077static int tcg_out_call_iarg_reg(TCGContext *s, int i, TCGReg arg) 1078{ 1079 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1080 tcg_out_mov(s, TCG_TYPE_REG, tcg_target_call_iarg_regs[i], arg); 1081 } else { 1082 /* For N32 and N64, the initial offset is different. But there 1083 we also have 8 argument register so we don't run out here. */ 1084 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1085 tcg_out_st(s, TCG_TYPE_REG, arg, TCG_REG_SP, 4 * i); 1086 } 1087 return i + 1; 1088} 1089 1090static int tcg_out_call_iarg_reg8(TCGContext *s, int i, TCGReg arg) 1091{ 1092 TCGReg tmp = TCG_TMP0; 1093 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1094 tmp = tcg_target_call_iarg_regs[i]; 1095 } 1096 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xff); 1097 return tcg_out_call_iarg_reg(s, i, tmp); 1098} 1099 1100static int tcg_out_call_iarg_reg16(TCGContext *s, int i, TCGReg arg) 1101{ 1102 TCGReg tmp = TCG_TMP0; 1103 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1104 tmp = tcg_target_call_iarg_regs[i]; 1105 } 1106 tcg_out_opc_imm(s, OPC_ANDI, tmp, arg, 0xffff); 1107 return tcg_out_call_iarg_reg(s, i, tmp); 1108} 1109 1110static int tcg_out_call_iarg_imm(TCGContext *s, int i, TCGArg arg) 1111{ 1112 TCGReg tmp = TCG_TMP0; 1113 if (arg == 0) { 1114 tmp = TCG_REG_ZERO; 1115 } else { 1116 if (i < ARRAY_SIZE(tcg_target_call_iarg_regs)) { 1117 tmp = tcg_target_call_iarg_regs[i]; 1118 } 1119 tcg_out_movi(s, TCG_TYPE_REG, tmp, arg); 1120 } 1121 return tcg_out_call_iarg_reg(s, i, tmp); 1122} 1123 1124static int tcg_out_call_iarg_reg2(TCGContext *s, int i, TCGReg al, TCGReg ah) 1125{ 1126 tcg_debug_assert(TCG_TARGET_REG_BITS == 32); 1127 i = (i + 1) & ~1; 1128 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? ah : al)); 1129 i = tcg_out_call_iarg_reg(s, i, (MIPS_BE ? al : ah)); 1130 return i; 1131} 1132 1133/* We expect to use a 16-bit negative offset from ENV. */ 1134QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1135QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1136 1137/* 1138 * Perform the tlb comparison operation. 1139 * The complete host address is placed in BASE. 1140 * Clobbers TMP0, TMP1, TMP2, TMP3. 1141 */ 1142static void tcg_out_tlb_load(TCGContext *s, TCGReg base, TCGReg addrl, 1143 TCGReg addrh, TCGMemOpIdx oi, 1144 tcg_insn_unit *label_ptr[2], bool is_load) 1145{ 1146 MemOp opc = get_memop(oi); 1147 unsigned s_bits = opc & MO_SIZE; 1148 unsigned a_bits = get_alignment_bits(opc); 1149 int mem_index = get_mmuidx(oi); 1150 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1151 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1152 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1153 int add_off = offsetof(CPUTLBEntry, addend); 1154 int cmp_off = (is_load ? offsetof(CPUTLBEntry, addr_read) 1155 : offsetof(CPUTLBEntry, addr_write)); 1156 target_ulong mask; 1157 1158 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1159 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1160 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1161 1162 /* Extract the TLB index from the address into TMP3. */ 1163 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrl, 1164 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1165 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1166 1167 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1168 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1169 1170 /* We don't currently support unaligned accesses. 1171 We could do so with mips32r6. */ 1172 if (a_bits < s_bits) { 1173 a_bits = s_bits; 1174 } 1175 1176 /* Mask the page bits, keeping the alignment bits to compare against. */ 1177 mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); 1178 1179 /* Load the (low-half) tlb comparator. */ 1180 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1181 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1182 tcg_out_movi(s, TCG_TYPE_I32, TCG_TMP1, mask); 1183 } else { 1184 tcg_out_ldst(s, (TARGET_LONG_BITS == 64 ? OPC_LD 1185 : TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW), 1186 TCG_TMP0, TCG_TMP3, cmp_off); 1187 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, mask); 1188 /* No second compare is required here; 1189 load the tlb addend for the fast path. */ 1190 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1191 } 1192 1193 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1194 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1195 tcg_out_ext32u(s, base, addrl); 1196 addrl = base; 1197 } 1198 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrl); 1199 1200 label_ptr[0] = s->code_ptr; 1201 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1202 1203 /* Load and test the high half tlb comparator. */ 1204 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1205 /* delay slot */ 1206 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1207 1208 /* Load the tlb addend for the fast path. */ 1209 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP2, TCG_TMP3, add_off); 1210 1211 label_ptr[1] = s->code_ptr; 1212 tcg_out_opc_br(s, OPC_BNE, addrh, TCG_TMP0); 1213 } 1214 1215 /* delay slot */ 1216 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP2, addrl); 1217} 1218 1219static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, 1220 TCGType ext, 1221 TCGReg datalo, TCGReg datahi, 1222 TCGReg addrlo, TCGReg addrhi, 1223 void *raddr, tcg_insn_unit *label_ptr[2]) 1224{ 1225 TCGLabelQemuLdst *label = new_ldst_label(s); 1226 1227 label->is_ld = is_ld; 1228 label->oi = oi; 1229 label->type = ext; 1230 label->datalo_reg = datalo; 1231 label->datahi_reg = datahi; 1232 label->addrlo_reg = addrlo; 1233 label->addrhi_reg = addrhi; 1234 label->raddr = tcg_splitwx_to_rx(raddr); 1235 label->label_ptr[0] = label_ptr[0]; 1236 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1237 label->label_ptr[1] = label_ptr[1]; 1238 } 1239} 1240 1241static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1242{ 1243 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1244 TCGMemOpIdx oi = l->oi; 1245 MemOp opc = get_memop(oi); 1246 TCGReg v0; 1247 int i; 1248 1249 /* resolve label address */ 1250 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1251 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1252 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1253 return false; 1254 } 1255 1256 i = 1; 1257 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1258 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1259 } else { 1260 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1261 } 1262 i = tcg_out_call_iarg_imm(s, i, oi); 1263 i = tcg_out_call_iarg_imm(s, i, (intptr_t)l->raddr); 1264 tcg_out_call_int(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)], false); 1265 /* delay slot */ 1266 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1267 1268 v0 = l->datalo_reg; 1269 if (TCG_TARGET_REG_BITS == 32 && (opc & MO_SIZE) == MO_64) { 1270 /* We eliminated V0 from the possible output registers, so it 1271 cannot be clobbered here. So we must move V1 first. */ 1272 if (MIPS_BE) { 1273 tcg_out_mov(s, TCG_TYPE_I32, v0, TCG_REG_V1); 1274 v0 = l->datahi_reg; 1275 } else { 1276 tcg_out_mov(s, TCG_TYPE_I32, l->datahi_reg, TCG_REG_V1); 1277 } 1278 } 1279 1280 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1281 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1282 return false; 1283 } 1284 1285 /* delay slot */ 1286 if (TCG_TARGET_REG_BITS == 64 && l->type == TCG_TYPE_I32) { 1287 /* we always sign-extend 32-bit loads */ 1288 tcg_out_opc_sa(s, OPC_SLL, v0, TCG_REG_V0, 0); 1289 } else { 1290 tcg_out_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO); 1291 } 1292 return true; 1293} 1294 1295static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1296{ 1297 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1298 TCGMemOpIdx oi = l->oi; 1299 MemOp opc = get_memop(oi); 1300 MemOp s_bits = opc & MO_SIZE; 1301 int i; 1302 1303 /* resolve label address */ 1304 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1305 || (TCG_TARGET_REG_BITS < TARGET_LONG_BITS 1306 && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1307 return false; 1308 } 1309 1310 i = 1; 1311 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1312 i = tcg_out_call_iarg_reg2(s, i, l->addrlo_reg, l->addrhi_reg); 1313 } else { 1314 i = tcg_out_call_iarg_reg(s, i, l->addrlo_reg); 1315 } 1316 switch (s_bits) { 1317 case MO_8: 1318 i = tcg_out_call_iarg_reg8(s, i, l->datalo_reg); 1319 break; 1320 case MO_16: 1321 i = tcg_out_call_iarg_reg16(s, i, l->datalo_reg); 1322 break; 1323 case MO_32: 1324 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1325 break; 1326 case MO_64: 1327 if (TCG_TARGET_REG_BITS == 32) { 1328 i = tcg_out_call_iarg_reg2(s, i, l->datalo_reg, l->datahi_reg); 1329 } else { 1330 i = tcg_out_call_iarg_reg(s, i, l->datalo_reg); 1331 } 1332 break; 1333 default: 1334 tcg_abort(); 1335 } 1336 i = tcg_out_call_iarg_imm(s, i, oi); 1337 1338 /* Tail call to the store helper. Thus force the return address 1339 computation to take place in the return address register. */ 1340 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_RA, (intptr_t)l->raddr); 1341 i = tcg_out_call_iarg_reg(s, i, TCG_REG_RA); 1342 tcg_out_call_int(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SIZE)], true); 1343 /* delay slot */ 1344 tcg_out_mov(s, TCG_TYPE_PTR, tcg_target_call_iarg_regs[0], TCG_AREG0); 1345 return true; 1346} 1347#endif 1348 1349static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1350 TCGReg base, MemOp opc, bool is_64) 1351{ 1352 switch (opc & (MO_SSIZE | MO_BSWAP)) { 1353 case MO_UB: 1354 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1355 break; 1356 case MO_SB: 1357 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1358 break; 1359 case MO_UW | MO_BSWAP: 1360 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1361 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OZ); 1362 break; 1363 case MO_UW: 1364 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1365 break; 1366 case MO_SW | MO_BSWAP: 1367 tcg_out_opc_imm(s, OPC_LHU, TCG_TMP1, base, 0); 1368 tcg_out_bswap16(s, lo, TCG_TMP1, TCG_BSWAP_IZ | TCG_BSWAP_OS); 1369 break; 1370 case MO_SW: 1371 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1372 break; 1373 case MO_UL | MO_BSWAP: 1374 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1375 if (use_mips32r2_instructions) { 1376 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1377 tcg_out_bswap32(s, lo, lo, TCG_BSWAP_IZ | TCG_BSWAP_OZ); 1378 } else { 1379 tcg_out_bswap_subr(s, bswap32u_addr); 1380 /* delay slot */ 1381 tcg_out_opc_imm(s, OPC_LWU, TCG_TMP0, base, 0); 1382 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1383 } 1384 break; 1385 } 1386 /* FALLTHRU */ 1387 case MO_SL | MO_BSWAP: 1388 if (use_mips32r2_instructions) { 1389 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1390 tcg_out_bswap32(s, lo, lo, 0); 1391 } else { 1392 tcg_out_bswap_subr(s, bswap32_addr); 1393 /* delay slot */ 1394 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1395 tcg_out_mov(s, TCG_TYPE_I32, lo, TCG_TMP3); 1396 } 1397 break; 1398 case MO_UL: 1399 if (TCG_TARGET_REG_BITS == 64 && is_64) { 1400 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1401 break; 1402 } 1403 /* FALLTHRU */ 1404 case MO_SL: 1405 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1406 break; 1407 case MO_Q | MO_BSWAP: 1408 if (TCG_TARGET_REG_BITS == 64) { 1409 if (use_mips32r2_instructions) { 1410 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1411 tcg_out_bswap64(s, lo, lo); 1412 } else { 1413 tcg_out_bswap_subr(s, bswap64_addr); 1414 /* delay slot */ 1415 tcg_out_opc_imm(s, OPC_LD, TCG_TMP0, base, 0); 1416 tcg_out_mov(s, TCG_TYPE_I64, lo, TCG_TMP3); 1417 } 1418 } else if (use_mips32r2_instructions) { 1419 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1420 tcg_out_opc_imm(s, OPC_LW, TCG_TMP1, base, 4); 1421 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, TCG_TMP0); 1422 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, TCG_TMP1); 1423 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? lo : hi, TCG_TMP0, 16); 1424 tcg_out_opc_sa(s, OPC_ROTR, MIPS_BE ? hi : lo, TCG_TMP1, 16); 1425 } else { 1426 tcg_out_bswap_subr(s, bswap32_addr); 1427 /* delay slot */ 1428 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 0); 1429 tcg_out_opc_imm(s, OPC_LW, TCG_TMP0, base, 4); 1430 tcg_out_bswap_subr(s, bswap32_addr); 1431 /* delay slot */ 1432 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? lo : hi, TCG_TMP3); 1433 tcg_out_mov(s, TCG_TYPE_I32, MIPS_BE ? hi : lo, TCG_TMP3); 1434 } 1435 break; 1436 case MO_Q: 1437 /* Prefer to load from offset 0 first, but allow for overlap. */ 1438 if (TCG_TARGET_REG_BITS == 64) { 1439 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1440 } else if (MIPS_BE ? hi != base : lo == base) { 1441 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1442 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1443 } else { 1444 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1445 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1446 } 1447 break; 1448 default: 1449 tcg_abort(); 1450 } 1451} 1452 1453static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) 1454{ 1455 TCGReg addr_regl, addr_regh __attribute__((unused)); 1456 TCGReg data_regl, data_regh; 1457 TCGMemOpIdx oi; 1458 MemOp opc; 1459#if defined(CONFIG_SOFTMMU) 1460 tcg_insn_unit *label_ptr[2]; 1461#endif 1462 TCGReg base = TCG_REG_A0; 1463 1464 data_regl = *args++; 1465 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1466 addr_regl = *args++; 1467 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1468 oi = *args++; 1469 opc = get_memop(oi); 1470 1471#if defined(CONFIG_SOFTMMU) 1472 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 1); 1473 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1474 add_qemu_ldst_label(s, 1, oi, 1475 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1476 data_regl, data_regh, addr_regl, addr_regh, 1477 s->code_ptr, label_ptr); 1478#else 1479 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1480 tcg_out_ext32u(s, base, addr_regl); 1481 addr_regl = base; 1482 } 1483 if (guest_base == 0 && data_regl != addr_regl) { 1484 base = addr_regl; 1485 } else if (guest_base == (int16_t)guest_base) { 1486 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1487 } else { 1488 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1489 } 1490 tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); 1491#endif 1492} 1493 1494static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1495 TCGReg base, MemOp opc) 1496{ 1497 /* Don't clutter the code below with checks to avoid bswapping ZERO. */ 1498 if ((lo | hi) == 0) { 1499 opc &= ~MO_BSWAP; 1500 } 1501 1502 switch (opc & (MO_SIZE | MO_BSWAP)) { 1503 case MO_8: 1504 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1505 break; 1506 1507 case MO_16 | MO_BSWAP: 1508 tcg_out_bswap16(s, TCG_TMP1, lo, 0); 1509 lo = TCG_TMP1; 1510 /* FALLTHRU */ 1511 case MO_16: 1512 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1513 break; 1514 1515 case MO_32 | MO_BSWAP: 1516 tcg_out_bswap32(s, TCG_TMP3, lo, 0); 1517 lo = TCG_TMP3; 1518 /* FALLTHRU */ 1519 case MO_32: 1520 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1521 break; 1522 1523 case MO_64 | MO_BSWAP: 1524 if (TCG_TARGET_REG_BITS == 64) { 1525 tcg_out_bswap64(s, TCG_TMP3, lo); 1526 tcg_out_opc_imm(s, OPC_SD, TCG_TMP3, base, 0); 1527 } else if (use_mips32r2_instructions) { 1528 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP0, 0, MIPS_BE ? lo : hi); 1529 tcg_out_opc_reg(s, OPC_WSBH, TCG_TMP1, 0, MIPS_BE ? hi : lo); 1530 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP0, TCG_TMP0, 16); 1531 tcg_out_opc_sa(s, OPC_ROTR, TCG_TMP1, TCG_TMP1, 16); 1532 tcg_out_opc_imm(s, OPC_SW, TCG_TMP0, base, 0); 1533 tcg_out_opc_imm(s, OPC_SW, TCG_TMP1, base, 4); 1534 } else { 1535 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? lo : hi, 0); 1536 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 0); 1537 tcg_out_bswap32(s, TCG_TMP3, MIPS_BE ? hi : lo, 0); 1538 tcg_out_opc_imm(s, OPC_SW, TCG_TMP3, base, 4); 1539 } 1540 break; 1541 case MO_64: 1542 if (TCG_TARGET_REG_BITS == 64) { 1543 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1544 } else { 1545 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1546 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1547 } 1548 break; 1549 1550 default: 1551 tcg_abort(); 1552 } 1553} 1554 1555static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) 1556{ 1557 TCGReg addr_regl, addr_regh __attribute__((unused)); 1558 TCGReg data_regl, data_regh; 1559 TCGMemOpIdx oi; 1560 MemOp opc; 1561#if defined(CONFIG_SOFTMMU) 1562 tcg_insn_unit *label_ptr[2]; 1563#endif 1564 TCGReg base = TCG_REG_A0; 1565 1566 data_regl = *args++; 1567 data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); 1568 addr_regl = *args++; 1569 addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); 1570 oi = *args++; 1571 opc = get_memop(oi); 1572 1573#if defined(CONFIG_SOFTMMU) 1574 tcg_out_tlb_load(s, base, addr_regl, addr_regh, oi, label_ptr, 0); 1575 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1576 add_qemu_ldst_label(s, 0, oi, 1577 (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), 1578 data_regl, data_regh, addr_regl, addr_regh, 1579 s->code_ptr, label_ptr); 1580#else 1581 base = TCG_REG_A0; 1582 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1583 tcg_out_ext32u(s, base, addr_regl); 1584 addr_regl = base; 1585 } 1586 if (guest_base == 0) { 1587 base = addr_regl; 1588 } else if (guest_base == (int16_t)guest_base) { 1589 tcg_out_opc_imm(s, ALIAS_PADDI, base, addr_regl, guest_base); 1590 } else { 1591 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_GUEST_BASE_REG, addr_regl); 1592 } 1593 tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); 1594#endif 1595} 1596 1597static void tcg_out_mb(TCGContext *s, TCGArg a0) 1598{ 1599 static const MIPSInsn sync[] = { 1600 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1601 as the former is an ordering barrier and the latter 1602 is a completion barrier. */ 1603 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1604 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1605 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1606 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1607 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1608 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1609 }; 1610 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1611} 1612 1613static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1614 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1615{ 1616 if (use_mips32r6_instructions) { 1617 if (a2 == width) { 1618 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1619 } else { 1620 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1621 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1622 } 1623 } else { 1624 if (a2 == width) { 1625 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1626 } else if (a0 == a2) { 1627 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1628 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1629 } else if (a0 != a1) { 1630 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1631 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1632 } else { 1633 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1634 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1635 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1636 } 1637 } 1638} 1639 1640static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, 1641 const TCGArg args[TCG_MAX_OP_ARGS], 1642 const int const_args[TCG_MAX_OP_ARGS]) 1643{ 1644 MIPSInsn i1, i2; 1645 TCGArg a0, a1, a2; 1646 int c2; 1647 1648 /* 1649 * Note that many operands use the constraint set "rZ". 1650 * We make use of the fact that 0 is the ZERO register, 1651 * and hence such cases need not check for const_args. 1652 */ 1653 a0 = args[0]; 1654 a1 = args[1]; 1655 a2 = args[2]; 1656 c2 = const_args[2]; 1657 1658 switch (opc) { 1659 case INDEX_op_exit_tb: 1660 { 1661 TCGReg b0 = TCG_REG_ZERO; 1662 1663 a0 = (intptr_t)a0; 1664 if (a0 & ~0xffff) { 1665 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 1666 b0 = TCG_REG_V0; 1667 } 1668 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1669 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, 1670 (uintptr_t)tb_ret_addr); 1671 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1672 } 1673 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 1674 } 1675 break; 1676 case INDEX_op_goto_tb: 1677 if (s->tb_jmp_insn_offset) { 1678 /* direct jump method */ 1679 s->tb_jmp_insn_offset[a0] = tcg_current_code_size(s); 1680 /* Avoid clobbering the address during retranslation. */ 1681 tcg_out32(s, OPC_J | (*(uint32_t *)s->code_ptr & 0x3ffffff)); 1682 } else { 1683 /* indirect jump method */ 1684 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 1685 (uintptr_t)(s->tb_jmp_target_addr + a0)); 1686 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1687 } 1688 tcg_out_nop(s); 1689 set_jmp_reset_offset(s, a0); 1690 break; 1691 case INDEX_op_goto_ptr: 1692 /* jmp to the given host address (could be epilogue) */ 1693 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1694 tcg_out_nop(s); 1695 break; 1696 case INDEX_op_br: 1697 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1698 arg_label(a0)); 1699 break; 1700 1701 case INDEX_op_ld8u_i32: 1702 case INDEX_op_ld8u_i64: 1703 i1 = OPC_LBU; 1704 goto do_ldst; 1705 case INDEX_op_ld8s_i32: 1706 case INDEX_op_ld8s_i64: 1707 i1 = OPC_LB; 1708 goto do_ldst; 1709 case INDEX_op_ld16u_i32: 1710 case INDEX_op_ld16u_i64: 1711 i1 = OPC_LHU; 1712 goto do_ldst; 1713 case INDEX_op_ld16s_i32: 1714 case INDEX_op_ld16s_i64: 1715 i1 = OPC_LH; 1716 goto do_ldst; 1717 case INDEX_op_ld_i32: 1718 case INDEX_op_ld32s_i64: 1719 i1 = OPC_LW; 1720 goto do_ldst; 1721 case INDEX_op_ld32u_i64: 1722 i1 = OPC_LWU; 1723 goto do_ldst; 1724 case INDEX_op_ld_i64: 1725 i1 = OPC_LD; 1726 goto do_ldst; 1727 case INDEX_op_st8_i32: 1728 case INDEX_op_st8_i64: 1729 i1 = OPC_SB; 1730 goto do_ldst; 1731 case INDEX_op_st16_i32: 1732 case INDEX_op_st16_i64: 1733 i1 = OPC_SH; 1734 goto do_ldst; 1735 case INDEX_op_st_i32: 1736 case INDEX_op_st32_i64: 1737 i1 = OPC_SW; 1738 goto do_ldst; 1739 case INDEX_op_st_i64: 1740 i1 = OPC_SD; 1741 do_ldst: 1742 tcg_out_ldst(s, i1, a0, a1, a2); 1743 break; 1744 1745 case INDEX_op_add_i32: 1746 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1747 goto do_binary; 1748 case INDEX_op_add_i64: 1749 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1750 goto do_binary; 1751 case INDEX_op_or_i32: 1752 case INDEX_op_or_i64: 1753 i1 = OPC_OR, i2 = OPC_ORI; 1754 goto do_binary; 1755 case INDEX_op_xor_i32: 1756 case INDEX_op_xor_i64: 1757 i1 = OPC_XOR, i2 = OPC_XORI; 1758 do_binary: 1759 if (c2) { 1760 tcg_out_opc_imm(s, i2, a0, a1, a2); 1761 break; 1762 } 1763 do_binaryv: 1764 tcg_out_opc_reg(s, i1, a0, a1, a2); 1765 break; 1766 1767 case INDEX_op_sub_i32: 1768 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1769 goto do_subtract; 1770 case INDEX_op_sub_i64: 1771 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1772 do_subtract: 1773 if (c2) { 1774 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1775 break; 1776 } 1777 goto do_binaryv; 1778 case INDEX_op_and_i32: 1779 if (c2 && a2 != (uint16_t)a2) { 1780 int msb = ctz32(~a2) - 1; 1781 tcg_debug_assert(use_mips32r2_instructions); 1782 tcg_debug_assert(is_p2m1(a2)); 1783 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1784 break; 1785 } 1786 i1 = OPC_AND, i2 = OPC_ANDI; 1787 goto do_binary; 1788 case INDEX_op_and_i64: 1789 if (c2 && a2 != (uint16_t)a2) { 1790 int msb = ctz64(~a2) - 1; 1791 tcg_debug_assert(use_mips32r2_instructions); 1792 tcg_debug_assert(is_p2m1(a2)); 1793 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1794 break; 1795 } 1796 i1 = OPC_AND, i2 = OPC_ANDI; 1797 goto do_binary; 1798 case INDEX_op_nor_i32: 1799 case INDEX_op_nor_i64: 1800 i1 = OPC_NOR; 1801 goto do_binaryv; 1802 1803 case INDEX_op_mul_i32: 1804 if (use_mips32_instructions) { 1805 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1806 break; 1807 } 1808 i1 = OPC_MULT, i2 = OPC_MFLO; 1809 goto do_hilo1; 1810 case INDEX_op_mulsh_i32: 1811 if (use_mips32r6_instructions) { 1812 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1813 break; 1814 } 1815 i1 = OPC_MULT, i2 = OPC_MFHI; 1816 goto do_hilo1; 1817 case INDEX_op_muluh_i32: 1818 if (use_mips32r6_instructions) { 1819 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1820 break; 1821 } 1822 i1 = OPC_MULTU, i2 = OPC_MFHI; 1823 goto do_hilo1; 1824 case INDEX_op_div_i32: 1825 if (use_mips32r6_instructions) { 1826 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1827 break; 1828 } 1829 i1 = OPC_DIV, i2 = OPC_MFLO; 1830 goto do_hilo1; 1831 case INDEX_op_divu_i32: 1832 if (use_mips32r6_instructions) { 1833 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1834 break; 1835 } 1836 i1 = OPC_DIVU, i2 = OPC_MFLO; 1837 goto do_hilo1; 1838 case INDEX_op_rem_i32: 1839 if (use_mips32r6_instructions) { 1840 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1841 break; 1842 } 1843 i1 = OPC_DIV, i2 = OPC_MFHI; 1844 goto do_hilo1; 1845 case INDEX_op_remu_i32: 1846 if (use_mips32r6_instructions) { 1847 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1848 break; 1849 } 1850 i1 = OPC_DIVU, i2 = OPC_MFHI; 1851 goto do_hilo1; 1852 case INDEX_op_mul_i64: 1853 if (use_mips32r6_instructions) { 1854 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1855 break; 1856 } 1857 i1 = OPC_DMULT, i2 = OPC_MFLO; 1858 goto do_hilo1; 1859 case INDEX_op_mulsh_i64: 1860 if (use_mips32r6_instructions) { 1861 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1862 break; 1863 } 1864 i1 = OPC_DMULT, i2 = OPC_MFHI; 1865 goto do_hilo1; 1866 case INDEX_op_muluh_i64: 1867 if (use_mips32r6_instructions) { 1868 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1869 break; 1870 } 1871 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1872 goto do_hilo1; 1873 case INDEX_op_div_i64: 1874 if (use_mips32r6_instructions) { 1875 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1876 break; 1877 } 1878 i1 = OPC_DDIV, i2 = OPC_MFLO; 1879 goto do_hilo1; 1880 case INDEX_op_divu_i64: 1881 if (use_mips32r6_instructions) { 1882 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1883 break; 1884 } 1885 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1886 goto do_hilo1; 1887 case INDEX_op_rem_i64: 1888 if (use_mips32r6_instructions) { 1889 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1890 break; 1891 } 1892 i1 = OPC_DDIV, i2 = OPC_MFHI; 1893 goto do_hilo1; 1894 case INDEX_op_remu_i64: 1895 if (use_mips32r6_instructions) { 1896 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1897 break; 1898 } 1899 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1900 do_hilo1: 1901 tcg_out_opc_reg(s, i1, 0, a1, a2); 1902 tcg_out_opc_reg(s, i2, a0, 0, 0); 1903 break; 1904 1905 case INDEX_op_muls2_i32: 1906 i1 = OPC_MULT; 1907 goto do_hilo2; 1908 case INDEX_op_mulu2_i32: 1909 i1 = OPC_MULTU; 1910 goto do_hilo2; 1911 case INDEX_op_muls2_i64: 1912 i1 = OPC_DMULT; 1913 goto do_hilo2; 1914 case INDEX_op_mulu2_i64: 1915 i1 = OPC_DMULTU; 1916 do_hilo2: 1917 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1918 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1919 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1920 break; 1921 1922 case INDEX_op_not_i32: 1923 case INDEX_op_not_i64: 1924 i1 = OPC_NOR; 1925 goto do_unary; 1926 case INDEX_op_ext8s_i32: 1927 case INDEX_op_ext8s_i64: 1928 i1 = OPC_SEB; 1929 goto do_unary; 1930 case INDEX_op_ext16s_i32: 1931 case INDEX_op_ext16s_i64: 1932 i1 = OPC_SEH; 1933 do_unary: 1934 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1935 break; 1936 1937 case INDEX_op_bswap16_i32: 1938 case INDEX_op_bswap16_i64: 1939 tcg_out_bswap16(s, a0, a1, a2); 1940 break; 1941 case INDEX_op_bswap32_i32: 1942 tcg_out_bswap32(s, a0, a1, 0); 1943 break; 1944 case INDEX_op_bswap32_i64: 1945 tcg_out_bswap32(s, a0, a1, a2); 1946 break; 1947 case INDEX_op_bswap64_i64: 1948 tcg_out_bswap64(s, a0, a1); 1949 break; 1950 case INDEX_op_extrh_i64_i32: 1951 tcg_out_dsra(s, a0, a1, 32); 1952 break; 1953 case INDEX_op_ext32s_i64: 1954 case INDEX_op_ext_i32_i64: 1955 case INDEX_op_extrl_i64_i32: 1956 tcg_out_opc_sa(s, OPC_SLL, a0, a1, 0); 1957 break; 1958 case INDEX_op_ext32u_i64: 1959 case INDEX_op_extu_i32_i64: 1960 tcg_out_ext32u(s, a0, a1); 1961 break; 1962 1963 case INDEX_op_sar_i32: 1964 i1 = OPC_SRAV, i2 = OPC_SRA; 1965 goto do_shift; 1966 case INDEX_op_shl_i32: 1967 i1 = OPC_SLLV, i2 = OPC_SLL; 1968 goto do_shift; 1969 case INDEX_op_shr_i32: 1970 i1 = OPC_SRLV, i2 = OPC_SRL; 1971 goto do_shift; 1972 case INDEX_op_rotr_i32: 1973 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1974 do_shift: 1975 if (c2) { 1976 tcg_out_opc_sa(s, i2, a0, a1, a2); 1977 break; 1978 } 1979 do_shiftv: 1980 tcg_out_opc_reg(s, i1, a0, a2, a1); 1981 break; 1982 case INDEX_op_rotl_i32: 1983 if (c2) { 1984 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 1985 } else { 1986 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1987 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 1988 } 1989 break; 1990 case INDEX_op_sar_i64: 1991 if (c2) { 1992 tcg_out_dsra(s, a0, a1, a2); 1993 break; 1994 } 1995 i1 = OPC_DSRAV; 1996 goto do_shiftv; 1997 case INDEX_op_shl_i64: 1998 if (c2) { 1999 tcg_out_dsll(s, a0, a1, a2); 2000 break; 2001 } 2002 i1 = OPC_DSLLV; 2003 goto do_shiftv; 2004 case INDEX_op_shr_i64: 2005 if (c2) { 2006 tcg_out_dsrl(s, a0, a1, a2); 2007 break; 2008 } 2009 i1 = OPC_DSRLV; 2010 goto do_shiftv; 2011 case INDEX_op_rotr_i64: 2012 if (c2) { 2013 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2014 break; 2015 } 2016 i1 = OPC_DROTRV; 2017 goto do_shiftv; 2018 case INDEX_op_rotl_i64: 2019 if (c2) { 2020 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2021 } else { 2022 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2023 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2024 } 2025 break; 2026 2027 case INDEX_op_clz_i32: 2028 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2029 break; 2030 case INDEX_op_clz_i64: 2031 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2032 break; 2033 2034 case INDEX_op_deposit_i32: 2035 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2036 break; 2037 case INDEX_op_deposit_i64: 2038 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2039 args[3] + args[4] - 1, args[3]); 2040 break; 2041 case INDEX_op_extract_i32: 2042 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2043 break; 2044 case INDEX_op_extract_i64: 2045 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2046 args[3] - 1, a2); 2047 break; 2048 2049 case INDEX_op_brcond_i32: 2050 case INDEX_op_brcond_i64: 2051 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2052 break; 2053 case INDEX_op_brcond2_i32: 2054 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2055 break; 2056 2057 case INDEX_op_movcond_i32: 2058 case INDEX_op_movcond_i64: 2059 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2060 break; 2061 2062 case INDEX_op_setcond_i32: 2063 case INDEX_op_setcond_i64: 2064 tcg_out_setcond(s, args[3], a0, a1, a2); 2065 break; 2066 case INDEX_op_setcond2_i32: 2067 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2068 break; 2069 2070 case INDEX_op_qemu_ld_i32: 2071 tcg_out_qemu_ld(s, args, false); 2072 break; 2073 case INDEX_op_qemu_ld_i64: 2074 tcg_out_qemu_ld(s, args, true); 2075 break; 2076 case INDEX_op_qemu_st_i32: 2077 tcg_out_qemu_st(s, args, false); 2078 break; 2079 case INDEX_op_qemu_st_i64: 2080 tcg_out_qemu_st(s, args, true); 2081 break; 2082 2083 case INDEX_op_add2_i32: 2084 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2085 const_args[4], const_args[5], false); 2086 break; 2087 case INDEX_op_sub2_i32: 2088 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2089 const_args[4], const_args[5], true); 2090 break; 2091 2092 case INDEX_op_mb: 2093 tcg_out_mb(s, a0); 2094 break; 2095 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2096 case INDEX_op_mov_i64: 2097 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2098 default: 2099 tcg_abort(); 2100 } 2101} 2102 2103static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2104{ 2105 switch (op) { 2106 case INDEX_op_goto_ptr: 2107 return C_O0_I1(r); 2108 2109 case INDEX_op_ld8u_i32: 2110 case INDEX_op_ld8s_i32: 2111 case INDEX_op_ld16u_i32: 2112 case INDEX_op_ld16s_i32: 2113 case INDEX_op_ld_i32: 2114 case INDEX_op_not_i32: 2115 case INDEX_op_bswap16_i32: 2116 case INDEX_op_bswap32_i32: 2117 case INDEX_op_ext8s_i32: 2118 case INDEX_op_ext16s_i32: 2119 case INDEX_op_extract_i32: 2120 case INDEX_op_ld8u_i64: 2121 case INDEX_op_ld8s_i64: 2122 case INDEX_op_ld16u_i64: 2123 case INDEX_op_ld16s_i64: 2124 case INDEX_op_ld32s_i64: 2125 case INDEX_op_ld32u_i64: 2126 case INDEX_op_ld_i64: 2127 case INDEX_op_not_i64: 2128 case INDEX_op_bswap16_i64: 2129 case INDEX_op_bswap32_i64: 2130 case INDEX_op_bswap64_i64: 2131 case INDEX_op_ext8s_i64: 2132 case INDEX_op_ext16s_i64: 2133 case INDEX_op_ext32s_i64: 2134 case INDEX_op_ext32u_i64: 2135 case INDEX_op_ext_i32_i64: 2136 case INDEX_op_extu_i32_i64: 2137 case INDEX_op_extrl_i64_i32: 2138 case INDEX_op_extrh_i64_i32: 2139 case INDEX_op_extract_i64: 2140 return C_O1_I1(r, r); 2141 2142 case INDEX_op_st8_i32: 2143 case INDEX_op_st16_i32: 2144 case INDEX_op_st_i32: 2145 case INDEX_op_st8_i64: 2146 case INDEX_op_st16_i64: 2147 case INDEX_op_st32_i64: 2148 case INDEX_op_st_i64: 2149 return C_O0_I2(rZ, r); 2150 2151 case INDEX_op_add_i32: 2152 case INDEX_op_add_i64: 2153 return C_O1_I2(r, r, rJ); 2154 case INDEX_op_sub_i32: 2155 case INDEX_op_sub_i64: 2156 return C_O1_I2(r, rZ, rN); 2157 case INDEX_op_mul_i32: 2158 case INDEX_op_mulsh_i32: 2159 case INDEX_op_muluh_i32: 2160 case INDEX_op_div_i32: 2161 case INDEX_op_divu_i32: 2162 case INDEX_op_rem_i32: 2163 case INDEX_op_remu_i32: 2164 case INDEX_op_nor_i32: 2165 case INDEX_op_setcond_i32: 2166 case INDEX_op_mul_i64: 2167 case INDEX_op_mulsh_i64: 2168 case INDEX_op_muluh_i64: 2169 case INDEX_op_div_i64: 2170 case INDEX_op_divu_i64: 2171 case INDEX_op_rem_i64: 2172 case INDEX_op_remu_i64: 2173 case INDEX_op_nor_i64: 2174 case INDEX_op_setcond_i64: 2175 return C_O1_I2(r, rZ, rZ); 2176 case INDEX_op_muls2_i32: 2177 case INDEX_op_mulu2_i32: 2178 case INDEX_op_muls2_i64: 2179 case INDEX_op_mulu2_i64: 2180 return C_O2_I2(r, r, r, r); 2181 case INDEX_op_and_i32: 2182 case INDEX_op_and_i64: 2183 return C_O1_I2(r, r, rIK); 2184 case INDEX_op_or_i32: 2185 case INDEX_op_xor_i32: 2186 case INDEX_op_or_i64: 2187 case INDEX_op_xor_i64: 2188 return C_O1_I2(r, r, rI); 2189 case INDEX_op_shl_i32: 2190 case INDEX_op_shr_i32: 2191 case INDEX_op_sar_i32: 2192 case INDEX_op_rotr_i32: 2193 case INDEX_op_rotl_i32: 2194 case INDEX_op_shl_i64: 2195 case INDEX_op_shr_i64: 2196 case INDEX_op_sar_i64: 2197 case INDEX_op_rotr_i64: 2198 case INDEX_op_rotl_i64: 2199 return C_O1_I2(r, r, ri); 2200 case INDEX_op_clz_i32: 2201 case INDEX_op_clz_i64: 2202 return C_O1_I2(r, r, rWZ); 2203 2204 case INDEX_op_deposit_i32: 2205 case INDEX_op_deposit_i64: 2206 return C_O1_I2(r, 0, rZ); 2207 case INDEX_op_brcond_i32: 2208 case INDEX_op_brcond_i64: 2209 return C_O0_I2(rZ, rZ); 2210 case INDEX_op_movcond_i32: 2211 case INDEX_op_movcond_i64: 2212 return (use_mips32r6_instructions 2213 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2214 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2215 case INDEX_op_add2_i32: 2216 case INDEX_op_sub2_i32: 2217 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2218 case INDEX_op_setcond2_i32: 2219 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2220 case INDEX_op_brcond2_i32: 2221 return C_O0_I4(rZ, rZ, rZ, rZ); 2222 2223 case INDEX_op_qemu_ld_i32: 2224 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2225 ? C_O1_I1(r, L) : C_O1_I2(r, L, L)); 2226 case INDEX_op_qemu_st_i32: 2227 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2228 ? C_O0_I2(SZ, S) : C_O0_I3(SZ, S, S)); 2229 case INDEX_op_qemu_ld_i64: 2230 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, L) 2231 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, L) 2232 : C_O2_I2(r, r, L, L)); 2233 case INDEX_op_qemu_st_i64: 2234 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(SZ, S) 2235 : TARGET_LONG_BITS == 32 ? C_O0_I3(SZ, SZ, S) 2236 : C_O0_I4(SZ, SZ, S, S)); 2237 2238 default: 2239 g_assert_not_reached(); 2240 } 2241} 2242 2243static const int tcg_target_callee_save_regs[] = { 2244 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2245 TCG_REG_S1, 2246 TCG_REG_S2, 2247 TCG_REG_S3, 2248 TCG_REG_S4, 2249 TCG_REG_S5, 2250 TCG_REG_S6, 2251 TCG_REG_S7, 2252 TCG_REG_S8, 2253 TCG_REG_RA, /* should be last for ABI compliance */ 2254}; 2255 2256/* The Linux kernel doesn't provide any information about the available 2257 instruction set. Probe it using a signal handler. */ 2258 2259 2260#ifndef use_movnz_instructions 2261bool use_movnz_instructions = false; 2262#endif 2263 2264#ifndef use_mips32_instructions 2265bool use_mips32_instructions = false; 2266#endif 2267 2268#ifndef use_mips32r2_instructions 2269bool use_mips32r2_instructions = false; 2270#endif 2271 2272static volatile sig_atomic_t got_sigill; 2273 2274static void sigill_handler(int signo, siginfo_t *si, void *data) 2275{ 2276 /* Skip the faulty instruction */ 2277 ucontext_t *uc = (ucontext_t *)data; 2278 uc->uc_mcontext.pc += 4; 2279 2280 got_sigill = 1; 2281} 2282 2283static void tcg_target_detect_isa(void) 2284{ 2285 struct sigaction sa_old, sa_new; 2286 2287 memset(&sa_new, 0, sizeof(sa_new)); 2288 sa_new.sa_flags = SA_SIGINFO; 2289 sa_new.sa_sigaction = sigill_handler; 2290 sigaction(SIGILL, &sa_new, &sa_old); 2291 2292 /* Probe for movn/movz, necessary to implement movcond. */ 2293#ifndef use_movnz_instructions 2294 got_sigill = 0; 2295 asm volatile(".set push\n" 2296 ".set mips32\n" 2297 "movn $zero, $zero, $zero\n" 2298 "movz $zero, $zero, $zero\n" 2299 ".set pop\n" 2300 : : : ); 2301 use_movnz_instructions = !got_sigill; 2302#endif 2303 2304 /* Probe for MIPS32 instructions. As no subsetting is allowed 2305 by the specification, it is only necessary to probe for one 2306 of the instructions. */ 2307#ifndef use_mips32_instructions 2308 got_sigill = 0; 2309 asm volatile(".set push\n" 2310 ".set mips32\n" 2311 "mul $zero, $zero\n" 2312 ".set pop\n" 2313 : : : ); 2314 use_mips32_instructions = !got_sigill; 2315#endif 2316 2317 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2318 available. As no subsetting is allowed by the specification, 2319 it is only necessary to probe for one of the instructions. */ 2320#ifndef use_mips32r2_instructions 2321 if (use_mips32_instructions) { 2322 got_sigill = 0; 2323 asm volatile(".set push\n" 2324 ".set mips32r2\n" 2325 "seb $zero, $zero\n" 2326 ".set pop\n" 2327 : : : ); 2328 use_mips32r2_instructions = !got_sigill; 2329 } 2330#endif 2331 2332 sigaction(SIGILL, &sa_old, NULL); 2333} 2334 2335static tcg_insn_unit *align_code_ptr(TCGContext *s) 2336{ 2337 uintptr_t p = (uintptr_t)s->code_ptr; 2338 if (p & 15) { 2339 p = (p + 15) & -16; 2340 s->code_ptr = (void *)p; 2341 } 2342 return s->code_ptr; 2343} 2344 2345/* Stack frame parameters. */ 2346#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2347#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2348#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2349 2350#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2351 + TCG_TARGET_STACK_ALIGN - 1) \ 2352 & -TCG_TARGET_STACK_ALIGN) 2353#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2354 2355/* We're expecting to be able to use an immediate for frame allocation. */ 2356QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2357 2358/* Generate global QEMU prologue and epilogue code */ 2359static void tcg_target_qemu_prologue(TCGContext *s) 2360{ 2361 int i; 2362 2363 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2364 2365 /* TB prologue */ 2366 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2367 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2368 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2369 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2370 } 2371 2372#ifndef CONFIG_SOFTMMU 2373 if (guest_base) { 2374 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2375 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2376 } 2377#endif 2378 2379 /* Call generated code */ 2380 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2381 /* delay slot */ 2382 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2383 2384 /* 2385 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2386 * and fall through to the rest of the epilogue. 2387 */ 2388 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2389 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2390 2391 /* TB epilogue */ 2392 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2393 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2394 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2395 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2396 } 2397 2398 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2399 /* delay slot */ 2400 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2401 2402 if (use_mips32r2_instructions) { 2403 return; 2404 } 2405 2406 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2407 clobbers TCG_TMP1, TCG_TMP2. */ 2408 2409 /* 2410 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2411 */ 2412 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2413 /* t3 = (ssss)d000 */ 2414 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2415 /* t1 = 000a */ 2416 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2417 /* t2 = 00c0 */ 2418 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2419 /* t3 = d00a */ 2420 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2421 /* t1 = 0abc */ 2422 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2423 /* t2 = 0c00 */ 2424 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2425 /* t1 = 00b0 */ 2426 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2427 /* t3 = dc0a */ 2428 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2429 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2430 /* t3 = dcba -- delay slot */ 2431 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2432 2433 if (TCG_TARGET_REG_BITS == 32) { 2434 return; 2435 } 2436 2437 /* 2438 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2439 */ 2440 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2441 /* t1 = (0000)000d */ 2442 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2443 /* t3 = 000a */ 2444 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2445 /* t1 = (0000)d000 */ 2446 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2447 /* t2 = 00c0 */ 2448 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2449 /* t3 = d00a */ 2450 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2451 /* t1 = 0abc */ 2452 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2453 /* t2 = 0c00 */ 2454 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2455 /* t1 = 00b0 */ 2456 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2457 /* t3 = dc0a */ 2458 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2459 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2460 /* t3 = dcba -- delay slot */ 2461 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2462 2463 /* 2464 * bswap64 -- 64-bit swap. a0 = abcdefgh 2465 */ 2466 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2467 /* t3 = h0000000 */ 2468 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2469 /* t1 = 0000000a */ 2470 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2471 2472 /* t2 = 000000g0 */ 2473 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2474 /* t3 = h000000a */ 2475 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2476 /* t1 = 00000abc */ 2477 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2478 /* t2 = 0g000000 */ 2479 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2480 /* t1 = 000000b0 */ 2481 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2482 2483 /* t3 = hg00000a */ 2484 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2485 /* t2 = 0000abcd */ 2486 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2487 /* t3 = hg0000ba */ 2488 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2489 2490 /* t1 = 000000c0 */ 2491 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2492 /* t2 = 0000000d */ 2493 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2494 /* t1 = 00000c00 */ 2495 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2496 /* t2 = 0000d000 */ 2497 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2498 2499 /* t3 = hg000cba */ 2500 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2501 /* t1 = 00abcdef */ 2502 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2503 /* t3 = hg00dcba */ 2504 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2505 2506 /* t2 = 0000000f */ 2507 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2508 /* t1 = 000000e0 */ 2509 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2510 /* t2 = 00f00000 */ 2511 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2512 /* t1 = 000e0000 */ 2513 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2514 2515 /* t3 = hgf0dcba */ 2516 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2517 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2518 /* t3 = hgfedcba -- delay slot */ 2519 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2520} 2521 2522static void tcg_target_init(TCGContext *s) 2523{ 2524 tcg_target_detect_isa(); 2525 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2526 if (TCG_TARGET_REG_BITS == 64) { 2527 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2528 } 2529 2530 tcg_target_call_clobber_regs = 0; 2531 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2532 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2533 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2534 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2535 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2536 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2537 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2538 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2539 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2540 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2541 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2542 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2543 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2544 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2545 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2546 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2547 2548 s->reserved_regs = 0; 2549 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2550 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2551 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2552 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2553 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2554 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2555 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2556 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2557 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2558 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2559} 2560 2561void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, 2562 uintptr_t jmp_rw, uintptr_t addr) 2563{ 2564 qatomic_set((uint32_t *)jmp_rw, deposit32(OPC_J, 0, 26, addr >> 2)); 2565 flush_idcache_range(jmp_rx, jmp_rw, 4); 2566} 2567 2568typedef struct { 2569 DebugFrameHeader h; 2570 uint8_t fde_def_cfa[4]; 2571 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2572} DebugFrame; 2573 2574#define ELF_HOST_MACHINE EM_MIPS 2575/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2576 which is good because they're really quite complicated for MIPS. */ 2577 2578static const DebugFrame debug_frame = { 2579 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2580 .h.cie.id = -1, 2581 .h.cie.version = 1, 2582 .h.cie.code_align = 1, 2583 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2584 .h.cie.return_column = TCG_REG_RA, 2585 2586 /* Total FDE size does not include the "len" member. */ 2587 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2588 2589 .fde_def_cfa = { 2590 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2591 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2592 (FRAME_SIZE >> 7) 2593 }, 2594 .fde_reg_ofs = { 2595 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2596 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2597 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2598 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2599 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2600 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2601 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2602 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2603 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2604 } 2605}; 2606 2607void tcg_register_jit(const void *buf, size_t buf_size) 2608{ 2609 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2610} 2611