1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_WSZ 0x800 /* word size */ 191 192#define ALL_GENERAL_REGS 0xffffffffu 193 194static bool is_p2m1(tcg_target_long val) 195{ 196 return val && ((val + 1) & val) == 0; 197} 198 199/* test if a constant matches the constraint */ 200static bool tcg_target_const_match(int64_t val, int ct, 201 TCGType type, TCGCond cond, int vece) 202{ 203 if (ct & TCG_CT_CONST) { 204 return 1; 205 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 206 return 1; 207 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 208 return 1; 209 } else if ((ct & TCG_CT_CONST_P2M1) 210 && use_mips32r2_instructions && is_p2m1(val)) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_WSZ) 213 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 214 return 1; 215 } 216 return 0; 217} 218 219/* instruction opcodes */ 220typedef enum { 221 OPC_J = 002 << 26, 222 OPC_JAL = 003 << 26, 223 OPC_BEQ = 004 << 26, 224 OPC_BNE = 005 << 26, 225 OPC_BLEZ = 006 << 26, 226 OPC_BGTZ = 007 << 26, 227 OPC_ADDIU = 011 << 26, 228 OPC_SLTI = 012 << 26, 229 OPC_SLTIU = 013 << 26, 230 OPC_ANDI = 014 << 26, 231 OPC_ORI = 015 << 26, 232 OPC_XORI = 016 << 26, 233 OPC_LUI = 017 << 26, 234 OPC_BNEL = 025 << 26, 235 OPC_BNEZALC_R6 = 030 << 26, 236 OPC_DADDIU = 031 << 26, 237 OPC_LDL = 032 << 26, 238 OPC_LDR = 033 << 26, 239 OPC_LB = 040 << 26, 240 OPC_LH = 041 << 26, 241 OPC_LWL = 042 << 26, 242 OPC_LW = 043 << 26, 243 OPC_LBU = 044 << 26, 244 OPC_LHU = 045 << 26, 245 OPC_LWR = 046 << 26, 246 OPC_LWU = 047 << 26, 247 OPC_SB = 050 << 26, 248 OPC_SH = 051 << 26, 249 OPC_SWL = 052 << 26, 250 OPC_SW = 053 << 26, 251 OPC_SDL = 054 << 26, 252 OPC_SDR = 055 << 26, 253 OPC_SWR = 056 << 26, 254 OPC_LD = 067 << 26, 255 OPC_SD = 077 << 26, 256 257 OPC_SPECIAL = 000 << 26, 258 OPC_SLL = OPC_SPECIAL | 000, 259 OPC_SRL = OPC_SPECIAL | 002, 260 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 261 OPC_SRA = OPC_SPECIAL | 003, 262 OPC_SLLV = OPC_SPECIAL | 004, 263 OPC_SRLV = OPC_SPECIAL | 006, 264 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 265 OPC_SRAV = OPC_SPECIAL | 007, 266 OPC_JR_R5 = OPC_SPECIAL | 010, 267 OPC_JALR = OPC_SPECIAL | 011, 268 OPC_MOVZ = OPC_SPECIAL | 012, 269 OPC_MOVN = OPC_SPECIAL | 013, 270 OPC_SYNC = OPC_SPECIAL | 017, 271 OPC_MFHI = OPC_SPECIAL | 020, 272 OPC_MFLO = OPC_SPECIAL | 022, 273 OPC_DSLLV = OPC_SPECIAL | 024, 274 OPC_DSRLV = OPC_SPECIAL | 026, 275 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 276 OPC_DSRAV = OPC_SPECIAL | 027, 277 OPC_MULT = OPC_SPECIAL | 030, 278 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 279 OPC_MUH = OPC_SPECIAL | 030 | 0300, 280 OPC_MULTU = OPC_SPECIAL | 031, 281 OPC_MULU = OPC_SPECIAL | 031 | 0200, 282 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 283 OPC_DIV = OPC_SPECIAL | 032, 284 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 285 OPC_MOD = OPC_SPECIAL | 032 | 0300, 286 OPC_DIVU = OPC_SPECIAL | 033, 287 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 288 OPC_MODU = OPC_SPECIAL | 033 | 0300, 289 OPC_DMULT = OPC_SPECIAL | 034, 290 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 291 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 292 OPC_DMULTU = OPC_SPECIAL | 035, 293 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 294 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 295 OPC_DDIV = OPC_SPECIAL | 036, 296 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 297 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 298 OPC_DDIVU = OPC_SPECIAL | 037, 299 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 300 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 301 OPC_ADDU = OPC_SPECIAL | 041, 302 OPC_SUBU = OPC_SPECIAL | 043, 303 OPC_AND = OPC_SPECIAL | 044, 304 OPC_OR = OPC_SPECIAL | 045, 305 OPC_XOR = OPC_SPECIAL | 046, 306 OPC_NOR = OPC_SPECIAL | 047, 307 OPC_SLT = OPC_SPECIAL | 052, 308 OPC_SLTU = OPC_SPECIAL | 053, 309 OPC_DADDU = OPC_SPECIAL | 055, 310 OPC_DSUBU = OPC_SPECIAL | 057, 311 OPC_SELEQZ = OPC_SPECIAL | 065, 312 OPC_SELNEZ = OPC_SPECIAL | 067, 313 OPC_DSLL = OPC_SPECIAL | 070, 314 OPC_DSRL = OPC_SPECIAL | 072, 315 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 316 OPC_DSRA = OPC_SPECIAL | 073, 317 OPC_DSLL32 = OPC_SPECIAL | 074, 318 OPC_DSRL32 = OPC_SPECIAL | 076, 319 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 320 OPC_DSRA32 = OPC_SPECIAL | 077, 321 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 322 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 323 324 OPC_REGIMM = 001 << 26, 325 OPC_BLTZ = OPC_REGIMM | (000 << 16), 326 OPC_BGEZ = OPC_REGIMM | (001 << 16), 327 328 OPC_SPECIAL2 = 034 << 26, 329 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 330 OPC_CLZ = OPC_SPECIAL2 | 040, 331 OPC_DCLZ = OPC_SPECIAL2 | 044, 332 333 OPC_SPECIAL3 = 037 << 26, 334 OPC_EXT = OPC_SPECIAL3 | 000, 335 OPC_DEXTM = OPC_SPECIAL3 | 001, 336 OPC_DEXTU = OPC_SPECIAL3 | 002, 337 OPC_DEXT = OPC_SPECIAL3 | 003, 338 OPC_INS = OPC_SPECIAL3 | 004, 339 OPC_DINSM = OPC_SPECIAL3 | 005, 340 OPC_DINSU = OPC_SPECIAL3 | 006, 341 OPC_DINS = OPC_SPECIAL3 | 007, 342 OPC_WSBH = OPC_SPECIAL3 | 00240, 343 OPC_DSBH = OPC_SPECIAL3 | 00244, 344 OPC_DSHD = OPC_SPECIAL3 | 00544, 345 OPC_SEB = OPC_SPECIAL3 | 02040, 346 OPC_SEH = OPC_SPECIAL3 | 03040, 347 348 /* MIPS r6 doesn't have JR, JALR should be used instead */ 349 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 350 351 /* 352 * MIPS r6 replaces MUL with an alternative encoding which is 353 * backwards-compatible at the assembly level. 354 */ 355 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 356 357 /* MIPS r6 introduced names for weaker variants of SYNC. These are 358 backward compatible to previous architecture revisions. */ 359 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 360 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 361 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 362 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 363 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 364 365 /* Aliases for convenience. */ 366 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 367 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 368} MIPSInsn; 369 370/* 371 * Type reg 372 */ 373static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 374 TCGReg rd, TCGReg rs, TCGReg rt) 375{ 376 int32_t inst; 377 378 inst = opc; 379 inst |= (rs & 0x1F) << 21; 380 inst |= (rt & 0x1F) << 16; 381 inst |= (rd & 0x1F) << 11; 382 tcg_out32(s, inst); 383} 384 385/* 386 * Type immediate 387 */ 388static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 389 TCGReg rt, TCGReg rs, TCGArg imm) 390{ 391 int32_t inst; 392 393 inst = opc; 394 inst |= (rs & 0x1F) << 21; 395 inst |= (rt & 0x1F) << 16; 396 inst |= (imm & 0xffff); 397 tcg_out32(s, inst); 398} 399 400/* 401 * Type bitfield 402 */ 403static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 404 TCGReg rs, int msb, int lsb) 405{ 406 int32_t inst; 407 408 inst = opc; 409 inst |= (rs & 0x1F) << 21; 410 inst |= (rt & 0x1F) << 16; 411 inst |= (msb & 0x1F) << 11; 412 inst |= (lsb & 0x1F) << 6; 413 tcg_out32(s, inst); 414} 415 416static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 417 MIPSInsn oph, TCGReg rt, TCGReg rs, 418 int msb, int lsb) 419{ 420 if (lsb >= 32) { 421 opc = oph; 422 msb -= 32; 423 lsb -= 32; 424 } else if (msb >= 32) { 425 opc = opm; 426 msb -= 32; 427 } 428 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 429} 430 431/* 432 * Type branch 433 */ 434static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 435{ 436 tcg_out_opc_imm(s, opc, rt, rs, 0); 437} 438 439/* 440 * Type sa 441 */ 442static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 443 TCGReg rd, TCGReg rt, TCGArg sa) 444{ 445 int32_t inst; 446 447 inst = opc; 448 inst |= (rt & 0x1F) << 16; 449 inst |= (rd & 0x1F) << 11; 450 inst |= (sa & 0x1F) << 6; 451 tcg_out32(s, inst); 452 453} 454 455static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 456 TCGReg rd, TCGReg rt, TCGArg sa) 457{ 458 int32_t inst; 459 460 inst = (sa & 32 ? opc2 : opc1); 461 inst |= (rt & 0x1F) << 16; 462 inst |= (rd & 0x1F) << 11; 463 inst |= (sa & 0x1F) << 6; 464 tcg_out32(s, inst); 465} 466 467/* 468 * Type jump. 469 * Returns true if the branch was in range and the insn was emitted. 470 */ 471static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 472{ 473 uintptr_t dest = (uintptr_t)target; 474 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 475 int32_t inst; 476 477 /* The pc-region branch happens within the 256MB region of 478 the delay slot (thus the +4). */ 479 if ((from ^ dest) & -(1 << 28)) { 480 return false; 481 } 482 tcg_debug_assert((dest & 3) == 0); 483 484 inst = opc; 485 inst |= (dest >> 2) & 0x3ffffff; 486 tcg_out32(s, inst); 487 return true; 488} 489 490static void tcg_out_nop(TCGContext *s) 491{ 492 tcg_out32(s, 0); 493} 494 495static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 496{ 497 memset(p, 0, count * sizeof(tcg_insn_unit)); 498} 499 500static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 501{ 502 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 503} 504 505static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 506{ 507 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 508} 509 510static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 511{ 512 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 513} 514 515static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 516{ 517 /* Simple reg-reg move, optimising out the 'do nothing' case */ 518 if (ret != arg) { 519 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 520 } 521 return true; 522} 523 524static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 525{ 526 if (arg == (int16_t)arg) { 527 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 528 return true; 529 } 530 if (arg == (uint16_t)arg) { 531 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 532 return true; 533 } 534 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 535 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 536 return true; 537 } 538 return false; 539} 540 541static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 542{ 543 /* 544 * All signed 32-bit constants are loadable with two immediates, 545 * and everything else requires more work. 546 */ 547 if (arg == (int32_t)arg) { 548 if (!tcg_out_movi_one(s, ret, arg)) { 549 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 550 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 551 } 552 return true; 553 } 554 return false; 555} 556 557static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 558 tcg_target_long arg, TCGReg tbreg) 559{ 560 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 561 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 562} 563 564static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 565 tcg_target_long arg, TCGReg tbreg) 566{ 567 tcg_target_long tmp; 568 int sh, lo; 569 570 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 571 arg = (int32_t)arg; 572 } 573 574 /* Load all 32-bit constants. */ 575 if (tcg_out_movi_two(s, ret, arg)) { 576 return; 577 } 578 assert(TCG_TARGET_REG_BITS == 64); 579 580 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 581 tmp = tcg_tbrel_diff(s, (void *)arg); 582 if (tmp == (int16_t)tmp) { 583 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 584 return; 585 } 586 if (tcg_out_movi_two(s, ret, tmp)) { 587 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 588 return; 589 } 590 591 /* 592 * Load bitmasks with a right-shift. This is good for things 593 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 594 * or similarly using LUI. For this to work, bit 31 must be set. 595 */ 596 if (arg > 0 && (int32_t)arg < 0) { 597 sh = clz64(arg); 598 if (tcg_out_movi_one(s, ret, arg << sh)) { 599 tcg_out_dsrl(s, ret, ret, sh); 600 return; 601 } 602 } 603 604 /* 605 * Load slightly larger constants using left-shift. 606 * Limit this sequence to 3 insns to avoid too much expansion. 607 */ 608 sh = ctz64(arg); 609 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 610 tcg_out_dsll(s, ret, ret, sh); 611 return; 612 } 613 614 /* 615 * Load slightly larger constants using left-shift and add/or. 616 * Prefer addi with a negative immediate when that would produce 617 * a larger shift. For this to work, bits 15 and 16 must be set. 618 */ 619 lo = arg & 0xffff; 620 if (lo) { 621 if ((arg & 0x18000) == 0x18000) { 622 lo = (int16_t)arg; 623 } 624 tmp = arg - lo; 625 sh = ctz64(tmp); 626 tmp >>= sh; 627 if (tcg_out_movi_one(s, ret, tmp)) { 628 tcg_out_dsll(s, ret, ret, sh); 629 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 630 return; 631 } 632 } 633 634 /* Otherwise, put 64-bit constants into the constant pool. */ 635 tcg_out_movi_pool(s, ret, arg, tbreg); 636} 637 638static void tcg_out_movi(TCGContext *s, TCGType type, 639 TCGReg ret, tcg_target_long arg) 640{ 641 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 642 tcg_out_movi_int(s, type, ret, arg, tbreg); 643} 644 645static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 646{ 647 tcg_debug_assert(use_mips32r2_instructions); 648 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 649} 650 651static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 652{ 653 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 654} 655 656static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 657{ 658 tcg_debug_assert(use_mips32r2_instructions); 659 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 660} 661 662static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 663{ 664 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 665} 666 667static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 668{ 669 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 670 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 671} 672 673static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 674{ 675 if (rd != rs) { 676 tcg_out_ext32s(s, rd, rs); 677 } 678} 679 680static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 681{ 682 tcg_out_ext32u(s, rd, rs); 683} 684 685static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 686{ 687 tcg_out_ext32s(s, rd, rs); 688} 689 690static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 691{ 692 return false; 693} 694 695static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 696 tcg_target_long imm) 697{ 698 /* This function is only used for passing structs by reference. */ 699 g_assert_not_reached(); 700} 701 702static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 703{ 704 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 705 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 706 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 707 } 708} 709 710static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 711{ 712 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 713 if (use_mips32r2_instructions) { 714 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 715 } else { 716 tcg_out_dsll(s, ret, arg, 32); 717 tcg_out_dsrl(s, ret, ret, 32); 718 } 719} 720 721static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 722 TCGReg addr, intptr_t ofs) 723{ 724 int16_t lo = ofs; 725 if (ofs != lo) { 726 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 727 if (addr != TCG_REG_ZERO) { 728 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 729 } 730 addr = TCG_TMP0; 731 } 732 tcg_out_opc_imm(s, opc, data, addr, lo); 733} 734 735static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 736 TCGReg arg1, intptr_t arg2) 737{ 738 MIPSInsn opc = OPC_LD; 739 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 740 opc = OPC_LW; 741 } 742 tcg_out_ldst(s, opc, arg, arg1, arg2); 743} 744 745static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 746 TCGReg arg1, intptr_t arg2) 747{ 748 MIPSInsn opc = OPC_SD; 749 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 750 opc = OPC_SW; 751 } 752 tcg_out_ldst(s, opc, arg, arg1, arg2); 753} 754 755static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 756 TCGReg base, intptr_t ofs) 757{ 758 if (val == 0) { 759 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 760 return true; 761 } 762 return false; 763} 764 765#define SETCOND_INV TCG_TARGET_NB_REGS 766#define SETCOND_NEZ (SETCOND_INV << 1) 767#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 768 769static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 770 TCGReg arg1, TCGReg arg2) 771{ 772 int flags = 0; 773 774 switch (cond) { 775 case TCG_COND_EQ: /* -> NE */ 776 case TCG_COND_GE: /* -> LT */ 777 case TCG_COND_GEU: /* -> LTU */ 778 case TCG_COND_LE: /* -> GT */ 779 case TCG_COND_LEU: /* -> GTU */ 780 cond = tcg_invert_cond(cond); 781 flags ^= SETCOND_INV; 782 break; 783 default: 784 break; 785 } 786 787 switch (cond) { 788 case TCG_COND_NE: 789 flags |= SETCOND_NEZ; 790 if (arg2 == 0) { 791 return arg1 | flags; 792 } 793 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 794 break; 795 case TCG_COND_LT: 796 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 797 break; 798 case TCG_COND_LTU: 799 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 800 break; 801 case TCG_COND_GT: 802 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 803 break; 804 case TCG_COND_GTU: 805 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 806 break; 807 default: 808 g_assert_not_reached(); 809 } 810 return ret | flags; 811} 812 813static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 814{ 815 if (tmpflags != ret) { 816 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 817 818 switch (tmpflags & SETCOND_FLAGS) { 819 case SETCOND_INV: 820 /* Intermediate result is boolean: simply invert. */ 821 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 822 break; 823 case SETCOND_NEZ: 824 /* Intermediate result is zero/non-zero: test != 0. */ 825 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 826 break; 827 case SETCOND_NEZ | SETCOND_INV: 828 /* Intermediate result is zero/non-zero: test == 0. */ 829 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 830 break; 831 default: 832 g_assert_not_reached(); 833 } 834 } 835} 836 837static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 838 TCGReg ret, TCGReg arg1, TCGReg arg2) 839{ 840 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 841 tcg_out_setcond_end(s, ret, tmpflags); 842} 843 844static const TCGOutOpSetcond outop_setcond = { 845 .base.static_constraint = C_O1_I2(r, r, rz), 846 .out_rrr = tgen_setcond, 847}; 848 849static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 850 TCGReg ret, TCGReg arg1, TCGReg arg2) 851{ 852 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 853 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 854 855 /* If intermediate result is zero/non-zero: test != 0. */ 856 if (tmpflags & SETCOND_NEZ) { 857 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 858 tmp = ret; 859 } 860 /* Produce the 0/-1 result. */ 861 if (tmpflags & SETCOND_INV) { 862 tcg_out_opc_imm(s, OPC_ADDIU, ret, tmp, -1); 863 } else { 864 tcg_out_opc_reg(s, OPC_SUBU, ret, TCG_REG_ZERO, tmp); 865 } 866} 867 868static const TCGOutOpSetcond outop_negsetcond = { 869 .base.static_constraint = C_O1_I2(r, r, rz), 870 .out_rrr = tgen_negsetcond, 871}; 872 873static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 874 TCGReg arg1, TCGReg arg2, TCGLabel *l) 875{ 876 static const MIPSInsn b_zero[16] = { 877 [TCG_COND_LT] = OPC_BLTZ, 878 [TCG_COND_GT] = OPC_BGTZ, 879 [TCG_COND_LE] = OPC_BLEZ, 880 [TCG_COND_GE] = OPC_BGEZ, 881 }; 882 883 MIPSInsn b_opc = 0; 884 885 switch (cond) { 886 case TCG_COND_EQ: 887 b_opc = OPC_BEQ; 888 break; 889 case TCG_COND_NE: 890 b_opc = OPC_BNE; 891 break; 892 case TCG_COND_LT: 893 case TCG_COND_GT: 894 case TCG_COND_LE: 895 case TCG_COND_GE: 896 if (arg2 == 0) { 897 b_opc = b_zero[cond]; 898 arg2 = arg1; 899 arg1 = 0; 900 } 901 break; 902 default: 903 break; 904 } 905 906 if (b_opc == 0) { 907 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 908 909 arg2 = TCG_REG_ZERO; 910 arg1 = tmpflags & ~SETCOND_FLAGS; 911 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 912 } 913 914 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 915 tcg_out_opc_br(s, b_opc, arg1, arg2); 916 tcg_out_nop(s); 917} 918 919static const TCGOutOpBrcond outop_brcond = { 920 .base.static_constraint = C_O0_I2(r, rz), 921 .out_rr = tgen_brcond, 922}; 923 924void tcg_out_br(TCGContext *s, TCGLabel *l) 925{ 926 tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, l); 927} 928 929static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 930 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 931{ 932 int flags = 0; 933 934 switch (cond) { 935 case TCG_COND_EQ: 936 flags |= SETCOND_INV; 937 /* fall through */ 938 case TCG_COND_NE: 939 flags |= SETCOND_NEZ; 940 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 941 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 942 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 943 break; 944 945 default: 946 tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); 947 tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), 948 TCG_TMP1, al, bl); 949 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 950 tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); 951 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 952 break; 953 } 954 return ret | flags; 955} 956 957static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 958 TCGReg al, TCGReg ah, 959 TCGArg bl, bool const_bl, 960 TCGArg bh, bool const_bh) 961{ 962 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 963 tcg_out_setcond_end(s, ret, tmpflags); 964} 965 966#if TCG_TARGET_REG_BITS != 32 967__attribute__((unused)) 968#endif 969static const TCGOutOpSetcond2 outop_setcond2 = { 970 .base.static_constraint = C_O1_I4(r, r, r, rz, rz), 971 .out = tgen_setcond2, 972}; 973 974static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 975 TCGArg bl, bool const_bl, 976 TCGArg bh, bool const_bh, TCGLabel *l) 977{ 978 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 979 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 980 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 981 982 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 983 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 984 tcg_out_nop(s); 985} 986 987#if TCG_TARGET_REG_BITS != 32 988__attribute__((unused)) 989#endif 990static const TCGOutOpBrcond2 outop_brcond2 = { 991 .base.static_constraint = C_O0_I4(r, r, rz, rz), 992 .out = tgen_brcond2, 993}; 994 995static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 996 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 997 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 998{ 999 int tmpflags; 1000 bool eqz; 1001 1002 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1003 if (use_mips32r6_instructions && v1 == 0) { 1004 v1 = v2; 1005 v2 = 0; 1006 cond = tcg_invert_cond(cond); 1007 } 1008 1009 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1010 c1 = tmpflags & ~SETCOND_FLAGS; 1011 eqz = tmpflags & SETCOND_INV; 1012 1013 if (use_mips32r6_instructions) { 1014 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1015 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1016 1017 if (v2 != 0) { 1018 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1019 } 1020 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1021 if (v2 != 0) { 1022 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1023 } 1024 return; 1025 } 1026 1027 /* This should be guaranteed via constraints */ 1028 tcg_debug_assert(v2 == ret); 1029 1030 if (use_movnz_instructions) { 1031 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1032 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1033 } else { 1034 /* Invert the condition in order to branch over the move. */ 1035 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1036 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1037 tcg_out_nop(s); 1038 /* Open-code tcg_out_mov, without the nop-move check. */ 1039 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1040 } 1041} 1042 1043static const TCGOutOpMovcond outop_movcond = { 1044 .base.static_constraint = (use_mips32r6_instructions 1045 ? C_O1_I4(r, r, rz, rz, rz) 1046 : C_O1_I4(r, r, rz, rz, 0)), 1047 .out = tgen_movcond, 1048}; 1049 1050static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1051{ 1052 /* 1053 * Note that __mips_abicalls requires the called function's address 1054 * to be loaded into $25 (t9), even if a direct branch is in range. 1055 * 1056 * For n64, always drop the pointer into the constant pool. 1057 * We can re-use helper addresses often and do not want any 1058 * of the longer sequences tcg_out_movi may try. 1059 */ 1060 if (sizeof(uintptr_t) == 8) { 1061 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1062 } else { 1063 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1064 } 1065 1066 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1067 if (tail) { 1068 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1069 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1070 } 1071 } else { 1072 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1073 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1074 } 1075 } 1076} 1077 1078static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1079 const TCGHelperInfo *info) 1080{ 1081 tcg_out_call_int(s, arg, false); 1082 tcg_out_nop(s); 1083} 1084 1085/* We have four temps, we might as well expose three of them. */ 1086static const TCGLdstHelperParam ldst_helper_param = { 1087 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1088}; 1089 1090static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1091{ 1092 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1093 MemOp opc = get_memop(l->oi); 1094 1095 /* resolve label address */ 1096 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1097 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1098 return false; 1099 } 1100 1101 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1102 1103 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1104 /* delay slot */ 1105 tcg_out_nop(s); 1106 1107 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1108 1109 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1110 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1111 return false; 1112 } 1113 1114 /* delay slot */ 1115 tcg_out_nop(s); 1116 return true; 1117} 1118 1119static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1120{ 1121 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1122 MemOp opc = get_memop(l->oi); 1123 1124 /* resolve label address */ 1125 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1126 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1127 return false; 1128 } 1129 1130 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1131 1132 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1133 /* delay slot */ 1134 tcg_out_nop(s); 1135 1136 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1137 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1138 return false; 1139 } 1140 1141 /* delay slot */ 1142 tcg_out_nop(s); 1143 return true; 1144} 1145 1146typedef struct { 1147 TCGReg base; 1148 TCGAtomAlign aa; 1149} HostAddress; 1150 1151bool tcg_target_has_memory_bswap(MemOp memop) 1152{ 1153 return false; 1154} 1155 1156/* We expect to use a 16-bit negative offset from ENV. */ 1157#define MIN_TLB_MASK_TABLE_OFS -32768 1158 1159/* 1160 * For system-mode, perform the TLB load and compare. 1161 * For user-mode, perform any required alignment tests. 1162 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1163 * is required and fill in @h with the host address for the fast path. 1164 */ 1165static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1166 TCGReg addr, MemOpIdx oi, bool is_ld) 1167{ 1168 TCGType addr_type = s->addr_type; 1169 TCGLabelQemuLdst *ldst = NULL; 1170 MemOp opc = get_memop(oi); 1171 MemOp a_bits; 1172 unsigned s_bits = opc & MO_SIZE; 1173 unsigned a_mask; 1174 TCGReg base; 1175 1176 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1177 a_bits = h->aa.align; 1178 a_mask = (1 << a_bits) - 1; 1179 1180 if (tcg_use_softmmu) { 1181 unsigned s_mask = (1 << s_bits) - 1; 1182 int mem_index = get_mmuidx(oi); 1183 int fast_off = tlb_mask_table_ofs(s, mem_index); 1184 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1185 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1186 int add_off = offsetof(CPUTLBEntry, addend); 1187 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1188 : offsetof(CPUTLBEntry, addr_write); 1189 1190 ldst = new_ldst_label(s); 1191 ldst->is_ld = is_ld; 1192 ldst->oi = oi; 1193 ldst->addr_reg = addr; 1194 1195 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1196 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1197 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1198 1199 /* Extract the TLB index from the address into TMP3. */ 1200 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1201 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1202 s->page_bits - CPU_TLB_ENTRY_BITS); 1203 } else { 1204 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1205 } 1206 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1207 1208 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1209 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1210 1211 /* Load the tlb comparator. */ 1212 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1213 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1214 cmp_off + HOST_BIG_ENDIAN * 4); 1215 } else { 1216 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1217 } 1218 1219 /* Load the tlb addend for the fast path. */ 1220 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1221 1222 /* 1223 * Mask the page bits, keeping the alignment bits to compare against. 1224 * For unaligned accesses, compare against the end of the access to 1225 * verify that it does not cross a page boundary. 1226 */ 1227 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1228 if (a_mask < s_mask) { 1229 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1230 || addr_type == TCG_TYPE_I32 1231 ? OPC_ADDIU : OPC_DADDIU), 1232 TCG_TMP2, addr, s_mask - a_mask); 1233 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1234 } else { 1235 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1236 } 1237 1238 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1239 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1240 tcg_out_ext32u(s, TCG_TMP2, addr); 1241 addr = TCG_TMP2; 1242 } 1243 1244 ldst->label_ptr[0] = s->code_ptr; 1245 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1246 1247 /* delay slot */ 1248 base = TCG_TMP3; 1249 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1250 } else { 1251 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1252 ldst = new_ldst_label(s); 1253 1254 ldst->is_ld = is_ld; 1255 ldst->oi = oi; 1256 ldst->addr_reg = addr; 1257 1258 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1259 tcg_debug_assert(a_bits < 16); 1260 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1261 1262 ldst->label_ptr[0] = s->code_ptr; 1263 if (use_mips32r6_instructions) { 1264 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1265 } else { 1266 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1267 tcg_out_nop(s); 1268 } 1269 } 1270 1271 base = addr; 1272 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1273 tcg_out_ext32u(s, TCG_REG_A0, base); 1274 base = TCG_REG_A0; 1275 } 1276 if (guest_base) { 1277 if (guest_base == (int16_t)guest_base) { 1278 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1279 } else { 1280 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1281 TCG_GUEST_BASE_REG); 1282 } 1283 base = TCG_REG_A0; 1284 } 1285 } 1286 1287 h->base = base; 1288 return ldst; 1289} 1290 1291static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1292 TCGReg base, MemOp opc, TCGType type) 1293{ 1294 switch (opc & MO_SSIZE) { 1295 case MO_UB: 1296 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1297 break; 1298 case MO_SB: 1299 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1300 break; 1301 case MO_UW: 1302 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1303 break; 1304 case MO_SW: 1305 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1306 break; 1307 case MO_UL: 1308 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1309 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1310 break; 1311 } 1312 /* FALLTHRU */ 1313 case MO_SL: 1314 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1315 break; 1316 case MO_UQ: 1317 /* Prefer to load from offset 0 first, but allow for overlap. */ 1318 if (TCG_TARGET_REG_BITS == 64) { 1319 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1320 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1321 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1322 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1323 } else { 1324 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1325 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1326 } 1327 break; 1328 default: 1329 g_assert_not_reached(); 1330 } 1331} 1332 1333static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1334 TCGReg base, MemOp opc, TCGType type) 1335{ 1336 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1337 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1338 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1339 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1340 bool sgn = opc & MO_SIGN; 1341 1342 switch (opc & MO_SIZE) { 1343 case MO_16: 1344 if (HOST_BIG_ENDIAN) { 1345 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1346 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1347 if (use_mips32r2_instructions) { 1348 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1349 } else { 1350 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1351 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1352 } 1353 } else if (use_mips32r2_instructions && lo != base) { 1354 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1355 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1356 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1357 } else { 1358 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1359 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1360 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1361 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1362 } 1363 break; 1364 1365 case MO_32: 1366 tcg_out_opc_imm(s, lw1, lo, base, 0); 1367 tcg_out_opc_imm(s, lw2, lo, base, 3); 1368 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1369 tcg_out_ext32u(s, lo, lo); 1370 } 1371 break; 1372 1373 case MO_64: 1374 if (TCG_TARGET_REG_BITS == 64) { 1375 tcg_out_opc_imm(s, ld1, lo, base, 0); 1376 tcg_out_opc_imm(s, ld2, lo, base, 7); 1377 } else { 1378 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1379 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1380 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1381 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1382 } 1383 break; 1384 1385 default: 1386 g_assert_not_reached(); 1387 } 1388} 1389 1390static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1391 TCGReg addr, MemOpIdx oi, TCGType data_type) 1392{ 1393 MemOp opc = get_memop(oi); 1394 TCGLabelQemuLdst *ldst; 1395 HostAddress h; 1396 1397 ldst = prepare_host_addr(s, &h, addr, oi, true); 1398 1399 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1400 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1401 } else { 1402 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1403 } 1404 1405 if (ldst) { 1406 ldst->type = data_type; 1407 ldst->datalo_reg = datalo; 1408 ldst->datahi_reg = datahi; 1409 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1410 } 1411} 1412 1413static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1414 TCGReg base, MemOp opc) 1415{ 1416 switch (opc & MO_SIZE) { 1417 case MO_8: 1418 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1419 break; 1420 case MO_16: 1421 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1422 break; 1423 case MO_32: 1424 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1425 break; 1426 case MO_64: 1427 if (TCG_TARGET_REG_BITS == 64) { 1428 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1429 } else { 1430 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1431 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1432 } 1433 break; 1434 default: 1435 g_assert_not_reached(); 1436 } 1437} 1438 1439static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1440 TCGReg base, MemOp opc) 1441{ 1442 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1443 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1444 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1445 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1446 1447 switch (opc & MO_SIZE) { 1448 case MO_16: 1449 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1450 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1451 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1452 break; 1453 1454 case MO_32: 1455 tcg_out_opc_imm(s, sw1, lo, base, 0); 1456 tcg_out_opc_imm(s, sw2, lo, base, 3); 1457 break; 1458 1459 case MO_64: 1460 if (TCG_TARGET_REG_BITS == 64) { 1461 tcg_out_opc_imm(s, sd1, lo, base, 0); 1462 tcg_out_opc_imm(s, sd2, lo, base, 7); 1463 } else { 1464 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1465 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1466 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1467 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1468 } 1469 break; 1470 1471 default: 1472 g_assert_not_reached(); 1473 } 1474} 1475 1476static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1477 TCGReg addr, MemOpIdx oi, TCGType data_type) 1478{ 1479 MemOp opc = get_memop(oi); 1480 TCGLabelQemuLdst *ldst; 1481 HostAddress h; 1482 1483 ldst = prepare_host_addr(s, &h, addr, oi, false); 1484 1485 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1486 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1487 } else { 1488 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1489 } 1490 1491 if (ldst) { 1492 ldst->type = data_type; 1493 ldst->datalo_reg = datalo; 1494 ldst->datahi_reg = datahi; 1495 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1496 } 1497} 1498 1499static void tcg_out_mb(TCGContext *s, unsigned a0) 1500{ 1501 static const MIPSInsn sync[] = { 1502 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1503 as the former is an ordering barrier and the latter 1504 is a completion barrier. */ 1505 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1506 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1507 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1508 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1509 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1510 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1511 }; 1512 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1513} 1514 1515static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1516{ 1517 TCGReg base = TCG_REG_ZERO; 1518 int16_t lo = 0; 1519 1520 if (a0) { 1521 intptr_t ofs; 1522 if (TCG_TARGET_REG_BITS == 64) { 1523 ofs = tcg_tbrel_diff(s, (void *)a0); 1524 lo = ofs; 1525 if (ofs == lo) { 1526 base = TCG_REG_TB; 1527 } else { 1528 base = TCG_REG_V0; 1529 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1530 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1531 } 1532 } else { 1533 ofs = a0; 1534 lo = ofs; 1535 base = TCG_REG_V0; 1536 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1537 } 1538 } 1539 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1540 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1541 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1542 } 1543 /* delay slot */ 1544 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1545} 1546 1547static void tcg_out_goto_tb(TCGContext *s, int which) 1548{ 1549 intptr_t ofs = get_jmp_target_addr(s, which); 1550 TCGReg base, dest; 1551 1552 /* indirect jump method */ 1553 if (TCG_TARGET_REG_BITS == 64) { 1554 dest = TCG_REG_TB; 1555 base = TCG_REG_TB; 1556 ofs = tcg_tbrel_diff(s, (void *)ofs); 1557 } else { 1558 dest = TCG_TMP0; 1559 base = TCG_REG_ZERO; 1560 } 1561 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1562 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1563 /* delay slot */ 1564 tcg_out_nop(s); 1565 1566 set_jmp_reset_offset(s, which); 1567 if (TCG_TARGET_REG_BITS == 64) { 1568 /* For the unlinked case, need to reset TCG_REG_TB. */ 1569 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1570 -tcg_current_code_size(s)); 1571 } 1572} 1573 1574static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) 1575{ 1576 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1577 if (TCG_TARGET_REG_BITS == 64) { 1578 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 1579 } else { 1580 tcg_out_nop(s); 1581 } 1582} 1583 1584void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1585 uintptr_t jmp_rx, uintptr_t jmp_rw) 1586{ 1587 /* Always indirect, nothing to do */ 1588} 1589 1590 1591static void tgen_add(TCGContext *s, TCGType type, 1592 TCGReg a0, TCGReg a1, TCGReg a2) 1593{ 1594 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1595 tcg_out_opc_reg(s, insn, a0, a1, a2); 1596} 1597 1598static void tgen_addi(TCGContext *s, TCGType type, 1599 TCGReg a0, TCGReg a1, tcg_target_long a2) 1600{ 1601 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1602 tcg_out_opc_imm(s, insn, a0, a1, a2); 1603} 1604 1605static const TCGOutOpBinary outop_add = { 1606 .base.static_constraint = C_O1_I2(r, r, rJ), 1607 .out_rrr = tgen_add, 1608 .out_rri = tgen_addi, 1609}; 1610 1611static const TCGOutOpBinary outop_addco = { 1612 .base.static_constraint = C_NotImplemented, 1613}; 1614 1615static const TCGOutOpAddSubCarry outop_addci = { 1616 .base.static_constraint = C_NotImplemented, 1617}; 1618 1619static const TCGOutOpBinary outop_addcio = { 1620 .base.static_constraint = C_NotImplemented, 1621}; 1622 1623static void tcg_out_set_carry(TCGContext *s) 1624{ 1625 g_assert_not_reached(); 1626} 1627 1628static void tgen_and(TCGContext *s, TCGType type, 1629 TCGReg a0, TCGReg a1, TCGReg a2) 1630{ 1631 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1632} 1633 1634static void tgen_andi(TCGContext *s, TCGType type, 1635 TCGReg a0, TCGReg a1, tcg_target_long a2) 1636{ 1637 int msb; 1638 1639 if (a2 == (uint16_t)a2) { 1640 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1641 return; 1642 } 1643 1644 tcg_debug_assert(use_mips32r2_instructions); 1645 tcg_debug_assert(is_p2m1(a2)); 1646 msb = ctz64(~a2) - 1; 1647 if (type == TCG_TYPE_I32) { 1648 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1649 } else { 1650 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1651 } 1652} 1653 1654static const TCGOutOpBinary outop_and = { 1655 .base.static_constraint = C_O1_I2(r, r, rIK), 1656 .out_rrr = tgen_and, 1657 .out_rri = tgen_andi, 1658}; 1659 1660static const TCGOutOpBinary outop_andc = { 1661 .base.static_constraint = C_NotImplemented, 1662}; 1663 1664static void tgen_clz(TCGContext *s, TCGType type, 1665 TCGReg a0, TCGReg a1, TCGReg a2) 1666{ 1667 if (use_mips32r6_instructions) { 1668 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1669 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1670 tgen_movcond(s, TCG_TYPE_REG, TCG_COND_EQ, a0, a1, a2, false, 1671 TCG_TMP0, false, TCG_REG_ZERO, false); 1672 } else { 1673 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1674 if (a0 == a2) { 1675 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1676 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1677 } else if (a0 != a1) { 1678 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1679 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1680 } else { 1681 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1682 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1683 tcg_out_mov(s, type, a0, TCG_TMP0); 1684 } 1685 } 1686} 1687 1688static void tgen_clzi(TCGContext *s, TCGType type, 1689 TCGReg a0, TCGReg a1, tcg_target_long a2) 1690{ 1691 if (a2 == 0) { 1692 tgen_clz(s, type, a0, a1, TCG_REG_ZERO); 1693 } else if (use_mips32r6_instructions) { 1694 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1695 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1696 } else { 1697 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1698 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1699 } 1700} 1701 1702static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 1703{ 1704 return use_mips32r2_instructions ? C_O1_I2(r, r, rzW) : C_NotImplemented; 1705} 1706 1707static const TCGOutOpBinary outop_clz = { 1708 .base.static_constraint = C_Dynamic, 1709 .base.dynamic_constraint = cset_clz, 1710 .out_rrr = tgen_clz, 1711 .out_rri = tgen_clzi, 1712}; 1713 1714static const TCGOutOpUnary outop_ctpop = { 1715 .base.static_constraint = C_NotImplemented, 1716}; 1717 1718static const TCGOutOpBinary outop_ctz = { 1719 .base.static_constraint = C_NotImplemented, 1720}; 1721 1722static void tgen_divs(TCGContext *s, TCGType type, 1723 TCGReg a0, TCGReg a1, TCGReg a2) 1724{ 1725 if (use_mips32r6_instructions) { 1726 if (type == TCG_TYPE_I32) { 1727 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1728 } else { 1729 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1730 } 1731 } else { 1732 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1733 tcg_out_opc_reg(s, insn, 0, a1, a2); 1734 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1735 } 1736} 1737 1738static const TCGOutOpBinary outop_divs = { 1739 .base.static_constraint = C_O1_I2(r, r, r), 1740 .out_rrr = tgen_divs, 1741}; 1742 1743static const TCGOutOpDivRem outop_divs2 = { 1744 .base.static_constraint = C_NotImplemented, 1745}; 1746 1747static void tgen_divu(TCGContext *s, TCGType type, 1748 TCGReg a0, TCGReg a1, TCGReg a2) 1749{ 1750 if (use_mips32r6_instructions) { 1751 if (type == TCG_TYPE_I32) { 1752 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1753 } else { 1754 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1755 } 1756 } else { 1757 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1758 tcg_out_opc_reg(s, insn, 0, a1, a2); 1759 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1760 } 1761} 1762 1763static const TCGOutOpBinary outop_divu = { 1764 .base.static_constraint = C_O1_I2(r, r, r), 1765 .out_rrr = tgen_divu, 1766}; 1767 1768static const TCGOutOpDivRem outop_divu2 = { 1769 .base.static_constraint = C_NotImplemented, 1770}; 1771 1772static const TCGOutOpBinary outop_eqv = { 1773 .base.static_constraint = C_NotImplemented, 1774}; 1775 1776#if TCG_TARGET_REG_BITS == 64 1777static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 1778{ 1779 tcg_out_dsra(s, a0, a1, 32); 1780} 1781 1782static const TCGOutOpUnary outop_extrh_i64_i32 = { 1783 .base.static_constraint = C_O1_I1(r, r), 1784 .out_rr = tgen_extrh_i64_i32, 1785}; 1786#endif 1787 1788static void tgen_mul(TCGContext *s, TCGType type, 1789 TCGReg a0, TCGReg a1, TCGReg a2) 1790{ 1791 MIPSInsn insn; 1792 1793 if (type == TCG_TYPE_I32) { 1794 if (use_mips32_instructions) { 1795 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1796 return; 1797 } 1798 insn = OPC_MULT; 1799 } else { 1800 if (use_mips32r6_instructions) { 1801 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1802 return; 1803 } 1804 insn = OPC_DMULT; 1805 } 1806 tcg_out_opc_reg(s, insn, 0, a1, a2); 1807 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1808} 1809 1810static const TCGOutOpBinary outop_mul = { 1811 .base.static_constraint = C_O1_I2(r, r, r), 1812 .out_rrr = tgen_mul, 1813}; 1814 1815static void tgen_muls2(TCGContext *s, TCGType type, 1816 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1817{ 1818 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1819 tcg_out_opc_reg(s, insn, 0, a2, a3); 1820 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1821 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1822} 1823 1824static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1825{ 1826 return use_mips32r6_instructions ? C_NotImplemented : C_O2_I2(r, r, r, r); 1827} 1828 1829static const TCGOutOpMul2 outop_muls2 = { 1830 .base.static_constraint = C_Dynamic, 1831 .base.dynamic_constraint = cset_mul2, 1832 .out_rrrr = tgen_muls2, 1833}; 1834 1835static void tgen_mulsh(TCGContext *s, TCGType type, 1836 TCGReg a0, TCGReg a1, TCGReg a2) 1837{ 1838 if (use_mips32r6_instructions) { 1839 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH; 1840 tcg_out_opc_reg(s, insn, a0, a1, a2); 1841 } else { 1842 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1843 tcg_out_opc_reg(s, insn, 0, a1, a2); 1844 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1845 } 1846} 1847 1848static const TCGOutOpBinary outop_mulsh = { 1849 .base.static_constraint = C_O1_I2(r, r, r), 1850 .out_rrr = tgen_mulsh, 1851}; 1852 1853static void tgen_mulu2(TCGContext *s, TCGType type, 1854 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1855{ 1856 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1857 tcg_out_opc_reg(s, insn, 0, a2, a3); 1858 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1859 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1860} 1861 1862static const TCGOutOpMul2 outop_mulu2 = { 1863 .base.static_constraint = C_Dynamic, 1864 .base.dynamic_constraint = cset_mul2, 1865 .out_rrrr = tgen_mulu2, 1866}; 1867 1868static void tgen_muluh(TCGContext *s, TCGType type, 1869 TCGReg a0, TCGReg a1, TCGReg a2) 1870{ 1871 if (use_mips32r6_instructions) { 1872 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; 1873 tcg_out_opc_reg(s, insn, a0, a1, a2); 1874 } else { 1875 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1876 tcg_out_opc_reg(s, insn, 0, a1, a2); 1877 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1878 } 1879} 1880 1881static const TCGOutOpBinary outop_muluh = { 1882 .base.static_constraint = C_O1_I2(r, r, r), 1883 .out_rrr = tgen_muluh, 1884}; 1885 1886static const TCGOutOpBinary outop_nand = { 1887 .base.static_constraint = C_NotImplemented, 1888}; 1889 1890static void tgen_nor(TCGContext *s, TCGType type, 1891 TCGReg a0, TCGReg a1, TCGReg a2) 1892{ 1893 tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); 1894} 1895 1896static const TCGOutOpBinary outop_nor = { 1897 .base.static_constraint = C_O1_I2(r, r, r), 1898 .out_rrr = tgen_nor, 1899}; 1900 1901static void tgen_or(TCGContext *s, TCGType type, 1902 TCGReg a0, TCGReg a1, TCGReg a2) 1903{ 1904 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1905} 1906 1907static void tgen_ori(TCGContext *s, TCGType type, 1908 TCGReg a0, TCGReg a1, tcg_target_long a2) 1909{ 1910 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1911} 1912 1913static const TCGOutOpBinary outop_or = { 1914 .base.static_constraint = C_O1_I2(r, r, rI), 1915 .out_rrr = tgen_or, 1916 .out_rri = tgen_ori, 1917}; 1918 1919static const TCGOutOpBinary outop_orc = { 1920 .base.static_constraint = C_NotImplemented, 1921}; 1922 1923static void tgen_rems(TCGContext *s, TCGType type, 1924 TCGReg a0, TCGReg a1, TCGReg a2) 1925{ 1926 if (use_mips32r6_instructions) { 1927 if (type == TCG_TYPE_I32) { 1928 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1929 } else { 1930 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1931 } 1932 } else { 1933 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1934 tcg_out_opc_reg(s, insn, 0, a1, a2); 1935 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1936 } 1937} 1938 1939static const TCGOutOpBinary outop_rems = { 1940 .base.static_constraint = C_O1_I2(r, r, r), 1941 .out_rrr = tgen_rems, 1942}; 1943 1944static void tgen_remu(TCGContext *s, TCGType type, 1945 TCGReg a0, TCGReg a1, TCGReg a2) 1946{ 1947 if (use_mips32r6_instructions) { 1948 if (type == TCG_TYPE_I32) { 1949 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1950 } else { 1951 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1952 } 1953 } else { 1954 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1955 tcg_out_opc_reg(s, insn, 0, a1, a2); 1956 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1957 } 1958} 1959 1960static const TCGOutOpBinary outop_remu = { 1961 .base.static_constraint = C_O1_I2(r, r, r), 1962 .out_rrr = tgen_remu, 1963}; 1964 1965static const TCGOutOpBinary outop_rotl = { 1966 .base.static_constraint = C_NotImplemented, 1967}; 1968 1969static TCGConstraintSetIndex cset_rotr(TCGType type, unsigned flags) 1970{ 1971 return use_mips32r2_instructions ? C_O1_I2(r, r, ri) : C_NotImplemented; 1972} 1973 1974static void tgen_rotr(TCGContext *s, TCGType type, 1975 TCGReg a0, TCGReg a1, TCGReg a2) 1976{ 1977 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; 1978 tcg_out_opc_reg(s, insn, a0, a1, a2); 1979} 1980 1981static void tgen_rotri(TCGContext *s, TCGType type, 1982 TCGReg a0, TCGReg a1, tcg_target_long a2) 1983{ 1984 if (type == TCG_TYPE_I32) { 1985 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); 1986 } else { 1987 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 1988 } 1989} 1990 1991static const TCGOutOpBinary outop_rotr = { 1992 .base.static_constraint = C_Dynamic, 1993 .base.dynamic_constraint = cset_rotr, 1994 .out_rrr = tgen_rotr, 1995 .out_rri = tgen_rotri, 1996}; 1997 1998static void tgen_sar(TCGContext *s, TCGType type, 1999 TCGReg a0, TCGReg a1, TCGReg a2) 2000{ 2001 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; 2002 tcg_out_opc_reg(s, insn, a0, a1, a2); 2003} 2004 2005static void tgen_sari(TCGContext *s, TCGType type, 2006 TCGReg a0, TCGReg a1, tcg_target_long a2) 2007{ 2008 if (type == TCG_TYPE_I32) { 2009 tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); 2010 } else { 2011 tcg_out_dsra(s, a0, a1, a2); 2012 } 2013} 2014 2015static const TCGOutOpBinary outop_sar = { 2016 .base.static_constraint = C_O1_I2(r, r, ri), 2017 .out_rrr = tgen_sar, 2018 .out_rri = tgen_sari, 2019}; 2020 2021static void tgen_shl(TCGContext *s, TCGType type, 2022 TCGReg a0, TCGReg a1, TCGReg a2) 2023{ 2024 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; 2025 tcg_out_opc_reg(s, insn, a0, a1, a2); 2026} 2027 2028static void tgen_shli(TCGContext *s, TCGType type, 2029 TCGReg a0, TCGReg a1, tcg_target_long a2) 2030{ 2031 if (type == TCG_TYPE_I32) { 2032 tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); 2033 } else { 2034 tcg_out_dsll(s, a0, a1, a2); 2035 } 2036} 2037 2038static const TCGOutOpBinary outop_shl = { 2039 .base.static_constraint = C_O1_I2(r, r, ri), 2040 .out_rrr = tgen_shl, 2041 .out_rri = tgen_shli, 2042}; 2043 2044static void tgen_shr(TCGContext *s, TCGType type, 2045 TCGReg a0, TCGReg a1, TCGReg a2) 2046{ 2047 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; 2048 tcg_out_opc_reg(s, insn, a0, a1, a2); 2049} 2050 2051static void tgen_shri(TCGContext *s, TCGType type, 2052 TCGReg a0, TCGReg a1, tcg_target_long a2) 2053{ 2054 if (type == TCG_TYPE_I32) { 2055 tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); 2056 } else { 2057 tcg_out_dsrl(s, a0, a1, a2); 2058 } 2059} 2060 2061static const TCGOutOpBinary outop_shr = { 2062 .base.static_constraint = C_O1_I2(r, r, ri), 2063 .out_rrr = tgen_shr, 2064 .out_rri = tgen_shri, 2065}; 2066 2067static void tgen_sub(TCGContext *s, TCGType type, 2068 TCGReg a0, TCGReg a1, TCGReg a2) 2069{ 2070 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU; 2071 tcg_out_opc_reg(s, insn, a0, a1, a2); 2072} 2073 2074static const TCGOutOpSubtract outop_sub = { 2075 .base.static_constraint = C_O1_I2(r, r, r), 2076 .out_rrr = tgen_sub, 2077}; 2078 2079static const TCGOutOpAddSubCarry outop_subbo = { 2080 .base.static_constraint = C_NotImplemented, 2081}; 2082 2083static const TCGOutOpAddSubCarry outop_subbi = { 2084 .base.static_constraint = C_NotImplemented, 2085}; 2086 2087static const TCGOutOpAddSubCarry outop_subbio = { 2088 .base.static_constraint = C_NotImplemented, 2089}; 2090 2091static void tcg_out_set_borrow(TCGContext *s) 2092{ 2093 g_assert_not_reached(); 2094} 2095 2096static void tgen_xor(TCGContext *s, TCGType type, 2097 TCGReg a0, TCGReg a1, TCGReg a2) 2098{ 2099 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2100} 2101 2102static void tgen_xori(TCGContext *s, TCGType type, 2103 TCGReg a0, TCGReg a1, tcg_target_long a2) 2104{ 2105 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2106} 2107 2108static const TCGOutOpBinary outop_xor = { 2109 .base.static_constraint = C_O1_I2(r, r, rI), 2110 .out_rrr = tgen_xor, 2111 .out_rri = tgen_xori, 2112}; 2113 2114static void tgen_bswap16(TCGContext *s, TCGType type, 2115 TCGReg ret, TCGReg arg, unsigned flags) 2116{ 2117 /* With arg = abcd: */ 2118 if (use_mips32r2_instructions) { 2119 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 2120 if (flags & TCG_BSWAP_OS) { 2121 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 2122 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2123 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 2124 } 2125 return; 2126 } 2127 2128 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 2129 if (!(flags & TCG_BSWAP_IZ)) { 2130 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 2131 } 2132 if (flags & TCG_BSWAP_OS) { 2133 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 2134 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 2135 } else { 2136 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 2137 if (flags & TCG_BSWAP_OZ) { 2138 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 2139 } 2140 } 2141 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 2142} 2143 2144static const TCGOutOpBswap outop_bswap16 = { 2145 .base.static_constraint = C_O1_I1(r, r), 2146 .out_rr = tgen_bswap16, 2147}; 2148 2149static void tgen_bswap32(TCGContext *s, TCGType type, 2150 TCGReg ret, TCGReg arg, unsigned flags) 2151{ 2152 if (use_mips32r2_instructions) { 2153 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 2154 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 2155 if (flags & TCG_BSWAP_OZ) { 2156 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 2157 } 2158 } else { 2159 if (flags & TCG_BSWAP_OZ) { 2160 tcg_out_bswap_subr(s, bswap32u_addr); 2161 } else { 2162 tcg_out_bswap_subr(s, bswap32_addr); 2163 } 2164 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2165 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2166 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2167 } 2168} 2169 2170static const TCGOutOpBswap outop_bswap32 = { 2171 .base.static_constraint = C_O1_I1(r, r), 2172 .out_rr = tgen_bswap32, 2173}; 2174 2175#if TCG_TARGET_REG_BITS == 64 2176static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 2177{ 2178 if (use_mips32r2_instructions) { 2179 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 2180 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 2181 } else { 2182 tcg_out_bswap_subr(s, bswap64_addr); 2183 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 2184 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 2185 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 2186 } 2187} 2188 2189static const TCGOutOpUnary outop_bswap64 = { 2190 .base.static_constraint = C_O1_I1(r, r), 2191 .out_rr = tgen_bswap64, 2192}; 2193#endif /* TCG_TARGET_REG_BITS == 64 */ 2194 2195static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2196{ 2197 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2198} 2199 2200static const TCGOutOpUnary outop_neg = { 2201 .base.static_constraint = C_O1_I1(r, r), 2202 .out_rr = tgen_neg, 2203}; 2204 2205static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2206{ 2207 tgen_nor(s, type, a0, TCG_REG_ZERO, a1); 2208} 2209 2210static const TCGOutOpUnary outop_not = { 2211 .base.static_constraint = C_O1_I1(r, r), 2212 .out_rr = tgen_not, 2213}; 2214 2215static void tgen_deposit(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2216 TCGReg a2, unsigned ofs, unsigned len) 2217{ 2218 if (type == TCG_TYPE_I32) { 2219 tcg_out_opc_bf(s, OPC_INS, a0, a2, ofs + len - 1, ofs); 2220 } else { 2221 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2222 ofs + len - 1, ofs); 2223 } 2224} 2225 2226static const TCGOutOpDeposit outop_deposit = { 2227 .base.static_constraint = C_O1_I2(r, 0, rz), 2228 .out_rrr = tgen_deposit, 2229}; 2230 2231static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2232 unsigned ofs, unsigned len) 2233{ 2234 if (ofs == 0 && len <= 16) { 2235 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << len) - 1); 2236 } else if (type == TCG_TYPE_I32) { 2237 tcg_out_opc_bf(s, OPC_EXT, a0, a1, len - 1, ofs); 2238 } else { 2239 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2240 a0, a1, len - 1, ofs); 2241 } 2242} 2243 2244static const TCGOutOpExtract outop_extract = { 2245 .base.static_constraint = C_O1_I1(r, r), 2246 .out_rr = tgen_extract, 2247}; 2248 2249static void tgen_sextract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 2250 unsigned ofs, unsigned len) 2251{ 2252 if (ofs == 0) { 2253 switch (len) { 2254 case 8: 2255 tcg_out_ext8s(s, type, a0, a1); 2256 return; 2257 case 16: 2258 tcg_out_ext16s(s, type, a0, a1); 2259 return; 2260 case 32: 2261 tcg_out_ext32s(s, a0, a1); 2262 return; 2263 } 2264 } 2265 g_assert_not_reached(); 2266} 2267 2268static const TCGOutOpExtract outop_sextract = { 2269 .base.static_constraint = C_O1_I1(r, r), 2270 .out_rr = tgen_sextract, 2271}; 2272 2273static const TCGOutOpExtract2 outop_extract2 = { 2274 .base.static_constraint = C_NotImplemented, 2275}; 2276 2277static void tgen_ld8u(TCGContext *s, TCGType type, TCGReg dest, 2278 TCGReg base, ptrdiff_t offset) 2279{ 2280 tcg_out_ldst(s, OPC_LBU, dest, base, offset); 2281} 2282 2283static const TCGOutOpLoad outop_ld8u = { 2284 .base.static_constraint = C_O1_I1(r, r), 2285 .out = tgen_ld8u, 2286}; 2287 2288static void tgen_ld8s(TCGContext *s, TCGType type, TCGReg dest, 2289 TCGReg base, ptrdiff_t offset) 2290{ 2291 tcg_out_ldst(s, OPC_LB, dest, base, offset); 2292} 2293 2294static const TCGOutOpLoad outop_ld8s = { 2295 .base.static_constraint = C_O1_I1(r, r), 2296 .out = tgen_ld8s, 2297}; 2298 2299static void tgen_ld16u(TCGContext *s, TCGType type, TCGReg dest, 2300 TCGReg base, ptrdiff_t offset) 2301{ 2302 tcg_out_ldst(s, OPC_LHU, dest, base, offset); 2303} 2304 2305static const TCGOutOpLoad outop_ld16u = { 2306 .base.static_constraint = C_O1_I1(r, r), 2307 .out = tgen_ld16u, 2308}; 2309 2310static void tgen_ld16s(TCGContext *s, TCGType type, TCGReg dest, 2311 TCGReg base, ptrdiff_t offset) 2312{ 2313 tcg_out_ldst(s, OPC_LH, dest, base, offset); 2314} 2315 2316static const TCGOutOpLoad outop_ld16s = { 2317 .base.static_constraint = C_O1_I1(r, r), 2318 .out = tgen_ld16s, 2319}; 2320 2321#if TCG_TARGET_REG_BITS == 64 2322static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, 2323 TCGReg base, ptrdiff_t offset) 2324{ 2325 tcg_out_ldst(s, OPC_LWU, dest, base, offset); 2326} 2327 2328static const TCGOutOpLoad outop_ld32u = { 2329 .base.static_constraint = C_O1_I1(r, r), 2330 .out = tgen_ld32u, 2331}; 2332 2333static void tgen_ld32s(TCGContext *s, TCGType type, TCGReg dest, 2334 TCGReg base, ptrdiff_t offset) 2335{ 2336 tcg_out_ldst(s, OPC_LW, dest, base, offset); 2337} 2338 2339static const TCGOutOpLoad outop_ld32s = { 2340 .base.static_constraint = C_O1_I1(r, r), 2341 .out = tgen_ld32s, 2342}; 2343#endif 2344 2345static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data, 2346 TCGReg base, ptrdiff_t offset) 2347{ 2348 tcg_out_ldst(s, OPC_SB, data, base, offset); 2349} 2350 2351static const TCGOutOpStore outop_st8 = { 2352 .base.static_constraint = C_O0_I2(rz, r), 2353 .out_r = tgen_st8_r, 2354}; 2355 2356static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data, 2357 TCGReg base, ptrdiff_t offset) 2358{ 2359 tcg_out_ldst(s, OPC_SH, data, base, offset); 2360} 2361 2362static const TCGOutOpStore outop_st16 = { 2363 .base.static_constraint = C_O0_I2(rz, r), 2364 .out_r = tgen_st16_r, 2365}; 2366 2367static const TCGOutOpStore outop_st = { 2368 .base.static_constraint = C_O0_I2(rz, r), 2369 .out_r = tcg_out_st, 2370}; 2371 2372 2373static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2374 const TCGArg args[TCG_MAX_OP_ARGS], 2375 const int const_args[TCG_MAX_OP_ARGS]) 2376{ 2377 TCGArg a0, a1, a2; 2378 2379 a0 = args[0]; 2380 a1 = args[1]; 2381 a2 = args[2]; 2382 2383 switch (opc) { 2384 case INDEX_op_qemu_ld_i32: 2385 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2386 break; 2387 case INDEX_op_qemu_ld_i64: 2388 if (TCG_TARGET_REG_BITS == 64) { 2389 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2390 } else { 2391 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2392 } 2393 break; 2394 2395 case INDEX_op_qemu_st_i32: 2396 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2397 break; 2398 case INDEX_op_qemu_st_i64: 2399 if (TCG_TARGET_REG_BITS == 64) { 2400 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2401 } else { 2402 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2403 } 2404 break; 2405 2406 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2407 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2408 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2409 default: 2410 g_assert_not_reached(); 2411 } 2412} 2413 2414static TCGConstraintSetIndex 2415tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2416{ 2417 switch (op) { 2418 case INDEX_op_qemu_ld_i32: 2419 return C_O1_I1(r, r); 2420 case INDEX_op_qemu_st_i32: 2421 return C_O0_I2(rz, r); 2422 case INDEX_op_qemu_ld_i64: 2423 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2424 case INDEX_op_qemu_st_i64: 2425 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2426 2427 default: 2428 return C_NotImplemented; 2429 } 2430} 2431 2432static const int tcg_target_callee_save_regs[] = { 2433 TCG_REG_S0, 2434 TCG_REG_S1, 2435 TCG_REG_S2, 2436 TCG_REG_S3, 2437 TCG_REG_S4, 2438 TCG_REG_S5, 2439 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2440 TCG_REG_S7, /* used for guest_base */ 2441 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2442 TCG_REG_RA, /* should be last for ABI compliance */ 2443}; 2444 2445/* The Linux kernel doesn't provide any information about the available 2446 instruction set. Probe it using a signal handler. */ 2447 2448 2449#ifndef use_movnz_instructions 2450bool use_movnz_instructions = false; 2451#endif 2452 2453#ifndef use_mips32_instructions 2454bool use_mips32_instructions = false; 2455#endif 2456 2457#ifndef use_mips32r2_instructions 2458bool use_mips32r2_instructions = false; 2459#endif 2460 2461static volatile sig_atomic_t got_sigill; 2462 2463static void sigill_handler(int signo, siginfo_t *si, void *data) 2464{ 2465 /* Skip the faulty instruction */ 2466 ucontext_t *uc = (ucontext_t *)data; 2467 uc->uc_mcontext.pc += 4; 2468 2469 got_sigill = 1; 2470} 2471 2472static void tcg_target_detect_isa(void) 2473{ 2474 struct sigaction sa_old, sa_new; 2475 2476 memset(&sa_new, 0, sizeof(sa_new)); 2477 sa_new.sa_flags = SA_SIGINFO; 2478 sa_new.sa_sigaction = sigill_handler; 2479 sigaction(SIGILL, &sa_new, &sa_old); 2480 2481 /* Probe for movn/movz, necessary to implement movcond. */ 2482#ifndef use_movnz_instructions 2483 got_sigill = 0; 2484 asm volatile(".set push\n" 2485 ".set mips32\n" 2486 "movn $zero, $zero, $zero\n" 2487 "movz $zero, $zero, $zero\n" 2488 ".set pop\n" 2489 : : : ); 2490 use_movnz_instructions = !got_sigill; 2491#endif 2492 2493 /* Probe for MIPS32 instructions. As no subsetting is allowed 2494 by the specification, it is only necessary to probe for one 2495 of the instructions. */ 2496#ifndef use_mips32_instructions 2497 got_sigill = 0; 2498 asm volatile(".set push\n" 2499 ".set mips32\n" 2500 "mul $zero, $zero\n" 2501 ".set pop\n" 2502 : : : ); 2503 use_mips32_instructions = !got_sigill; 2504#endif 2505 2506 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2507 available. As no subsetting is allowed by the specification, 2508 it is only necessary to probe for one of the instructions. */ 2509#ifndef use_mips32r2_instructions 2510 if (use_mips32_instructions) { 2511 got_sigill = 0; 2512 asm volatile(".set push\n" 2513 ".set mips32r2\n" 2514 "seb $zero, $zero\n" 2515 ".set pop\n" 2516 : : : ); 2517 use_mips32r2_instructions = !got_sigill; 2518 } 2519#endif 2520 2521 sigaction(SIGILL, &sa_old, NULL); 2522} 2523 2524static tcg_insn_unit *align_code_ptr(TCGContext *s) 2525{ 2526 uintptr_t p = (uintptr_t)s->code_ptr; 2527 if (p & 15) { 2528 p = (p + 15) & -16; 2529 s->code_ptr = (void *)p; 2530 } 2531 return s->code_ptr; 2532} 2533 2534/* Stack frame parameters. */ 2535#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2536#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2537#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2538 2539#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2540 + TCG_TARGET_STACK_ALIGN - 1) \ 2541 & -TCG_TARGET_STACK_ALIGN) 2542#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2543 2544/* We're expecting to be able to use an immediate for frame allocation. */ 2545QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2546 2547/* Generate global QEMU prologue and epilogue code */ 2548static void tcg_target_qemu_prologue(TCGContext *s) 2549{ 2550 int i; 2551 2552 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2553 2554 /* TB prologue */ 2555 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2556 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2557 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2558 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2559 } 2560 2561 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2562 /* 2563 * The function call abi for n32 and n64 will have loaded $25 (t9) 2564 * with the address of the prologue, so we can use that instead 2565 * of TCG_REG_TB. 2566 */ 2567#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2568# error "Unknown mips abi" 2569#endif 2570 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2571 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2572 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2573 } 2574 2575 if (TCG_TARGET_REG_BITS == 64) { 2576 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2577 } 2578 2579 /* Call generated code */ 2580 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2581 /* delay slot */ 2582 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2583 2584 /* 2585 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2586 * and fall through to the rest of the epilogue. 2587 */ 2588 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2589 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2590 2591 /* TB epilogue */ 2592 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2593 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2594 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2595 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2596 } 2597 2598 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2599 /* delay slot */ 2600 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2601 2602 if (use_mips32r2_instructions) { 2603 return; 2604 } 2605 2606 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2607 clobbers TCG_TMP1, TCG_TMP2. */ 2608 2609 /* 2610 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2611 */ 2612 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2613 /* t3 = (ssss)d000 */ 2614 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2615 /* t1 = 000a */ 2616 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2617 /* t2 = 00c0 */ 2618 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2619 /* t3 = d00a */ 2620 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2621 /* t1 = 0abc */ 2622 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2623 /* t2 = 0c00 */ 2624 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2625 /* t1 = 00b0 */ 2626 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2627 /* t3 = dc0a */ 2628 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2629 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2630 /* t3 = dcba -- delay slot */ 2631 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2632 2633 if (TCG_TARGET_REG_BITS == 32) { 2634 return; 2635 } 2636 2637 /* 2638 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2639 */ 2640 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2641 /* t1 = (0000)000d */ 2642 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2643 /* t3 = 000a */ 2644 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2645 /* t1 = (0000)d000 */ 2646 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2647 /* t2 = 00c0 */ 2648 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2649 /* t3 = d00a */ 2650 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2651 /* t1 = 0abc */ 2652 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2653 /* t2 = 0c00 */ 2654 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2655 /* t1 = 00b0 */ 2656 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2657 /* t3 = dc0a */ 2658 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2659 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2660 /* t3 = dcba -- delay slot */ 2661 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2662 2663 /* 2664 * bswap64 -- 64-bit swap. a0 = abcdefgh 2665 */ 2666 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2667 /* t3 = h0000000 */ 2668 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2669 /* t1 = 0000000a */ 2670 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2671 2672 /* t2 = 000000g0 */ 2673 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2674 /* t3 = h000000a */ 2675 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2676 /* t1 = 00000abc */ 2677 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2678 /* t2 = 0g000000 */ 2679 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2680 /* t1 = 000000b0 */ 2681 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2682 2683 /* t3 = hg00000a */ 2684 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2685 /* t2 = 0000abcd */ 2686 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2687 /* t3 = hg0000ba */ 2688 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2689 2690 /* t1 = 000000c0 */ 2691 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2692 /* t2 = 0000000d */ 2693 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2694 /* t1 = 00000c00 */ 2695 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2696 /* t2 = 0000d000 */ 2697 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2698 2699 /* t3 = hg000cba */ 2700 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2701 /* t1 = 00abcdef */ 2702 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2703 /* t3 = hg00dcba */ 2704 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2705 2706 /* t2 = 0000000f */ 2707 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2708 /* t1 = 000000e0 */ 2709 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2710 /* t2 = 00f00000 */ 2711 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2712 /* t1 = 000e0000 */ 2713 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2714 2715 /* t3 = hgf0dcba */ 2716 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2717 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2718 /* t3 = hgfedcba -- delay slot */ 2719 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2720} 2721 2722static void tcg_out_tb_start(TCGContext *s) 2723{ 2724 /* nothing to do */ 2725} 2726 2727static void tcg_target_init(TCGContext *s) 2728{ 2729 tcg_target_detect_isa(); 2730 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2731 if (TCG_TARGET_REG_BITS == 64) { 2732 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2733 } 2734 2735 tcg_target_call_clobber_regs = 0; 2736 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2737 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2738 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2741 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2742 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2743 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2744 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2745 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2746 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2747 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2748 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2749 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2750 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2751 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2752 2753 s->reserved_regs = 0; 2754 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2755 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2756 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2757 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2758 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2759 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2760 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2761 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2762 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2763 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2764 if (TCG_TARGET_REG_BITS == 64) { 2765 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2766 } 2767} 2768 2769typedef struct { 2770 DebugFrameHeader h; 2771 uint8_t fde_def_cfa[4]; 2772 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2773} DebugFrame; 2774 2775#define ELF_HOST_MACHINE EM_MIPS 2776/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2777 which is good because they're really quite complicated for MIPS. */ 2778 2779static const DebugFrame debug_frame = { 2780 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2781 .h.cie.id = -1, 2782 .h.cie.version = 1, 2783 .h.cie.code_align = 1, 2784 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2785 .h.cie.return_column = TCG_REG_RA, 2786 2787 /* Total FDE size does not include the "len" member. */ 2788 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2789 2790 .fde_def_cfa = { 2791 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2792 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2793 (FRAME_SIZE >> 7) 2794 }, 2795 .fde_reg_ofs = { 2796 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2797 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2798 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2799 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2800 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2801 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2802 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2803 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2804 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2805 } 2806}; 2807 2808void tcg_register_jit(const void *buf, size_t buf_size) 2809{ 2810 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2811} 2812