1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28#include "../tcg-pool.c.inc" 29 30#if TCG_TARGET_REG_BITS == 32 31# define LO_OFF (HOST_BIG_ENDIAN * 4) 32# define HI_OFF (4 - LO_OFF) 33#else 34/* Assert at compile-time that these values are never used for 64-bit. */ 35# define LO_OFF ({ qemu_build_not_reached(); 0; }) 36# define HI_OFF ({ qemu_build_not_reached(); 0; }) 37#endif 38 39#ifdef CONFIG_DEBUG_TCG 40static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 41 "zero", 42 "at", 43 "v0", 44 "v1", 45 "a0", 46 "a1", 47 "a2", 48 "a3", 49 "t0", 50 "t1", 51 "t2", 52 "t3", 53 "t4", 54 "t5", 55 "t6", 56 "t7", 57 "s0", 58 "s1", 59 "s2", 60 "s3", 61 "s4", 62 "s5", 63 "s6", 64 "s7", 65 "t8", 66 "t9", 67 "k0", 68 "k1", 69 "gp", 70 "sp", 71 "s8", 72 "ra", 73}; 74#endif 75 76#define TCG_TMP0 TCG_REG_AT 77#define TCG_TMP1 TCG_REG_T9 78#define TCG_TMP2 TCG_REG_T8 79#define TCG_TMP3 TCG_REG_T7 80 81#define TCG_GUEST_BASE_REG TCG_REG_S7 82#if TCG_TARGET_REG_BITS == 64 83#define TCG_REG_TB TCG_REG_S6 84#else 85#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 86#endif 87 88/* check if we really need so many registers :P */ 89static const int tcg_target_reg_alloc_order[] = { 90 /* Call saved registers. */ 91 TCG_REG_S0, 92 TCG_REG_S1, 93 TCG_REG_S2, 94 TCG_REG_S3, 95 TCG_REG_S4, 96 TCG_REG_S5, 97 TCG_REG_S6, 98 TCG_REG_S7, 99 TCG_REG_S8, 100 101 /* Call clobbered registers. */ 102 TCG_REG_T4, 103 TCG_REG_T5, 104 TCG_REG_T6, 105 TCG_REG_T7, 106 TCG_REG_T8, 107 TCG_REG_T9, 108 TCG_REG_V1, 109 TCG_REG_V0, 110 111 /* Argument registers, opposite order of allocation. */ 112 TCG_REG_T3, 113 TCG_REG_T2, 114 TCG_REG_T1, 115 TCG_REG_T0, 116 TCG_REG_A3, 117 TCG_REG_A2, 118 TCG_REG_A1, 119 TCG_REG_A0, 120}; 121 122static const TCGReg tcg_target_call_iarg_regs[] = { 123 TCG_REG_A0, 124 TCG_REG_A1, 125 TCG_REG_A2, 126 TCG_REG_A3, 127#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 128 TCG_REG_T0, 129 TCG_REG_T1, 130 TCG_REG_T2, 131 TCG_REG_T3, 132#endif 133}; 134 135static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 136{ 137 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 138 tcg_debug_assert(slot >= 0 && slot <= 1); 139 return TCG_REG_V0 + slot; 140} 141 142static const tcg_insn_unit *tb_ret_addr; 143static const tcg_insn_unit *bswap32_addr; 144static const tcg_insn_unit *bswap32u_addr; 145static const tcg_insn_unit *bswap64_addr; 146 147static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 148{ 149 /* Let the compiler perform the right-shift as part of the arithmetic. */ 150 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 151 ptrdiff_t disp = target - (src_rx + 1); 152 if (disp == (int16_t)disp) { 153 *src_rw = deposit32(*src_rw, 0, 16, disp); 154 return true; 155 } 156 return false; 157} 158 159static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 160 intptr_t value, intptr_t addend) 161{ 162 value += addend; 163 switch (type) { 164 case R_MIPS_PC16: 165 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 166 case R_MIPS_16: 167 if (value != (int16_t)value) { 168 return false; 169 } 170 *code_ptr = deposit32(*code_ptr, 0, 16, value); 171 return true; 172 } 173 g_assert_not_reached(); 174} 175 176#define TCG_CT_CONST_ZERO 0x100 177#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 178#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 179#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 180#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 181#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 182 183#define ALL_GENERAL_REGS 0xffffffffu 184 185static bool is_p2m1(tcg_target_long val) 186{ 187 return val && ((val + 1) & val) == 0; 188} 189 190/* test if a constant matches the constraint */ 191static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece) 192{ 193 if (ct & TCG_CT_CONST) { 194 return 1; 195 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 196 return 1; 197 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 198 return 1; 199 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 200 return 1; 201 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 202 return 1; 203 } else if ((ct & TCG_CT_CONST_P2M1) 204 && use_mips32r2_instructions && is_p2m1(val)) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_WSZ) 207 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return 1; 209 } 210 return 0; 211} 212 213/* instruction opcodes */ 214typedef enum { 215 OPC_J = 002 << 26, 216 OPC_JAL = 003 << 26, 217 OPC_BEQ = 004 << 26, 218 OPC_BNE = 005 << 26, 219 OPC_BLEZ = 006 << 26, 220 OPC_BGTZ = 007 << 26, 221 OPC_ADDIU = 011 << 26, 222 OPC_SLTI = 012 << 26, 223 OPC_SLTIU = 013 << 26, 224 OPC_ANDI = 014 << 26, 225 OPC_ORI = 015 << 26, 226 OPC_XORI = 016 << 26, 227 OPC_LUI = 017 << 26, 228 OPC_BNEL = 025 << 26, 229 OPC_BNEZALC_R6 = 030 << 26, 230 OPC_DADDIU = 031 << 26, 231 OPC_LDL = 032 << 26, 232 OPC_LDR = 033 << 26, 233 OPC_LB = 040 << 26, 234 OPC_LH = 041 << 26, 235 OPC_LWL = 042 << 26, 236 OPC_LW = 043 << 26, 237 OPC_LBU = 044 << 26, 238 OPC_LHU = 045 << 26, 239 OPC_LWR = 046 << 26, 240 OPC_LWU = 047 << 26, 241 OPC_SB = 050 << 26, 242 OPC_SH = 051 << 26, 243 OPC_SWL = 052 << 26, 244 OPC_SW = 053 << 26, 245 OPC_SDL = 054 << 26, 246 OPC_SDR = 055 << 26, 247 OPC_SWR = 056 << 26, 248 OPC_LD = 067 << 26, 249 OPC_SD = 077 << 26, 250 251 OPC_SPECIAL = 000 << 26, 252 OPC_SLL = OPC_SPECIAL | 000, 253 OPC_SRL = OPC_SPECIAL | 002, 254 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 255 OPC_SRA = OPC_SPECIAL | 003, 256 OPC_SLLV = OPC_SPECIAL | 004, 257 OPC_SRLV = OPC_SPECIAL | 006, 258 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 259 OPC_SRAV = OPC_SPECIAL | 007, 260 OPC_JR_R5 = OPC_SPECIAL | 010, 261 OPC_JALR = OPC_SPECIAL | 011, 262 OPC_MOVZ = OPC_SPECIAL | 012, 263 OPC_MOVN = OPC_SPECIAL | 013, 264 OPC_SYNC = OPC_SPECIAL | 017, 265 OPC_MFHI = OPC_SPECIAL | 020, 266 OPC_MFLO = OPC_SPECIAL | 022, 267 OPC_DSLLV = OPC_SPECIAL | 024, 268 OPC_DSRLV = OPC_SPECIAL | 026, 269 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 270 OPC_DSRAV = OPC_SPECIAL | 027, 271 OPC_MULT = OPC_SPECIAL | 030, 272 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 273 OPC_MUH = OPC_SPECIAL | 030 | 0300, 274 OPC_MULTU = OPC_SPECIAL | 031, 275 OPC_MULU = OPC_SPECIAL | 031 | 0200, 276 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 277 OPC_DIV = OPC_SPECIAL | 032, 278 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 279 OPC_MOD = OPC_SPECIAL | 032 | 0300, 280 OPC_DIVU = OPC_SPECIAL | 033, 281 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 282 OPC_MODU = OPC_SPECIAL | 033 | 0300, 283 OPC_DMULT = OPC_SPECIAL | 034, 284 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 285 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 286 OPC_DMULTU = OPC_SPECIAL | 035, 287 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 288 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 289 OPC_DDIV = OPC_SPECIAL | 036, 290 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 291 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 292 OPC_DDIVU = OPC_SPECIAL | 037, 293 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 294 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 295 OPC_ADDU = OPC_SPECIAL | 041, 296 OPC_SUBU = OPC_SPECIAL | 043, 297 OPC_AND = OPC_SPECIAL | 044, 298 OPC_OR = OPC_SPECIAL | 045, 299 OPC_XOR = OPC_SPECIAL | 046, 300 OPC_NOR = OPC_SPECIAL | 047, 301 OPC_SLT = OPC_SPECIAL | 052, 302 OPC_SLTU = OPC_SPECIAL | 053, 303 OPC_DADDU = OPC_SPECIAL | 055, 304 OPC_DSUBU = OPC_SPECIAL | 057, 305 OPC_SELEQZ = OPC_SPECIAL | 065, 306 OPC_SELNEZ = OPC_SPECIAL | 067, 307 OPC_DSLL = OPC_SPECIAL | 070, 308 OPC_DSRL = OPC_SPECIAL | 072, 309 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 310 OPC_DSRA = OPC_SPECIAL | 073, 311 OPC_DSLL32 = OPC_SPECIAL | 074, 312 OPC_DSRL32 = OPC_SPECIAL | 076, 313 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 314 OPC_DSRA32 = OPC_SPECIAL | 077, 315 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 316 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 317 318 OPC_REGIMM = 001 << 26, 319 OPC_BLTZ = OPC_REGIMM | (000 << 16), 320 OPC_BGEZ = OPC_REGIMM | (001 << 16), 321 322 OPC_SPECIAL2 = 034 << 26, 323 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 324 OPC_CLZ = OPC_SPECIAL2 | 040, 325 OPC_DCLZ = OPC_SPECIAL2 | 044, 326 327 OPC_SPECIAL3 = 037 << 26, 328 OPC_EXT = OPC_SPECIAL3 | 000, 329 OPC_DEXTM = OPC_SPECIAL3 | 001, 330 OPC_DEXTU = OPC_SPECIAL3 | 002, 331 OPC_DEXT = OPC_SPECIAL3 | 003, 332 OPC_INS = OPC_SPECIAL3 | 004, 333 OPC_DINSM = OPC_SPECIAL3 | 005, 334 OPC_DINSU = OPC_SPECIAL3 | 006, 335 OPC_DINS = OPC_SPECIAL3 | 007, 336 OPC_WSBH = OPC_SPECIAL3 | 00240, 337 OPC_DSBH = OPC_SPECIAL3 | 00244, 338 OPC_DSHD = OPC_SPECIAL3 | 00544, 339 OPC_SEB = OPC_SPECIAL3 | 02040, 340 OPC_SEH = OPC_SPECIAL3 | 03040, 341 342 /* MIPS r6 doesn't have JR, JALR should be used instead */ 343 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 344 345 /* 346 * MIPS r6 replaces MUL with an alternative encoding which is 347 * backwards-compatible at the assembly level. 348 */ 349 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 350 351 /* MIPS r6 introduced names for weaker variants of SYNC. These are 352 backward compatible to previous architecture revisions. */ 353 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 354 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 355 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 356 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 357 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 358 359 /* Aliases for convenience. */ 360 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 361 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 362} MIPSInsn; 363 364/* 365 * Type reg 366 */ 367static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 368 TCGReg rd, TCGReg rs, TCGReg rt) 369{ 370 int32_t inst; 371 372 inst = opc; 373 inst |= (rs & 0x1F) << 21; 374 inst |= (rt & 0x1F) << 16; 375 inst |= (rd & 0x1F) << 11; 376 tcg_out32(s, inst); 377} 378 379/* 380 * Type immediate 381 */ 382static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 383 TCGReg rt, TCGReg rs, TCGArg imm) 384{ 385 int32_t inst; 386 387 inst = opc; 388 inst |= (rs & 0x1F) << 21; 389 inst |= (rt & 0x1F) << 16; 390 inst |= (imm & 0xffff); 391 tcg_out32(s, inst); 392} 393 394/* 395 * Type bitfield 396 */ 397static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 398 TCGReg rs, int msb, int lsb) 399{ 400 int32_t inst; 401 402 inst = opc; 403 inst |= (rs & 0x1F) << 21; 404 inst |= (rt & 0x1F) << 16; 405 inst |= (msb & 0x1F) << 11; 406 inst |= (lsb & 0x1F) << 6; 407 tcg_out32(s, inst); 408} 409 410static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 411 MIPSInsn oph, TCGReg rt, TCGReg rs, 412 int msb, int lsb) 413{ 414 if (lsb >= 32) { 415 opc = oph; 416 msb -= 32; 417 lsb -= 32; 418 } else if (msb >= 32) { 419 opc = opm; 420 msb -= 32; 421 } 422 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 423} 424 425/* 426 * Type branch 427 */ 428static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 429{ 430 tcg_out_opc_imm(s, opc, rt, rs, 0); 431} 432 433/* 434 * Type sa 435 */ 436static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 437 TCGReg rd, TCGReg rt, TCGArg sa) 438{ 439 int32_t inst; 440 441 inst = opc; 442 inst |= (rt & 0x1F) << 16; 443 inst |= (rd & 0x1F) << 11; 444 inst |= (sa & 0x1F) << 6; 445 tcg_out32(s, inst); 446 447} 448 449static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 450 TCGReg rd, TCGReg rt, TCGArg sa) 451{ 452 int32_t inst; 453 454 inst = (sa & 32 ? opc2 : opc1); 455 inst |= (rt & 0x1F) << 16; 456 inst |= (rd & 0x1F) << 11; 457 inst |= (sa & 0x1F) << 6; 458 tcg_out32(s, inst); 459} 460 461/* 462 * Type jump. 463 * Returns true if the branch was in range and the insn was emitted. 464 */ 465static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 466{ 467 uintptr_t dest = (uintptr_t)target; 468 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 469 int32_t inst; 470 471 /* The pc-region branch happens within the 256MB region of 472 the delay slot (thus the +4). */ 473 if ((from ^ dest) & -(1 << 28)) { 474 return false; 475 } 476 tcg_debug_assert((dest & 3) == 0); 477 478 inst = opc; 479 inst |= (dest >> 2) & 0x3ffffff; 480 tcg_out32(s, inst); 481 return true; 482} 483 484static void tcg_out_nop(TCGContext *s) 485{ 486 tcg_out32(s, 0); 487} 488 489static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 490{ 491 memset(p, 0, count * sizeof(tcg_insn_unit)); 492} 493 494static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 495{ 496 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 497} 498 499static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 500{ 501 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 502} 503 504static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 505{ 506 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 507} 508 509static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 510{ 511 /* Simple reg-reg move, optimising out the 'do nothing' case */ 512 if (ret != arg) { 513 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 514 } 515 return true; 516} 517 518static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 519{ 520 if (arg == (int16_t)arg) { 521 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 522 return true; 523 } 524 if (arg == (uint16_t)arg) { 525 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 526 return true; 527 } 528 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 529 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 530 return true; 531 } 532 return false; 533} 534 535static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 536{ 537 /* 538 * All signed 32-bit constants are loadable with two immediates, 539 * and everything else requires more work. 540 */ 541 if (arg == (int32_t)arg) { 542 if (!tcg_out_movi_one(s, ret, arg)) { 543 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 544 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 545 } 546 return true; 547 } 548 return false; 549} 550 551static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 552 tcg_target_long arg, TCGReg tbreg) 553{ 554 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 555 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 556} 557 558static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 559 tcg_target_long arg, TCGReg tbreg) 560{ 561 tcg_target_long tmp; 562 int sh, lo; 563 564 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 565 arg = (int32_t)arg; 566 } 567 568 /* Load all 32-bit constants. */ 569 if (tcg_out_movi_two(s, ret, arg)) { 570 return; 571 } 572 assert(TCG_TARGET_REG_BITS == 64); 573 574 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 575 tmp = tcg_tbrel_diff(s, (void *)arg); 576 if (tmp == (int16_t)tmp) { 577 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 578 return; 579 } 580 if (tcg_out_movi_two(s, ret, tmp)) { 581 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 582 return; 583 } 584 585 /* 586 * Load bitmasks with a right-shift. This is good for things 587 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 588 * or similarly using LUI. For this to work, bit 31 must be set. 589 */ 590 if (arg > 0 && (int32_t)arg < 0) { 591 sh = clz64(arg); 592 if (tcg_out_movi_one(s, ret, arg << sh)) { 593 tcg_out_dsrl(s, ret, ret, sh); 594 return; 595 } 596 } 597 598 /* 599 * Load slightly larger constants using left-shift. 600 * Limit this sequence to 3 insns to avoid too much expansion. 601 */ 602 sh = ctz64(arg); 603 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 604 tcg_out_dsll(s, ret, ret, sh); 605 return; 606 } 607 608 /* 609 * Load slightly larger constants using left-shift and add/or. 610 * Prefer addi with a negative immediate when that would produce 611 * a larger shift. For this to work, bits 15 and 16 must be set. 612 */ 613 lo = arg & 0xffff; 614 if (lo) { 615 if ((arg & 0x18000) == 0x18000) { 616 lo = (int16_t)arg; 617 } 618 tmp = arg - lo; 619 sh = ctz64(tmp); 620 tmp >>= sh; 621 if (tcg_out_movi_one(s, ret, tmp)) { 622 tcg_out_dsll(s, ret, ret, sh); 623 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 624 return; 625 } 626 } 627 628 /* Otherwise, put 64-bit constants into the constant pool. */ 629 tcg_out_movi_pool(s, ret, arg, tbreg); 630} 631 632static void tcg_out_movi(TCGContext *s, TCGType type, 633 TCGReg ret, tcg_target_long arg) 634{ 635 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 636 tcg_out_movi_int(s, type, ret, arg, tbreg); 637} 638 639static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 640{ 641 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); 642 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 643} 644 645static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 646{ 647 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 648} 649 650static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 651{ 652 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); 653 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 654} 655 656static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 657{ 658 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 659} 660 661static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 662{ 663 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 664 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 665} 666 667static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 668{ 669 if (rd != rs) { 670 tcg_out_ext32s(s, rd, rs); 671 } 672} 673 674static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 675{ 676 tcg_out_ext32u(s, rd, rs); 677} 678 679static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 680{ 681 tcg_out_ext32s(s, rd, rs); 682} 683 684static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 685{ 686 return false; 687} 688 689static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 690 tcg_target_long imm) 691{ 692 /* This function is only used for passing structs by reference. */ 693 g_assert_not_reached(); 694} 695 696static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 697{ 698 /* ret and arg can't be register tmp0 */ 699 tcg_debug_assert(ret != TCG_TMP0); 700 tcg_debug_assert(arg != TCG_TMP0); 701 702 /* With arg = abcd: */ 703 if (use_mips32r2_instructions) { 704 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 705 if (flags & TCG_BSWAP_OS) { 706 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 707 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 708 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 709 } 710 return; 711 } 712 713 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 714 if (!(flags & TCG_BSWAP_IZ)) { 715 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 716 } 717 if (flags & TCG_BSWAP_OS) { 718 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 719 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 720 } else { 721 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 722 if (flags & TCG_BSWAP_OZ) { 723 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 724 } 725 } 726 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 727} 728 729static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 730{ 731 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 732 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 733 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 734 } 735} 736 737static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 738{ 739 if (use_mips32r2_instructions) { 740 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 741 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 742 if (flags & TCG_BSWAP_OZ) { 743 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 744 } 745 } else { 746 if (flags & TCG_BSWAP_OZ) { 747 tcg_out_bswap_subr(s, bswap32u_addr); 748 } else { 749 tcg_out_bswap_subr(s, bswap32_addr); 750 } 751 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 752 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 753 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 754 } 755} 756 757static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 758{ 759 if (use_mips32r2_instructions) { 760 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 761 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 762 } else { 763 tcg_out_bswap_subr(s, bswap64_addr); 764 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 765 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 766 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 767 } 768} 769 770static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 771{ 772 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 773 if (use_mips32r2_instructions) { 774 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 775 } else { 776 tcg_out_dsll(s, ret, arg, 32); 777 tcg_out_dsrl(s, ret, ret, 32); 778 } 779} 780 781static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 782 TCGReg addr, intptr_t ofs) 783{ 784 int16_t lo = ofs; 785 if (ofs != lo) { 786 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 787 if (addr != TCG_REG_ZERO) { 788 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 789 } 790 addr = TCG_TMP0; 791 } 792 tcg_out_opc_imm(s, opc, data, addr, lo); 793} 794 795static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 796 TCGReg arg1, intptr_t arg2) 797{ 798 MIPSInsn opc = OPC_LD; 799 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 800 opc = OPC_LW; 801 } 802 tcg_out_ldst(s, opc, arg, arg1, arg2); 803} 804 805static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 806 TCGReg arg1, intptr_t arg2) 807{ 808 MIPSInsn opc = OPC_SD; 809 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 810 opc = OPC_SW; 811 } 812 tcg_out_ldst(s, opc, arg, arg1, arg2); 813} 814 815static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 816 TCGReg base, intptr_t ofs) 817{ 818 if (val == 0) { 819 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 820 return true; 821 } 822 return false; 823} 824 825static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 826 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 827 bool cbh, bool is_sub) 828{ 829 TCGReg th = TCG_TMP1; 830 831 /* If we have a negative constant such that negating it would 832 make the high part zero, we can (usually) eliminate one insn. */ 833 if (cbl && cbh && bh == -1 && bl != 0) { 834 bl = -bl; 835 bh = 0; 836 is_sub = !is_sub; 837 } 838 839 /* By operating on the high part first, we get to use the final 840 carry operation to move back from the temporary. */ 841 if (!cbh) { 842 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 843 } else if (bh != 0 || ah == rl) { 844 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 845 } else { 846 th = ah; 847 } 848 849 /* Note that tcg optimization should eliminate the bl == 0 case. */ 850 if (is_sub) { 851 if (cbl) { 852 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 853 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 854 } else { 855 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 856 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 857 } 858 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 859 } else { 860 if (cbl) { 861 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 862 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 863 } else if (rl == al && rl == bl) { 864 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 865 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 866 } else { 867 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 868 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 869 } 870 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 871 } 872} 873 874/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 875#define MIPS_CMP_INV 1 876#define MIPS_CMP_SWAP 2 877 878static const uint8_t mips_cmp_map[16] = { 879 [TCG_COND_LT] = 0, 880 [TCG_COND_LTU] = 0, 881 [TCG_COND_GE] = MIPS_CMP_INV, 882 [TCG_COND_GEU] = MIPS_CMP_INV, 883 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 884 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 885 [TCG_COND_GT] = MIPS_CMP_SWAP, 886 [TCG_COND_GTU] = MIPS_CMP_SWAP, 887}; 888 889static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 890 TCGReg arg1, TCGReg arg2) 891{ 892 MIPSInsn s_opc = OPC_SLTU; 893 int cmp_map; 894 895 switch (cond) { 896 case TCG_COND_EQ: 897 if (arg2 != 0) { 898 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 899 arg1 = ret; 900 } 901 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 902 break; 903 904 case TCG_COND_NE: 905 if (arg2 != 0) { 906 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 907 arg1 = ret; 908 } 909 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 910 break; 911 912 case TCG_COND_LT: 913 case TCG_COND_GE: 914 case TCG_COND_LE: 915 case TCG_COND_GT: 916 s_opc = OPC_SLT; 917 /* FALLTHRU */ 918 919 case TCG_COND_LTU: 920 case TCG_COND_GEU: 921 case TCG_COND_LEU: 922 case TCG_COND_GTU: 923 cmp_map = mips_cmp_map[cond]; 924 if (cmp_map & MIPS_CMP_SWAP) { 925 TCGReg t = arg1; 926 arg1 = arg2; 927 arg2 = t; 928 } 929 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 930 if (cmp_map & MIPS_CMP_INV) { 931 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 932 } 933 break; 934 935 default: 936 g_assert_not_reached(); 937 break; 938 } 939} 940 941static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 942 TCGReg arg2, TCGLabel *l) 943{ 944 static const MIPSInsn b_zero[16] = { 945 [TCG_COND_LT] = OPC_BLTZ, 946 [TCG_COND_GT] = OPC_BGTZ, 947 [TCG_COND_LE] = OPC_BLEZ, 948 [TCG_COND_GE] = OPC_BGEZ, 949 }; 950 951 MIPSInsn s_opc = OPC_SLTU; 952 MIPSInsn b_opc; 953 int cmp_map; 954 955 switch (cond) { 956 case TCG_COND_EQ: 957 b_opc = OPC_BEQ; 958 break; 959 case TCG_COND_NE: 960 b_opc = OPC_BNE; 961 break; 962 963 case TCG_COND_LT: 964 case TCG_COND_GT: 965 case TCG_COND_LE: 966 case TCG_COND_GE: 967 if (arg2 == 0) { 968 b_opc = b_zero[cond]; 969 arg2 = arg1; 970 arg1 = 0; 971 break; 972 } 973 s_opc = OPC_SLT; 974 /* FALLTHRU */ 975 976 case TCG_COND_LTU: 977 case TCG_COND_GTU: 978 case TCG_COND_LEU: 979 case TCG_COND_GEU: 980 cmp_map = mips_cmp_map[cond]; 981 if (cmp_map & MIPS_CMP_SWAP) { 982 TCGReg t = arg1; 983 arg1 = arg2; 984 arg2 = t; 985 } 986 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 987 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 988 arg1 = TCG_TMP0; 989 arg2 = TCG_REG_ZERO; 990 break; 991 992 default: 993 g_assert_not_reached(); 994 break; 995 } 996 997 tcg_out_opc_br(s, b_opc, arg1, arg2); 998 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 999 tcg_out_nop(s); 1000} 1001 1002static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 1003 TCGReg al, TCGReg ah, 1004 TCGReg bl, TCGReg bh) 1005{ 1006 /* Merge highpart comparison into AH. */ 1007 if (bh != 0) { 1008 if (ah != 0) { 1009 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 1010 ah = tmp0; 1011 } else { 1012 ah = bh; 1013 } 1014 } 1015 /* Merge lowpart comparison into AL. */ 1016 if (bl != 0) { 1017 if (al != 0) { 1018 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 1019 al = tmp1; 1020 } else { 1021 al = bl; 1022 } 1023 } 1024 /* Merge high and low part comparisons into AL. */ 1025 if (ah != 0) { 1026 if (al != 0) { 1027 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 1028 al = tmp0; 1029 } else { 1030 al = ah; 1031 } 1032 } 1033 return al; 1034} 1035 1036static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1037 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1038{ 1039 TCGReg tmp0 = TCG_TMP0; 1040 TCGReg tmp1 = ret; 1041 1042 tcg_debug_assert(ret != TCG_TMP0); 1043 if (ret == ah || ret == bh) { 1044 tcg_debug_assert(ret != TCG_TMP1); 1045 tmp1 = TCG_TMP1; 1046 } 1047 1048 switch (cond) { 1049 case TCG_COND_EQ: 1050 case TCG_COND_NE: 1051 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 1052 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 1053 break; 1054 1055 default: 1056 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 1057 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 1058 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 1059 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 1060 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 1061 break; 1062 } 1063} 1064 1065static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1066 TCGReg bl, TCGReg bh, TCGLabel *l) 1067{ 1068 TCGCond b_cond = TCG_COND_NE; 1069 TCGReg tmp = TCG_TMP1; 1070 1071 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 1072 With setcond, we emit between 3 and 10 insns and only 1 branch, 1073 which ought to get better branch prediction. */ 1074 switch (cond) { 1075 case TCG_COND_EQ: 1076 case TCG_COND_NE: 1077 b_cond = cond; 1078 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 1079 break; 1080 1081 default: 1082 /* Minimize code size by preferring a compare not requiring INV. */ 1083 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1084 cond = tcg_invert_cond(cond); 1085 b_cond = TCG_COND_EQ; 1086 } 1087 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 1088 break; 1089 } 1090 1091 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 1092} 1093 1094static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 1095 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1096{ 1097 bool eqz = false; 1098 1099 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1100 if (use_mips32r6_instructions && v1 == 0) { 1101 v1 = v2; 1102 v2 = 0; 1103 cond = tcg_invert_cond(cond); 1104 } 1105 1106 switch (cond) { 1107 case TCG_COND_EQ: 1108 eqz = true; 1109 /* FALLTHRU */ 1110 case TCG_COND_NE: 1111 if (c2 != 0) { 1112 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 1113 c1 = TCG_TMP0; 1114 } 1115 break; 1116 1117 default: 1118 /* Minimize code size by preferring a compare not requiring INV. */ 1119 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1120 cond = tcg_invert_cond(cond); 1121 eqz = true; 1122 } 1123 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 1124 c1 = TCG_TMP0; 1125 break; 1126 } 1127 1128 if (use_mips32r6_instructions) { 1129 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1130 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1131 1132 if (v2 != 0) { 1133 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1134 } 1135 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1136 if (v2 != 0) { 1137 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1138 } 1139 } else { 1140 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1141 1142 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1143 1144 /* This should be guaranteed via constraints */ 1145 tcg_debug_assert(v2 == ret); 1146 } 1147} 1148 1149static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1150{ 1151 /* 1152 * Note that __mips_abicalls requires the called function's address 1153 * to be loaded into $25 (t9), even if a direct branch is in range. 1154 * 1155 * For n64, always drop the pointer into the constant pool. 1156 * We can re-use helper addresses often and do not want any 1157 * of the longer sequences tcg_out_movi may try. 1158 */ 1159 if (sizeof(uintptr_t) == 8) { 1160 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1161 } else { 1162 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1163 } 1164 1165 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1166 if (tail) { 1167 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1168 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1169 } 1170 } else { 1171 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1172 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1173 } 1174 } 1175} 1176 1177static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1178 const TCGHelperInfo *info) 1179{ 1180 tcg_out_call_int(s, arg, false); 1181 tcg_out_nop(s); 1182} 1183 1184/* We have four temps, we might as well expose three of them. */ 1185static const TCGLdstHelperParam ldst_helper_param = { 1186 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1187}; 1188 1189static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1190{ 1191 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1192 MemOp opc = get_memop(l->oi); 1193 1194 /* resolve label address */ 1195 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1196 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1197 return false; 1198 } 1199 1200 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1201 1202 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1203 /* delay slot */ 1204 tcg_out_nop(s); 1205 1206 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1207 1208 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1209 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1210 return false; 1211 } 1212 1213 /* delay slot */ 1214 tcg_out_nop(s); 1215 return true; 1216} 1217 1218static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1219{ 1220 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1221 MemOp opc = get_memop(l->oi); 1222 1223 /* resolve label address */ 1224 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1225 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1226 return false; 1227 } 1228 1229 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1230 1231 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1232 /* delay slot */ 1233 tcg_out_nop(s); 1234 1235 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1236 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1237 return false; 1238 } 1239 1240 /* delay slot */ 1241 tcg_out_nop(s); 1242 return true; 1243} 1244 1245typedef struct { 1246 TCGReg base; 1247 TCGAtomAlign aa; 1248} HostAddress; 1249 1250bool tcg_target_has_memory_bswap(MemOp memop) 1251{ 1252 return false; 1253} 1254 1255/* We expect to use a 16-bit negative offset from ENV. */ 1256#define MIN_TLB_MASK_TABLE_OFS -32768 1257 1258/* 1259 * For system-mode, perform the TLB load and compare. 1260 * For user-mode, perform any required alignment tests. 1261 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1262 * is required and fill in @h with the host address for the fast path. 1263 */ 1264static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1265 TCGReg addrlo, TCGReg addrhi, 1266 MemOpIdx oi, bool is_ld) 1267{ 1268 TCGType addr_type = s->addr_type; 1269 TCGLabelQemuLdst *ldst = NULL; 1270 MemOp opc = get_memop(oi); 1271 MemOp a_bits; 1272 unsigned s_bits = opc & MO_SIZE; 1273 unsigned a_mask; 1274 TCGReg base; 1275 1276 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1277 a_bits = h->aa.align; 1278 a_mask = (1 << a_bits) - 1; 1279 1280 if (tcg_use_softmmu) { 1281 unsigned s_mask = (1 << s_bits) - 1; 1282 int mem_index = get_mmuidx(oi); 1283 int fast_off = tlb_mask_table_ofs(s, mem_index); 1284 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1285 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1286 int add_off = offsetof(CPUTLBEntry, addend); 1287 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1288 : offsetof(CPUTLBEntry, addr_write); 1289 1290 ldst = new_ldst_label(s); 1291 ldst->is_ld = is_ld; 1292 ldst->oi = oi; 1293 ldst->addrlo_reg = addrlo; 1294 ldst->addrhi_reg = addrhi; 1295 1296 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1297 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1298 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1299 1300 /* Extract the TLB index from the address into TMP3. */ 1301 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1302 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, 1303 s->page_bits - CPU_TLB_ENTRY_BITS); 1304 } else { 1305 tcg_out_dsrl(s, TCG_TMP3, addrlo, 1306 s->page_bits - CPU_TLB_ENTRY_BITS); 1307 } 1308 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1309 1310 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1311 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1312 1313 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1314 /* Load the (low half) tlb comparator. */ 1315 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1316 cmp_off + HOST_BIG_ENDIAN * 4); 1317 } else { 1318 tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off); 1319 } 1320 1321 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { 1322 /* Load the tlb addend for the fast path. */ 1323 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1324 } 1325 1326 /* 1327 * Mask the page bits, keeping the alignment bits to compare against. 1328 * For unaligned accesses, compare against the end of the access to 1329 * verify that it does not cross a page boundary. 1330 */ 1331 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1332 if (a_mask < s_mask) { 1333 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1334 || addr_type == TCG_TYPE_I32 1335 ? OPC_ADDIU : OPC_DADDIU), 1336 TCG_TMP2, addrlo, s_mask - a_mask); 1337 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1338 } else { 1339 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); 1340 } 1341 1342 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1343 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1344 tcg_out_ext32u(s, TCG_TMP2, addrlo); 1345 addrlo = TCG_TMP2; 1346 } 1347 1348 ldst->label_ptr[0] = s->code_ptr; 1349 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1350 1351 /* Load and test the high half tlb comparator. */ 1352 if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { 1353 /* delay slot */ 1354 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1355 1356 /* Load the tlb addend for the fast path. */ 1357 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1358 1359 ldst->label_ptr[1] = s->code_ptr; 1360 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); 1361 } 1362 1363 /* delay slot */ 1364 base = TCG_TMP3; 1365 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); 1366 } else { 1367 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1368 ldst = new_ldst_label(s); 1369 1370 ldst->is_ld = is_ld; 1371 ldst->oi = oi; 1372 ldst->addrlo_reg = addrlo; 1373 ldst->addrhi_reg = addrhi; 1374 1375 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1376 tcg_debug_assert(a_bits < 16); 1377 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); 1378 1379 ldst->label_ptr[0] = s->code_ptr; 1380 if (use_mips32r6_instructions) { 1381 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1382 } else { 1383 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1384 tcg_out_nop(s); 1385 } 1386 } 1387 1388 base = addrlo; 1389 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1390 tcg_out_ext32u(s, TCG_REG_A0, base); 1391 base = TCG_REG_A0; 1392 } 1393 if (guest_base) { 1394 if (guest_base == (int16_t)guest_base) { 1395 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1396 } else { 1397 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1398 TCG_GUEST_BASE_REG); 1399 } 1400 base = TCG_REG_A0; 1401 } 1402 } 1403 1404 h->base = base; 1405 return ldst; 1406} 1407 1408static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1409 TCGReg base, MemOp opc, TCGType type) 1410{ 1411 switch (opc & MO_SSIZE) { 1412 case MO_UB: 1413 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1414 break; 1415 case MO_SB: 1416 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1417 break; 1418 case MO_UW: 1419 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1420 break; 1421 case MO_SW: 1422 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1423 break; 1424 case MO_UL: 1425 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1426 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1427 break; 1428 } 1429 /* FALLTHRU */ 1430 case MO_SL: 1431 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1432 break; 1433 case MO_UQ: 1434 /* Prefer to load from offset 0 first, but allow for overlap. */ 1435 if (TCG_TARGET_REG_BITS == 64) { 1436 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1437 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1438 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1439 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1440 } else { 1441 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1442 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1443 } 1444 break; 1445 default: 1446 g_assert_not_reached(); 1447 } 1448} 1449 1450static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1451 TCGReg base, MemOp opc, TCGType type) 1452{ 1453 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1454 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1455 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1456 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1457 bool sgn = opc & MO_SIGN; 1458 1459 switch (opc & MO_SIZE) { 1460 case MO_16: 1461 if (HOST_BIG_ENDIAN) { 1462 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1463 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1464 if (use_mips32r2_instructions) { 1465 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1466 } else { 1467 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1468 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1469 } 1470 } else if (use_mips32r2_instructions && lo != base) { 1471 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1472 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1473 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1474 } else { 1475 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1476 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1477 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1478 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1479 } 1480 break; 1481 1482 case MO_32: 1483 tcg_out_opc_imm(s, lw1, lo, base, 0); 1484 tcg_out_opc_imm(s, lw2, lo, base, 3); 1485 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1486 tcg_out_ext32u(s, lo, lo); 1487 } 1488 break; 1489 1490 case MO_64: 1491 if (TCG_TARGET_REG_BITS == 64) { 1492 tcg_out_opc_imm(s, ld1, lo, base, 0); 1493 tcg_out_opc_imm(s, ld2, lo, base, 7); 1494 } else { 1495 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1496 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1497 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1498 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1499 } 1500 break; 1501 1502 default: 1503 g_assert_not_reached(); 1504 } 1505} 1506 1507static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1508 TCGReg addrlo, TCGReg addrhi, 1509 MemOpIdx oi, TCGType data_type) 1510{ 1511 MemOp opc = get_memop(oi); 1512 TCGLabelQemuLdst *ldst; 1513 HostAddress h; 1514 1515 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 1516 1517 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1518 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1519 } else { 1520 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1521 } 1522 1523 if (ldst) { 1524 ldst->type = data_type; 1525 ldst->datalo_reg = datalo; 1526 ldst->datahi_reg = datahi; 1527 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1528 } 1529} 1530 1531static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1532 TCGReg base, MemOp opc) 1533{ 1534 switch (opc & MO_SIZE) { 1535 case MO_8: 1536 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1537 break; 1538 case MO_16: 1539 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1540 break; 1541 case MO_32: 1542 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1543 break; 1544 case MO_64: 1545 if (TCG_TARGET_REG_BITS == 64) { 1546 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1547 } else { 1548 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1549 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1550 } 1551 break; 1552 default: 1553 g_assert_not_reached(); 1554 } 1555} 1556 1557static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1558 TCGReg base, MemOp opc) 1559{ 1560 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1561 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1562 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1563 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1564 1565 switch (opc & MO_SIZE) { 1566 case MO_16: 1567 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1568 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1569 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1570 break; 1571 1572 case MO_32: 1573 tcg_out_opc_imm(s, sw1, lo, base, 0); 1574 tcg_out_opc_imm(s, sw2, lo, base, 3); 1575 break; 1576 1577 case MO_64: 1578 if (TCG_TARGET_REG_BITS == 64) { 1579 tcg_out_opc_imm(s, sd1, lo, base, 0); 1580 tcg_out_opc_imm(s, sd2, lo, base, 7); 1581 } else { 1582 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1583 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1584 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1585 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1586 } 1587 break; 1588 1589 default: 1590 g_assert_not_reached(); 1591 } 1592} 1593 1594static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1595 TCGReg addrlo, TCGReg addrhi, 1596 MemOpIdx oi, TCGType data_type) 1597{ 1598 MemOp opc = get_memop(oi); 1599 TCGLabelQemuLdst *ldst; 1600 HostAddress h; 1601 1602 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 1603 1604 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1605 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1606 } else { 1607 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1608 } 1609 1610 if (ldst) { 1611 ldst->type = data_type; 1612 ldst->datalo_reg = datalo; 1613 ldst->datahi_reg = datahi; 1614 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1615 } 1616} 1617 1618static void tcg_out_mb(TCGContext *s, TCGArg a0) 1619{ 1620 static const MIPSInsn sync[] = { 1621 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1622 as the former is an ordering barrier and the latter 1623 is a completion barrier. */ 1624 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1625 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1626 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1627 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1628 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1629 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1630 }; 1631 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1632} 1633 1634static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1635 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1636{ 1637 if (use_mips32r6_instructions) { 1638 if (a2 == width) { 1639 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1640 } else { 1641 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1642 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1643 } 1644 } else { 1645 if (a2 == width) { 1646 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1647 } else if (a0 == a2) { 1648 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1649 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1650 } else if (a0 != a1) { 1651 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1652 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1653 } else { 1654 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1655 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1656 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1657 } 1658 } 1659} 1660 1661static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1662{ 1663 TCGReg base = TCG_REG_ZERO; 1664 int16_t lo = 0; 1665 1666 if (a0) { 1667 intptr_t ofs; 1668 if (TCG_TARGET_REG_BITS == 64) { 1669 ofs = tcg_tbrel_diff(s, (void *)a0); 1670 lo = ofs; 1671 if (ofs == lo) { 1672 base = TCG_REG_TB; 1673 } else { 1674 base = TCG_REG_V0; 1675 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1676 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1677 } 1678 } else { 1679 ofs = a0; 1680 lo = ofs; 1681 base = TCG_REG_V0; 1682 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1683 } 1684 } 1685 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1686 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1687 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1688 } 1689 /* delay slot */ 1690 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1691} 1692 1693static void tcg_out_goto_tb(TCGContext *s, int which) 1694{ 1695 intptr_t ofs = get_jmp_target_addr(s, which); 1696 TCGReg base, dest; 1697 1698 /* indirect jump method */ 1699 if (TCG_TARGET_REG_BITS == 64) { 1700 dest = TCG_REG_TB; 1701 base = TCG_REG_TB; 1702 ofs = tcg_tbrel_diff(s, (void *)ofs); 1703 } else { 1704 dest = TCG_TMP0; 1705 base = TCG_REG_ZERO; 1706 } 1707 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1708 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1709 /* delay slot */ 1710 tcg_out_nop(s); 1711 1712 set_jmp_reset_offset(s, which); 1713 if (TCG_TARGET_REG_BITS == 64) { 1714 /* For the unlinked case, need to reset TCG_REG_TB. */ 1715 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1716 -tcg_current_code_size(s)); 1717 } 1718} 1719 1720void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1721 uintptr_t jmp_rx, uintptr_t jmp_rw) 1722{ 1723 /* Always indirect, nothing to do */ 1724} 1725 1726static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1727 const TCGArg args[TCG_MAX_OP_ARGS], 1728 const int const_args[TCG_MAX_OP_ARGS]) 1729{ 1730 MIPSInsn i1, i2; 1731 TCGArg a0, a1, a2; 1732 int c2; 1733 1734 /* 1735 * Note that many operands use the constraint set "rZ". 1736 * We make use of the fact that 0 is the ZERO register, 1737 * and hence such cases need not check for const_args. 1738 */ 1739 a0 = args[0]; 1740 a1 = args[1]; 1741 a2 = args[2]; 1742 c2 = const_args[2]; 1743 1744 switch (opc) { 1745 case INDEX_op_goto_ptr: 1746 /* jmp to the given host address (could be epilogue) */ 1747 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1748 if (TCG_TARGET_REG_BITS == 64) { 1749 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 1750 } else { 1751 tcg_out_nop(s); 1752 } 1753 break; 1754 case INDEX_op_br: 1755 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1756 arg_label(a0)); 1757 break; 1758 1759 case INDEX_op_ld8u_i32: 1760 case INDEX_op_ld8u_i64: 1761 i1 = OPC_LBU; 1762 goto do_ldst; 1763 case INDEX_op_ld8s_i32: 1764 case INDEX_op_ld8s_i64: 1765 i1 = OPC_LB; 1766 goto do_ldst; 1767 case INDEX_op_ld16u_i32: 1768 case INDEX_op_ld16u_i64: 1769 i1 = OPC_LHU; 1770 goto do_ldst; 1771 case INDEX_op_ld16s_i32: 1772 case INDEX_op_ld16s_i64: 1773 i1 = OPC_LH; 1774 goto do_ldst; 1775 case INDEX_op_ld_i32: 1776 case INDEX_op_ld32s_i64: 1777 i1 = OPC_LW; 1778 goto do_ldst; 1779 case INDEX_op_ld32u_i64: 1780 i1 = OPC_LWU; 1781 goto do_ldst; 1782 case INDEX_op_ld_i64: 1783 i1 = OPC_LD; 1784 goto do_ldst; 1785 case INDEX_op_st8_i32: 1786 case INDEX_op_st8_i64: 1787 i1 = OPC_SB; 1788 goto do_ldst; 1789 case INDEX_op_st16_i32: 1790 case INDEX_op_st16_i64: 1791 i1 = OPC_SH; 1792 goto do_ldst; 1793 case INDEX_op_st_i32: 1794 case INDEX_op_st32_i64: 1795 i1 = OPC_SW; 1796 goto do_ldst; 1797 case INDEX_op_st_i64: 1798 i1 = OPC_SD; 1799 do_ldst: 1800 tcg_out_ldst(s, i1, a0, a1, a2); 1801 break; 1802 1803 case INDEX_op_add_i32: 1804 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1805 goto do_binary; 1806 case INDEX_op_add_i64: 1807 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1808 goto do_binary; 1809 case INDEX_op_or_i32: 1810 case INDEX_op_or_i64: 1811 i1 = OPC_OR, i2 = OPC_ORI; 1812 goto do_binary; 1813 case INDEX_op_xor_i32: 1814 case INDEX_op_xor_i64: 1815 i1 = OPC_XOR, i2 = OPC_XORI; 1816 do_binary: 1817 if (c2) { 1818 tcg_out_opc_imm(s, i2, a0, a1, a2); 1819 break; 1820 } 1821 do_binaryv: 1822 tcg_out_opc_reg(s, i1, a0, a1, a2); 1823 break; 1824 1825 case INDEX_op_sub_i32: 1826 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1827 goto do_subtract; 1828 case INDEX_op_sub_i64: 1829 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1830 do_subtract: 1831 if (c2) { 1832 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1833 break; 1834 } 1835 goto do_binaryv; 1836 case INDEX_op_and_i32: 1837 if (c2 && a2 != (uint16_t)a2) { 1838 int msb = ctz32(~a2) - 1; 1839 tcg_debug_assert(use_mips32r2_instructions); 1840 tcg_debug_assert(is_p2m1(a2)); 1841 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1842 break; 1843 } 1844 i1 = OPC_AND, i2 = OPC_ANDI; 1845 goto do_binary; 1846 case INDEX_op_and_i64: 1847 if (c2 && a2 != (uint16_t)a2) { 1848 int msb = ctz64(~a2) - 1; 1849 tcg_debug_assert(use_mips32r2_instructions); 1850 tcg_debug_assert(is_p2m1(a2)); 1851 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1852 break; 1853 } 1854 i1 = OPC_AND, i2 = OPC_ANDI; 1855 goto do_binary; 1856 case INDEX_op_nor_i32: 1857 case INDEX_op_nor_i64: 1858 i1 = OPC_NOR; 1859 goto do_binaryv; 1860 1861 case INDEX_op_mul_i32: 1862 if (use_mips32_instructions) { 1863 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1864 break; 1865 } 1866 i1 = OPC_MULT, i2 = OPC_MFLO; 1867 goto do_hilo1; 1868 case INDEX_op_mulsh_i32: 1869 if (use_mips32r6_instructions) { 1870 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1871 break; 1872 } 1873 i1 = OPC_MULT, i2 = OPC_MFHI; 1874 goto do_hilo1; 1875 case INDEX_op_muluh_i32: 1876 if (use_mips32r6_instructions) { 1877 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1878 break; 1879 } 1880 i1 = OPC_MULTU, i2 = OPC_MFHI; 1881 goto do_hilo1; 1882 case INDEX_op_div_i32: 1883 if (use_mips32r6_instructions) { 1884 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1885 break; 1886 } 1887 i1 = OPC_DIV, i2 = OPC_MFLO; 1888 goto do_hilo1; 1889 case INDEX_op_divu_i32: 1890 if (use_mips32r6_instructions) { 1891 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1892 break; 1893 } 1894 i1 = OPC_DIVU, i2 = OPC_MFLO; 1895 goto do_hilo1; 1896 case INDEX_op_rem_i32: 1897 if (use_mips32r6_instructions) { 1898 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1899 break; 1900 } 1901 i1 = OPC_DIV, i2 = OPC_MFHI; 1902 goto do_hilo1; 1903 case INDEX_op_remu_i32: 1904 if (use_mips32r6_instructions) { 1905 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1906 break; 1907 } 1908 i1 = OPC_DIVU, i2 = OPC_MFHI; 1909 goto do_hilo1; 1910 case INDEX_op_mul_i64: 1911 if (use_mips32r6_instructions) { 1912 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1913 break; 1914 } 1915 i1 = OPC_DMULT, i2 = OPC_MFLO; 1916 goto do_hilo1; 1917 case INDEX_op_mulsh_i64: 1918 if (use_mips32r6_instructions) { 1919 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1920 break; 1921 } 1922 i1 = OPC_DMULT, i2 = OPC_MFHI; 1923 goto do_hilo1; 1924 case INDEX_op_muluh_i64: 1925 if (use_mips32r6_instructions) { 1926 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1927 break; 1928 } 1929 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1930 goto do_hilo1; 1931 case INDEX_op_div_i64: 1932 if (use_mips32r6_instructions) { 1933 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1934 break; 1935 } 1936 i1 = OPC_DDIV, i2 = OPC_MFLO; 1937 goto do_hilo1; 1938 case INDEX_op_divu_i64: 1939 if (use_mips32r6_instructions) { 1940 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1941 break; 1942 } 1943 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1944 goto do_hilo1; 1945 case INDEX_op_rem_i64: 1946 if (use_mips32r6_instructions) { 1947 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1948 break; 1949 } 1950 i1 = OPC_DDIV, i2 = OPC_MFHI; 1951 goto do_hilo1; 1952 case INDEX_op_remu_i64: 1953 if (use_mips32r6_instructions) { 1954 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1955 break; 1956 } 1957 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1958 do_hilo1: 1959 tcg_out_opc_reg(s, i1, 0, a1, a2); 1960 tcg_out_opc_reg(s, i2, a0, 0, 0); 1961 break; 1962 1963 case INDEX_op_muls2_i32: 1964 i1 = OPC_MULT; 1965 goto do_hilo2; 1966 case INDEX_op_mulu2_i32: 1967 i1 = OPC_MULTU; 1968 goto do_hilo2; 1969 case INDEX_op_muls2_i64: 1970 i1 = OPC_DMULT; 1971 goto do_hilo2; 1972 case INDEX_op_mulu2_i64: 1973 i1 = OPC_DMULTU; 1974 do_hilo2: 1975 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1976 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1977 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1978 break; 1979 1980 case INDEX_op_not_i32: 1981 case INDEX_op_not_i64: 1982 i1 = OPC_NOR; 1983 goto do_unary; 1984 do_unary: 1985 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1986 break; 1987 1988 case INDEX_op_bswap16_i32: 1989 case INDEX_op_bswap16_i64: 1990 tcg_out_bswap16(s, a0, a1, a2); 1991 break; 1992 case INDEX_op_bswap32_i32: 1993 tcg_out_bswap32(s, a0, a1, 0); 1994 break; 1995 case INDEX_op_bswap32_i64: 1996 tcg_out_bswap32(s, a0, a1, a2); 1997 break; 1998 case INDEX_op_bswap64_i64: 1999 tcg_out_bswap64(s, a0, a1); 2000 break; 2001 case INDEX_op_extrh_i64_i32: 2002 tcg_out_dsra(s, a0, a1, 32); 2003 break; 2004 2005 case INDEX_op_sar_i32: 2006 i1 = OPC_SRAV, i2 = OPC_SRA; 2007 goto do_shift; 2008 case INDEX_op_shl_i32: 2009 i1 = OPC_SLLV, i2 = OPC_SLL; 2010 goto do_shift; 2011 case INDEX_op_shr_i32: 2012 i1 = OPC_SRLV, i2 = OPC_SRL; 2013 goto do_shift; 2014 case INDEX_op_rotr_i32: 2015 i1 = OPC_ROTRV, i2 = OPC_ROTR; 2016 do_shift: 2017 if (c2) { 2018 tcg_out_opc_sa(s, i2, a0, a1, a2); 2019 break; 2020 } 2021 do_shiftv: 2022 tcg_out_opc_reg(s, i1, a0, a2, a1); 2023 break; 2024 case INDEX_op_rotl_i32: 2025 if (c2) { 2026 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 2027 } else { 2028 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2029 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 2030 } 2031 break; 2032 case INDEX_op_sar_i64: 2033 if (c2) { 2034 tcg_out_dsra(s, a0, a1, a2); 2035 break; 2036 } 2037 i1 = OPC_DSRAV; 2038 goto do_shiftv; 2039 case INDEX_op_shl_i64: 2040 if (c2) { 2041 tcg_out_dsll(s, a0, a1, a2); 2042 break; 2043 } 2044 i1 = OPC_DSLLV; 2045 goto do_shiftv; 2046 case INDEX_op_shr_i64: 2047 if (c2) { 2048 tcg_out_dsrl(s, a0, a1, a2); 2049 break; 2050 } 2051 i1 = OPC_DSRLV; 2052 goto do_shiftv; 2053 case INDEX_op_rotr_i64: 2054 if (c2) { 2055 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2056 break; 2057 } 2058 i1 = OPC_DROTRV; 2059 goto do_shiftv; 2060 case INDEX_op_rotl_i64: 2061 if (c2) { 2062 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 2063 } else { 2064 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 2065 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 2066 } 2067 break; 2068 2069 case INDEX_op_clz_i32: 2070 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 2071 break; 2072 case INDEX_op_clz_i64: 2073 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 2074 break; 2075 2076 case INDEX_op_deposit_i32: 2077 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2078 break; 2079 case INDEX_op_deposit_i64: 2080 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2081 args[3] + args[4] - 1, args[3]); 2082 break; 2083 case INDEX_op_extract_i32: 2084 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2085 break; 2086 case INDEX_op_extract_i64: 2087 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 2088 args[3] - 1, a2); 2089 break; 2090 2091 case INDEX_op_brcond_i32: 2092 case INDEX_op_brcond_i64: 2093 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 2094 break; 2095 case INDEX_op_brcond2_i32: 2096 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 2097 break; 2098 2099 case INDEX_op_movcond_i32: 2100 case INDEX_op_movcond_i64: 2101 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 2102 break; 2103 2104 case INDEX_op_setcond_i32: 2105 case INDEX_op_setcond_i64: 2106 tcg_out_setcond(s, args[3], a0, a1, a2); 2107 break; 2108 case INDEX_op_setcond2_i32: 2109 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 2110 break; 2111 2112 case INDEX_op_qemu_ld_a64_i32: 2113 if (TCG_TARGET_REG_BITS == 32) { 2114 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 2115 break; 2116 } 2117 /* fall through */ 2118 case INDEX_op_qemu_ld_a32_i32: 2119 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 2120 break; 2121 case INDEX_op_qemu_ld_a32_i64: 2122 if (TCG_TARGET_REG_BITS == 64) { 2123 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2124 } else { 2125 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 2126 } 2127 break; 2128 case INDEX_op_qemu_ld_a64_i64: 2129 if (TCG_TARGET_REG_BITS == 64) { 2130 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2131 } else { 2132 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2133 } 2134 break; 2135 2136 case INDEX_op_qemu_st_a64_i32: 2137 if (TCG_TARGET_REG_BITS == 32) { 2138 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 2139 break; 2140 } 2141 /* fall through */ 2142 case INDEX_op_qemu_st_a32_i32: 2143 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 2144 break; 2145 case INDEX_op_qemu_st_a32_i64: 2146 if (TCG_TARGET_REG_BITS == 64) { 2147 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2148 } else { 2149 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 2150 } 2151 break; 2152 case INDEX_op_qemu_st_a64_i64: 2153 if (TCG_TARGET_REG_BITS == 64) { 2154 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2155 } else { 2156 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2157 } 2158 break; 2159 2160 case INDEX_op_add2_i32: 2161 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2162 const_args[4], const_args[5], false); 2163 break; 2164 case INDEX_op_sub2_i32: 2165 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2166 const_args[4], const_args[5], true); 2167 break; 2168 2169 case INDEX_op_mb: 2170 tcg_out_mb(s, a0); 2171 break; 2172 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2173 case INDEX_op_mov_i64: 2174 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2175 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2176 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2177 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2178 case INDEX_op_ext8s_i64: 2179 case INDEX_op_ext8u_i32: 2180 case INDEX_op_ext8u_i64: 2181 case INDEX_op_ext16s_i32: 2182 case INDEX_op_ext16s_i64: 2183 case INDEX_op_ext32s_i64: 2184 case INDEX_op_ext32u_i64: 2185 case INDEX_op_ext_i32_i64: 2186 case INDEX_op_extu_i32_i64: 2187 case INDEX_op_extrl_i64_i32: 2188 default: 2189 g_assert_not_reached(); 2190 } 2191} 2192 2193static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2194{ 2195 switch (op) { 2196 case INDEX_op_goto_ptr: 2197 return C_O0_I1(r); 2198 2199 case INDEX_op_ld8u_i32: 2200 case INDEX_op_ld8s_i32: 2201 case INDEX_op_ld16u_i32: 2202 case INDEX_op_ld16s_i32: 2203 case INDEX_op_ld_i32: 2204 case INDEX_op_not_i32: 2205 case INDEX_op_bswap16_i32: 2206 case INDEX_op_bswap32_i32: 2207 case INDEX_op_ext8s_i32: 2208 case INDEX_op_ext16s_i32: 2209 case INDEX_op_extract_i32: 2210 case INDEX_op_ld8u_i64: 2211 case INDEX_op_ld8s_i64: 2212 case INDEX_op_ld16u_i64: 2213 case INDEX_op_ld16s_i64: 2214 case INDEX_op_ld32s_i64: 2215 case INDEX_op_ld32u_i64: 2216 case INDEX_op_ld_i64: 2217 case INDEX_op_not_i64: 2218 case INDEX_op_bswap16_i64: 2219 case INDEX_op_bswap32_i64: 2220 case INDEX_op_bswap64_i64: 2221 case INDEX_op_ext8s_i64: 2222 case INDEX_op_ext16s_i64: 2223 case INDEX_op_ext32s_i64: 2224 case INDEX_op_ext32u_i64: 2225 case INDEX_op_ext_i32_i64: 2226 case INDEX_op_extu_i32_i64: 2227 case INDEX_op_extrl_i64_i32: 2228 case INDEX_op_extrh_i64_i32: 2229 case INDEX_op_extract_i64: 2230 return C_O1_I1(r, r); 2231 2232 case INDEX_op_st8_i32: 2233 case INDEX_op_st16_i32: 2234 case INDEX_op_st_i32: 2235 case INDEX_op_st8_i64: 2236 case INDEX_op_st16_i64: 2237 case INDEX_op_st32_i64: 2238 case INDEX_op_st_i64: 2239 return C_O0_I2(rZ, r); 2240 2241 case INDEX_op_add_i32: 2242 case INDEX_op_add_i64: 2243 return C_O1_I2(r, r, rJ); 2244 case INDEX_op_sub_i32: 2245 case INDEX_op_sub_i64: 2246 return C_O1_I2(r, rZ, rN); 2247 case INDEX_op_mul_i32: 2248 case INDEX_op_mulsh_i32: 2249 case INDEX_op_muluh_i32: 2250 case INDEX_op_div_i32: 2251 case INDEX_op_divu_i32: 2252 case INDEX_op_rem_i32: 2253 case INDEX_op_remu_i32: 2254 case INDEX_op_nor_i32: 2255 case INDEX_op_setcond_i32: 2256 case INDEX_op_mul_i64: 2257 case INDEX_op_mulsh_i64: 2258 case INDEX_op_muluh_i64: 2259 case INDEX_op_div_i64: 2260 case INDEX_op_divu_i64: 2261 case INDEX_op_rem_i64: 2262 case INDEX_op_remu_i64: 2263 case INDEX_op_nor_i64: 2264 case INDEX_op_setcond_i64: 2265 return C_O1_I2(r, rZ, rZ); 2266 case INDEX_op_muls2_i32: 2267 case INDEX_op_mulu2_i32: 2268 case INDEX_op_muls2_i64: 2269 case INDEX_op_mulu2_i64: 2270 return C_O2_I2(r, r, r, r); 2271 case INDEX_op_and_i32: 2272 case INDEX_op_and_i64: 2273 return C_O1_I2(r, r, rIK); 2274 case INDEX_op_or_i32: 2275 case INDEX_op_xor_i32: 2276 case INDEX_op_or_i64: 2277 case INDEX_op_xor_i64: 2278 return C_O1_I2(r, r, rI); 2279 case INDEX_op_shl_i32: 2280 case INDEX_op_shr_i32: 2281 case INDEX_op_sar_i32: 2282 case INDEX_op_rotr_i32: 2283 case INDEX_op_rotl_i32: 2284 case INDEX_op_shl_i64: 2285 case INDEX_op_shr_i64: 2286 case INDEX_op_sar_i64: 2287 case INDEX_op_rotr_i64: 2288 case INDEX_op_rotl_i64: 2289 return C_O1_I2(r, r, ri); 2290 case INDEX_op_clz_i32: 2291 case INDEX_op_clz_i64: 2292 return C_O1_I2(r, r, rWZ); 2293 2294 case INDEX_op_deposit_i32: 2295 case INDEX_op_deposit_i64: 2296 return C_O1_I2(r, 0, rZ); 2297 case INDEX_op_brcond_i32: 2298 case INDEX_op_brcond_i64: 2299 return C_O0_I2(rZ, rZ); 2300 case INDEX_op_movcond_i32: 2301 case INDEX_op_movcond_i64: 2302 return (use_mips32r6_instructions 2303 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2304 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2305 case INDEX_op_add2_i32: 2306 case INDEX_op_sub2_i32: 2307 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2308 case INDEX_op_setcond2_i32: 2309 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2310 case INDEX_op_brcond2_i32: 2311 return C_O0_I4(rZ, rZ, rZ, rZ); 2312 2313 case INDEX_op_qemu_ld_a32_i32: 2314 return C_O1_I1(r, r); 2315 case INDEX_op_qemu_ld_a64_i32: 2316 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r); 2317 case INDEX_op_qemu_st_a32_i32: 2318 return C_O0_I2(rZ, r); 2319 case INDEX_op_qemu_st_a64_i32: 2320 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r); 2321 case INDEX_op_qemu_ld_a32_i64: 2322 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2323 case INDEX_op_qemu_ld_a64_i64: 2324 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r); 2325 case INDEX_op_qemu_st_a32_i64: 2326 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r); 2327 case INDEX_op_qemu_st_a64_i64: 2328 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) 2329 : C_O0_I4(rZ, rZ, r, r)); 2330 2331 default: 2332 g_assert_not_reached(); 2333 } 2334} 2335 2336static const int tcg_target_callee_save_regs[] = { 2337 TCG_REG_S0, 2338 TCG_REG_S1, 2339 TCG_REG_S2, 2340 TCG_REG_S3, 2341 TCG_REG_S4, 2342 TCG_REG_S5, 2343 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2344 TCG_REG_S7, /* used for guest_base */ 2345 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2346 TCG_REG_RA, /* should be last for ABI compliance */ 2347}; 2348 2349/* The Linux kernel doesn't provide any information about the available 2350 instruction set. Probe it using a signal handler. */ 2351 2352 2353#ifndef use_movnz_instructions 2354bool use_movnz_instructions = false; 2355#endif 2356 2357#ifndef use_mips32_instructions 2358bool use_mips32_instructions = false; 2359#endif 2360 2361#ifndef use_mips32r2_instructions 2362bool use_mips32r2_instructions = false; 2363#endif 2364 2365static volatile sig_atomic_t got_sigill; 2366 2367static void sigill_handler(int signo, siginfo_t *si, void *data) 2368{ 2369 /* Skip the faulty instruction */ 2370 ucontext_t *uc = (ucontext_t *)data; 2371 uc->uc_mcontext.pc += 4; 2372 2373 got_sigill = 1; 2374} 2375 2376static void tcg_target_detect_isa(void) 2377{ 2378 struct sigaction sa_old, sa_new; 2379 2380 memset(&sa_new, 0, sizeof(sa_new)); 2381 sa_new.sa_flags = SA_SIGINFO; 2382 sa_new.sa_sigaction = sigill_handler; 2383 sigaction(SIGILL, &sa_new, &sa_old); 2384 2385 /* Probe for movn/movz, necessary to implement movcond. */ 2386#ifndef use_movnz_instructions 2387 got_sigill = 0; 2388 asm volatile(".set push\n" 2389 ".set mips32\n" 2390 "movn $zero, $zero, $zero\n" 2391 "movz $zero, $zero, $zero\n" 2392 ".set pop\n" 2393 : : : ); 2394 use_movnz_instructions = !got_sigill; 2395#endif 2396 2397 /* Probe for MIPS32 instructions. As no subsetting is allowed 2398 by the specification, it is only necessary to probe for one 2399 of the instructions. */ 2400#ifndef use_mips32_instructions 2401 got_sigill = 0; 2402 asm volatile(".set push\n" 2403 ".set mips32\n" 2404 "mul $zero, $zero\n" 2405 ".set pop\n" 2406 : : : ); 2407 use_mips32_instructions = !got_sigill; 2408#endif 2409 2410 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2411 available. As no subsetting is allowed by the specification, 2412 it is only necessary to probe for one of the instructions. */ 2413#ifndef use_mips32r2_instructions 2414 if (use_mips32_instructions) { 2415 got_sigill = 0; 2416 asm volatile(".set push\n" 2417 ".set mips32r2\n" 2418 "seb $zero, $zero\n" 2419 ".set pop\n" 2420 : : : ); 2421 use_mips32r2_instructions = !got_sigill; 2422 } 2423#endif 2424 2425 sigaction(SIGILL, &sa_old, NULL); 2426} 2427 2428static tcg_insn_unit *align_code_ptr(TCGContext *s) 2429{ 2430 uintptr_t p = (uintptr_t)s->code_ptr; 2431 if (p & 15) { 2432 p = (p + 15) & -16; 2433 s->code_ptr = (void *)p; 2434 } 2435 return s->code_ptr; 2436} 2437 2438/* Stack frame parameters. */ 2439#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2440#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2441#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2442 2443#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2444 + TCG_TARGET_STACK_ALIGN - 1) \ 2445 & -TCG_TARGET_STACK_ALIGN) 2446#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2447 2448/* We're expecting to be able to use an immediate for frame allocation. */ 2449QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2450 2451/* Generate global QEMU prologue and epilogue code */ 2452static void tcg_target_qemu_prologue(TCGContext *s) 2453{ 2454 int i; 2455 2456 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2457 2458 /* TB prologue */ 2459 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2460 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2461 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2462 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2463 } 2464 2465 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2466 /* 2467 * The function call abi for n32 and n64 will have loaded $25 (t9) 2468 * with the address of the prologue, so we can use that instead 2469 * of TCG_REG_TB. 2470 */ 2471#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2472# error "Unknown mips abi" 2473#endif 2474 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2475 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2476 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2477 } 2478 2479 if (TCG_TARGET_REG_BITS == 64) { 2480 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2481 } 2482 2483 /* Call generated code */ 2484 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2485 /* delay slot */ 2486 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2487 2488 /* 2489 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2490 * and fall through to the rest of the epilogue. 2491 */ 2492 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2493 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2494 2495 /* TB epilogue */ 2496 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2497 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2498 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2499 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2500 } 2501 2502 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2503 /* delay slot */ 2504 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2505 2506 if (use_mips32r2_instructions) { 2507 return; 2508 } 2509 2510 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2511 clobbers TCG_TMP1, TCG_TMP2. */ 2512 2513 /* 2514 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2515 */ 2516 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2517 /* t3 = (ssss)d000 */ 2518 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2519 /* t1 = 000a */ 2520 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2521 /* t2 = 00c0 */ 2522 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2523 /* t3 = d00a */ 2524 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2525 /* t1 = 0abc */ 2526 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2527 /* t2 = 0c00 */ 2528 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2529 /* t1 = 00b0 */ 2530 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2531 /* t3 = dc0a */ 2532 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2533 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2534 /* t3 = dcba -- delay slot */ 2535 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2536 2537 if (TCG_TARGET_REG_BITS == 32) { 2538 return; 2539 } 2540 2541 /* 2542 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2543 */ 2544 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2545 /* t1 = (0000)000d */ 2546 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2547 /* t3 = 000a */ 2548 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2549 /* t1 = (0000)d000 */ 2550 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2551 /* t2 = 00c0 */ 2552 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2553 /* t3 = d00a */ 2554 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2555 /* t1 = 0abc */ 2556 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2557 /* t2 = 0c00 */ 2558 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2559 /* t1 = 00b0 */ 2560 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2561 /* t3 = dc0a */ 2562 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2563 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2564 /* t3 = dcba -- delay slot */ 2565 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2566 2567 /* 2568 * bswap64 -- 64-bit swap. a0 = abcdefgh 2569 */ 2570 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2571 /* t3 = h0000000 */ 2572 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2573 /* t1 = 0000000a */ 2574 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2575 2576 /* t2 = 000000g0 */ 2577 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2578 /* t3 = h000000a */ 2579 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2580 /* t1 = 00000abc */ 2581 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2582 /* t2 = 0g000000 */ 2583 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2584 /* t1 = 000000b0 */ 2585 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2586 2587 /* t3 = hg00000a */ 2588 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2589 /* t2 = 0000abcd */ 2590 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2591 /* t3 = hg0000ba */ 2592 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2593 2594 /* t1 = 000000c0 */ 2595 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2596 /* t2 = 0000000d */ 2597 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2598 /* t1 = 00000c00 */ 2599 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2600 /* t2 = 0000d000 */ 2601 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2602 2603 /* t3 = hg000cba */ 2604 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2605 /* t1 = 00abcdef */ 2606 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2607 /* t3 = hg00dcba */ 2608 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2609 2610 /* t2 = 0000000f */ 2611 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2612 /* t1 = 000000e0 */ 2613 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2614 /* t2 = 00f00000 */ 2615 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2616 /* t1 = 000e0000 */ 2617 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2618 2619 /* t3 = hgf0dcba */ 2620 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2621 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2622 /* t3 = hgfedcba -- delay slot */ 2623 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2624} 2625 2626static void tcg_out_tb_start(TCGContext *s) 2627{ 2628 /* nothing to do */ 2629} 2630 2631static void tcg_target_init(TCGContext *s) 2632{ 2633 tcg_target_detect_isa(); 2634 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2635 if (TCG_TARGET_REG_BITS == 64) { 2636 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2637 } 2638 2639 tcg_target_call_clobber_regs = 0; 2640 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2641 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2642 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2643 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2644 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2645 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2646 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2647 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2648 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2649 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2650 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2651 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2652 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2653 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2654 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2655 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2656 2657 s->reserved_regs = 0; 2658 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2659 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2660 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2661 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2662 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2663 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2664 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2665 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2666 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2667 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2668 if (TCG_TARGET_REG_BITS == 64) { 2669 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2670 } 2671} 2672 2673typedef struct { 2674 DebugFrameHeader h; 2675 uint8_t fde_def_cfa[4]; 2676 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2677} DebugFrame; 2678 2679#define ELF_HOST_MACHINE EM_MIPS 2680/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2681 which is good because they're really quite complicated for MIPS. */ 2682 2683static const DebugFrame debug_frame = { 2684 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2685 .h.cie.id = -1, 2686 .h.cie.version = 1, 2687 .h.cie.code_align = 1, 2688 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2689 .h.cie.return_column = TCG_REG_RA, 2690 2691 /* Total FDE size does not include the "len" member. */ 2692 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2693 2694 .fde_def_cfa = { 2695 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2696 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2697 (FRAME_SIZE >> 7) 2698 }, 2699 .fde_reg_ofs = { 2700 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2701 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2702 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2703 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2704 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2705 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2706 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2707 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2708 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2709 } 2710}; 2711 2712void tcg_register_jit(const void *buf, size_t buf_size) 2713{ 2714 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2715} 2716