1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28 29#if HOST_BIG_ENDIAN 30# define MIPS_BE 1 31#else 32# define MIPS_BE 0 33#endif 34 35#if TCG_TARGET_REG_BITS == 32 36# define LO_OFF (MIPS_BE * 4) 37# define HI_OFF (4 - LO_OFF) 38#else 39/* To assert at compile-time that these values are never used 40 for TCG_TARGET_REG_BITS == 64. */ 41int link_error(void); 42# define LO_OFF link_error() 43# define HI_OFF link_error() 44#endif 45 46#ifdef CONFIG_DEBUG_TCG 47static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 48 "zero", 49 "at", 50 "v0", 51 "v1", 52 "a0", 53 "a1", 54 "a2", 55 "a3", 56 "t0", 57 "t1", 58 "t2", 59 "t3", 60 "t4", 61 "t5", 62 "t6", 63 "t7", 64 "s0", 65 "s1", 66 "s2", 67 "s3", 68 "s4", 69 "s5", 70 "s6", 71 "s7", 72 "t8", 73 "t9", 74 "k0", 75 "k1", 76 "gp", 77 "sp", 78 "s8", 79 "ra", 80}; 81#endif 82 83#define TCG_TMP0 TCG_REG_AT 84#define TCG_TMP1 TCG_REG_T9 85#define TCG_TMP2 TCG_REG_T8 86#define TCG_TMP3 TCG_REG_T7 87 88#ifndef CONFIG_SOFTMMU 89#define TCG_GUEST_BASE_REG TCG_REG_S1 90#endif 91 92/* check if we really need so many registers :P */ 93static const int tcg_target_reg_alloc_order[] = { 94 /* Call saved registers. */ 95 TCG_REG_S0, 96 TCG_REG_S1, 97 TCG_REG_S2, 98 TCG_REG_S3, 99 TCG_REG_S4, 100 TCG_REG_S5, 101 TCG_REG_S6, 102 TCG_REG_S7, 103 TCG_REG_S8, 104 105 /* Call clobbered registers. */ 106 TCG_REG_T4, 107 TCG_REG_T5, 108 TCG_REG_T6, 109 TCG_REG_T7, 110 TCG_REG_T8, 111 TCG_REG_T9, 112 TCG_REG_V1, 113 TCG_REG_V0, 114 115 /* Argument registers, opposite order of allocation. */ 116 TCG_REG_T3, 117 TCG_REG_T2, 118 TCG_REG_T1, 119 TCG_REG_T0, 120 TCG_REG_A3, 121 TCG_REG_A2, 122 TCG_REG_A1, 123 TCG_REG_A0, 124}; 125 126static const TCGReg tcg_target_call_iarg_regs[] = { 127 TCG_REG_A0, 128 TCG_REG_A1, 129 TCG_REG_A2, 130 TCG_REG_A3, 131#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 132 TCG_REG_T0, 133 TCG_REG_T1, 134 TCG_REG_T2, 135 TCG_REG_T3, 136#endif 137}; 138 139static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 140{ 141 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 142 tcg_debug_assert(slot >= 0 && slot <= 1); 143 return TCG_REG_V0 + slot; 144} 145 146static const tcg_insn_unit *tb_ret_addr; 147static const tcg_insn_unit *bswap32_addr; 148static const tcg_insn_unit *bswap32u_addr; 149static const tcg_insn_unit *bswap64_addr; 150 151static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 152{ 153 /* Let the compiler perform the right-shift as part of the arithmetic. */ 154 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 155 ptrdiff_t disp = target - (src_rx + 1); 156 if (disp == (int16_t)disp) { 157 *src_rw = deposit32(*src_rw, 0, 16, disp); 158 return true; 159 } 160 return false; 161} 162 163static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 164 intptr_t value, intptr_t addend) 165{ 166 tcg_debug_assert(type == R_MIPS_PC16); 167 tcg_debug_assert(addend == 0); 168 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 169} 170 171#define TCG_CT_CONST_ZERO 0x100 172#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 173#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 174#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 175#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 176#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 177 178#define ALL_GENERAL_REGS 0xffffffffu 179 180static bool is_p2m1(tcg_target_long val) 181{ 182 return val && ((val + 1) & val) == 0; 183} 184 185/* test if a constant matches the constraint */ 186static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 187{ 188 if (ct & TCG_CT_CONST) { 189 return 1; 190 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 191 return 1; 192 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 193 return 1; 194 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 195 return 1; 196 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 197 return 1; 198 } else if ((ct & TCG_CT_CONST_P2M1) 199 && use_mips32r2_instructions && is_p2m1(val)) { 200 return 1; 201 } else if ((ct & TCG_CT_CONST_WSZ) 202 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 203 return 1; 204 } 205 return 0; 206} 207 208/* instruction opcodes */ 209typedef enum { 210 OPC_J = 002 << 26, 211 OPC_JAL = 003 << 26, 212 OPC_BEQ = 004 << 26, 213 OPC_BNE = 005 << 26, 214 OPC_BLEZ = 006 << 26, 215 OPC_BGTZ = 007 << 26, 216 OPC_ADDIU = 011 << 26, 217 OPC_SLTI = 012 << 26, 218 OPC_SLTIU = 013 << 26, 219 OPC_ANDI = 014 << 26, 220 OPC_ORI = 015 << 26, 221 OPC_XORI = 016 << 26, 222 OPC_LUI = 017 << 26, 223 OPC_BNEL = 025 << 26, 224 OPC_BNEZALC_R6 = 030 << 26, 225 OPC_DADDIU = 031 << 26, 226 OPC_LDL = 032 << 26, 227 OPC_LDR = 033 << 26, 228 OPC_LB = 040 << 26, 229 OPC_LH = 041 << 26, 230 OPC_LWL = 042 << 26, 231 OPC_LW = 043 << 26, 232 OPC_LBU = 044 << 26, 233 OPC_LHU = 045 << 26, 234 OPC_LWR = 046 << 26, 235 OPC_LWU = 047 << 26, 236 OPC_SB = 050 << 26, 237 OPC_SH = 051 << 26, 238 OPC_SWL = 052 << 26, 239 OPC_SW = 053 << 26, 240 OPC_SDL = 054 << 26, 241 OPC_SDR = 055 << 26, 242 OPC_SWR = 056 << 26, 243 OPC_LD = 067 << 26, 244 OPC_SD = 077 << 26, 245 246 OPC_SPECIAL = 000 << 26, 247 OPC_SLL = OPC_SPECIAL | 000, 248 OPC_SRL = OPC_SPECIAL | 002, 249 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 250 OPC_SRA = OPC_SPECIAL | 003, 251 OPC_SLLV = OPC_SPECIAL | 004, 252 OPC_SRLV = OPC_SPECIAL | 006, 253 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 254 OPC_SRAV = OPC_SPECIAL | 007, 255 OPC_JR_R5 = OPC_SPECIAL | 010, 256 OPC_JALR = OPC_SPECIAL | 011, 257 OPC_MOVZ = OPC_SPECIAL | 012, 258 OPC_MOVN = OPC_SPECIAL | 013, 259 OPC_SYNC = OPC_SPECIAL | 017, 260 OPC_MFHI = OPC_SPECIAL | 020, 261 OPC_MFLO = OPC_SPECIAL | 022, 262 OPC_DSLLV = OPC_SPECIAL | 024, 263 OPC_DSRLV = OPC_SPECIAL | 026, 264 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 265 OPC_DSRAV = OPC_SPECIAL | 027, 266 OPC_MULT = OPC_SPECIAL | 030, 267 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 268 OPC_MUH = OPC_SPECIAL | 030 | 0300, 269 OPC_MULTU = OPC_SPECIAL | 031, 270 OPC_MULU = OPC_SPECIAL | 031 | 0200, 271 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 272 OPC_DIV = OPC_SPECIAL | 032, 273 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 274 OPC_MOD = OPC_SPECIAL | 032 | 0300, 275 OPC_DIVU = OPC_SPECIAL | 033, 276 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 277 OPC_MODU = OPC_SPECIAL | 033 | 0300, 278 OPC_DMULT = OPC_SPECIAL | 034, 279 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 280 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 281 OPC_DMULTU = OPC_SPECIAL | 035, 282 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 283 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 284 OPC_DDIV = OPC_SPECIAL | 036, 285 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 286 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 287 OPC_DDIVU = OPC_SPECIAL | 037, 288 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 289 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 290 OPC_ADDU = OPC_SPECIAL | 041, 291 OPC_SUBU = OPC_SPECIAL | 043, 292 OPC_AND = OPC_SPECIAL | 044, 293 OPC_OR = OPC_SPECIAL | 045, 294 OPC_XOR = OPC_SPECIAL | 046, 295 OPC_NOR = OPC_SPECIAL | 047, 296 OPC_SLT = OPC_SPECIAL | 052, 297 OPC_SLTU = OPC_SPECIAL | 053, 298 OPC_DADDU = OPC_SPECIAL | 055, 299 OPC_DSUBU = OPC_SPECIAL | 057, 300 OPC_SELEQZ = OPC_SPECIAL | 065, 301 OPC_SELNEZ = OPC_SPECIAL | 067, 302 OPC_DSLL = OPC_SPECIAL | 070, 303 OPC_DSRL = OPC_SPECIAL | 072, 304 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 305 OPC_DSRA = OPC_SPECIAL | 073, 306 OPC_DSLL32 = OPC_SPECIAL | 074, 307 OPC_DSRL32 = OPC_SPECIAL | 076, 308 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 309 OPC_DSRA32 = OPC_SPECIAL | 077, 310 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 311 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 312 313 OPC_REGIMM = 001 << 26, 314 OPC_BLTZ = OPC_REGIMM | (000 << 16), 315 OPC_BGEZ = OPC_REGIMM | (001 << 16), 316 317 OPC_SPECIAL2 = 034 << 26, 318 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 319 OPC_CLZ = OPC_SPECIAL2 | 040, 320 OPC_DCLZ = OPC_SPECIAL2 | 044, 321 322 OPC_SPECIAL3 = 037 << 26, 323 OPC_EXT = OPC_SPECIAL3 | 000, 324 OPC_DEXTM = OPC_SPECIAL3 | 001, 325 OPC_DEXTU = OPC_SPECIAL3 | 002, 326 OPC_DEXT = OPC_SPECIAL3 | 003, 327 OPC_INS = OPC_SPECIAL3 | 004, 328 OPC_DINSM = OPC_SPECIAL3 | 005, 329 OPC_DINSU = OPC_SPECIAL3 | 006, 330 OPC_DINS = OPC_SPECIAL3 | 007, 331 OPC_WSBH = OPC_SPECIAL3 | 00240, 332 OPC_DSBH = OPC_SPECIAL3 | 00244, 333 OPC_DSHD = OPC_SPECIAL3 | 00544, 334 OPC_SEB = OPC_SPECIAL3 | 02040, 335 OPC_SEH = OPC_SPECIAL3 | 03040, 336 337 /* MIPS r6 doesn't have JR, JALR should be used instead */ 338 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 339 340 /* 341 * MIPS r6 replaces MUL with an alternative encoding which is 342 * backwards-compatible at the assembly level. 343 */ 344 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 345 346 /* MIPS r6 introduced names for weaker variants of SYNC. These are 347 backward compatible to previous architecture revisions. */ 348 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 349 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 350 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 351 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 352 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 353 354 /* Aliases for convenience. */ 355 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 356 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 357 ALIAS_TSRL = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 358 ? OPC_SRL : OPC_DSRL, 359 ALIAS_TADDI = TARGET_LONG_BITS == 32 || TCG_TARGET_REG_BITS == 32 360 ? OPC_ADDIU : OPC_DADDIU, 361} MIPSInsn; 362 363/* 364 * Type reg 365 */ 366static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 367 TCGReg rd, TCGReg rs, TCGReg rt) 368{ 369 int32_t inst; 370 371 inst = opc; 372 inst |= (rs & 0x1F) << 21; 373 inst |= (rt & 0x1F) << 16; 374 inst |= (rd & 0x1F) << 11; 375 tcg_out32(s, inst); 376} 377 378/* 379 * Type immediate 380 */ 381static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 382 TCGReg rt, TCGReg rs, TCGArg imm) 383{ 384 int32_t inst; 385 386 inst = opc; 387 inst |= (rs & 0x1F) << 21; 388 inst |= (rt & 0x1F) << 16; 389 inst |= (imm & 0xffff); 390 tcg_out32(s, inst); 391} 392 393/* 394 * Type bitfield 395 */ 396static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 397 TCGReg rs, int msb, int lsb) 398{ 399 int32_t inst; 400 401 inst = opc; 402 inst |= (rs & 0x1F) << 21; 403 inst |= (rt & 0x1F) << 16; 404 inst |= (msb & 0x1F) << 11; 405 inst |= (lsb & 0x1F) << 6; 406 tcg_out32(s, inst); 407} 408 409static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 410 MIPSInsn oph, TCGReg rt, TCGReg rs, 411 int msb, int lsb) 412{ 413 if (lsb >= 32) { 414 opc = oph; 415 msb -= 32; 416 lsb -= 32; 417 } else if (msb >= 32) { 418 opc = opm; 419 msb -= 32; 420 } 421 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 422} 423 424/* 425 * Type branch 426 */ 427static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 428{ 429 tcg_out_opc_imm(s, opc, rt, rs, 0); 430} 431 432/* 433 * Type sa 434 */ 435static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 436 TCGReg rd, TCGReg rt, TCGArg sa) 437{ 438 int32_t inst; 439 440 inst = opc; 441 inst |= (rt & 0x1F) << 16; 442 inst |= (rd & 0x1F) << 11; 443 inst |= (sa & 0x1F) << 6; 444 tcg_out32(s, inst); 445 446} 447 448static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 449 TCGReg rd, TCGReg rt, TCGArg sa) 450{ 451 int32_t inst; 452 453 inst = (sa & 32 ? opc2 : opc1); 454 inst |= (rt & 0x1F) << 16; 455 inst |= (rd & 0x1F) << 11; 456 inst |= (sa & 0x1F) << 6; 457 tcg_out32(s, inst); 458} 459 460/* 461 * Type jump. 462 * Returns true if the branch was in range and the insn was emitted. 463 */ 464static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 465{ 466 uintptr_t dest = (uintptr_t)target; 467 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 468 int32_t inst; 469 470 /* The pc-region branch happens within the 256MB region of 471 the delay slot (thus the +4). */ 472 if ((from ^ dest) & -(1 << 28)) { 473 return false; 474 } 475 tcg_debug_assert((dest & 3) == 0); 476 477 inst = opc; 478 inst |= (dest >> 2) & 0x3ffffff; 479 tcg_out32(s, inst); 480 return true; 481} 482 483static void tcg_out_nop(TCGContext *s) 484{ 485 tcg_out32(s, 0); 486} 487 488static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 489{ 490 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 491} 492 493static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 494{ 495 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 496} 497 498static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 499{ 500 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 501} 502 503static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 504{ 505 /* Simple reg-reg move, optimising out the 'do nothing' case */ 506 if (ret != arg) { 507 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 508 } 509 return true; 510} 511 512static void tcg_out_movi(TCGContext *s, TCGType type, 513 TCGReg ret, tcg_target_long arg) 514{ 515 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 516 arg = (int32_t)arg; 517 } 518 if (arg == (int16_t)arg) { 519 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 520 return; 521 } 522 if (arg == (uint16_t)arg) { 523 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 524 return; 525 } 526 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 527 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 528 } else { 529 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 530 if (arg & 0xffff0000ull) { 531 tcg_out_dsll(s, ret, ret, 16); 532 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 533 tcg_out_dsll(s, ret, ret, 16); 534 } else { 535 tcg_out_dsll(s, ret, ret, 32); 536 } 537 } 538 if (arg & 0xffff) { 539 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 540 } 541} 542 543static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 544{ 545 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); 546 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 547} 548 549static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 550{ 551 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 552} 553 554static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 555{ 556 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); 557 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 558} 559 560static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 561{ 562 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 563} 564 565static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 566{ 567 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 568 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 569} 570 571static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 572{ 573 if (rd != rs) { 574 tcg_out_ext32s(s, rd, rs); 575 } 576} 577 578static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 579{ 580 tcg_out_ext32u(s, rd, rs); 581} 582 583static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 584{ 585 tcg_out_ext32s(s, rd, rs); 586} 587 588static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 589{ 590 return false; 591} 592 593static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 594 tcg_target_long imm) 595{ 596 /* This function is only used for passing structs by reference. */ 597 g_assert_not_reached(); 598} 599 600static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 601{ 602 /* ret and arg can't be register tmp0 */ 603 tcg_debug_assert(ret != TCG_TMP0); 604 tcg_debug_assert(arg != TCG_TMP0); 605 606 /* With arg = abcd: */ 607 if (use_mips32r2_instructions) { 608 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 609 if (flags & TCG_BSWAP_OS) { 610 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 611 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 612 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 613 } 614 return; 615 } 616 617 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 618 if (!(flags & TCG_BSWAP_IZ)) { 619 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 620 } 621 if (flags & TCG_BSWAP_OS) { 622 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 623 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 624 } else { 625 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 626 if (flags & TCG_BSWAP_OZ) { 627 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 628 } 629 } 630 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 631} 632 633static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 634{ 635 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 636 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 637 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 638 } 639} 640 641static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 642{ 643 if (use_mips32r2_instructions) { 644 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 645 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 646 if (flags & TCG_BSWAP_OZ) { 647 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 648 } 649 } else { 650 if (flags & TCG_BSWAP_OZ) { 651 tcg_out_bswap_subr(s, bswap32u_addr); 652 } else { 653 tcg_out_bswap_subr(s, bswap32_addr); 654 } 655 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 656 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 657 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 658 } 659} 660 661static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 662{ 663 if (use_mips32r2_instructions) { 664 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 665 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 666 } else { 667 tcg_out_bswap_subr(s, bswap64_addr); 668 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 669 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 670 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 671 } 672} 673 674static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 675{ 676 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 677 if (use_mips32r2_instructions) { 678 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 679 } else { 680 tcg_out_dsll(s, ret, arg, 32); 681 tcg_out_dsrl(s, ret, ret, 32); 682 } 683} 684 685static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 686 TCGReg addr, intptr_t ofs) 687{ 688 int16_t lo = ofs; 689 if (ofs != lo) { 690 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 691 if (addr != TCG_REG_ZERO) { 692 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 693 } 694 addr = TCG_TMP0; 695 } 696 tcg_out_opc_imm(s, opc, data, addr, lo); 697} 698 699static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 700 TCGReg arg1, intptr_t arg2) 701{ 702 MIPSInsn opc = OPC_LD; 703 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 704 opc = OPC_LW; 705 } 706 tcg_out_ldst(s, opc, arg, arg1, arg2); 707} 708 709static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 710 TCGReg arg1, intptr_t arg2) 711{ 712 MIPSInsn opc = OPC_SD; 713 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 714 opc = OPC_SW; 715 } 716 tcg_out_ldst(s, opc, arg, arg1, arg2); 717} 718 719static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 720 TCGReg base, intptr_t ofs) 721{ 722 if (val == 0) { 723 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 724 return true; 725 } 726 return false; 727} 728 729static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 730 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 731 bool cbh, bool is_sub) 732{ 733 TCGReg th = TCG_TMP1; 734 735 /* If we have a negative constant such that negating it would 736 make the high part zero, we can (usually) eliminate one insn. */ 737 if (cbl && cbh && bh == -1 && bl != 0) { 738 bl = -bl; 739 bh = 0; 740 is_sub = !is_sub; 741 } 742 743 /* By operating on the high part first, we get to use the final 744 carry operation to move back from the temporary. */ 745 if (!cbh) { 746 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 747 } else if (bh != 0 || ah == rl) { 748 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 749 } else { 750 th = ah; 751 } 752 753 /* Note that tcg optimization should eliminate the bl == 0 case. */ 754 if (is_sub) { 755 if (cbl) { 756 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 757 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 758 } else { 759 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 760 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 761 } 762 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 763 } else { 764 if (cbl) { 765 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 766 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 767 } else if (rl == al && rl == bl) { 768 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 769 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 770 } else { 771 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 772 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 773 } 774 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 775 } 776} 777 778/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 779#define MIPS_CMP_INV 1 780#define MIPS_CMP_SWAP 2 781 782static const uint8_t mips_cmp_map[16] = { 783 [TCG_COND_LT] = 0, 784 [TCG_COND_LTU] = 0, 785 [TCG_COND_GE] = MIPS_CMP_INV, 786 [TCG_COND_GEU] = MIPS_CMP_INV, 787 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 788 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 789 [TCG_COND_GT] = MIPS_CMP_SWAP, 790 [TCG_COND_GTU] = MIPS_CMP_SWAP, 791}; 792 793static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 794 TCGReg arg1, TCGReg arg2) 795{ 796 MIPSInsn s_opc = OPC_SLTU; 797 int cmp_map; 798 799 switch (cond) { 800 case TCG_COND_EQ: 801 if (arg2 != 0) { 802 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 803 arg1 = ret; 804 } 805 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 806 break; 807 808 case TCG_COND_NE: 809 if (arg2 != 0) { 810 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 811 arg1 = ret; 812 } 813 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 814 break; 815 816 case TCG_COND_LT: 817 case TCG_COND_GE: 818 case TCG_COND_LE: 819 case TCG_COND_GT: 820 s_opc = OPC_SLT; 821 /* FALLTHRU */ 822 823 case TCG_COND_LTU: 824 case TCG_COND_GEU: 825 case TCG_COND_LEU: 826 case TCG_COND_GTU: 827 cmp_map = mips_cmp_map[cond]; 828 if (cmp_map & MIPS_CMP_SWAP) { 829 TCGReg t = arg1; 830 arg1 = arg2; 831 arg2 = t; 832 } 833 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 834 if (cmp_map & MIPS_CMP_INV) { 835 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 836 } 837 break; 838 839 default: 840 g_assert_not_reached(); 841 break; 842 } 843} 844 845static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 846 TCGReg arg2, TCGLabel *l) 847{ 848 static const MIPSInsn b_zero[16] = { 849 [TCG_COND_LT] = OPC_BLTZ, 850 [TCG_COND_GT] = OPC_BGTZ, 851 [TCG_COND_LE] = OPC_BLEZ, 852 [TCG_COND_GE] = OPC_BGEZ, 853 }; 854 855 MIPSInsn s_opc = OPC_SLTU; 856 MIPSInsn b_opc; 857 int cmp_map; 858 859 switch (cond) { 860 case TCG_COND_EQ: 861 b_opc = OPC_BEQ; 862 break; 863 case TCG_COND_NE: 864 b_opc = OPC_BNE; 865 break; 866 867 case TCG_COND_LT: 868 case TCG_COND_GT: 869 case TCG_COND_LE: 870 case TCG_COND_GE: 871 if (arg2 == 0) { 872 b_opc = b_zero[cond]; 873 arg2 = arg1; 874 arg1 = 0; 875 break; 876 } 877 s_opc = OPC_SLT; 878 /* FALLTHRU */ 879 880 case TCG_COND_LTU: 881 case TCG_COND_GTU: 882 case TCG_COND_LEU: 883 case TCG_COND_GEU: 884 cmp_map = mips_cmp_map[cond]; 885 if (cmp_map & MIPS_CMP_SWAP) { 886 TCGReg t = arg1; 887 arg1 = arg2; 888 arg2 = t; 889 } 890 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 891 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 892 arg1 = TCG_TMP0; 893 arg2 = TCG_REG_ZERO; 894 break; 895 896 default: 897 g_assert_not_reached(); 898 break; 899 } 900 901 tcg_out_opc_br(s, b_opc, arg1, arg2); 902 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 903 tcg_out_nop(s); 904} 905 906static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 907 TCGReg al, TCGReg ah, 908 TCGReg bl, TCGReg bh) 909{ 910 /* Merge highpart comparison into AH. */ 911 if (bh != 0) { 912 if (ah != 0) { 913 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 914 ah = tmp0; 915 } else { 916 ah = bh; 917 } 918 } 919 /* Merge lowpart comparison into AL. */ 920 if (bl != 0) { 921 if (al != 0) { 922 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 923 al = tmp1; 924 } else { 925 al = bl; 926 } 927 } 928 /* Merge high and low part comparisons into AL. */ 929 if (ah != 0) { 930 if (al != 0) { 931 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 932 al = tmp0; 933 } else { 934 al = ah; 935 } 936 } 937 return al; 938} 939 940static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 941 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 942{ 943 TCGReg tmp0 = TCG_TMP0; 944 TCGReg tmp1 = ret; 945 946 tcg_debug_assert(ret != TCG_TMP0); 947 if (ret == ah || ret == bh) { 948 tcg_debug_assert(ret != TCG_TMP1); 949 tmp1 = TCG_TMP1; 950 } 951 952 switch (cond) { 953 case TCG_COND_EQ: 954 case TCG_COND_NE: 955 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 956 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 957 break; 958 959 default: 960 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 961 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 962 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 963 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 964 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 965 break; 966 } 967} 968 969static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 970 TCGReg bl, TCGReg bh, TCGLabel *l) 971{ 972 TCGCond b_cond = TCG_COND_NE; 973 TCGReg tmp = TCG_TMP1; 974 975 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 976 With setcond, we emit between 3 and 10 insns and only 1 branch, 977 which ought to get better branch prediction. */ 978 switch (cond) { 979 case TCG_COND_EQ: 980 case TCG_COND_NE: 981 b_cond = cond; 982 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 983 break; 984 985 default: 986 /* Minimize code size by preferring a compare not requiring INV. */ 987 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 988 cond = tcg_invert_cond(cond); 989 b_cond = TCG_COND_EQ; 990 } 991 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 992 break; 993 } 994 995 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 996} 997 998static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 999 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 1000{ 1001 bool eqz = false; 1002 1003 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1004 if (use_mips32r6_instructions && v1 == 0) { 1005 v1 = v2; 1006 v2 = 0; 1007 cond = tcg_invert_cond(cond); 1008 } 1009 1010 switch (cond) { 1011 case TCG_COND_EQ: 1012 eqz = true; 1013 /* FALLTHRU */ 1014 case TCG_COND_NE: 1015 if (c2 != 0) { 1016 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 1017 c1 = TCG_TMP0; 1018 } 1019 break; 1020 1021 default: 1022 /* Minimize code size by preferring a compare not requiring INV. */ 1023 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1024 cond = tcg_invert_cond(cond); 1025 eqz = true; 1026 } 1027 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 1028 c1 = TCG_TMP0; 1029 break; 1030 } 1031 1032 if (use_mips32r6_instructions) { 1033 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1034 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1035 1036 if (v2 != 0) { 1037 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1038 } 1039 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1040 if (v2 != 0) { 1041 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1042 } 1043 } else { 1044 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1045 1046 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1047 1048 /* This should be guaranteed via constraints */ 1049 tcg_debug_assert(v2 == ret); 1050 } 1051} 1052 1053static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1054{ 1055 /* Note that the ABI requires the called function's address to be 1056 loaded into T9, even if a direct branch is in range. */ 1057 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1058 1059 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1060 if (tail) { 1061 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1062 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1063 } 1064 } else { 1065 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1066 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1067 } 1068 } 1069} 1070 1071static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1072 const TCGHelperInfo *info) 1073{ 1074 tcg_out_call_int(s, arg, false); 1075 tcg_out_nop(s); 1076} 1077 1078/* We have four temps, we might as well expose three of them. */ 1079static const TCGLdstHelperParam ldst_helper_param = { 1080 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1081}; 1082 1083static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1084{ 1085 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1086 MemOp opc = get_memop(l->oi); 1087 1088 /* resolve label address */ 1089 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1090 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1091 return false; 1092 } 1093 1094 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1095 1096 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1097 /* delay slot */ 1098 tcg_out_nop(s); 1099 1100 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1101 1102 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1103 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1104 return false; 1105 } 1106 1107 /* delay slot */ 1108 tcg_out_nop(s); 1109 return true; 1110} 1111 1112static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1113{ 1114 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1115 MemOp opc = get_memop(l->oi); 1116 1117 /* resolve label address */ 1118 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1119 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1120 return false; 1121 } 1122 1123 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1124 1125 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1126 /* delay slot */ 1127 tcg_out_nop(s); 1128 1129 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1130 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1131 return false; 1132 } 1133 1134 /* delay slot */ 1135 tcg_out_nop(s); 1136 return true; 1137} 1138 1139typedef struct { 1140 TCGReg base; 1141 MemOp align; 1142} HostAddress; 1143 1144bool tcg_target_has_memory_bswap(MemOp memop) 1145{ 1146 return false; 1147} 1148 1149/* 1150 * For softmmu, perform the TLB load and compare. 1151 * For useronly, perform any required alignment tests. 1152 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1153 * is required and fill in @h with the host address for the fast path. 1154 */ 1155static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1156 TCGReg addrlo, TCGReg addrhi, 1157 MemOpIdx oi, bool is_ld) 1158{ 1159 TCGLabelQemuLdst *ldst = NULL; 1160 MemOp opc = get_memop(oi); 1161 unsigned a_bits = get_alignment_bits(opc); 1162 unsigned s_bits = opc & MO_SIZE; 1163 unsigned a_mask = (1 << a_bits) - 1; 1164 TCGReg base; 1165 1166#ifdef CONFIG_SOFTMMU 1167 unsigned s_mask = (1 << s_bits) - 1; 1168 int mem_index = get_mmuidx(oi); 1169 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1170 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1171 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1172 int add_off = offsetof(CPUTLBEntry, addend); 1173 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1174 : offsetof(CPUTLBEntry, addr_write); 1175 1176 ldst = new_ldst_label(s); 1177 ldst->is_ld = is_ld; 1178 ldst->oi = oi; 1179 ldst->addrlo_reg = addrlo; 1180 ldst->addrhi_reg = addrhi; 1181 1182 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1183 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1184 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1185 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1186 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1187 1188 /* Extract the TLB index from the address into TMP3. */ 1189 tcg_out_opc_sa(s, ALIAS_TSRL, TCG_TMP3, addrlo, 1190 TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); 1191 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1192 1193 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1194 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1195 1196 /* Load the (low-half) tlb comparator. */ 1197 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1198 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1199 } else { 1200 tcg_out_ld(s, TCG_TYPE_TL, TCG_TMP0, TCG_TMP3, cmp_off); 1201 } 1202 1203 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 1204 /* Load the tlb addend for the fast path. */ 1205 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1206 } 1207 1208 /* 1209 * Mask the page bits, keeping the alignment bits to compare against. 1210 * For unaligned accesses, compare against the end of the access to 1211 * verify that it does not cross a page boundary. 1212 */ 1213 tcg_out_movi(s, TCG_TYPE_TL, TCG_TMP1, TARGET_PAGE_MASK | a_mask); 1214 if (a_mask < s_mask) { 1215 tcg_out_opc_imm(s, ALIAS_TADDI, TCG_TMP2, addrlo, s_mask - a_mask); 1216 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1217 } else { 1218 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); 1219 } 1220 1221 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1222 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1223 tcg_out_ext32u(s, TCG_TMP2, addrlo); 1224 addrlo = TCG_TMP2; 1225 } 1226 1227 ldst->label_ptr[0] = s->code_ptr; 1228 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1229 1230 /* Load and test the high half tlb comparator. */ 1231 if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { 1232 /* delay slot */ 1233 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1234 1235 /* Load the tlb addend for the fast path. */ 1236 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1237 1238 ldst->label_ptr[1] = s->code_ptr; 1239 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); 1240 } 1241 1242 /* delay slot */ 1243 base = TCG_TMP3; 1244 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); 1245#else 1246 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1247 ldst = new_ldst_label(s); 1248 1249 ldst->is_ld = is_ld; 1250 ldst->oi = oi; 1251 ldst->addrlo_reg = addrlo; 1252 ldst->addrhi_reg = addrhi; 1253 1254 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1255 tcg_debug_assert(a_bits < 16); 1256 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); 1257 1258 ldst->label_ptr[0] = s->code_ptr; 1259 if (use_mips32r6_instructions) { 1260 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1261 } else { 1262 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1263 tcg_out_nop(s); 1264 } 1265 } 1266 1267 base = addrlo; 1268 if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { 1269 tcg_out_ext32u(s, TCG_REG_A0, base); 1270 base = TCG_REG_A0; 1271 } 1272 if (guest_base) { 1273 if (guest_base == (int16_t)guest_base) { 1274 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1275 } else { 1276 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1277 TCG_GUEST_BASE_REG); 1278 } 1279 base = TCG_REG_A0; 1280 } 1281#endif 1282 1283 h->base = base; 1284 h->align = a_bits; 1285 return ldst; 1286} 1287 1288static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1289 TCGReg base, MemOp opc, TCGType type) 1290{ 1291 switch (opc & MO_SSIZE) { 1292 case MO_UB: 1293 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1294 break; 1295 case MO_SB: 1296 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1297 break; 1298 case MO_UW: 1299 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1300 break; 1301 case MO_SW: 1302 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1303 break; 1304 case MO_UL: 1305 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1306 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1307 break; 1308 } 1309 /* FALLTHRU */ 1310 case MO_SL: 1311 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1312 break; 1313 case MO_UQ: 1314 /* Prefer to load from offset 0 first, but allow for overlap. */ 1315 if (TCG_TARGET_REG_BITS == 64) { 1316 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1317 } else if (MIPS_BE ? hi != base : lo == base) { 1318 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1319 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1320 } else { 1321 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1322 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1323 } 1324 break; 1325 default: 1326 g_assert_not_reached(); 1327 } 1328} 1329 1330static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1331 TCGReg base, MemOp opc, TCGType type) 1332{ 1333 const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR; 1334 const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL; 1335 const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR; 1336 const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL; 1337 bool sgn = opc & MO_SIGN; 1338 1339 switch (opc & MO_SIZE) { 1340 case MO_16: 1341 if (HOST_BIG_ENDIAN) { 1342 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1343 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1344 if (use_mips32r2_instructions) { 1345 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1346 } else { 1347 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1348 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1349 } 1350 } else if (use_mips32r2_instructions && lo != base) { 1351 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1352 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1353 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1354 } else { 1355 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1356 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1357 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1358 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1359 } 1360 break; 1361 1362 case MO_32: 1363 tcg_out_opc_imm(s, lw1, lo, base, 0); 1364 tcg_out_opc_imm(s, lw2, lo, base, 3); 1365 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1366 tcg_out_ext32u(s, lo, lo); 1367 } 1368 break; 1369 1370 case MO_64: 1371 if (TCG_TARGET_REG_BITS == 64) { 1372 tcg_out_opc_imm(s, ld1, lo, base, 0); 1373 tcg_out_opc_imm(s, ld2, lo, base, 7); 1374 } else { 1375 tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0); 1376 tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3); 1377 tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0); 1378 tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3); 1379 } 1380 break; 1381 1382 default: 1383 g_assert_not_reached(); 1384 } 1385} 1386 1387static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1388 TCGReg addrlo, TCGReg addrhi, 1389 MemOpIdx oi, TCGType data_type) 1390{ 1391 MemOp opc = get_memop(oi); 1392 TCGLabelQemuLdst *ldst; 1393 HostAddress h; 1394 1395 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 1396 1397 if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) { 1398 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1399 } else { 1400 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1401 } 1402 1403 if (ldst) { 1404 ldst->type = data_type; 1405 ldst->datalo_reg = datalo; 1406 ldst->datahi_reg = datahi; 1407 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1408 } 1409} 1410 1411static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1412 TCGReg base, MemOp opc) 1413{ 1414 switch (opc & MO_SIZE) { 1415 case MO_8: 1416 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1417 break; 1418 case MO_16: 1419 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1420 break; 1421 case MO_32: 1422 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1423 break; 1424 case MO_64: 1425 if (TCG_TARGET_REG_BITS == 64) { 1426 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1427 } else { 1428 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1429 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1430 } 1431 break; 1432 default: 1433 g_assert_not_reached(); 1434 } 1435} 1436 1437static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1438 TCGReg base, MemOp opc) 1439{ 1440 const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR; 1441 const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL; 1442 const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR; 1443 const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL; 1444 1445 switch (opc & MO_SIZE) { 1446 case MO_16: 1447 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1448 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1449 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1450 break; 1451 1452 case MO_32: 1453 tcg_out_opc_imm(s, sw1, lo, base, 0); 1454 tcg_out_opc_imm(s, sw2, lo, base, 3); 1455 break; 1456 1457 case MO_64: 1458 if (TCG_TARGET_REG_BITS == 64) { 1459 tcg_out_opc_imm(s, sd1, lo, base, 0); 1460 tcg_out_opc_imm(s, sd2, lo, base, 7); 1461 } else { 1462 tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0); 1463 tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3); 1464 tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0); 1465 tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3); 1466 } 1467 break; 1468 1469 default: 1470 g_assert_not_reached(); 1471 } 1472} 1473 1474static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1475 TCGReg addrlo, TCGReg addrhi, 1476 MemOpIdx oi, TCGType data_type) 1477{ 1478 MemOp opc = get_memop(oi); 1479 TCGLabelQemuLdst *ldst; 1480 HostAddress h; 1481 1482 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 1483 1484 if (use_mips32r6_instructions || h.align >= (opc & MO_SIZE)) { 1485 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1486 } else { 1487 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1488 } 1489 1490 if (ldst) { 1491 ldst->type = data_type; 1492 ldst->datalo_reg = datalo; 1493 ldst->datahi_reg = datahi; 1494 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1495 } 1496} 1497 1498static void tcg_out_mb(TCGContext *s, TCGArg a0) 1499{ 1500 static const MIPSInsn sync[] = { 1501 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1502 as the former is an ordering barrier and the latter 1503 is a completion barrier. */ 1504 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1505 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1506 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1507 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1508 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1509 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1510 }; 1511 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1512} 1513 1514static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1515 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1516{ 1517 if (use_mips32r6_instructions) { 1518 if (a2 == width) { 1519 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1520 } else { 1521 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1522 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1523 } 1524 } else { 1525 if (a2 == width) { 1526 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1527 } else if (a0 == a2) { 1528 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1529 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1530 } else if (a0 != a1) { 1531 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1532 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1533 } else { 1534 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1535 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1536 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1537 } 1538 } 1539} 1540 1541static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1542{ 1543 TCGReg b0 = TCG_REG_ZERO; 1544 1545 if (a0 & ~0xffff) { 1546 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 1547 b0 = TCG_REG_V0; 1548 } 1549 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1550 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1551 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1552 } 1553 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 1554} 1555 1556static void tcg_out_goto_tb(TCGContext *s, int which) 1557{ 1558 /* indirect jump method */ 1559 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 1560 get_jmp_target_addr(s, which)); 1561 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1562 tcg_out_nop(s); 1563 set_jmp_reset_offset(s, which); 1564} 1565 1566void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1567 uintptr_t jmp_rx, uintptr_t jmp_rw) 1568{ 1569 /* Always indirect, nothing to do */ 1570} 1571 1572static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1573 const TCGArg args[TCG_MAX_OP_ARGS], 1574 const int const_args[TCG_MAX_OP_ARGS]) 1575{ 1576 MIPSInsn i1, i2; 1577 TCGArg a0, a1, a2; 1578 int c2; 1579 1580 /* 1581 * Note that many operands use the constraint set "rZ". 1582 * We make use of the fact that 0 is the ZERO register, 1583 * and hence such cases need not check for const_args. 1584 */ 1585 a0 = args[0]; 1586 a1 = args[1]; 1587 a2 = args[2]; 1588 c2 = const_args[2]; 1589 1590 switch (opc) { 1591 case INDEX_op_goto_ptr: 1592 /* jmp to the given host address (could be epilogue) */ 1593 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1594 tcg_out_nop(s); 1595 break; 1596 case INDEX_op_br: 1597 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1598 arg_label(a0)); 1599 break; 1600 1601 case INDEX_op_ld8u_i32: 1602 case INDEX_op_ld8u_i64: 1603 i1 = OPC_LBU; 1604 goto do_ldst; 1605 case INDEX_op_ld8s_i32: 1606 case INDEX_op_ld8s_i64: 1607 i1 = OPC_LB; 1608 goto do_ldst; 1609 case INDEX_op_ld16u_i32: 1610 case INDEX_op_ld16u_i64: 1611 i1 = OPC_LHU; 1612 goto do_ldst; 1613 case INDEX_op_ld16s_i32: 1614 case INDEX_op_ld16s_i64: 1615 i1 = OPC_LH; 1616 goto do_ldst; 1617 case INDEX_op_ld_i32: 1618 case INDEX_op_ld32s_i64: 1619 i1 = OPC_LW; 1620 goto do_ldst; 1621 case INDEX_op_ld32u_i64: 1622 i1 = OPC_LWU; 1623 goto do_ldst; 1624 case INDEX_op_ld_i64: 1625 i1 = OPC_LD; 1626 goto do_ldst; 1627 case INDEX_op_st8_i32: 1628 case INDEX_op_st8_i64: 1629 i1 = OPC_SB; 1630 goto do_ldst; 1631 case INDEX_op_st16_i32: 1632 case INDEX_op_st16_i64: 1633 i1 = OPC_SH; 1634 goto do_ldst; 1635 case INDEX_op_st_i32: 1636 case INDEX_op_st32_i64: 1637 i1 = OPC_SW; 1638 goto do_ldst; 1639 case INDEX_op_st_i64: 1640 i1 = OPC_SD; 1641 do_ldst: 1642 tcg_out_ldst(s, i1, a0, a1, a2); 1643 break; 1644 1645 case INDEX_op_add_i32: 1646 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1647 goto do_binary; 1648 case INDEX_op_add_i64: 1649 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1650 goto do_binary; 1651 case INDEX_op_or_i32: 1652 case INDEX_op_or_i64: 1653 i1 = OPC_OR, i2 = OPC_ORI; 1654 goto do_binary; 1655 case INDEX_op_xor_i32: 1656 case INDEX_op_xor_i64: 1657 i1 = OPC_XOR, i2 = OPC_XORI; 1658 do_binary: 1659 if (c2) { 1660 tcg_out_opc_imm(s, i2, a0, a1, a2); 1661 break; 1662 } 1663 do_binaryv: 1664 tcg_out_opc_reg(s, i1, a0, a1, a2); 1665 break; 1666 1667 case INDEX_op_sub_i32: 1668 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1669 goto do_subtract; 1670 case INDEX_op_sub_i64: 1671 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1672 do_subtract: 1673 if (c2) { 1674 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1675 break; 1676 } 1677 goto do_binaryv; 1678 case INDEX_op_and_i32: 1679 if (c2 && a2 != (uint16_t)a2) { 1680 int msb = ctz32(~a2) - 1; 1681 tcg_debug_assert(use_mips32r2_instructions); 1682 tcg_debug_assert(is_p2m1(a2)); 1683 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1684 break; 1685 } 1686 i1 = OPC_AND, i2 = OPC_ANDI; 1687 goto do_binary; 1688 case INDEX_op_and_i64: 1689 if (c2 && a2 != (uint16_t)a2) { 1690 int msb = ctz64(~a2) - 1; 1691 tcg_debug_assert(use_mips32r2_instructions); 1692 tcg_debug_assert(is_p2m1(a2)); 1693 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1694 break; 1695 } 1696 i1 = OPC_AND, i2 = OPC_ANDI; 1697 goto do_binary; 1698 case INDEX_op_nor_i32: 1699 case INDEX_op_nor_i64: 1700 i1 = OPC_NOR; 1701 goto do_binaryv; 1702 1703 case INDEX_op_mul_i32: 1704 if (use_mips32_instructions) { 1705 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1706 break; 1707 } 1708 i1 = OPC_MULT, i2 = OPC_MFLO; 1709 goto do_hilo1; 1710 case INDEX_op_mulsh_i32: 1711 if (use_mips32r6_instructions) { 1712 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1713 break; 1714 } 1715 i1 = OPC_MULT, i2 = OPC_MFHI; 1716 goto do_hilo1; 1717 case INDEX_op_muluh_i32: 1718 if (use_mips32r6_instructions) { 1719 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1720 break; 1721 } 1722 i1 = OPC_MULTU, i2 = OPC_MFHI; 1723 goto do_hilo1; 1724 case INDEX_op_div_i32: 1725 if (use_mips32r6_instructions) { 1726 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1727 break; 1728 } 1729 i1 = OPC_DIV, i2 = OPC_MFLO; 1730 goto do_hilo1; 1731 case INDEX_op_divu_i32: 1732 if (use_mips32r6_instructions) { 1733 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1734 break; 1735 } 1736 i1 = OPC_DIVU, i2 = OPC_MFLO; 1737 goto do_hilo1; 1738 case INDEX_op_rem_i32: 1739 if (use_mips32r6_instructions) { 1740 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1741 break; 1742 } 1743 i1 = OPC_DIV, i2 = OPC_MFHI; 1744 goto do_hilo1; 1745 case INDEX_op_remu_i32: 1746 if (use_mips32r6_instructions) { 1747 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1748 break; 1749 } 1750 i1 = OPC_DIVU, i2 = OPC_MFHI; 1751 goto do_hilo1; 1752 case INDEX_op_mul_i64: 1753 if (use_mips32r6_instructions) { 1754 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1755 break; 1756 } 1757 i1 = OPC_DMULT, i2 = OPC_MFLO; 1758 goto do_hilo1; 1759 case INDEX_op_mulsh_i64: 1760 if (use_mips32r6_instructions) { 1761 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1762 break; 1763 } 1764 i1 = OPC_DMULT, i2 = OPC_MFHI; 1765 goto do_hilo1; 1766 case INDEX_op_muluh_i64: 1767 if (use_mips32r6_instructions) { 1768 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1769 break; 1770 } 1771 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1772 goto do_hilo1; 1773 case INDEX_op_div_i64: 1774 if (use_mips32r6_instructions) { 1775 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1776 break; 1777 } 1778 i1 = OPC_DDIV, i2 = OPC_MFLO; 1779 goto do_hilo1; 1780 case INDEX_op_divu_i64: 1781 if (use_mips32r6_instructions) { 1782 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1783 break; 1784 } 1785 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1786 goto do_hilo1; 1787 case INDEX_op_rem_i64: 1788 if (use_mips32r6_instructions) { 1789 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1790 break; 1791 } 1792 i1 = OPC_DDIV, i2 = OPC_MFHI; 1793 goto do_hilo1; 1794 case INDEX_op_remu_i64: 1795 if (use_mips32r6_instructions) { 1796 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1797 break; 1798 } 1799 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1800 do_hilo1: 1801 tcg_out_opc_reg(s, i1, 0, a1, a2); 1802 tcg_out_opc_reg(s, i2, a0, 0, 0); 1803 break; 1804 1805 case INDEX_op_muls2_i32: 1806 i1 = OPC_MULT; 1807 goto do_hilo2; 1808 case INDEX_op_mulu2_i32: 1809 i1 = OPC_MULTU; 1810 goto do_hilo2; 1811 case INDEX_op_muls2_i64: 1812 i1 = OPC_DMULT; 1813 goto do_hilo2; 1814 case INDEX_op_mulu2_i64: 1815 i1 = OPC_DMULTU; 1816 do_hilo2: 1817 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1818 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1819 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1820 break; 1821 1822 case INDEX_op_not_i32: 1823 case INDEX_op_not_i64: 1824 i1 = OPC_NOR; 1825 goto do_unary; 1826 do_unary: 1827 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1828 break; 1829 1830 case INDEX_op_bswap16_i32: 1831 case INDEX_op_bswap16_i64: 1832 tcg_out_bswap16(s, a0, a1, a2); 1833 break; 1834 case INDEX_op_bswap32_i32: 1835 tcg_out_bswap32(s, a0, a1, 0); 1836 break; 1837 case INDEX_op_bswap32_i64: 1838 tcg_out_bswap32(s, a0, a1, a2); 1839 break; 1840 case INDEX_op_bswap64_i64: 1841 tcg_out_bswap64(s, a0, a1); 1842 break; 1843 case INDEX_op_extrh_i64_i32: 1844 tcg_out_dsra(s, a0, a1, 32); 1845 break; 1846 1847 case INDEX_op_sar_i32: 1848 i1 = OPC_SRAV, i2 = OPC_SRA; 1849 goto do_shift; 1850 case INDEX_op_shl_i32: 1851 i1 = OPC_SLLV, i2 = OPC_SLL; 1852 goto do_shift; 1853 case INDEX_op_shr_i32: 1854 i1 = OPC_SRLV, i2 = OPC_SRL; 1855 goto do_shift; 1856 case INDEX_op_rotr_i32: 1857 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1858 do_shift: 1859 if (c2) { 1860 tcg_out_opc_sa(s, i2, a0, a1, a2); 1861 break; 1862 } 1863 do_shiftv: 1864 tcg_out_opc_reg(s, i1, a0, a2, a1); 1865 break; 1866 case INDEX_op_rotl_i32: 1867 if (c2) { 1868 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 1869 } else { 1870 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1871 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 1872 } 1873 break; 1874 case INDEX_op_sar_i64: 1875 if (c2) { 1876 tcg_out_dsra(s, a0, a1, a2); 1877 break; 1878 } 1879 i1 = OPC_DSRAV; 1880 goto do_shiftv; 1881 case INDEX_op_shl_i64: 1882 if (c2) { 1883 tcg_out_dsll(s, a0, a1, a2); 1884 break; 1885 } 1886 i1 = OPC_DSLLV; 1887 goto do_shiftv; 1888 case INDEX_op_shr_i64: 1889 if (c2) { 1890 tcg_out_dsrl(s, a0, a1, a2); 1891 break; 1892 } 1893 i1 = OPC_DSRLV; 1894 goto do_shiftv; 1895 case INDEX_op_rotr_i64: 1896 if (c2) { 1897 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 1898 break; 1899 } 1900 i1 = OPC_DROTRV; 1901 goto do_shiftv; 1902 case INDEX_op_rotl_i64: 1903 if (c2) { 1904 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 1905 } else { 1906 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1907 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 1908 } 1909 break; 1910 1911 case INDEX_op_clz_i32: 1912 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 1913 break; 1914 case INDEX_op_clz_i64: 1915 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 1916 break; 1917 1918 case INDEX_op_deposit_i32: 1919 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 1920 break; 1921 case INDEX_op_deposit_i64: 1922 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 1923 args[3] + args[4] - 1, args[3]); 1924 break; 1925 case INDEX_op_extract_i32: 1926 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 1927 break; 1928 case INDEX_op_extract_i64: 1929 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 1930 args[3] - 1, a2); 1931 break; 1932 1933 case INDEX_op_brcond_i32: 1934 case INDEX_op_brcond_i64: 1935 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1936 break; 1937 case INDEX_op_brcond2_i32: 1938 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 1939 break; 1940 1941 case INDEX_op_movcond_i32: 1942 case INDEX_op_movcond_i64: 1943 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 1944 break; 1945 1946 case INDEX_op_setcond_i32: 1947 case INDEX_op_setcond_i64: 1948 tcg_out_setcond(s, args[3], a0, a1, a2); 1949 break; 1950 case INDEX_op_setcond2_i32: 1951 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 1952 break; 1953 1954 case INDEX_op_qemu_ld_i32: 1955 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 1956 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 1957 } else { 1958 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 1959 } 1960 break; 1961 case INDEX_op_qemu_ld_i64: 1962 if (TCG_TARGET_REG_BITS == 64) { 1963 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 1964 } else if (TARGET_LONG_BITS == 32) { 1965 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 1966 } else { 1967 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 1968 } 1969 break; 1970 case INDEX_op_qemu_st_i32: 1971 if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { 1972 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 1973 } else { 1974 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 1975 } 1976 break; 1977 case INDEX_op_qemu_st_i64: 1978 if (TCG_TARGET_REG_BITS == 64) { 1979 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 1980 } else if (TARGET_LONG_BITS == 32) { 1981 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 1982 } else { 1983 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 1984 } 1985 break; 1986 1987 case INDEX_op_add2_i32: 1988 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1989 const_args[4], const_args[5], false); 1990 break; 1991 case INDEX_op_sub2_i32: 1992 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 1993 const_args[4], const_args[5], true); 1994 break; 1995 1996 case INDEX_op_mb: 1997 tcg_out_mb(s, a0); 1998 break; 1999 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2000 case INDEX_op_mov_i64: 2001 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2002 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2003 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2004 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2005 case INDEX_op_ext8s_i64: 2006 case INDEX_op_ext8u_i32: 2007 case INDEX_op_ext8u_i64: 2008 case INDEX_op_ext16s_i32: 2009 case INDEX_op_ext16s_i64: 2010 case INDEX_op_ext32s_i64: 2011 case INDEX_op_ext32u_i64: 2012 case INDEX_op_ext_i32_i64: 2013 case INDEX_op_extu_i32_i64: 2014 case INDEX_op_extrl_i64_i32: 2015 default: 2016 g_assert_not_reached(); 2017 } 2018} 2019 2020static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2021{ 2022 switch (op) { 2023 case INDEX_op_goto_ptr: 2024 return C_O0_I1(r); 2025 2026 case INDEX_op_ld8u_i32: 2027 case INDEX_op_ld8s_i32: 2028 case INDEX_op_ld16u_i32: 2029 case INDEX_op_ld16s_i32: 2030 case INDEX_op_ld_i32: 2031 case INDEX_op_not_i32: 2032 case INDEX_op_bswap16_i32: 2033 case INDEX_op_bswap32_i32: 2034 case INDEX_op_ext8s_i32: 2035 case INDEX_op_ext16s_i32: 2036 case INDEX_op_extract_i32: 2037 case INDEX_op_ld8u_i64: 2038 case INDEX_op_ld8s_i64: 2039 case INDEX_op_ld16u_i64: 2040 case INDEX_op_ld16s_i64: 2041 case INDEX_op_ld32s_i64: 2042 case INDEX_op_ld32u_i64: 2043 case INDEX_op_ld_i64: 2044 case INDEX_op_not_i64: 2045 case INDEX_op_bswap16_i64: 2046 case INDEX_op_bswap32_i64: 2047 case INDEX_op_bswap64_i64: 2048 case INDEX_op_ext8s_i64: 2049 case INDEX_op_ext16s_i64: 2050 case INDEX_op_ext32s_i64: 2051 case INDEX_op_ext32u_i64: 2052 case INDEX_op_ext_i32_i64: 2053 case INDEX_op_extu_i32_i64: 2054 case INDEX_op_extrl_i64_i32: 2055 case INDEX_op_extrh_i64_i32: 2056 case INDEX_op_extract_i64: 2057 return C_O1_I1(r, r); 2058 2059 case INDEX_op_st8_i32: 2060 case INDEX_op_st16_i32: 2061 case INDEX_op_st_i32: 2062 case INDEX_op_st8_i64: 2063 case INDEX_op_st16_i64: 2064 case INDEX_op_st32_i64: 2065 case INDEX_op_st_i64: 2066 return C_O0_I2(rZ, r); 2067 2068 case INDEX_op_add_i32: 2069 case INDEX_op_add_i64: 2070 return C_O1_I2(r, r, rJ); 2071 case INDEX_op_sub_i32: 2072 case INDEX_op_sub_i64: 2073 return C_O1_I2(r, rZ, rN); 2074 case INDEX_op_mul_i32: 2075 case INDEX_op_mulsh_i32: 2076 case INDEX_op_muluh_i32: 2077 case INDEX_op_div_i32: 2078 case INDEX_op_divu_i32: 2079 case INDEX_op_rem_i32: 2080 case INDEX_op_remu_i32: 2081 case INDEX_op_nor_i32: 2082 case INDEX_op_setcond_i32: 2083 case INDEX_op_mul_i64: 2084 case INDEX_op_mulsh_i64: 2085 case INDEX_op_muluh_i64: 2086 case INDEX_op_div_i64: 2087 case INDEX_op_divu_i64: 2088 case INDEX_op_rem_i64: 2089 case INDEX_op_remu_i64: 2090 case INDEX_op_nor_i64: 2091 case INDEX_op_setcond_i64: 2092 return C_O1_I2(r, rZ, rZ); 2093 case INDEX_op_muls2_i32: 2094 case INDEX_op_mulu2_i32: 2095 case INDEX_op_muls2_i64: 2096 case INDEX_op_mulu2_i64: 2097 return C_O2_I2(r, r, r, r); 2098 case INDEX_op_and_i32: 2099 case INDEX_op_and_i64: 2100 return C_O1_I2(r, r, rIK); 2101 case INDEX_op_or_i32: 2102 case INDEX_op_xor_i32: 2103 case INDEX_op_or_i64: 2104 case INDEX_op_xor_i64: 2105 return C_O1_I2(r, r, rI); 2106 case INDEX_op_shl_i32: 2107 case INDEX_op_shr_i32: 2108 case INDEX_op_sar_i32: 2109 case INDEX_op_rotr_i32: 2110 case INDEX_op_rotl_i32: 2111 case INDEX_op_shl_i64: 2112 case INDEX_op_shr_i64: 2113 case INDEX_op_sar_i64: 2114 case INDEX_op_rotr_i64: 2115 case INDEX_op_rotl_i64: 2116 return C_O1_I2(r, r, ri); 2117 case INDEX_op_clz_i32: 2118 case INDEX_op_clz_i64: 2119 return C_O1_I2(r, r, rWZ); 2120 2121 case INDEX_op_deposit_i32: 2122 case INDEX_op_deposit_i64: 2123 return C_O1_I2(r, 0, rZ); 2124 case INDEX_op_brcond_i32: 2125 case INDEX_op_brcond_i64: 2126 return C_O0_I2(rZ, rZ); 2127 case INDEX_op_movcond_i32: 2128 case INDEX_op_movcond_i64: 2129 return (use_mips32r6_instructions 2130 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2131 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2132 case INDEX_op_add2_i32: 2133 case INDEX_op_sub2_i32: 2134 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2135 case INDEX_op_setcond2_i32: 2136 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2137 case INDEX_op_brcond2_i32: 2138 return C_O0_I4(rZ, rZ, rZ, rZ); 2139 2140 case INDEX_op_qemu_ld_i32: 2141 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2142 ? C_O1_I1(r, r) : C_O1_I2(r, r, r)); 2143 case INDEX_op_qemu_st_i32: 2144 return (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 32 2145 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r)); 2146 case INDEX_op_qemu_ld_i64: 2147 return (TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) 2148 : TARGET_LONG_BITS == 32 ? C_O2_I1(r, r, r) 2149 : C_O2_I2(r, r, r, r)); 2150 case INDEX_op_qemu_st_i64: 2151 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) 2152 : TARGET_LONG_BITS == 32 ? C_O0_I3(rZ, rZ, r) 2153 : C_O0_I4(rZ, rZ, r, r)); 2154 2155 default: 2156 g_assert_not_reached(); 2157 } 2158} 2159 2160static const int tcg_target_callee_save_regs[] = { 2161 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2162 TCG_REG_S1, 2163 TCG_REG_S2, 2164 TCG_REG_S3, 2165 TCG_REG_S4, 2166 TCG_REG_S5, 2167 TCG_REG_S6, 2168 TCG_REG_S7, 2169 TCG_REG_S8, 2170 TCG_REG_RA, /* should be last for ABI compliance */ 2171}; 2172 2173/* The Linux kernel doesn't provide any information about the available 2174 instruction set. Probe it using a signal handler. */ 2175 2176 2177#ifndef use_movnz_instructions 2178bool use_movnz_instructions = false; 2179#endif 2180 2181#ifndef use_mips32_instructions 2182bool use_mips32_instructions = false; 2183#endif 2184 2185#ifndef use_mips32r2_instructions 2186bool use_mips32r2_instructions = false; 2187#endif 2188 2189static volatile sig_atomic_t got_sigill; 2190 2191static void sigill_handler(int signo, siginfo_t *si, void *data) 2192{ 2193 /* Skip the faulty instruction */ 2194 ucontext_t *uc = (ucontext_t *)data; 2195 uc->uc_mcontext.pc += 4; 2196 2197 got_sigill = 1; 2198} 2199 2200static void tcg_target_detect_isa(void) 2201{ 2202 struct sigaction sa_old, sa_new; 2203 2204 memset(&sa_new, 0, sizeof(sa_new)); 2205 sa_new.sa_flags = SA_SIGINFO; 2206 sa_new.sa_sigaction = sigill_handler; 2207 sigaction(SIGILL, &sa_new, &sa_old); 2208 2209 /* Probe for movn/movz, necessary to implement movcond. */ 2210#ifndef use_movnz_instructions 2211 got_sigill = 0; 2212 asm volatile(".set push\n" 2213 ".set mips32\n" 2214 "movn $zero, $zero, $zero\n" 2215 "movz $zero, $zero, $zero\n" 2216 ".set pop\n" 2217 : : : ); 2218 use_movnz_instructions = !got_sigill; 2219#endif 2220 2221 /* Probe for MIPS32 instructions. As no subsetting is allowed 2222 by the specification, it is only necessary to probe for one 2223 of the instructions. */ 2224#ifndef use_mips32_instructions 2225 got_sigill = 0; 2226 asm volatile(".set push\n" 2227 ".set mips32\n" 2228 "mul $zero, $zero\n" 2229 ".set pop\n" 2230 : : : ); 2231 use_mips32_instructions = !got_sigill; 2232#endif 2233 2234 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2235 available. As no subsetting is allowed by the specification, 2236 it is only necessary to probe for one of the instructions. */ 2237#ifndef use_mips32r2_instructions 2238 if (use_mips32_instructions) { 2239 got_sigill = 0; 2240 asm volatile(".set push\n" 2241 ".set mips32r2\n" 2242 "seb $zero, $zero\n" 2243 ".set pop\n" 2244 : : : ); 2245 use_mips32r2_instructions = !got_sigill; 2246 } 2247#endif 2248 2249 sigaction(SIGILL, &sa_old, NULL); 2250} 2251 2252static tcg_insn_unit *align_code_ptr(TCGContext *s) 2253{ 2254 uintptr_t p = (uintptr_t)s->code_ptr; 2255 if (p & 15) { 2256 p = (p + 15) & -16; 2257 s->code_ptr = (void *)p; 2258 } 2259 return s->code_ptr; 2260} 2261 2262/* Stack frame parameters. */ 2263#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2264#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2265#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2266 2267#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2268 + TCG_TARGET_STACK_ALIGN - 1) \ 2269 & -TCG_TARGET_STACK_ALIGN) 2270#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2271 2272/* We're expecting to be able to use an immediate for frame allocation. */ 2273QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2274 2275/* Generate global QEMU prologue and epilogue code */ 2276static void tcg_target_qemu_prologue(TCGContext *s) 2277{ 2278 int i; 2279 2280 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2281 2282 /* TB prologue */ 2283 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2284 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2285 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2286 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2287 } 2288 2289#ifndef CONFIG_SOFTMMU 2290 if (guest_base) { 2291 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2292 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2293 } 2294#endif 2295 2296 /* Call generated code */ 2297 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2298 /* delay slot */ 2299 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2300 2301 /* 2302 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2303 * and fall through to the rest of the epilogue. 2304 */ 2305 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2306 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2307 2308 /* TB epilogue */ 2309 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2310 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2311 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2312 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2313 } 2314 2315 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2316 /* delay slot */ 2317 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2318 2319 if (use_mips32r2_instructions) { 2320 return; 2321 } 2322 2323 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2324 clobbers TCG_TMP1, TCG_TMP2. */ 2325 2326 /* 2327 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2328 */ 2329 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2330 /* t3 = (ssss)d000 */ 2331 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2332 /* t1 = 000a */ 2333 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2334 /* t2 = 00c0 */ 2335 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2336 /* t3 = d00a */ 2337 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2338 /* t1 = 0abc */ 2339 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2340 /* t2 = 0c00 */ 2341 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2342 /* t1 = 00b0 */ 2343 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2344 /* t3 = dc0a */ 2345 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2346 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2347 /* t3 = dcba -- delay slot */ 2348 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2349 2350 if (TCG_TARGET_REG_BITS == 32) { 2351 return; 2352 } 2353 2354 /* 2355 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2356 */ 2357 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2358 /* t1 = (0000)000d */ 2359 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2360 /* t3 = 000a */ 2361 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2362 /* t1 = (0000)d000 */ 2363 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2364 /* t2 = 00c0 */ 2365 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2366 /* t3 = d00a */ 2367 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2368 /* t1 = 0abc */ 2369 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2370 /* t2 = 0c00 */ 2371 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2372 /* t1 = 00b0 */ 2373 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2374 /* t3 = dc0a */ 2375 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2376 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2377 /* t3 = dcba -- delay slot */ 2378 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2379 2380 /* 2381 * bswap64 -- 64-bit swap. a0 = abcdefgh 2382 */ 2383 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2384 /* t3 = h0000000 */ 2385 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2386 /* t1 = 0000000a */ 2387 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2388 2389 /* t2 = 000000g0 */ 2390 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2391 /* t3 = h000000a */ 2392 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2393 /* t1 = 00000abc */ 2394 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2395 /* t2 = 0g000000 */ 2396 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2397 /* t1 = 000000b0 */ 2398 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2399 2400 /* t3 = hg00000a */ 2401 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2402 /* t2 = 0000abcd */ 2403 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2404 /* t3 = hg0000ba */ 2405 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2406 2407 /* t1 = 000000c0 */ 2408 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2409 /* t2 = 0000000d */ 2410 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2411 /* t1 = 00000c00 */ 2412 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2413 /* t2 = 0000d000 */ 2414 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2415 2416 /* t3 = hg000cba */ 2417 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2418 /* t1 = 00abcdef */ 2419 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2420 /* t3 = hg00dcba */ 2421 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2422 2423 /* t2 = 0000000f */ 2424 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2425 /* t1 = 000000e0 */ 2426 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2427 /* t2 = 00f00000 */ 2428 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2429 /* t1 = 000e0000 */ 2430 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2431 2432 /* t3 = hgf0dcba */ 2433 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2434 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2435 /* t3 = hgfedcba -- delay slot */ 2436 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2437} 2438 2439static void tcg_target_init(TCGContext *s) 2440{ 2441 tcg_target_detect_isa(); 2442 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2443 if (TCG_TARGET_REG_BITS == 64) { 2444 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2445 } 2446 2447 tcg_target_call_clobber_regs = 0; 2448 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2449 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2450 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2451 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2452 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2453 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2454 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2455 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2456 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2457 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2458 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2459 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2460 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2461 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2462 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2463 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2464 2465 s->reserved_regs = 0; 2466 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2467 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2468 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2469 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2470 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2471 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2472 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2473 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2474 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2475 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2476} 2477 2478typedef struct { 2479 DebugFrameHeader h; 2480 uint8_t fde_def_cfa[4]; 2481 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2482} DebugFrame; 2483 2484#define ELF_HOST_MACHINE EM_MIPS 2485/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2486 which is good because they're really quite complicated for MIPS. */ 2487 2488static const DebugFrame debug_frame = { 2489 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2490 .h.cie.id = -1, 2491 .h.cie.version = 1, 2492 .h.cie.code_align = 1, 2493 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2494 .h.cie.return_column = TCG_REG_RA, 2495 2496 /* Total FDE size does not include the "len" member. */ 2497 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2498 2499 .fde_def_cfa = { 2500 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2501 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2502 (FRAME_SIZE >> 7) 2503 }, 2504 .fde_reg_ofs = { 2505 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2506 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2507 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2508 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2509 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2510 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2511 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2512 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2513 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2514 } 2515}; 2516 2517void tcg_register_jit(const void *buf, size_t buf_size) 2518{ 2519 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2520} 2521