1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27#include "../tcg-ldst.c.inc" 28 29#if HOST_BIG_ENDIAN 30# define MIPS_BE 1 31#else 32# define MIPS_BE 0 33#endif 34 35#if TCG_TARGET_REG_BITS == 32 36# define LO_OFF (MIPS_BE * 4) 37# define HI_OFF (4 - LO_OFF) 38#else 39/* To assert at compile-time that these values are never used 40 for TCG_TARGET_REG_BITS == 64. */ 41int link_error(void); 42# define LO_OFF link_error() 43# define HI_OFF link_error() 44#endif 45 46#ifdef CONFIG_DEBUG_TCG 47static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 48 "zero", 49 "at", 50 "v0", 51 "v1", 52 "a0", 53 "a1", 54 "a2", 55 "a3", 56 "t0", 57 "t1", 58 "t2", 59 "t3", 60 "t4", 61 "t5", 62 "t6", 63 "t7", 64 "s0", 65 "s1", 66 "s2", 67 "s3", 68 "s4", 69 "s5", 70 "s6", 71 "s7", 72 "t8", 73 "t9", 74 "k0", 75 "k1", 76 "gp", 77 "sp", 78 "s8", 79 "ra", 80}; 81#endif 82 83#define TCG_TMP0 TCG_REG_AT 84#define TCG_TMP1 TCG_REG_T9 85#define TCG_TMP2 TCG_REG_T8 86#define TCG_TMP3 TCG_REG_T7 87 88#ifndef CONFIG_SOFTMMU 89#define TCG_GUEST_BASE_REG TCG_REG_S1 90#endif 91 92/* check if we really need so many registers :P */ 93static const int tcg_target_reg_alloc_order[] = { 94 /* Call saved registers. */ 95 TCG_REG_S0, 96 TCG_REG_S1, 97 TCG_REG_S2, 98 TCG_REG_S3, 99 TCG_REG_S4, 100 TCG_REG_S5, 101 TCG_REG_S6, 102 TCG_REG_S7, 103 TCG_REG_S8, 104 105 /* Call clobbered registers. */ 106 TCG_REG_T4, 107 TCG_REG_T5, 108 TCG_REG_T6, 109 TCG_REG_T7, 110 TCG_REG_T8, 111 TCG_REG_T9, 112 TCG_REG_V1, 113 TCG_REG_V0, 114 115 /* Argument registers, opposite order of allocation. */ 116 TCG_REG_T3, 117 TCG_REG_T2, 118 TCG_REG_T1, 119 TCG_REG_T0, 120 TCG_REG_A3, 121 TCG_REG_A2, 122 TCG_REG_A1, 123 TCG_REG_A0, 124}; 125 126static const TCGReg tcg_target_call_iarg_regs[] = { 127 TCG_REG_A0, 128 TCG_REG_A1, 129 TCG_REG_A2, 130 TCG_REG_A3, 131#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 132 TCG_REG_T0, 133 TCG_REG_T1, 134 TCG_REG_T2, 135 TCG_REG_T3, 136#endif 137}; 138 139static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 140{ 141 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 142 tcg_debug_assert(slot >= 0 && slot <= 1); 143 return TCG_REG_V0 + slot; 144} 145 146static const tcg_insn_unit *tb_ret_addr; 147static const tcg_insn_unit *bswap32_addr; 148static const tcg_insn_unit *bswap32u_addr; 149static const tcg_insn_unit *bswap64_addr; 150 151static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 152{ 153 /* Let the compiler perform the right-shift as part of the arithmetic. */ 154 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 155 ptrdiff_t disp = target - (src_rx + 1); 156 if (disp == (int16_t)disp) { 157 *src_rw = deposit32(*src_rw, 0, 16, disp); 158 return true; 159 } 160 return false; 161} 162 163static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 164 intptr_t value, intptr_t addend) 165{ 166 tcg_debug_assert(type == R_MIPS_PC16); 167 tcg_debug_assert(addend == 0); 168 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 169} 170 171#define TCG_CT_CONST_ZERO 0x100 172#define TCG_CT_CONST_U16 0x200 /* Unsigned 16-bit: 0 - 0xffff. */ 173#define TCG_CT_CONST_S16 0x400 /* Signed 16-bit: -32768 - 32767 */ 174#define TCG_CT_CONST_P2M1 0x800 /* Power of 2 minus 1. */ 175#define TCG_CT_CONST_N16 0x1000 /* "Negatable" 16-bit: -32767 - 32767 */ 176#define TCG_CT_CONST_WSZ 0x2000 /* word size */ 177 178#define ALL_GENERAL_REGS 0xffffffffu 179 180static bool is_p2m1(tcg_target_long val) 181{ 182 return val && ((val + 1) & val) == 0; 183} 184 185/* test if a constant matches the constraint */ 186static bool tcg_target_const_match(int64_t val, TCGType type, int ct) 187{ 188 if (ct & TCG_CT_CONST) { 189 return 1; 190 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 191 return 1; 192 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 193 return 1; 194 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 195 return 1; 196 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 197 return 1; 198 } else if ((ct & TCG_CT_CONST_P2M1) 199 && use_mips32r2_instructions && is_p2m1(val)) { 200 return 1; 201 } else if ((ct & TCG_CT_CONST_WSZ) 202 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 203 return 1; 204 } 205 return 0; 206} 207 208/* instruction opcodes */ 209typedef enum { 210 OPC_J = 002 << 26, 211 OPC_JAL = 003 << 26, 212 OPC_BEQ = 004 << 26, 213 OPC_BNE = 005 << 26, 214 OPC_BLEZ = 006 << 26, 215 OPC_BGTZ = 007 << 26, 216 OPC_ADDIU = 011 << 26, 217 OPC_SLTI = 012 << 26, 218 OPC_SLTIU = 013 << 26, 219 OPC_ANDI = 014 << 26, 220 OPC_ORI = 015 << 26, 221 OPC_XORI = 016 << 26, 222 OPC_LUI = 017 << 26, 223 OPC_BNEL = 025 << 26, 224 OPC_BNEZALC_R6 = 030 << 26, 225 OPC_DADDIU = 031 << 26, 226 OPC_LDL = 032 << 26, 227 OPC_LDR = 033 << 26, 228 OPC_LB = 040 << 26, 229 OPC_LH = 041 << 26, 230 OPC_LWL = 042 << 26, 231 OPC_LW = 043 << 26, 232 OPC_LBU = 044 << 26, 233 OPC_LHU = 045 << 26, 234 OPC_LWR = 046 << 26, 235 OPC_LWU = 047 << 26, 236 OPC_SB = 050 << 26, 237 OPC_SH = 051 << 26, 238 OPC_SWL = 052 << 26, 239 OPC_SW = 053 << 26, 240 OPC_SDL = 054 << 26, 241 OPC_SDR = 055 << 26, 242 OPC_SWR = 056 << 26, 243 OPC_LD = 067 << 26, 244 OPC_SD = 077 << 26, 245 246 OPC_SPECIAL = 000 << 26, 247 OPC_SLL = OPC_SPECIAL | 000, 248 OPC_SRL = OPC_SPECIAL | 002, 249 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 250 OPC_SRA = OPC_SPECIAL | 003, 251 OPC_SLLV = OPC_SPECIAL | 004, 252 OPC_SRLV = OPC_SPECIAL | 006, 253 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 254 OPC_SRAV = OPC_SPECIAL | 007, 255 OPC_JR_R5 = OPC_SPECIAL | 010, 256 OPC_JALR = OPC_SPECIAL | 011, 257 OPC_MOVZ = OPC_SPECIAL | 012, 258 OPC_MOVN = OPC_SPECIAL | 013, 259 OPC_SYNC = OPC_SPECIAL | 017, 260 OPC_MFHI = OPC_SPECIAL | 020, 261 OPC_MFLO = OPC_SPECIAL | 022, 262 OPC_DSLLV = OPC_SPECIAL | 024, 263 OPC_DSRLV = OPC_SPECIAL | 026, 264 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 265 OPC_DSRAV = OPC_SPECIAL | 027, 266 OPC_MULT = OPC_SPECIAL | 030, 267 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 268 OPC_MUH = OPC_SPECIAL | 030 | 0300, 269 OPC_MULTU = OPC_SPECIAL | 031, 270 OPC_MULU = OPC_SPECIAL | 031 | 0200, 271 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 272 OPC_DIV = OPC_SPECIAL | 032, 273 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 274 OPC_MOD = OPC_SPECIAL | 032 | 0300, 275 OPC_DIVU = OPC_SPECIAL | 033, 276 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 277 OPC_MODU = OPC_SPECIAL | 033 | 0300, 278 OPC_DMULT = OPC_SPECIAL | 034, 279 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 280 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 281 OPC_DMULTU = OPC_SPECIAL | 035, 282 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 283 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 284 OPC_DDIV = OPC_SPECIAL | 036, 285 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 286 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 287 OPC_DDIVU = OPC_SPECIAL | 037, 288 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 289 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 290 OPC_ADDU = OPC_SPECIAL | 041, 291 OPC_SUBU = OPC_SPECIAL | 043, 292 OPC_AND = OPC_SPECIAL | 044, 293 OPC_OR = OPC_SPECIAL | 045, 294 OPC_XOR = OPC_SPECIAL | 046, 295 OPC_NOR = OPC_SPECIAL | 047, 296 OPC_SLT = OPC_SPECIAL | 052, 297 OPC_SLTU = OPC_SPECIAL | 053, 298 OPC_DADDU = OPC_SPECIAL | 055, 299 OPC_DSUBU = OPC_SPECIAL | 057, 300 OPC_SELEQZ = OPC_SPECIAL | 065, 301 OPC_SELNEZ = OPC_SPECIAL | 067, 302 OPC_DSLL = OPC_SPECIAL | 070, 303 OPC_DSRL = OPC_SPECIAL | 072, 304 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 305 OPC_DSRA = OPC_SPECIAL | 073, 306 OPC_DSLL32 = OPC_SPECIAL | 074, 307 OPC_DSRL32 = OPC_SPECIAL | 076, 308 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 309 OPC_DSRA32 = OPC_SPECIAL | 077, 310 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 311 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 312 313 OPC_REGIMM = 001 << 26, 314 OPC_BLTZ = OPC_REGIMM | (000 << 16), 315 OPC_BGEZ = OPC_REGIMM | (001 << 16), 316 317 OPC_SPECIAL2 = 034 << 26, 318 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 319 OPC_CLZ = OPC_SPECIAL2 | 040, 320 OPC_DCLZ = OPC_SPECIAL2 | 044, 321 322 OPC_SPECIAL3 = 037 << 26, 323 OPC_EXT = OPC_SPECIAL3 | 000, 324 OPC_DEXTM = OPC_SPECIAL3 | 001, 325 OPC_DEXTU = OPC_SPECIAL3 | 002, 326 OPC_DEXT = OPC_SPECIAL3 | 003, 327 OPC_INS = OPC_SPECIAL3 | 004, 328 OPC_DINSM = OPC_SPECIAL3 | 005, 329 OPC_DINSU = OPC_SPECIAL3 | 006, 330 OPC_DINS = OPC_SPECIAL3 | 007, 331 OPC_WSBH = OPC_SPECIAL3 | 00240, 332 OPC_DSBH = OPC_SPECIAL3 | 00244, 333 OPC_DSHD = OPC_SPECIAL3 | 00544, 334 OPC_SEB = OPC_SPECIAL3 | 02040, 335 OPC_SEH = OPC_SPECIAL3 | 03040, 336 337 /* MIPS r6 doesn't have JR, JALR should be used instead */ 338 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 339 340 /* 341 * MIPS r6 replaces MUL with an alternative encoding which is 342 * backwards-compatible at the assembly level. 343 */ 344 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 345 346 /* MIPS r6 introduced names for weaker variants of SYNC. These are 347 backward compatible to previous architecture revisions. */ 348 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 349 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 350 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 351 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 352 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 353 354 /* Aliases for convenience. */ 355 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 356 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 357} MIPSInsn; 358 359/* 360 * Type reg 361 */ 362static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 363 TCGReg rd, TCGReg rs, TCGReg rt) 364{ 365 int32_t inst; 366 367 inst = opc; 368 inst |= (rs & 0x1F) << 21; 369 inst |= (rt & 0x1F) << 16; 370 inst |= (rd & 0x1F) << 11; 371 tcg_out32(s, inst); 372} 373 374/* 375 * Type immediate 376 */ 377static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 378 TCGReg rt, TCGReg rs, TCGArg imm) 379{ 380 int32_t inst; 381 382 inst = opc; 383 inst |= (rs & 0x1F) << 21; 384 inst |= (rt & 0x1F) << 16; 385 inst |= (imm & 0xffff); 386 tcg_out32(s, inst); 387} 388 389/* 390 * Type bitfield 391 */ 392static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 393 TCGReg rs, int msb, int lsb) 394{ 395 int32_t inst; 396 397 inst = opc; 398 inst |= (rs & 0x1F) << 21; 399 inst |= (rt & 0x1F) << 16; 400 inst |= (msb & 0x1F) << 11; 401 inst |= (lsb & 0x1F) << 6; 402 tcg_out32(s, inst); 403} 404 405static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 406 MIPSInsn oph, TCGReg rt, TCGReg rs, 407 int msb, int lsb) 408{ 409 if (lsb >= 32) { 410 opc = oph; 411 msb -= 32; 412 lsb -= 32; 413 } else if (msb >= 32) { 414 opc = opm; 415 msb -= 32; 416 } 417 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 418} 419 420/* 421 * Type branch 422 */ 423static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 424{ 425 tcg_out_opc_imm(s, opc, rt, rs, 0); 426} 427 428/* 429 * Type sa 430 */ 431static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 432 TCGReg rd, TCGReg rt, TCGArg sa) 433{ 434 int32_t inst; 435 436 inst = opc; 437 inst |= (rt & 0x1F) << 16; 438 inst |= (rd & 0x1F) << 11; 439 inst |= (sa & 0x1F) << 6; 440 tcg_out32(s, inst); 441 442} 443 444static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 445 TCGReg rd, TCGReg rt, TCGArg sa) 446{ 447 int32_t inst; 448 449 inst = (sa & 32 ? opc2 : opc1); 450 inst |= (rt & 0x1F) << 16; 451 inst |= (rd & 0x1F) << 11; 452 inst |= (sa & 0x1F) << 6; 453 tcg_out32(s, inst); 454} 455 456/* 457 * Type jump. 458 * Returns true if the branch was in range and the insn was emitted. 459 */ 460static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 461{ 462 uintptr_t dest = (uintptr_t)target; 463 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 464 int32_t inst; 465 466 /* The pc-region branch happens within the 256MB region of 467 the delay slot (thus the +4). */ 468 if ((from ^ dest) & -(1 << 28)) { 469 return false; 470 } 471 tcg_debug_assert((dest & 3) == 0); 472 473 inst = opc; 474 inst |= (dest >> 2) & 0x3ffffff; 475 tcg_out32(s, inst); 476 return true; 477} 478 479static void tcg_out_nop(TCGContext *s) 480{ 481 tcg_out32(s, 0); 482} 483 484static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 485{ 486 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 487} 488 489static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 490{ 491 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 492} 493 494static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 495{ 496 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 497} 498 499static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 500{ 501 /* Simple reg-reg move, optimising out the 'do nothing' case */ 502 if (ret != arg) { 503 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 504 } 505 return true; 506} 507 508static void tcg_out_movi(TCGContext *s, TCGType type, 509 TCGReg ret, tcg_target_long arg) 510{ 511 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 512 arg = (int32_t)arg; 513 } 514 if (arg == (int16_t)arg) { 515 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 516 return; 517 } 518 if (arg == (uint16_t)arg) { 519 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 520 return; 521 } 522 if (TCG_TARGET_REG_BITS == 32 || arg == (int32_t)arg) { 523 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 524 } else { 525 tcg_out_movi(s, TCG_TYPE_I32, ret, arg >> 31 >> 1); 526 if (arg & 0xffff0000ull) { 527 tcg_out_dsll(s, ret, ret, 16); 528 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg >> 16); 529 tcg_out_dsll(s, ret, ret, 16); 530 } else { 531 tcg_out_dsll(s, ret, ret, 32); 532 } 533 } 534 if (arg & 0xffff) { 535 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 536 } 537} 538 539static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 540{ 541 tcg_debug_assert(TCG_TARGET_HAS_ext8s_i32); 542 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 543} 544 545static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 546{ 547 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 548} 549 550static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 551{ 552 tcg_debug_assert(TCG_TARGET_HAS_ext16s_i32); 553 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 554} 555 556static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 557{ 558 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 559} 560 561static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 562{ 563 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 564 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 565} 566 567static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 568{ 569 if (rd != rs) { 570 tcg_out_ext32s(s, rd, rs); 571 } 572} 573 574static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 575{ 576 tcg_out_ext32u(s, rd, rs); 577} 578 579static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 580{ 581 tcg_out_ext32s(s, rd, rs); 582} 583 584static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 585{ 586 return false; 587} 588 589static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 590 tcg_target_long imm) 591{ 592 /* This function is only used for passing structs by reference. */ 593 g_assert_not_reached(); 594} 595 596static void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 597{ 598 /* ret and arg can't be register tmp0 */ 599 tcg_debug_assert(ret != TCG_TMP0); 600 tcg_debug_assert(arg != TCG_TMP0); 601 602 /* With arg = abcd: */ 603 if (use_mips32r2_instructions) { 604 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 605 if (flags & TCG_BSWAP_OS) { 606 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 607 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 608 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 609 } 610 return; 611 } 612 613 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 614 if (!(flags & TCG_BSWAP_IZ)) { 615 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 616 } 617 if (flags & TCG_BSWAP_OS) { 618 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 619 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 620 } else { 621 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 622 if (flags & TCG_BSWAP_OZ) { 623 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 624 } 625 } 626 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 627} 628 629static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 630{ 631 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 632 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 633 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 634 } 635} 636 637static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 638{ 639 if (use_mips32r2_instructions) { 640 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 641 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 642 if (flags & TCG_BSWAP_OZ) { 643 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 644 } 645 } else { 646 if (flags & TCG_BSWAP_OZ) { 647 tcg_out_bswap_subr(s, bswap32u_addr); 648 } else { 649 tcg_out_bswap_subr(s, bswap32_addr); 650 } 651 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 652 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 653 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 654 } 655} 656 657static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 658{ 659 if (use_mips32r2_instructions) { 660 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 661 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 662 } else { 663 tcg_out_bswap_subr(s, bswap64_addr); 664 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 665 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 666 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 667 } 668} 669 670static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 671{ 672 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 673 if (use_mips32r2_instructions) { 674 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 675 } else { 676 tcg_out_dsll(s, ret, arg, 32); 677 tcg_out_dsrl(s, ret, ret, 32); 678 } 679} 680 681static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 682 TCGReg addr, intptr_t ofs) 683{ 684 int16_t lo = ofs; 685 if (ofs != lo) { 686 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 687 if (addr != TCG_REG_ZERO) { 688 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 689 } 690 addr = TCG_TMP0; 691 } 692 tcg_out_opc_imm(s, opc, data, addr, lo); 693} 694 695static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 696 TCGReg arg1, intptr_t arg2) 697{ 698 MIPSInsn opc = OPC_LD; 699 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 700 opc = OPC_LW; 701 } 702 tcg_out_ldst(s, opc, arg, arg1, arg2); 703} 704 705static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 706 TCGReg arg1, intptr_t arg2) 707{ 708 MIPSInsn opc = OPC_SD; 709 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 710 opc = OPC_SW; 711 } 712 tcg_out_ldst(s, opc, arg, arg1, arg2); 713} 714 715static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 716 TCGReg base, intptr_t ofs) 717{ 718 if (val == 0) { 719 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 720 return true; 721 } 722 return false; 723} 724 725static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 726 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 727 bool cbh, bool is_sub) 728{ 729 TCGReg th = TCG_TMP1; 730 731 /* If we have a negative constant such that negating it would 732 make the high part zero, we can (usually) eliminate one insn. */ 733 if (cbl && cbh && bh == -1 && bl != 0) { 734 bl = -bl; 735 bh = 0; 736 is_sub = !is_sub; 737 } 738 739 /* By operating on the high part first, we get to use the final 740 carry operation to move back from the temporary. */ 741 if (!cbh) { 742 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 743 } else if (bh != 0 || ah == rl) { 744 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 745 } else { 746 th = ah; 747 } 748 749 /* Note that tcg optimization should eliminate the bl == 0 case. */ 750 if (is_sub) { 751 if (cbl) { 752 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 753 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 754 } else { 755 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 756 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 757 } 758 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 759 } else { 760 if (cbl) { 761 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 762 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 763 } else if (rl == al && rl == bl) { 764 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 765 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 766 } else { 767 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 768 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 769 } 770 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 771 } 772} 773 774/* Bit 0 set if inversion required; bit 1 set if swapping required. */ 775#define MIPS_CMP_INV 1 776#define MIPS_CMP_SWAP 2 777 778static const uint8_t mips_cmp_map[16] = { 779 [TCG_COND_LT] = 0, 780 [TCG_COND_LTU] = 0, 781 [TCG_COND_GE] = MIPS_CMP_INV, 782 [TCG_COND_GEU] = MIPS_CMP_INV, 783 [TCG_COND_LE] = MIPS_CMP_INV | MIPS_CMP_SWAP, 784 [TCG_COND_LEU] = MIPS_CMP_INV | MIPS_CMP_SWAP, 785 [TCG_COND_GT] = MIPS_CMP_SWAP, 786 [TCG_COND_GTU] = MIPS_CMP_SWAP, 787}; 788 789static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 790 TCGReg arg1, TCGReg arg2) 791{ 792 MIPSInsn s_opc = OPC_SLTU; 793 int cmp_map; 794 795 switch (cond) { 796 case TCG_COND_EQ: 797 if (arg2 != 0) { 798 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 799 arg1 = ret; 800 } 801 tcg_out_opc_imm(s, OPC_SLTIU, ret, arg1, 1); 802 break; 803 804 case TCG_COND_NE: 805 if (arg2 != 0) { 806 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 807 arg1 = ret; 808 } 809 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, arg1); 810 break; 811 812 case TCG_COND_LT: 813 case TCG_COND_GE: 814 case TCG_COND_LE: 815 case TCG_COND_GT: 816 s_opc = OPC_SLT; 817 /* FALLTHRU */ 818 819 case TCG_COND_LTU: 820 case TCG_COND_GEU: 821 case TCG_COND_LEU: 822 case TCG_COND_GTU: 823 cmp_map = mips_cmp_map[cond]; 824 if (cmp_map & MIPS_CMP_SWAP) { 825 TCGReg t = arg1; 826 arg1 = arg2; 827 arg2 = t; 828 } 829 tcg_out_opc_reg(s, s_opc, ret, arg1, arg2); 830 if (cmp_map & MIPS_CMP_INV) { 831 tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); 832 } 833 break; 834 835 default: 836 g_assert_not_reached(); 837 break; 838 } 839} 840 841static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 842 TCGReg arg2, TCGLabel *l) 843{ 844 static const MIPSInsn b_zero[16] = { 845 [TCG_COND_LT] = OPC_BLTZ, 846 [TCG_COND_GT] = OPC_BGTZ, 847 [TCG_COND_LE] = OPC_BLEZ, 848 [TCG_COND_GE] = OPC_BGEZ, 849 }; 850 851 MIPSInsn s_opc = OPC_SLTU; 852 MIPSInsn b_opc; 853 int cmp_map; 854 855 switch (cond) { 856 case TCG_COND_EQ: 857 b_opc = OPC_BEQ; 858 break; 859 case TCG_COND_NE: 860 b_opc = OPC_BNE; 861 break; 862 863 case TCG_COND_LT: 864 case TCG_COND_GT: 865 case TCG_COND_LE: 866 case TCG_COND_GE: 867 if (arg2 == 0) { 868 b_opc = b_zero[cond]; 869 arg2 = arg1; 870 arg1 = 0; 871 break; 872 } 873 s_opc = OPC_SLT; 874 /* FALLTHRU */ 875 876 case TCG_COND_LTU: 877 case TCG_COND_GTU: 878 case TCG_COND_LEU: 879 case TCG_COND_GEU: 880 cmp_map = mips_cmp_map[cond]; 881 if (cmp_map & MIPS_CMP_SWAP) { 882 TCGReg t = arg1; 883 arg1 = arg2; 884 arg2 = t; 885 } 886 tcg_out_opc_reg(s, s_opc, TCG_TMP0, arg1, arg2); 887 b_opc = (cmp_map & MIPS_CMP_INV ? OPC_BEQ : OPC_BNE); 888 arg1 = TCG_TMP0; 889 arg2 = TCG_REG_ZERO; 890 break; 891 892 default: 893 g_assert_not_reached(); 894 break; 895 } 896 897 tcg_out_opc_br(s, b_opc, arg1, arg2); 898 tcg_out_reloc(s, s->code_ptr - 1, R_MIPS_PC16, l, 0); 899 tcg_out_nop(s); 900} 901 902static TCGReg tcg_out_reduce_eq2(TCGContext *s, TCGReg tmp0, TCGReg tmp1, 903 TCGReg al, TCGReg ah, 904 TCGReg bl, TCGReg bh) 905{ 906 /* Merge highpart comparison into AH. */ 907 if (bh != 0) { 908 if (ah != 0) { 909 tcg_out_opc_reg(s, OPC_XOR, tmp0, ah, bh); 910 ah = tmp0; 911 } else { 912 ah = bh; 913 } 914 } 915 /* Merge lowpart comparison into AL. */ 916 if (bl != 0) { 917 if (al != 0) { 918 tcg_out_opc_reg(s, OPC_XOR, tmp1, al, bl); 919 al = tmp1; 920 } else { 921 al = bl; 922 } 923 } 924 /* Merge high and low part comparisons into AL. */ 925 if (ah != 0) { 926 if (al != 0) { 927 tcg_out_opc_reg(s, OPC_OR, tmp0, ah, al); 928 al = tmp0; 929 } else { 930 al = ah; 931 } 932 } 933 return al; 934} 935 936static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 937 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 938{ 939 TCGReg tmp0 = TCG_TMP0; 940 TCGReg tmp1 = ret; 941 942 tcg_debug_assert(ret != TCG_TMP0); 943 if (ret == ah || ret == bh) { 944 tcg_debug_assert(ret != TCG_TMP1); 945 tmp1 = TCG_TMP1; 946 } 947 948 switch (cond) { 949 case TCG_COND_EQ: 950 case TCG_COND_NE: 951 tmp1 = tcg_out_reduce_eq2(s, tmp0, tmp1, al, ah, bl, bh); 952 tcg_out_setcond(s, cond, ret, tmp1, TCG_REG_ZERO); 953 break; 954 955 default: 956 tcg_out_setcond(s, TCG_COND_EQ, tmp0, ah, bh); 957 tcg_out_setcond(s, tcg_unsigned_cond(cond), tmp1, al, bl); 958 tcg_out_opc_reg(s, OPC_AND, tmp1, tmp1, tmp0); 959 tcg_out_setcond(s, tcg_high_cond(cond), tmp0, ah, bh); 960 tcg_out_opc_reg(s, OPC_OR, ret, tmp1, tmp0); 961 break; 962 } 963} 964 965static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 966 TCGReg bl, TCGReg bh, TCGLabel *l) 967{ 968 TCGCond b_cond = TCG_COND_NE; 969 TCGReg tmp = TCG_TMP1; 970 971 /* With branches, we emit between 4 and 9 insns with 2 or 3 branches. 972 With setcond, we emit between 3 and 10 insns and only 1 branch, 973 which ought to get better branch prediction. */ 974 switch (cond) { 975 case TCG_COND_EQ: 976 case TCG_COND_NE: 977 b_cond = cond; 978 tmp = tcg_out_reduce_eq2(s, TCG_TMP0, TCG_TMP1, al, ah, bl, bh); 979 break; 980 981 default: 982 /* Minimize code size by preferring a compare not requiring INV. */ 983 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 984 cond = tcg_invert_cond(cond); 985 b_cond = TCG_COND_EQ; 986 } 987 tcg_out_setcond2(s, cond, tmp, al, ah, bl, bh); 988 break; 989 } 990 991 tcg_out_brcond(s, b_cond, tmp, TCG_REG_ZERO, l); 992} 993 994static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 995 TCGReg c1, TCGReg c2, TCGReg v1, TCGReg v2) 996{ 997 bool eqz = false; 998 999 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1000 if (use_mips32r6_instructions && v1 == 0) { 1001 v1 = v2; 1002 v2 = 0; 1003 cond = tcg_invert_cond(cond); 1004 } 1005 1006 switch (cond) { 1007 case TCG_COND_EQ: 1008 eqz = true; 1009 /* FALLTHRU */ 1010 case TCG_COND_NE: 1011 if (c2 != 0) { 1012 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, c1, c2); 1013 c1 = TCG_TMP0; 1014 } 1015 break; 1016 1017 default: 1018 /* Minimize code size by preferring a compare not requiring INV. */ 1019 if (mips_cmp_map[cond] & MIPS_CMP_INV) { 1020 cond = tcg_invert_cond(cond); 1021 eqz = true; 1022 } 1023 tcg_out_setcond(s, cond, TCG_TMP0, c1, c2); 1024 c1 = TCG_TMP0; 1025 break; 1026 } 1027 1028 if (use_mips32r6_instructions) { 1029 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1030 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1031 1032 if (v2 != 0) { 1033 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1034 } 1035 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1036 if (v2 != 0) { 1037 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1038 } 1039 } else { 1040 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1041 1042 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1043 1044 /* This should be guaranteed via constraints */ 1045 tcg_debug_assert(v2 == ret); 1046 } 1047} 1048 1049static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1050{ 1051 /* Note that the ABI requires the called function's address to be 1052 loaded into T9, even if a direct branch is in range. */ 1053 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1054 1055 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1056 if (tail) { 1057 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1058 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1059 } 1060 } else { 1061 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1062 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1063 } 1064 } 1065} 1066 1067static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1068 const TCGHelperInfo *info) 1069{ 1070 tcg_out_call_int(s, arg, false); 1071 tcg_out_nop(s); 1072} 1073 1074/* We have four temps, we might as well expose three of them. */ 1075static const TCGLdstHelperParam ldst_helper_param = { 1076 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1077}; 1078 1079static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1080{ 1081 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1082 MemOp opc = get_memop(l->oi); 1083 1084 /* resolve label address */ 1085 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1086 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1087 return false; 1088 } 1089 1090 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1091 1092 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1093 /* delay slot */ 1094 tcg_out_nop(s); 1095 1096 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1097 1098 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1099 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1100 return false; 1101 } 1102 1103 /* delay slot */ 1104 tcg_out_nop(s); 1105 return true; 1106} 1107 1108static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1109{ 1110 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1111 MemOp opc = get_memop(l->oi); 1112 1113 /* resolve label address */ 1114 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1115 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1116 return false; 1117 } 1118 1119 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1120 1121 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1122 /* delay slot */ 1123 tcg_out_nop(s); 1124 1125 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1126 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1127 return false; 1128 } 1129 1130 /* delay slot */ 1131 tcg_out_nop(s); 1132 return true; 1133} 1134 1135typedef struct { 1136 TCGReg base; 1137 TCGAtomAlign aa; 1138} HostAddress; 1139 1140bool tcg_target_has_memory_bswap(MemOp memop) 1141{ 1142 return false; 1143} 1144 1145/* 1146 * For softmmu, perform the TLB load and compare. 1147 * For useronly, perform any required alignment tests. 1148 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1149 * is required and fill in @h with the host address for the fast path. 1150 */ 1151static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1152 TCGReg addrlo, TCGReg addrhi, 1153 MemOpIdx oi, bool is_ld) 1154{ 1155 TCGType addr_type = s->addr_type; 1156 TCGLabelQemuLdst *ldst = NULL; 1157 MemOp opc = get_memop(oi); 1158 MemOp a_bits; 1159 unsigned s_bits = opc & MO_SIZE; 1160 unsigned a_mask; 1161 TCGReg base; 1162 1163 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1164 a_bits = h->aa.align; 1165 a_mask = (1 << a_bits) - 1; 1166 1167#ifdef CONFIG_SOFTMMU 1168 unsigned s_mask = (1 << s_bits) - 1; 1169 int mem_index = get_mmuidx(oi); 1170 int fast_off = TLB_MASK_TABLE_OFS(mem_index); 1171 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1172 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1173 int add_off = offsetof(CPUTLBEntry, addend); 1174 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1175 : offsetof(CPUTLBEntry, addr_write); 1176 1177 ldst = new_ldst_label(s); 1178 ldst->is_ld = is_ld; 1179 ldst->oi = oi; 1180 ldst->addrlo_reg = addrlo; 1181 ldst->addrhi_reg = addrhi; 1182 1183 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1184 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); 1185 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); 1186 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1187 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1188 1189 /* Extract the TLB index from the address into TMP3. */ 1190 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1191 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addrlo, 1192 s->page_bits - CPU_TLB_ENTRY_BITS); 1193 } else { 1194 tcg_out_dsrl(s, TCG_TMP3, addrlo, 1195 s->page_bits - CPU_TLB_ENTRY_BITS); 1196 } 1197 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1198 1199 /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ 1200 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1201 1202 if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { 1203 /* Load the tlb comparator. */ 1204 tcg_out_ld(s, addr_type, TCG_TMP0, TCG_TMP3, cmp_off); 1205 /* Load the tlb addend for the fast path. */ 1206 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1207 } else { 1208 /* Load the low half of the tlb comparator. */ 1209 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); 1210 } 1211 1212 /* 1213 * Mask the page bits, keeping the alignment bits to compare against. 1214 * For unaligned accesses, compare against the end of the access to 1215 * verify that it does not cross a page boundary. 1216 */ 1217 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1218 if (a_mask < s_mask) { 1219 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1220 tcg_out_opc_imm(s, OPC_ADDIU, TCG_TMP2, addrlo, s_mask - a_mask); 1221 } else { 1222 tcg_out_opc_imm(s, OPC_DADDIU, TCG_TMP2, addrlo, s_mask - a_mask); 1223 } 1224 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1225 } else { 1226 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addrlo); 1227 } 1228 1229 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1230 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1231 tcg_out_ext32u(s, TCG_TMP2, addrlo); 1232 addrlo = TCG_TMP2; 1233 } 1234 1235 ldst->label_ptr[0] = s->code_ptr; 1236 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1237 1238 /* Load and test the high half tlb comparator. */ 1239 if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { 1240 /* delay slot */ 1241 tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + HI_OFF); 1242 1243 /* Load the tlb addend for the fast path. */ 1244 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1245 1246 ldst->label_ptr[1] = s->code_ptr; 1247 tcg_out_opc_br(s, OPC_BNE, addrhi, TCG_TMP0); 1248 } 1249 1250 /* delay slot */ 1251 base = TCG_TMP3; 1252 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addrlo); 1253#else 1254 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1255 ldst = new_ldst_label(s); 1256 1257 ldst->is_ld = is_ld; 1258 ldst->oi = oi; 1259 ldst->addrlo_reg = addrlo; 1260 ldst->addrhi_reg = addrhi; 1261 1262 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1263 tcg_debug_assert(a_bits < 16); 1264 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addrlo, a_mask); 1265 1266 ldst->label_ptr[0] = s->code_ptr; 1267 if (use_mips32r6_instructions) { 1268 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1269 } else { 1270 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1271 tcg_out_nop(s); 1272 } 1273 } 1274 1275 base = addrlo; 1276 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1277 tcg_out_ext32u(s, TCG_REG_A0, base); 1278 base = TCG_REG_A0; 1279 } 1280 if (guest_base) { 1281 if (guest_base == (int16_t)guest_base) { 1282 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1283 } else { 1284 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1285 TCG_GUEST_BASE_REG); 1286 } 1287 base = TCG_REG_A0; 1288 } 1289#endif 1290 1291 h->base = base; 1292 return ldst; 1293} 1294 1295static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1296 TCGReg base, MemOp opc, TCGType type) 1297{ 1298 switch (opc & MO_SSIZE) { 1299 case MO_UB: 1300 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1301 break; 1302 case MO_SB: 1303 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1304 break; 1305 case MO_UW: 1306 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1307 break; 1308 case MO_SW: 1309 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1310 break; 1311 case MO_UL: 1312 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1313 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1314 break; 1315 } 1316 /* FALLTHRU */ 1317 case MO_SL: 1318 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1319 break; 1320 case MO_UQ: 1321 /* Prefer to load from offset 0 first, but allow for overlap. */ 1322 if (TCG_TARGET_REG_BITS == 64) { 1323 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1324 } else if (MIPS_BE ? hi != base : lo == base) { 1325 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1326 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1327 } else { 1328 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1329 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1330 } 1331 break; 1332 default: 1333 g_assert_not_reached(); 1334 } 1335} 1336 1337static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1338 TCGReg base, MemOp opc, TCGType type) 1339{ 1340 const MIPSInsn lw1 = MIPS_BE ? OPC_LWL : OPC_LWR; 1341 const MIPSInsn lw2 = MIPS_BE ? OPC_LWR : OPC_LWL; 1342 const MIPSInsn ld1 = MIPS_BE ? OPC_LDL : OPC_LDR; 1343 const MIPSInsn ld2 = MIPS_BE ? OPC_LDR : OPC_LDL; 1344 bool sgn = opc & MO_SIGN; 1345 1346 switch (opc & MO_SIZE) { 1347 case MO_16: 1348 if (HOST_BIG_ENDIAN) { 1349 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1350 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1351 if (use_mips32r2_instructions) { 1352 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1353 } else { 1354 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1355 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1356 } 1357 } else if (use_mips32r2_instructions && lo != base) { 1358 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1359 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1360 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1361 } else { 1362 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1363 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1364 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1365 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1366 } 1367 break; 1368 1369 case MO_32: 1370 tcg_out_opc_imm(s, lw1, lo, base, 0); 1371 tcg_out_opc_imm(s, lw2, lo, base, 3); 1372 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1373 tcg_out_ext32u(s, lo, lo); 1374 } 1375 break; 1376 1377 case MO_64: 1378 if (TCG_TARGET_REG_BITS == 64) { 1379 tcg_out_opc_imm(s, ld1, lo, base, 0); 1380 tcg_out_opc_imm(s, ld2, lo, base, 7); 1381 } else { 1382 tcg_out_opc_imm(s, lw1, MIPS_BE ? hi : lo, base, 0 + 0); 1383 tcg_out_opc_imm(s, lw2, MIPS_BE ? hi : lo, base, 0 + 3); 1384 tcg_out_opc_imm(s, lw1, MIPS_BE ? lo : hi, base, 4 + 0); 1385 tcg_out_opc_imm(s, lw2, MIPS_BE ? lo : hi, base, 4 + 3); 1386 } 1387 break; 1388 1389 default: 1390 g_assert_not_reached(); 1391 } 1392} 1393 1394static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1395 TCGReg addrlo, TCGReg addrhi, 1396 MemOpIdx oi, TCGType data_type) 1397{ 1398 MemOp opc = get_memop(oi); 1399 TCGLabelQemuLdst *ldst; 1400 HostAddress h; 1401 1402 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, true); 1403 1404 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1405 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1406 } else { 1407 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1408 } 1409 1410 if (ldst) { 1411 ldst->type = data_type; 1412 ldst->datalo_reg = datalo; 1413 ldst->datahi_reg = datahi; 1414 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1415 } 1416} 1417 1418static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1419 TCGReg base, MemOp opc) 1420{ 1421 switch (opc & MO_SIZE) { 1422 case MO_8: 1423 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1424 break; 1425 case MO_16: 1426 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1427 break; 1428 case MO_32: 1429 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1430 break; 1431 case MO_64: 1432 if (TCG_TARGET_REG_BITS == 64) { 1433 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1434 } else { 1435 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? hi : lo, base, 0); 1436 tcg_out_opc_imm(s, OPC_SW, MIPS_BE ? lo : hi, base, 4); 1437 } 1438 break; 1439 default: 1440 g_assert_not_reached(); 1441 } 1442} 1443 1444static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1445 TCGReg base, MemOp opc) 1446{ 1447 const MIPSInsn sw1 = MIPS_BE ? OPC_SWL : OPC_SWR; 1448 const MIPSInsn sw2 = MIPS_BE ? OPC_SWR : OPC_SWL; 1449 const MIPSInsn sd1 = MIPS_BE ? OPC_SDL : OPC_SDR; 1450 const MIPSInsn sd2 = MIPS_BE ? OPC_SDR : OPC_SDL; 1451 1452 switch (opc & MO_SIZE) { 1453 case MO_16: 1454 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1455 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1456 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1457 break; 1458 1459 case MO_32: 1460 tcg_out_opc_imm(s, sw1, lo, base, 0); 1461 tcg_out_opc_imm(s, sw2, lo, base, 3); 1462 break; 1463 1464 case MO_64: 1465 if (TCG_TARGET_REG_BITS == 64) { 1466 tcg_out_opc_imm(s, sd1, lo, base, 0); 1467 tcg_out_opc_imm(s, sd2, lo, base, 7); 1468 } else { 1469 tcg_out_opc_imm(s, sw1, MIPS_BE ? hi : lo, base, 0 + 0); 1470 tcg_out_opc_imm(s, sw2, MIPS_BE ? hi : lo, base, 0 + 3); 1471 tcg_out_opc_imm(s, sw1, MIPS_BE ? lo : hi, base, 4 + 0); 1472 tcg_out_opc_imm(s, sw2, MIPS_BE ? lo : hi, base, 4 + 3); 1473 } 1474 break; 1475 1476 default: 1477 g_assert_not_reached(); 1478 } 1479} 1480 1481static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1482 TCGReg addrlo, TCGReg addrhi, 1483 MemOpIdx oi, TCGType data_type) 1484{ 1485 MemOp opc = get_memop(oi); 1486 TCGLabelQemuLdst *ldst; 1487 HostAddress h; 1488 1489 ldst = prepare_host_addr(s, &h, addrlo, addrhi, oi, false); 1490 1491 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1492 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1493 } else { 1494 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1495 } 1496 1497 if (ldst) { 1498 ldst->type = data_type; 1499 ldst->datalo_reg = datalo; 1500 ldst->datahi_reg = datahi; 1501 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1502 } 1503} 1504 1505static void tcg_out_mb(TCGContext *s, TCGArg a0) 1506{ 1507 static const MIPSInsn sync[] = { 1508 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1509 as the former is an ordering barrier and the latter 1510 is a completion barrier. */ 1511 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1512 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1513 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1514 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1515 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1516 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1517 }; 1518 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1519} 1520 1521static void tcg_out_clz(TCGContext *s, MIPSInsn opcv2, MIPSInsn opcv6, 1522 int width, TCGReg a0, TCGReg a1, TCGArg a2) 1523{ 1524 if (use_mips32r6_instructions) { 1525 if (a2 == width) { 1526 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1527 } else { 1528 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1529 tcg_out_movcond(s, TCG_COND_EQ, a0, a1, 0, a2, TCG_TMP0); 1530 } 1531 } else { 1532 if (a2 == width) { 1533 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1534 } else if (a0 == a2) { 1535 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1536 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1537 } else if (a0 != a1) { 1538 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1539 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1540 } else { 1541 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1542 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1543 tcg_out_mov(s, TCG_TYPE_REG, a0, TCG_TMP0); 1544 } 1545 } 1546} 1547 1548static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1549{ 1550 TCGReg b0 = TCG_REG_ZERO; 1551 1552 if (a0 & ~0xffff) { 1553 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_V0, a0 & ~0xffff); 1554 b0 = TCG_REG_V0; 1555 } 1556 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1557 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1558 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1559 } 1560 tcg_out_opc_imm(s, OPC_ORI, TCG_REG_V0, b0, a0 & 0xffff); 1561} 1562 1563static void tcg_out_goto_tb(TCGContext *s, int which) 1564{ 1565 /* indirect jump method */ 1566 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_REG_ZERO, 1567 get_jmp_target_addr(s, which)); 1568 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1569 tcg_out_nop(s); 1570 set_jmp_reset_offset(s, which); 1571} 1572 1573void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1574 uintptr_t jmp_rx, uintptr_t jmp_rw) 1575{ 1576 /* Always indirect, nothing to do */ 1577} 1578 1579static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1580 const TCGArg args[TCG_MAX_OP_ARGS], 1581 const int const_args[TCG_MAX_OP_ARGS]) 1582{ 1583 MIPSInsn i1, i2; 1584 TCGArg a0, a1, a2; 1585 int c2; 1586 1587 /* 1588 * Note that many operands use the constraint set "rZ". 1589 * We make use of the fact that 0 is the ZERO register, 1590 * and hence such cases need not check for const_args. 1591 */ 1592 a0 = args[0]; 1593 a1 = args[1]; 1594 a2 = args[2]; 1595 c2 = const_args[2]; 1596 1597 switch (opc) { 1598 case INDEX_op_goto_ptr: 1599 /* jmp to the given host address (could be epilogue) */ 1600 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 1601 tcg_out_nop(s); 1602 break; 1603 case INDEX_op_br: 1604 tcg_out_brcond(s, TCG_COND_EQ, TCG_REG_ZERO, TCG_REG_ZERO, 1605 arg_label(a0)); 1606 break; 1607 1608 case INDEX_op_ld8u_i32: 1609 case INDEX_op_ld8u_i64: 1610 i1 = OPC_LBU; 1611 goto do_ldst; 1612 case INDEX_op_ld8s_i32: 1613 case INDEX_op_ld8s_i64: 1614 i1 = OPC_LB; 1615 goto do_ldst; 1616 case INDEX_op_ld16u_i32: 1617 case INDEX_op_ld16u_i64: 1618 i1 = OPC_LHU; 1619 goto do_ldst; 1620 case INDEX_op_ld16s_i32: 1621 case INDEX_op_ld16s_i64: 1622 i1 = OPC_LH; 1623 goto do_ldst; 1624 case INDEX_op_ld_i32: 1625 case INDEX_op_ld32s_i64: 1626 i1 = OPC_LW; 1627 goto do_ldst; 1628 case INDEX_op_ld32u_i64: 1629 i1 = OPC_LWU; 1630 goto do_ldst; 1631 case INDEX_op_ld_i64: 1632 i1 = OPC_LD; 1633 goto do_ldst; 1634 case INDEX_op_st8_i32: 1635 case INDEX_op_st8_i64: 1636 i1 = OPC_SB; 1637 goto do_ldst; 1638 case INDEX_op_st16_i32: 1639 case INDEX_op_st16_i64: 1640 i1 = OPC_SH; 1641 goto do_ldst; 1642 case INDEX_op_st_i32: 1643 case INDEX_op_st32_i64: 1644 i1 = OPC_SW; 1645 goto do_ldst; 1646 case INDEX_op_st_i64: 1647 i1 = OPC_SD; 1648 do_ldst: 1649 tcg_out_ldst(s, i1, a0, a1, a2); 1650 break; 1651 1652 case INDEX_op_add_i32: 1653 i1 = OPC_ADDU, i2 = OPC_ADDIU; 1654 goto do_binary; 1655 case INDEX_op_add_i64: 1656 i1 = OPC_DADDU, i2 = OPC_DADDIU; 1657 goto do_binary; 1658 case INDEX_op_or_i32: 1659 case INDEX_op_or_i64: 1660 i1 = OPC_OR, i2 = OPC_ORI; 1661 goto do_binary; 1662 case INDEX_op_xor_i32: 1663 case INDEX_op_xor_i64: 1664 i1 = OPC_XOR, i2 = OPC_XORI; 1665 do_binary: 1666 if (c2) { 1667 tcg_out_opc_imm(s, i2, a0, a1, a2); 1668 break; 1669 } 1670 do_binaryv: 1671 tcg_out_opc_reg(s, i1, a0, a1, a2); 1672 break; 1673 1674 case INDEX_op_sub_i32: 1675 i1 = OPC_SUBU, i2 = OPC_ADDIU; 1676 goto do_subtract; 1677 case INDEX_op_sub_i64: 1678 i1 = OPC_DSUBU, i2 = OPC_DADDIU; 1679 do_subtract: 1680 if (c2) { 1681 tcg_out_opc_imm(s, i2, a0, a1, -a2); 1682 break; 1683 } 1684 goto do_binaryv; 1685 case INDEX_op_and_i32: 1686 if (c2 && a2 != (uint16_t)a2) { 1687 int msb = ctz32(~a2) - 1; 1688 tcg_debug_assert(use_mips32r2_instructions); 1689 tcg_debug_assert(is_p2m1(a2)); 1690 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1691 break; 1692 } 1693 i1 = OPC_AND, i2 = OPC_ANDI; 1694 goto do_binary; 1695 case INDEX_op_and_i64: 1696 if (c2 && a2 != (uint16_t)a2) { 1697 int msb = ctz64(~a2) - 1; 1698 tcg_debug_assert(use_mips32r2_instructions); 1699 tcg_debug_assert(is_p2m1(a2)); 1700 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1701 break; 1702 } 1703 i1 = OPC_AND, i2 = OPC_ANDI; 1704 goto do_binary; 1705 case INDEX_op_nor_i32: 1706 case INDEX_op_nor_i64: 1707 i1 = OPC_NOR; 1708 goto do_binaryv; 1709 1710 case INDEX_op_mul_i32: 1711 if (use_mips32_instructions) { 1712 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1713 break; 1714 } 1715 i1 = OPC_MULT, i2 = OPC_MFLO; 1716 goto do_hilo1; 1717 case INDEX_op_mulsh_i32: 1718 if (use_mips32r6_instructions) { 1719 tcg_out_opc_reg(s, OPC_MUH, a0, a1, a2); 1720 break; 1721 } 1722 i1 = OPC_MULT, i2 = OPC_MFHI; 1723 goto do_hilo1; 1724 case INDEX_op_muluh_i32: 1725 if (use_mips32r6_instructions) { 1726 tcg_out_opc_reg(s, OPC_MUHU, a0, a1, a2); 1727 break; 1728 } 1729 i1 = OPC_MULTU, i2 = OPC_MFHI; 1730 goto do_hilo1; 1731 case INDEX_op_div_i32: 1732 if (use_mips32r6_instructions) { 1733 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1734 break; 1735 } 1736 i1 = OPC_DIV, i2 = OPC_MFLO; 1737 goto do_hilo1; 1738 case INDEX_op_divu_i32: 1739 if (use_mips32r6_instructions) { 1740 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1741 break; 1742 } 1743 i1 = OPC_DIVU, i2 = OPC_MFLO; 1744 goto do_hilo1; 1745 case INDEX_op_rem_i32: 1746 if (use_mips32r6_instructions) { 1747 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1748 break; 1749 } 1750 i1 = OPC_DIV, i2 = OPC_MFHI; 1751 goto do_hilo1; 1752 case INDEX_op_remu_i32: 1753 if (use_mips32r6_instructions) { 1754 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1755 break; 1756 } 1757 i1 = OPC_DIVU, i2 = OPC_MFHI; 1758 goto do_hilo1; 1759 case INDEX_op_mul_i64: 1760 if (use_mips32r6_instructions) { 1761 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1762 break; 1763 } 1764 i1 = OPC_DMULT, i2 = OPC_MFLO; 1765 goto do_hilo1; 1766 case INDEX_op_mulsh_i64: 1767 if (use_mips32r6_instructions) { 1768 tcg_out_opc_reg(s, OPC_DMUH, a0, a1, a2); 1769 break; 1770 } 1771 i1 = OPC_DMULT, i2 = OPC_MFHI; 1772 goto do_hilo1; 1773 case INDEX_op_muluh_i64: 1774 if (use_mips32r6_instructions) { 1775 tcg_out_opc_reg(s, OPC_DMUHU, a0, a1, a2); 1776 break; 1777 } 1778 i1 = OPC_DMULTU, i2 = OPC_MFHI; 1779 goto do_hilo1; 1780 case INDEX_op_div_i64: 1781 if (use_mips32r6_instructions) { 1782 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1783 break; 1784 } 1785 i1 = OPC_DDIV, i2 = OPC_MFLO; 1786 goto do_hilo1; 1787 case INDEX_op_divu_i64: 1788 if (use_mips32r6_instructions) { 1789 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1790 break; 1791 } 1792 i1 = OPC_DDIVU, i2 = OPC_MFLO; 1793 goto do_hilo1; 1794 case INDEX_op_rem_i64: 1795 if (use_mips32r6_instructions) { 1796 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1797 break; 1798 } 1799 i1 = OPC_DDIV, i2 = OPC_MFHI; 1800 goto do_hilo1; 1801 case INDEX_op_remu_i64: 1802 if (use_mips32r6_instructions) { 1803 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1804 break; 1805 } 1806 i1 = OPC_DDIVU, i2 = OPC_MFHI; 1807 do_hilo1: 1808 tcg_out_opc_reg(s, i1, 0, a1, a2); 1809 tcg_out_opc_reg(s, i2, a0, 0, 0); 1810 break; 1811 1812 case INDEX_op_muls2_i32: 1813 i1 = OPC_MULT; 1814 goto do_hilo2; 1815 case INDEX_op_mulu2_i32: 1816 i1 = OPC_MULTU; 1817 goto do_hilo2; 1818 case INDEX_op_muls2_i64: 1819 i1 = OPC_DMULT; 1820 goto do_hilo2; 1821 case INDEX_op_mulu2_i64: 1822 i1 = OPC_DMULTU; 1823 do_hilo2: 1824 tcg_out_opc_reg(s, i1, 0, a2, args[3]); 1825 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1826 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1827 break; 1828 1829 case INDEX_op_not_i32: 1830 case INDEX_op_not_i64: 1831 i1 = OPC_NOR; 1832 goto do_unary; 1833 do_unary: 1834 tcg_out_opc_reg(s, i1, a0, TCG_REG_ZERO, a1); 1835 break; 1836 1837 case INDEX_op_bswap16_i32: 1838 case INDEX_op_bswap16_i64: 1839 tcg_out_bswap16(s, a0, a1, a2); 1840 break; 1841 case INDEX_op_bswap32_i32: 1842 tcg_out_bswap32(s, a0, a1, 0); 1843 break; 1844 case INDEX_op_bswap32_i64: 1845 tcg_out_bswap32(s, a0, a1, a2); 1846 break; 1847 case INDEX_op_bswap64_i64: 1848 tcg_out_bswap64(s, a0, a1); 1849 break; 1850 case INDEX_op_extrh_i64_i32: 1851 tcg_out_dsra(s, a0, a1, 32); 1852 break; 1853 1854 case INDEX_op_sar_i32: 1855 i1 = OPC_SRAV, i2 = OPC_SRA; 1856 goto do_shift; 1857 case INDEX_op_shl_i32: 1858 i1 = OPC_SLLV, i2 = OPC_SLL; 1859 goto do_shift; 1860 case INDEX_op_shr_i32: 1861 i1 = OPC_SRLV, i2 = OPC_SRL; 1862 goto do_shift; 1863 case INDEX_op_rotr_i32: 1864 i1 = OPC_ROTRV, i2 = OPC_ROTR; 1865 do_shift: 1866 if (c2) { 1867 tcg_out_opc_sa(s, i2, a0, a1, a2); 1868 break; 1869 } 1870 do_shiftv: 1871 tcg_out_opc_reg(s, i1, a0, a2, a1); 1872 break; 1873 case INDEX_op_rotl_i32: 1874 if (c2) { 1875 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, 32 - a2); 1876 } else { 1877 tcg_out_opc_reg(s, OPC_SUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1878 tcg_out_opc_reg(s, OPC_ROTRV, a0, TCG_TMP0, a1); 1879 } 1880 break; 1881 case INDEX_op_sar_i64: 1882 if (c2) { 1883 tcg_out_dsra(s, a0, a1, a2); 1884 break; 1885 } 1886 i1 = OPC_DSRAV; 1887 goto do_shiftv; 1888 case INDEX_op_shl_i64: 1889 if (c2) { 1890 tcg_out_dsll(s, a0, a1, a2); 1891 break; 1892 } 1893 i1 = OPC_DSLLV; 1894 goto do_shiftv; 1895 case INDEX_op_shr_i64: 1896 if (c2) { 1897 tcg_out_dsrl(s, a0, a1, a2); 1898 break; 1899 } 1900 i1 = OPC_DSRLV; 1901 goto do_shiftv; 1902 case INDEX_op_rotr_i64: 1903 if (c2) { 1904 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 1905 break; 1906 } 1907 i1 = OPC_DROTRV; 1908 goto do_shiftv; 1909 case INDEX_op_rotl_i64: 1910 if (c2) { 1911 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, 64 - a2); 1912 } else { 1913 tcg_out_opc_reg(s, OPC_DSUBU, TCG_TMP0, TCG_REG_ZERO, a2); 1914 tcg_out_opc_reg(s, OPC_DROTRV, a0, TCG_TMP0, a1); 1915 } 1916 break; 1917 1918 case INDEX_op_clz_i32: 1919 tcg_out_clz(s, OPC_CLZ, OPC_CLZ_R6, 32, a0, a1, a2); 1920 break; 1921 case INDEX_op_clz_i64: 1922 tcg_out_clz(s, OPC_DCLZ, OPC_DCLZ_R6, 64, a0, a1, a2); 1923 break; 1924 1925 case INDEX_op_deposit_i32: 1926 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 1927 break; 1928 case INDEX_op_deposit_i64: 1929 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 1930 args[3] + args[4] - 1, args[3]); 1931 break; 1932 case INDEX_op_extract_i32: 1933 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 1934 break; 1935 case INDEX_op_extract_i64: 1936 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, 1937 args[3] - 1, a2); 1938 break; 1939 1940 case INDEX_op_brcond_i32: 1941 case INDEX_op_brcond_i64: 1942 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1943 break; 1944 case INDEX_op_brcond2_i32: 1945 tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); 1946 break; 1947 1948 case INDEX_op_movcond_i32: 1949 case INDEX_op_movcond_i64: 1950 tcg_out_movcond(s, args[5], a0, a1, a2, args[3], args[4]); 1951 break; 1952 1953 case INDEX_op_setcond_i32: 1954 case INDEX_op_setcond_i64: 1955 tcg_out_setcond(s, args[3], a0, a1, a2); 1956 break; 1957 case INDEX_op_setcond2_i32: 1958 tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); 1959 break; 1960 1961 case INDEX_op_qemu_ld_a64_i32: 1962 if (TCG_TARGET_REG_BITS == 32) { 1963 tcg_out_qemu_ld(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 1964 break; 1965 } 1966 /* fall through */ 1967 case INDEX_op_qemu_ld_a32_i32: 1968 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 1969 break; 1970 case INDEX_op_qemu_ld_a32_i64: 1971 if (TCG_TARGET_REG_BITS == 64) { 1972 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 1973 } else { 1974 tcg_out_qemu_ld(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 1975 } 1976 break; 1977 case INDEX_op_qemu_ld_a64_i64: 1978 if (TCG_TARGET_REG_BITS == 64) { 1979 tcg_out_qemu_ld(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 1980 } else { 1981 tcg_out_qemu_ld(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 1982 } 1983 break; 1984 1985 case INDEX_op_qemu_st_a64_i32: 1986 if (TCG_TARGET_REG_BITS == 32) { 1987 tcg_out_qemu_st(s, a0, 0, a1, a2, args[3], TCG_TYPE_I32); 1988 break; 1989 } 1990 /* fall through */ 1991 case INDEX_op_qemu_st_a32_i32: 1992 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I32); 1993 break; 1994 case INDEX_op_qemu_st_a32_i64: 1995 if (TCG_TARGET_REG_BITS == 64) { 1996 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 1997 } else { 1998 tcg_out_qemu_st(s, a0, a1, a2, 0, args[3], TCG_TYPE_I64); 1999 } 2000 break; 2001 case INDEX_op_qemu_st_a64_i64: 2002 if (TCG_TARGET_REG_BITS == 64) { 2003 tcg_out_qemu_st(s, a0, 0, a1, 0, a2, TCG_TYPE_I64); 2004 } else { 2005 tcg_out_qemu_st(s, a0, a1, a2, args[3], args[4], TCG_TYPE_I64); 2006 } 2007 break; 2008 2009 case INDEX_op_add2_i32: 2010 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2011 const_args[4], const_args[5], false); 2012 break; 2013 case INDEX_op_sub2_i32: 2014 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2015 const_args[4], const_args[5], true); 2016 break; 2017 2018 case INDEX_op_mb: 2019 tcg_out_mb(s, a0); 2020 break; 2021 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 2022 case INDEX_op_mov_i64: 2023 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2024 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2025 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2026 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 2027 case INDEX_op_ext8s_i64: 2028 case INDEX_op_ext8u_i32: 2029 case INDEX_op_ext8u_i64: 2030 case INDEX_op_ext16s_i32: 2031 case INDEX_op_ext16s_i64: 2032 case INDEX_op_ext32s_i64: 2033 case INDEX_op_ext32u_i64: 2034 case INDEX_op_ext_i32_i64: 2035 case INDEX_op_extu_i32_i64: 2036 case INDEX_op_extrl_i64_i32: 2037 default: 2038 g_assert_not_reached(); 2039 } 2040} 2041 2042static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2043{ 2044 switch (op) { 2045 case INDEX_op_goto_ptr: 2046 return C_O0_I1(r); 2047 2048 case INDEX_op_ld8u_i32: 2049 case INDEX_op_ld8s_i32: 2050 case INDEX_op_ld16u_i32: 2051 case INDEX_op_ld16s_i32: 2052 case INDEX_op_ld_i32: 2053 case INDEX_op_not_i32: 2054 case INDEX_op_bswap16_i32: 2055 case INDEX_op_bswap32_i32: 2056 case INDEX_op_ext8s_i32: 2057 case INDEX_op_ext16s_i32: 2058 case INDEX_op_extract_i32: 2059 case INDEX_op_ld8u_i64: 2060 case INDEX_op_ld8s_i64: 2061 case INDEX_op_ld16u_i64: 2062 case INDEX_op_ld16s_i64: 2063 case INDEX_op_ld32s_i64: 2064 case INDEX_op_ld32u_i64: 2065 case INDEX_op_ld_i64: 2066 case INDEX_op_not_i64: 2067 case INDEX_op_bswap16_i64: 2068 case INDEX_op_bswap32_i64: 2069 case INDEX_op_bswap64_i64: 2070 case INDEX_op_ext8s_i64: 2071 case INDEX_op_ext16s_i64: 2072 case INDEX_op_ext32s_i64: 2073 case INDEX_op_ext32u_i64: 2074 case INDEX_op_ext_i32_i64: 2075 case INDEX_op_extu_i32_i64: 2076 case INDEX_op_extrl_i64_i32: 2077 case INDEX_op_extrh_i64_i32: 2078 case INDEX_op_extract_i64: 2079 return C_O1_I1(r, r); 2080 2081 case INDEX_op_st8_i32: 2082 case INDEX_op_st16_i32: 2083 case INDEX_op_st_i32: 2084 case INDEX_op_st8_i64: 2085 case INDEX_op_st16_i64: 2086 case INDEX_op_st32_i64: 2087 case INDEX_op_st_i64: 2088 return C_O0_I2(rZ, r); 2089 2090 case INDEX_op_add_i32: 2091 case INDEX_op_add_i64: 2092 return C_O1_I2(r, r, rJ); 2093 case INDEX_op_sub_i32: 2094 case INDEX_op_sub_i64: 2095 return C_O1_I2(r, rZ, rN); 2096 case INDEX_op_mul_i32: 2097 case INDEX_op_mulsh_i32: 2098 case INDEX_op_muluh_i32: 2099 case INDEX_op_div_i32: 2100 case INDEX_op_divu_i32: 2101 case INDEX_op_rem_i32: 2102 case INDEX_op_remu_i32: 2103 case INDEX_op_nor_i32: 2104 case INDEX_op_setcond_i32: 2105 case INDEX_op_mul_i64: 2106 case INDEX_op_mulsh_i64: 2107 case INDEX_op_muluh_i64: 2108 case INDEX_op_div_i64: 2109 case INDEX_op_divu_i64: 2110 case INDEX_op_rem_i64: 2111 case INDEX_op_remu_i64: 2112 case INDEX_op_nor_i64: 2113 case INDEX_op_setcond_i64: 2114 return C_O1_I2(r, rZ, rZ); 2115 case INDEX_op_muls2_i32: 2116 case INDEX_op_mulu2_i32: 2117 case INDEX_op_muls2_i64: 2118 case INDEX_op_mulu2_i64: 2119 return C_O2_I2(r, r, r, r); 2120 case INDEX_op_and_i32: 2121 case INDEX_op_and_i64: 2122 return C_O1_I2(r, r, rIK); 2123 case INDEX_op_or_i32: 2124 case INDEX_op_xor_i32: 2125 case INDEX_op_or_i64: 2126 case INDEX_op_xor_i64: 2127 return C_O1_I2(r, r, rI); 2128 case INDEX_op_shl_i32: 2129 case INDEX_op_shr_i32: 2130 case INDEX_op_sar_i32: 2131 case INDEX_op_rotr_i32: 2132 case INDEX_op_rotl_i32: 2133 case INDEX_op_shl_i64: 2134 case INDEX_op_shr_i64: 2135 case INDEX_op_sar_i64: 2136 case INDEX_op_rotr_i64: 2137 case INDEX_op_rotl_i64: 2138 return C_O1_I2(r, r, ri); 2139 case INDEX_op_clz_i32: 2140 case INDEX_op_clz_i64: 2141 return C_O1_I2(r, r, rWZ); 2142 2143 case INDEX_op_deposit_i32: 2144 case INDEX_op_deposit_i64: 2145 return C_O1_I2(r, 0, rZ); 2146 case INDEX_op_brcond_i32: 2147 case INDEX_op_brcond_i64: 2148 return C_O0_I2(rZ, rZ); 2149 case INDEX_op_movcond_i32: 2150 case INDEX_op_movcond_i64: 2151 return (use_mips32r6_instructions 2152 ? C_O1_I4(r, rZ, rZ, rZ, rZ) 2153 : C_O1_I4(r, rZ, rZ, rZ, 0)); 2154 case INDEX_op_add2_i32: 2155 case INDEX_op_sub2_i32: 2156 return C_O2_I4(r, r, rZ, rZ, rN, rN); 2157 case INDEX_op_setcond2_i32: 2158 return C_O1_I4(r, rZ, rZ, rZ, rZ); 2159 case INDEX_op_brcond2_i32: 2160 return C_O0_I4(rZ, rZ, rZ, rZ); 2161 2162 case INDEX_op_qemu_ld_a32_i32: 2163 return C_O1_I1(r, r); 2164 case INDEX_op_qemu_ld_a64_i32: 2165 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O1_I2(r, r, r); 2166 case INDEX_op_qemu_st_a32_i32: 2167 return C_O0_I2(rZ, r); 2168 case INDEX_op_qemu_st_a64_i32: 2169 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, r, r); 2170 case INDEX_op_qemu_ld_a32_i64: 2171 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2172 case INDEX_op_qemu_ld_a64_i64: 2173 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I2(r, r, r, r); 2174 case INDEX_op_qemu_st_a32_i64: 2175 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) : C_O0_I3(rZ, rZ, r); 2176 case INDEX_op_qemu_st_a64_i64: 2177 return (TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rZ, r) 2178 : C_O0_I4(rZ, rZ, r, r)); 2179 2180 default: 2181 g_assert_not_reached(); 2182 } 2183} 2184 2185static const int tcg_target_callee_save_regs[] = { 2186 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2187 TCG_REG_S1, 2188 TCG_REG_S2, 2189 TCG_REG_S3, 2190 TCG_REG_S4, 2191 TCG_REG_S5, 2192 TCG_REG_S6, 2193 TCG_REG_S7, 2194 TCG_REG_S8, 2195 TCG_REG_RA, /* should be last for ABI compliance */ 2196}; 2197 2198/* The Linux kernel doesn't provide any information about the available 2199 instruction set. Probe it using a signal handler. */ 2200 2201 2202#ifndef use_movnz_instructions 2203bool use_movnz_instructions = false; 2204#endif 2205 2206#ifndef use_mips32_instructions 2207bool use_mips32_instructions = false; 2208#endif 2209 2210#ifndef use_mips32r2_instructions 2211bool use_mips32r2_instructions = false; 2212#endif 2213 2214static volatile sig_atomic_t got_sigill; 2215 2216static void sigill_handler(int signo, siginfo_t *si, void *data) 2217{ 2218 /* Skip the faulty instruction */ 2219 ucontext_t *uc = (ucontext_t *)data; 2220 uc->uc_mcontext.pc += 4; 2221 2222 got_sigill = 1; 2223} 2224 2225static void tcg_target_detect_isa(void) 2226{ 2227 struct sigaction sa_old, sa_new; 2228 2229 memset(&sa_new, 0, sizeof(sa_new)); 2230 sa_new.sa_flags = SA_SIGINFO; 2231 sa_new.sa_sigaction = sigill_handler; 2232 sigaction(SIGILL, &sa_new, &sa_old); 2233 2234 /* Probe for movn/movz, necessary to implement movcond. */ 2235#ifndef use_movnz_instructions 2236 got_sigill = 0; 2237 asm volatile(".set push\n" 2238 ".set mips32\n" 2239 "movn $zero, $zero, $zero\n" 2240 "movz $zero, $zero, $zero\n" 2241 ".set pop\n" 2242 : : : ); 2243 use_movnz_instructions = !got_sigill; 2244#endif 2245 2246 /* Probe for MIPS32 instructions. As no subsetting is allowed 2247 by the specification, it is only necessary to probe for one 2248 of the instructions. */ 2249#ifndef use_mips32_instructions 2250 got_sigill = 0; 2251 asm volatile(".set push\n" 2252 ".set mips32\n" 2253 "mul $zero, $zero\n" 2254 ".set pop\n" 2255 : : : ); 2256 use_mips32_instructions = !got_sigill; 2257#endif 2258 2259 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2260 available. As no subsetting is allowed by the specification, 2261 it is only necessary to probe for one of the instructions. */ 2262#ifndef use_mips32r2_instructions 2263 if (use_mips32_instructions) { 2264 got_sigill = 0; 2265 asm volatile(".set push\n" 2266 ".set mips32r2\n" 2267 "seb $zero, $zero\n" 2268 ".set pop\n" 2269 : : : ); 2270 use_mips32r2_instructions = !got_sigill; 2271 } 2272#endif 2273 2274 sigaction(SIGILL, &sa_old, NULL); 2275} 2276 2277static tcg_insn_unit *align_code_ptr(TCGContext *s) 2278{ 2279 uintptr_t p = (uintptr_t)s->code_ptr; 2280 if (p & 15) { 2281 p = (p + 15) & -16; 2282 s->code_ptr = (void *)p; 2283 } 2284 return s->code_ptr; 2285} 2286 2287/* Stack frame parameters. */ 2288#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2289#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2290#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2291 2292#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2293 + TCG_TARGET_STACK_ALIGN - 1) \ 2294 & -TCG_TARGET_STACK_ALIGN) 2295#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2296 2297/* We're expecting to be able to use an immediate for frame allocation. */ 2298QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2299 2300/* Generate global QEMU prologue and epilogue code */ 2301static void tcg_target_qemu_prologue(TCGContext *s) 2302{ 2303 int i; 2304 2305 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2306 2307 /* TB prologue */ 2308 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2309 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2310 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2311 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2312 } 2313 2314#ifndef CONFIG_SOFTMMU 2315 if (guest_base) { 2316 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2317 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2318 } 2319#endif 2320 2321 /* Call generated code */ 2322 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2323 /* delay slot */ 2324 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2325 2326 /* 2327 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2328 * and fall through to the rest of the epilogue. 2329 */ 2330 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2331 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2332 2333 /* TB epilogue */ 2334 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2335 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2336 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2337 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2338 } 2339 2340 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2341 /* delay slot */ 2342 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2343 2344 if (use_mips32r2_instructions) { 2345 return; 2346 } 2347 2348 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2349 clobbers TCG_TMP1, TCG_TMP2. */ 2350 2351 /* 2352 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2353 */ 2354 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2355 /* t3 = (ssss)d000 */ 2356 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2357 /* t1 = 000a */ 2358 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2359 /* t2 = 00c0 */ 2360 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2361 /* t3 = d00a */ 2362 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2363 /* t1 = 0abc */ 2364 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2365 /* t2 = 0c00 */ 2366 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2367 /* t1 = 00b0 */ 2368 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2369 /* t3 = dc0a */ 2370 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2371 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2372 /* t3 = dcba -- delay slot */ 2373 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2374 2375 if (TCG_TARGET_REG_BITS == 32) { 2376 return; 2377 } 2378 2379 /* 2380 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2381 */ 2382 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2383 /* t1 = (0000)000d */ 2384 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2385 /* t3 = 000a */ 2386 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2387 /* t1 = (0000)d000 */ 2388 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2389 /* t2 = 00c0 */ 2390 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2391 /* t3 = d00a */ 2392 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2393 /* t1 = 0abc */ 2394 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2395 /* t2 = 0c00 */ 2396 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2397 /* t1 = 00b0 */ 2398 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2399 /* t3 = dc0a */ 2400 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2401 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2402 /* t3 = dcba -- delay slot */ 2403 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2404 2405 /* 2406 * bswap64 -- 64-bit swap. a0 = abcdefgh 2407 */ 2408 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2409 /* t3 = h0000000 */ 2410 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2411 /* t1 = 0000000a */ 2412 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2413 2414 /* t2 = 000000g0 */ 2415 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2416 /* t3 = h000000a */ 2417 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2418 /* t1 = 00000abc */ 2419 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2420 /* t2 = 0g000000 */ 2421 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2422 /* t1 = 000000b0 */ 2423 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2424 2425 /* t3 = hg00000a */ 2426 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2427 /* t2 = 0000abcd */ 2428 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2429 /* t3 = hg0000ba */ 2430 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2431 2432 /* t1 = 000000c0 */ 2433 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2434 /* t2 = 0000000d */ 2435 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2436 /* t1 = 00000c00 */ 2437 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2438 /* t2 = 0000d000 */ 2439 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2440 2441 /* t3 = hg000cba */ 2442 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2443 /* t1 = 00abcdef */ 2444 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2445 /* t3 = hg00dcba */ 2446 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2447 2448 /* t2 = 0000000f */ 2449 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2450 /* t1 = 000000e0 */ 2451 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2452 /* t2 = 00f00000 */ 2453 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2454 /* t1 = 000e0000 */ 2455 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2456 2457 /* t3 = hgf0dcba */ 2458 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2459 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2460 /* t3 = hgfedcba -- delay slot */ 2461 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2462} 2463 2464static void tcg_target_init(TCGContext *s) 2465{ 2466 tcg_target_detect_isa(); 2467 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2468 if (TCG_TARGET_REG_BITS == 64) { 2469 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2470 } 2471 2472 tcg_target_call_clobber_regs = 0; 2473 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2474 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2475 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2476 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2477 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2478 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2479 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2480 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2481 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2482 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2483 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2484 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2485 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2486 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2487 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2488 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2489 2490 s->reserved_regs = 0; 2491 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2492 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2493 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2494 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2495 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2496 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2497 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2498 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2499 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2500 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2501} 2502 2503typedef struct { 2504 DebugFrameHeader h; 2505 uint8_t fde_def_cfa[4]; 2506 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2507} DebugFrame; 2508 2509#define ELF_HOST_MACHINE EM_MIPS 2510/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2511 which is good because they're really quite complicated for MIPS. */ 2512 2513static const DebugFrame debug_frame = { 2514 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2515 .h.cie.id = -1, 2516 .h.cie.version = 1, 2517 .h.cie.code_align = 1, 2518 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2519 .h.cie.return_column = TCG_REG_RA, 2520 2521 /* Total FDE size does not include the "len" member. */ 2522 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2523 2524 .fde_def_cfa = { 2525 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2526 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2527 (FRAME_SIZE >> 7) 2528 }, 2529 .fde_reg_ofs = { 2530 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2531 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2532 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2533 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2534 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2535 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2536 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2537 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2538 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2539 } 2540}; 2541 2542void tcg_register_jit(const void *buf, size_t buf_size) 2543{ 2544 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2545} 2546