1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27/* used for function call generation */ 28#define TCG_TARGET_STACK_ALIGN 16 29#if _MIPS_SIM == _ABIO32 30# define TCG_TARGET_CALL_STACK_OFFSET 16 31# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_EVEN 32# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_BY_REF 33#else 34# define TCG_TARGET_CALL_STACK_OFFSET 0 35# define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 36# define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 37#endif 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_EVEN 40 41#if TCG_TARGET_REG_BITS == 32 42# define LO_OFF (HOST_BIG_ENDIAN * 4) 43# define HI_OFF (4 - LO_OFF) 44#else 45/* Assert at compile-time that these values are never used for 64-bit. */ 46# define LO_OFF ({ qemu_build_not_reached(); 0; }) 47# define HI_OFF ({ qemu_build_not_reached(); 0; }) 48#endif 49 50#ifdef CONFIG_DEBUG_TCG 51static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 52 "zero", 53 "at", 54 "v0", 55 "v1", 56 "a0", 57 "a1", 58 "a2", 59 "a3", 60 "t0", 61 "t1", 62 "t2", 63 "t3", 64 "t4", 65 "t5", 66 "t6", 67 "t7", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "t8", 77 "t9", 78 "k0", 79 "k1", 80 "gp", 81 "sp", 82 "s8", 83 "ra", 84}; 85#endif 86 87#define TCG_TMP0 TCG_REG_AT 88#define TCG_TMP1 TCG_REG_T9 89#define TCG_TMP2 TCG_REG_T8 90#define TCG_TMP3 TCG_REG_T7 91 92#define TCG_GUEST_BASE_REG TCG_REG_S7 93#if TCG_TARGET_REG_BITS == 64 94#define TCG_REG_TB TCG_REG_S6 95#else 96#define TCG_REG_TB ({ qemu_build_not_reached(); TCG_REG_ZERO; }) 97#endif 98 99/* check if we really need so many registers :P */ 100static const int tcg_target_reg_alloc_order[] = { 101 /* Call saved registers. */ 102 TCG_REG_S0, 103 TCG_REG_S1, 104 TCG_REG_S2, 105 TCG_REG_S3, 106 TCG_REG_S4, 107 TCG_REG_S5, 108 TCG_REG_S6, 109 TCG_REG_S7, 110 TCG_REG_S8, 111 112 /* Call clobbered registers. */ 113 TCG_REG_T4, 114 TCG_REG_T5, 115 TCG_REG_T6, 116 TCG_REG_T7, 117 TCG_REG_T8, 118 TCG_REG_T9, 119 TCG_REG_V1, 120 TCG_REG_V0, 121 122 /* Argument registers, opposite order of allocation. */ 123 TCG_REG_T3, 124 TCG_REG_T2, 125 TCG_REG_T1, 126 TCG_REG_T0, 127 TCG_REG_A3, 128 TCG_REG_A2, 129 TCG_REG_A1, 130 TCG_REG_A0, 131}; 132 133static const TCGReg tcg_target_call_iarg_regs[] = { 134 TCG_REG_A0, 135 TCG_REG_A1, 136 TCG_REG_A2, 137 TCG_REG_A3, 138#if _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 139 TCG_REG_T0, 140 TCG_REG_T1, 141 TCG_REG_T2, 142 TCG_REG_T3, 143#endif 144}; 145 146static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 147{ 148 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 149 tcg_debug_assert(slot >= 0 && slot <= 1); 150 return TCG_REG_V0 + slot; 151} 152 153static const tcg_insn_unit *tb_ret_addr; 154static const tcg_insn_unit *bswap32_addr; 155static const tcg_insn_unit *bswap32u_addr; 156static const tcg_insn_unit *bswap64_addr; 157 158static bool reloc_pc16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 159{ 160 /* Let the compiler perform the right-shift as part of the arithmetic. */ 161 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 162 ptrdiff_t disp = target - (src_rx + 1); 163 if (disp == (int16_t)disp) { 164 *src_rw = deposit32(*src_rw, 0, 16, disp); 165 return true; 166 } 167 return false; 168} 169 170static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 171 intptr_t value, intptr_t addend) 172{ 173 value += addend; 174 switch (type) { 175 case R_MIPS_PC16: 176 return reloc_pc16(code_ptr, (const tcg_insn_unit *)value); 177 case R_MIPS_16: 178 if (value != (int16_t)value) { 179 return false; 180 } 181 *code_ptr = deposit32(*code_ptr, 0, 16, value); 182 return true; 183 } 184 g_assert_not_reached(); 185} 186 187#define TCG_CT_CONST_U16 0x100 /* Unsigned 16-bit: 0 - 0xffff. */ 188#define TCG_CT_CONST_S16 0x200 /* Signed 16-bit: -32768 - 32767 */ 189#define TCG_CT_CONST_P2M1 0x400 /* Power of 2 minus 1. */ 190#define TCG_CT_CONST_N16 0x800 /* "Negatable" 16-bit: -32767 - 32767 */ 191#define TCG_CT_CONST_WSZ 0x1000 /* word size */ 192 193#define ALL_GENERAL_REGS 0xffffffffu 194 195static bool is_p2m1(tcg_target_long val) 196{ 197 return val && ((val + 1) & val) == 0; 198} 199 200/* test if a constant matches the constraint */ 201static bool tcg_target_const_match(int64_t val, int ct, 202 TCGType type, TCGCond cond, int vece) 203{ 204 if (ct & TCG_CT_CONST) { 205 return 1; 206 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) { 207 return 1; 208 } else if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) { 209 return 1; 210 } else if ((ct & TCG_CT_CONST_N16) && val >= -32767 && val <= 32767) { 211 return 1; 212 } else if ((ct & TCG_CT_CONST_P2M1) 213 && use_mips32r2_instructions && is_p2m1(val)) { 214 return 1; 215 } else if ((ct & TCG_CT_CONST_WSZ) 216 && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 217 return 1; 218 } 219 return 0; 220} 221 222/* instruction opcodes */ 223typedef enum { 224 OPC_J = 002 << 26, 225 OPC_JAL = 003 << 26, 226 OPC_BEQ = 004 << 26, 227 OPC_BNE = 005 << 26, 228 OPC_BLEZ = 006 << 26, 229 OPC_BGTZ = 007 << 26, 230 OPC_ADDIU = 011 << 26, 231 OPC_SLTI = 012 << 26, 232 OPC_SLTIU = 013 << 26, 233 OPC_ANDI = 014 << 26, 234 OPC_ORI = 015 << 26, 235 OPC_XORI = 016 << 26, 236 OPC_LUI = 017 << 26, 237 OPC_BNEL = 025 << 26, 238 OPC_BNEZALC_R6 = 030 << 26, 239 OPC_DADDIU = 031 << 26, 240 OPC_LDL = 032 << 26, 241 OPC_LDR = 033 << 26, 242 OPC_LB = 040 << 26, 243 OPC_LH = 041 << 26, 244 OPC_LWL = 042 << 26, 245 OPC_LW = 043 << 26, 246 OPC_LBU = 044 << 26, 247 OPC_LHU = 045 << 26, 248 OPC_LWR = 046 << 26, 249 OPC_LWU = 047 << 26, 250 OPC_SB = 050 << 26, 251 OPC_SH = 051 << 26, 252 OPC_SWL = 052 << 26, 253 OPC_SW = 053 << 26, 254 OPC_SDL = 054 << 26, 255 OPC_SDR = 055 << 26, 256 OPC_SWR = 056 << 26, 257 OPC_LD = 067 << 26, 258 OPC_SD = 077 << 26, 259 260 OPC_SPECIAL = 000 << 26, 261 OPC_SLL = OPC_SPECIAL | 000, 262 OPC_SRL = OPC_SPECIAL | 002, 263 OPC_ROTR = OPC_SPECIAL | 002 | (1 << 21), 264 OPC_SRA = OPC_SPECIAL | 003, 265 OPC_SLLV = OPC_SPECIAL | 004, 266 OPC_SRLV = OPC_SPECIAL | 006, 267 OPC_ROTRV = OPC_SPECIAL | 006 | 0100, 268 OPC_SRAV = OPC_SPECIAL | 007, 269 OPC_JR_R5 = OPC_SPECIAL | 010, 270 OPC_JALR = OPC_SPECIAL | 011, 271 OPC_MOVZ = OPC_SPECIAL | 012, 272 OPC_MOVN = OPC_SPECIAL | 013, 273 OPC_SYNC = OPC_SPECIAL | 017, 274 OPC_MFHI = OPC_SPECIAL | 020, 275 OPC_MFLO = OPC_SPECIAL | 022, 276 OPC_DSLLV = OPC_SPECIAL | 024, 277 OPC_DSRLV = OPC_SPECIAL | 026, 278 OPC_DROTRV = OPC_SPECIAL | 026 | 0100, 279 OPC_DSRAV = OPC_SPECIAL | 027, 280 OPC_MULT = OPC_SPECIAL | 030, 281 OPC_MUL_R6 = OPC_SPECIAL | 030 | 0200, 282 OPC_MUH = OPC_SPECIAL | 030 | 0300, 283 OPC_MULTU = OPC_SPECIAL | 031, 284 OPC_MULU = OPC_SPECIAL | 031 | 0200, 285 OPC_MUHU = OPC_SPECIAL | 031 | 0300, 286 OPC_DIV = OPC_SPECIAL | 032, 287 OPC_DIV_R6 = OPC_SPECIAL | 032 | 0200, 288 OPC_MOD = OPC_SPECIAL | 032 | 0300, 289 OPC_DIVU = OPC_SPECIAL | 033, 290 OPC_DIVU_R6 = OPC_SPECIAL | 033 | 0200, 291 OPC_MODU = OPC_SPECIAL | 033 | 0300, 292 OPC_DMULT = OPC_SPECIAL | 034, 293 OPC_DMUL = OPC_SPECIAL | 034 | 0200, 294 OPC_DMUH = OPC_SPECIAL | 034 | 0300, 295 OPC_DMULTU = OPC_SPECIAL | 035, 296 OPC_DMULU = OPC_SPECIAL | 035 | 0200, 297 OPC_DMUHU = OPC_SPECIAL | 035 | 0300, 298 OPC_DDIV = OPC_SPECIAL | 036, 299 OPC_DDIV_R6 = OPC_SPECIAL | 036 | 0200, 300 OPC_DMOD = OPC_SPECIAL | 036 | 0300, 301 OPC_DDIVU = OPC_SPECIAL | 037, 302 OPC_DDIVU_R6 = OPC_SPECIAL | 037 | 0200, 303 OPC_DMODU = OPC_SPECIAL | 037 | 0300, 304 OPC_ADDU = OPC_SPECIAL | 041, 305 OPC_SUBU = OPC_SPECIAL | 043, 306 OPC_AND = OPC_SPECIAL | 044, 307 OPC_OR = OPC_SPECIAL | 045, 308 OPC_XOR = OPC_SPECIAL | 046, 309 OPC_NOR = OPC_SPECIAL | 047, 310 OPC_SLT = OPC_SPECIAL | 052, 311 OPC_SLTU = OPC_SPECIAL | 053, 312 OPC_DADDU = OPC_SPECIAL | 055, 313 OPC_DSUBU = OPC_SPECIAL | 057, 314 OPC_SELEQZ = OPC_SPECIAL | 065, 315 OPC_SELNEZ = OPC_SPECIAL | 067, 316 OPC_DSLL = OPC_SPECIAL | 070, 317 OPC_DSRL = OPC_SPECIAL | 072, 318 OPC_DROTR = OPC_SPECIAL | 072 | (1 << 21), 319 OPC_DSRA = OPC_SPECIAL | 073, 320 OPC_DSLL32 = OPC_SPECIAL | 074, 321 OPC_DSRL32 = OPC_SPECIAL | 076, 322 OPC_DROTR32 = OPC_SPECIAL | 076 | (1 << 21), 323 OPC_DSRA32 = OPC_SPECIAL | 077, 324 OPC_CLZ_R6 = OPC_SPECIAL | 0120, 325 OPC_DCLZ_R6 = OPC_SPECIAL | 0122, 326 327 OPC_REGIMM = 001 << 26, 328 OPC_BLTZ = OPC_REGIMM | (000 << 16), 329 OPC_BGEZ = OPC_REGIMM | (001 << 16), 330 331 OPC_SPECIAL2 = 034 << 26, 332 OPC_MUL_R5 = OPC_SPECIAL2 | 002, 333 OPC_CLZ = OPC_SPECIAL2 | 040, 334 OPC_DCLZ = OPC_SPECIAL2 | 044, 335 336 OPC_SPECIAL3 = 037 << 26, 337 OPC_EXT = OPC_SPECIAL3 | 000, 338 OPC_DEXTM = OPC_SPECIAL3 | 001, 339 OPC_DEXTU = OPC_SPECIAL3 | 002, 340 OPC_DEXT = OPC_SPECIAL3 | 003, 341 OPC_INS = OPC_SPECIAL3 | 004, 342 OPC_DINSM = OPC_SPECIAL3 | 005, 343 OPC_DINSU = OPC_SPECIAL3 | 006, 344 OPC_DINS = OPC_SPECIAL3 | 007, 345 OPC_WSBH = OPC_SPECIAL3 | 00240, 346 OPC_DSBH = OPC_SPECIAL3 | 00244, 347 OPC_DSHD = OPC_SPECIAL3 | 00544, 348 OPC_SEB = OPC_SPECIAL3 | 02040, 349 OPC_SEH = OPC_SPECIAL3 | 03040, 350 351 /* MIPS r6 doesn't have JR, JALR should be used instead */ 352 OPC_JR = use_mips32r6_instructions ? OPC_JALR : OPC_JR_R5, 353 354 /* 355 * MIPS r6 replaces MUL with an alternative encoding which is 356 * backwards-compatible at the assembly level. 357 */ 358 OPC_MUL = use_mips32r6_instructions ? OPC_MUL_R6 : OPC_MUL_R5, 359 360 /* MIPS r6 introduced names for weaker variants of SYNC. These are 361 backward compatible to previous architecture revisions. */ 362 OPC_SYNC_WMB = OPC_SYNC | 0x04 << 6, 363 OPC_SYNC_MB = OPC_SYNC | 0x10 << 6, 364 OPC_SYNC_ACQUIRE = OPC_SYNC | 0x11 << 6, 365 OPC_SYNC_RELEASE = OPC_SYNC | 0x12 << 6, 366 OPC_SYNC_RMB = OPC_SYNC | 0x13 << 6, 367 368 /* Aliases for convenience. */ 369 ALIAS_PADD = sizeof(void *) == 4 ? OPC_ADDU : OPC_DADDU, 370 ALIAS_PADDI = sizeof(void *) == 4 ? OPC_ADDIU : OPC_DADDIU, 371} MIPSInsn; 372 373/* 374 * Type reg 375 */ 376static void tcg_out_opc_reg(TCGContext *s, MIPSInsn opc, 377 TCGReg rd, TCGReg rs, TCGReg rt) 378{ 379 int32_t inst; 380 381 inst = opc; 382 inst |= (rs & 0x1F) << 21; 383 inst |= (rt & 0x1F) << 16; 384 inst |= (rd & 0x1F) << 11; 385 tcg_out32(s, inst); 386} 387 388/* 389 * Type immediate 390 */ 391static void tcg_out_opc_imm(TCGContext *s, MIPSInsn opc, 392 TCGReg rt, TCGReg rs, TCGArg imm) 393{ 394 int32_t inst; 395 396 inst = opc; 397 inst |= (rs & 0x1F) << 21; 398 inst |= (rt & 0x1F) << 16; 399 inst |= (imm & 0xffff); 400 tcg_out32(s, inst); 401} 402 403/* 404 * Type bitfield 405 */ 406static void tcg_out_opc_bf(TCGContext *s, MIPSInsn opc, TCGReg rt, 407 TCGReg rs, int msb, int lsb) 408{ 409 int32_t inst; 410 411 inst = opc; 412 inst |= (rs & 0x1F) << 21; 413 inst |= (rt & 0x1F) << 16; 414 inst |= (msb & 0x1F) << 11; 415 inst |= (lsb & 0x1F) << 6; 416 tcg_out32(s, inst); 417} 418 419static void tcg_out_opc_bf64(TCGContext *s, MIPSInsn opc, MIPSInsn opm, 420 MIPSInsn oph, TCGReg rt, TCGReg rs, 421 int msb, int lsb) 422{ 423 if (lsb >= 32) { 424 opc = oph; 425 msb -= 32; 426 lsb -= 32; 427 } else if (msb >= 32) { 428 opc = opm; 429 msb -= 32; 430 } 431 tcg_out_opc_bf(s, opc, rt, rs, msb, lsb); 432} 433 434/* 435 * Type branch 436 */ 437static void tcg_out_opc_br(TCGContext *s, MIPSInsn opc, TCGReg rt, TCGReg rs) 438{ 439 tcg_out_opc_imm(s, opc, rt, rs, 0); 440} 441 442/* 443 * Type sa 444 */ 445static void tcg_out_opc_sa(TCGContext *s, MIPSInsn opc, 446 TCGReg rd, TCGReg rt, TCGArg sa) 447{ 448 int32_t inst; 449 450 inst = opc; 451 inst |= (rt & 0x1F) << 16; 452 inst |= (rd & 0x1F) << 11; 453 inst |= (sa & 0x1F) << 6; 454 tcg_out32(s, inst); 455 456} 457 458static void tcg_out_opc_sa64(TCGContext *s, MIPSInsn opc1, MIPSInsn opc2, 459 TCGReg rd, TCGReg rt, TCGArg sa) 460{ 461 int32_t inst; 462 463 inst = (sa & 32 ? opc2 : opc1); 464 inst |= (rt & 0x1F) << 16; 465 inst |= (rd & 0x1F) << 11; 466 inst |= (sa & 0x1F) << 6; 467 tcg_out32(s, inst); 468} 469 470/* 471 * Type jump. 472 * Returns true if the branch was in range and the insn was emitted. 473 */ 474static bool tcg_out_opc_jmp(TCGContext *s, MIPSInsn opc, const void *target) 475{ 476 uintptr_t dest = (uintptr_t)target; 477 uintptr_t from = (uintptr_t)tcg_splitwx_to_rx(s->code_ptr) + 4; 478 int32_t inst; 479 480 /* The pc-region branch happens within the 256MB region of 481 the delay slot (thus the +4). */ 482 if ((from ^ dest) & -(1 << 28)) { 483 return false; 484 } 485 tcg_debug_assert((dest & 3) == 0); 486 487 inst = opc; 488 inst |= (dest >> 2) & 0x3ffffff; 489 tcg_out32(s, inst); 490 return true; 491} 492 493static void tcg_out_nop(TCGContext *s) 494{ 495 tcg_out32(s, 0); 496} 497 498static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 499{ 500 memset(p, 0, count * sizeof(tcg_insn_unit)); 501} 502 503static void tcg_out_dsll(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 504{ 505 tcg_out_opc_sa64(s, OPC_DSLL, OPC_DSLL32, rd, rt, sa); 506} 507 508static void tcg_out_dsrl(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 509{ 510 tcg_out_opc_sa64(s, OPC_DSRL, OPC_DSRL32, rd, rt, sa); 511} 512 513static void tcg_out_dsra(TCGContext *s, TCGReg rd, TCGReg rt, TCGArg sa) 514{ 515 tcg_out_opc_sa64(s, OPC_DSRA, OPC_DSRA32, rd, rt, sa); 516} 517 518static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 519{ 520 /* Simple reg-reg move, optimising out the 'do nothing' case */ 521 if (ret != arg) { 522 tcg_out_opc_reg(s, OPC_OR, ret, arg, TCG_REG_ZERO); 523 } 524 return true; 525} 526 527static bool tcg_out_movi_one(TCGContext *s, TCGReg ret, tcg_target_long arg) 528{ 529 if (arg == (int16_t)arg) { 530 tcg_out_opc_imm(s, OPC_ADDIU, ret, TCG_REG_ZERO, arg); 531 return true; 532 } 533 if (arg == (uint16_t)arg) { 534 tcg_out_opc_imm(s, OPC_ORI, ret, TCG_REG_ZERO, arg); 535 return true; 536 } 537 if (arg == (int32_t)arg && (arg & 0xffff) == 0) { 538 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 539 return true; 540 } 541 return false; 542} 543 544static bool tcg_out_movi_two(TCGContext *s, TCGReg ret, tcg_target_long arg) 545{ 546 /* 547 * All signed 32-bit constants are loadable with two immediates, 548 * and everything else requires more work. 549 */ 550 if (arg == (int32_t)arg) { 551 if (!tcg_out_movi_one(s, ret, arg)) { 552 tcg_out_opc_imm(s, OPC_LUI, ret, TCG_REG_ZERO, arg >> 16); 553 tcg_out_opc_imm(s, OPC_ORI, ret, ret, arg & 0xffff); 554 } 555 return true; 556 } 557 return false; 558} 559 560static void tcg_out_movi_pool(TCGContext *s, TCGReg ret, 561 tcg_target_long arg, TCGReg tbreg) 562{ 563 new_pool_label(s, arg, R_MIPS_16, s->code_ptr, tcg_tbrel_diff(s, NULL)); 564 tcg_out_opc_imm(s, OPC_LD, ret, tbreg, 0); 565} 566 567static void tcg_out_movi_int(TCGContext *s, TCGType type, TCGReg ret, 568 tcg_target_long arg, TCGReg tbreg) 569{ 570 tcg_target_long tmp; 571 int sh, lo; 572 573 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { 574 arg = (int32_t)arg; 575 } 576 577 /* Load all 32-bit constants. */ 578 if (tcg_out_movi_two(s, ret, arg)) { 579 return; 580 } 581 assert(TCG_TARGET_REG_BITS == 64); 582 583 /* Load addresses within 2GB of TB with 1 or 3 insns. */ 584 tmp = tcg_tbrel_diff(s, (void *)arg); 585 if (tmp == (int16_t)tmp) { 586 tcg_out_opc_imm(s, OPC_DADDIU, ret, tbreg, tmp); 587 return; 588 } 589 if (tcg_out_movi_two(s, ret, tmp)) { 590 tcg_out_opc_reg(s, OPC_DADDU, ret, ret, tbreg); 591 return; 592 } 593 594 /* 595 * Load bitmasks with a right-shift. This is good for things 596 * like 0x0fff_ffff_ffff_fff0: ADDUI r,0,0xff00 + DSRL r,r,4. 597 * or similarly using LUI. For this to work, bit 31 must be set. 598 */ 599 if (arg > 0 && (int32_t)arg < 0) { 600 sh = clz64(arg); 601 if (tcg_out_movi_one(s, ret, arg << sh)) { 602 tcg_out_dsrl(s, ret, ret, sh); 603 return; 604 } 605 } 606 607 /* 608 * Load slightly larger constants using left-shift. 609 * Limit this sequence to 3 insns to avoid too much expansion. 610 */ 611 sh = ctz64(arg); 612 if (sh && tcg_out_movi_two(s, ret, arg >> sh)) { 613 tcg_out_dsll(s, ret, ret, sh); 614 return; 615 } 616 617 /* 618 * Load slightly larger constants using left-shift and add/or. 619 * Prefer addi with a negative immediate when that would produce 620 * a larger shift. For this to work, bits 15 and 16 must be set. 621 */ 622 lo = arg & 0xffff; 623 if (lo) { 624 if ((arg & 0x18000) == 0x18000) { 625 lo = (int16_t)arg; 626 } 627 tmp = arg - lo; 628 sh = ctz64(tmp); 629 tmp >>= sh; 630 if (tcg_out_movi_one(s, ret, tmp)) { 631 tcg_out_dsll(s, ret, ret, sh); 632 tcg_out_opc_imm(s, lo < 0 ? OPC_DADDIU : OPC_ORI, ret, ret, lo); 633 return; 634 } 635 } 636 637 /* Otherwise, put 64-bit constants into the constant pool. */ 638 tcg_out_movi_pool(s, ret, arg, tbreg); 639} 640 641static void tcg_out_movi(TCGContext *s, TCGType type, 642 TCGReg ret, tcg_target_long arg) 643{ 644 TCGReg tbreg = TCG_TARGET_REG_BITS == 64 ? TCG_REG_TB : 0; 645 tcg_out_movi_int(s, type, ret, arg, tbreg); 646} 647 648static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 649{ 650 tcg_debug_assert(use_mips32r2_instructions); 651 tcg_out_opc_reg(s, OPC_SEB, rd, TCG_REG_ZERO, rs); 652} 653 654static void tcg_out_ext8u(TCGContext *s, TCGReg rd, TCGReg rs) 655{ 656 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xff); 657} 658 659static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg rd, TCGReg rs) 660{ 661 tcg_debug_assert(use_mips32r2_instructions); 662 tcg_out_opc_reg(s, OPC_SEH, rd, TCG_REG_ZERO, rs); 663} 664 665static void tcg_out_ext16u(TCGContext *s, TCGReg rd, TCGReg rs) 666{ 667 tcg_out_opc_imm(s, OPC_ANDI, rd, rs, 0xffff); 668} 669 670static void tcg_out_ext32s(TCGContext *s, TCGReg rd, TCGReg rs) 671{ 672 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 673 tcg_out_opc_sa(s, OPC_SLL, rd, rs, 0); 674} 675 676static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 677{ 678 if (rd != rs) { 679 tcg_out_ext32s(s, rd, rs); 680 } 681} 682 683static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg rd, TCGReg rs) 684{ 685 tcg_out_ext32u(s, rd, rs); 686} 687 688static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg rd, TCGReg rs) 689{ 690 tcg_out_ext32s(s, rd, rs); 691} 692 693static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 694{ 695 return false; 696} 697 698static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 699 tcg_target_long imm) 700{ 701 /* This function is only used for passing structs by reference. */ 702 g_assert_not_reached(); 703} 704 705static void tcg_out_bswap_subr(TCGContext *s, const tcg_insn_unit *sub) 706{ 707 if (!tcg_out_opc_jmp(s, OPC_JAL, sub)) { 708 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP1, (uintptr_t)sub); 709 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_TMP1, 0); 710 } 711} 712 713static void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg, int flags) 714{ 715 if (use_mips32r2_instructions) { 716 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); 717 tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); 718 if (flags & TCG_BSWAP_OZ) { 719 tcg_out_opc_bf(s, OPC_DEXT, ret, ret, 31, 0); 720 } 721 } else { 722 if (flags & TCG_BSWAP_OZ) { 723 tcg_out_bswap_subr(s, bswap32u_addr); 724 } else { 725 tcg_out_bswap_subr(s, bswap32_addr); 726 } 727 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 728 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 729 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 730 } 731} 732 733static void tcg_out_bswap64(TCGContext *s, TCGReg ret, TCGReg arg) 734{ 735 if (use_mips32r2_instructions) { 736 tcg_out_opc_reg(s, OPC_DSBH, ret, 0, arg); 737 tcg_out_opc_reg(s, OPC_DSHD, ret, 0, ret); 738 } else { 739 tcg_out_bswap_subr(s, bswap64_addr); 740 /* delay slot -- never omit the insn, like tcg_out_mov might. */ 741 tcg_out_opc_reg(s, OPC_OR, TCG_TMP0, arg, TCG_REG_ZERO); 742 tcg_out_mov(s, TCG_TYPE_I32, ret, TCG_TMP3); 743 } 744} 745 746static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 747{ 748 tcg_debug_assert(TCG_TARGET_REG_BITS == 64); 749 if (use_mips32r2_instructions) { 750 tcg_out_opc_bf(s, OPC_DEXT, ret, arg, 31, 0); 751 } else { 752 tcg_out_dsll(s, ret, arg, 32); 753 tcg_out_dsrl(s, ret, ret, 32); 754 } 755} 756 757static void tcg_out_ldst(TCGContext *s, MIPSInsn opc, TCGReg data, 758 TCGReg addr, intptr_t ofs) 759{ 760 int16_t lo = ofs; 761 if (ofs != lo) { 762 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, ofs - lo); 763 if (addr != TCG_REG_ZERO) { 764 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP0, TCG_TMP0, addr); 765 } 766 addr = TCG_TMP0; 767 } 768 tcg_out_opc_imm(s, opc, data, addr, lo); 769} 770 771static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 772 TCGReg arg1, intptr_t arg2) 773{ 774 MIPSInsn opc = OPC_LD; 775 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 776 opc = OPC_LW; 777 } 778 tcg_out_ldst(s, opc, arg, arg1, arg2); 779} 780 781static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 782 TCGReg arg1, intptr_t arg2) 783{ 784 MIPSInsn opc = OPC_SD; 785 if (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32) { 786 opc = OPC_SW; 787 } 788 tcg_out_ldst(s, opc, arg, arg1, arg2); 789} 790 791static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 792 TCGReg base, intptr_t ofs) 793{ 794 if (val == 0) { 795 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 796 return true; 797 } 798 return false; 799} 800 801static void tcg_out_addsub2(TCGContext *s, TCGReg rl, TCGReg rh, TCGReg al, 802 TCGReg ah, TCGArg bl, TCGArg bh, bool cbl, 803 bool cbh, bool is_sub) 804{ 805 TCGReg th = TCG_TMP1; 806 807 /* If we have a negative constant such that negating it would 808 make the high part zero, we can (usually) eliminate one insn. */ 809 if (cbl && cbh && bh == -1 && bl != 0) { 810 bl = -bl; 811 bh = 0; 812 is_sub = !is_sub; 813 } 814 815 /* By operating on the high part first, we get to use the final 816 carry operation to move back from the temporary. */ 817 if (!cbh) { 818 tcg_out_opc_reg(s, (is_sub ? OPC_SUBU : OPC_ADDU), th, ah, bh); 819 } else if (bh != 0 || ah == rl) { 820 tcg_out_opc_imm(s, OPC_ADDIU, th, ah, (is_sub ? -bh : bh)); 821 } else { 822 th = ah; 823 } 824 825 /* Note that tcg optimization should eliminate the bl == 0 case. */ 826 if (is_sub) { 827 if (cbl) { 828 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, al, bl); 829 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, -bl); 830 } else { 831 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, al, bl); 832 tcg_out_opc_reg(s, OPC_SUBU, rl, al, bl); 833 } 834 tcg_out_opc_reg(s, OPC_SUBU, rh, th, TCG_TMP0); 835 } else { 836 if (cbl) { 837 tcg_out_opc_imm(s, OPC_ADDIU, rl, al, bl); 838 tcg_out_opc_imm(s, OPC_SLTIU, TCG_TMP0, rl, bl); 839 } else if (rl == al && rl == bl) { 840 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, al, TCG_TARGET_REG_BITS - 1); 841 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 842 } else { 843 tcg_out_opc_reg(s, OPC_ADDU, rl, al, bl); 844 tcg_out_opc_reg(s, OPC_SLTU, TCG_TMP0, rl, (rl == bl ? al : bl)); 845 } 846 tcg_out_opc_reg(s, OPC_ADDU, rh, th, TCG_TMP0); 847 } 848} 849 850#define SETCOND_INV TCG_TARGET_NB_REGS 851#define SETCOND_NEZ (SETCOND_INV << 1) 852#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 853 854static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 855 TCGReg arg1, TCGReg arg2) 856{ 857 int flags = 0; 858 859 switch (cond) { 860 case TCG_COND_EQ: /* -> NE */ 861 case TCG_COND_GE: /* -> LT */ 862 case TCG_COND_GEU: /* -> LTU */ 863 case TCG_COND_LE: /* -> GT */ 864 case TCG_COND_LEU: /* -> GTU */ 865 cond = tcg_invert_cond(cond); 866 flags ^= SETCOND_INV; 867 break; 868 default: 869 break; 870 } 871 872 switch (cond) { 873 case TCG_COND_NE: 874 flags |= SETCOND_NEZ; 875 if (arg2 == 0) { 876 return arg1 | flags; 877 } 878 tcg_out_opc_reg(s, OPC_XOR, ret, arg1, arg2); 879 break; 880 case TCG_COND_LT: 881 tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); 882 break; 883 case TCG_COND_LTU: 884 tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); 885 break; 886 case TCG_COND_GT: 887 tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); 888 break; 889 case TCG_COND_GTU: 890 tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); 891 break; 892 default: 893 g_assert_not_reached(); 894 } 895 return ret | flags; 896} 897 898static void tcg_out_setcond_end(TCGContext *s, TCGReg ret, int tmpflags) 899{ 900 if (tmpflags != ret) { 901 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 902 903 switch (tmpflags & SETCOND_FLAGS) { 904 case SETCOND_INV: 905 /* Intermediate result is boolean: simply invert. */ 906 tcg_out_opc_imm(s, OPC_XORI, ret, tmp, 1); 907 break; 908 case SETCOND_NEZ: 909 /* Intermediate result is zero/non-zero: test != 0. */ 910 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 911 break; 912 case SETCOND_NEZ | SETCOND_INV: 913 /* Intermediate result is zero/non-zero: test == 0. */ 914 tcg_out_opc_imm(s, OPC_SLTIU, ret, tmp, 1); 915 break; 916 default: 917 g_assert_not_reached(); 918 } 919 } 920} 921 922static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 923 TCGReg ret, TCGReg arg1, TCGReg arg2) 924{ 925 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 926 tcg_out_setcond_end(s, ret, tmpflags); 927} 928 929static const TCGOutOpSetcond outop_setcond = { 930 .base.static_constraint = C_O1_I2(r, r, rz), 931 .out_rrr = tgen_setcond, 932}; 933 934static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 935 TCGReg ret, TCGReg arg1, TCGReg arg2) 936{ 937 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2); 938 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 939 940 /* If intermediate result is zero/non-zero: test != 0. */ 941 if (tmpflags & SETCOND_NEZ) { 942 tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, tmp); 943 tmp = ret; 944 } 945 /* Produce the 0/-1 result. */ 946 if (tmpflags & SETCOND_INV) { 947 tcg_out_opc_imm(s, OPC_ADDIU, ret, tmp, -1); 948 } else { 949 tcg_out_opc_reg(s, OPC_SUBU, ret, TCG_REG_ZERO, tmp); 950 } 951} 952 953static const TCGOutOpSetcond outop_negsetcond = { 954 .base.static_constraint = C_O1_I2(r, r, rz), 955 .out_rrr = tgen_negsetcond, 956}; 957 958static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 959 TCGReg arg1, TCGReg arg2, TCGLabel *l) 960{ 961 static const MIPSInsn b_zero[16] = { 962 [TCG_COND_LT] = OPC_BLTZ, 963 [TCG_COND_GT] = OPC_BGTZ, 964 [TCG_COND_LE] = OPC_BLEZ, 965 [TCG_COND_GE] = OPC_BGEZ, 966 }; 967 968 MIPSInsn b_opc = 0; 969 970 switch (cond) { 971 case TCG_COND_EQ: 972 b_opc = OPC_BEQ; 973 break; 974 case TCG_COND_NE: 975 b_opc = OPC_BNE; 976 break; 977 case TCG_COND_LT: 978 case TCG_COND_GT: 979 case TCG_COND_LE: 980 case TCG_COND_GE: 981 if (arg2 == 0) { 982 b_opc = b_zero[cond]; 983 arg2 = arg1; 984 arg1 = 0; 985 } 986 break; 987 default: 988 break; 989 } 990 991 if (b_opc == 0) { 992 int tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, arg1, arg2); 993 994 arg2 = TCG_REG_ZERO; 995 arg1 = tmpflags & ~SETCOND_FLAGS; 996 b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 997 } 998 999 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1000 tcg_out_opc_br(s, b_opc, arg1, arg2); 1001 tcg_out_nop(s); 1002} 1003 1004static const TCGOutOpBrcond outop_brcond = { 1005 .base.static_constraint = C_O0_I2(r, rz), 1006 .out_rr = tgen_brcond, 1007}; 1008 1009static int tcg_out_setcond2_int(TCGContext *s, TCGCond cond, TCGReg ret, 1010 TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) 1011{ 1012 int flags = 0; 1013 1014 switch (cond) { 1015 case TCG_COND_EQ: 1016 flags |= SETCOND_INV; 1017 /* fall through */ 1018 case TCG_COND_NE: 1019 flags |= SETCOND_NEZ; 1020 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP0, al, bl); 1021 tcg_out_opc_reg(s, OPC_XOR, TCG_TMP1, ah, bh); 1022 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1023 break; 1024 1025 default: 1026 tgen_setcond(s, TCG_TYPE_I32, TCG_COND_EQ, TCG_TMP0, ah, bh); 1027 tgen_setcond(s, TCG_TYPE_I32, tcg_unsigned_cond(cond), 1028 TCG_TMP1, al, bl); 1029 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP0); 1030 tgen_setcond(s, TCG_TYPE_I32, tcg_high_cond(cond), TCG_TMP0, ah, bh); 1031 tcg_out_opc_reg(s, OPC_OR, ret, TCG_TMP0, TCG_TMP1); 1032 break; 1033 } 1034 return ret | flags; 1035} 1036 1037static void tgen_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, 1038 TCGReg al, TCGReg ah, 1039 TCGArg bl, bool const_bl, 1040 TCGArg bh, bool const_bh) 1041{ 1042 int tmpflags = tcg_out_setcond2_int(s, cond, ret, al, ah, bl, bh); 1043 tcg_out_setcond_end(s, ret, tmpflags); 1044} 1045 1046#if TCG_TARGET_REG_BITS != 32 1047__attribute__((unused)) 1048#endif 1049static const TCGOutOpSetcond2 outop_setcond2 = { 1050 .base.static_constraint = C_O1_I4(r, r, r, rz, rz), 1051 .out = tgen_setcond2, 1052}; 1053 1054static void tgen_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, 1055 TCGArg bl, bool const_bl, 1056 TCGArg bh, bool const_bh, TCGLabel *l) 1057{ 1058 int tmpflags = tcg_out_setcond2_int(s, cond, TCG_TMP0, al, ah, bl, bh); 1059 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 1060 MIPSInsn b_opc = tmpflags & SETCOND_INV ? OPC_BEQ : OPC_BNE; 1061 1062 tcg_out_reloc(s, s->code_ptr, R_MIPS_PC16, l, 0); 1063 tcg_out_opc_br(s, b_opc, tmp, TCG_REG_ZERO); 1064 tcg_out_nop(s); 1065} 1066 1067#if TCG_TARGET_REG_BITS != 32 1068__attribute__((unused)) 1069#endif 1070static const TCGOutOpBrcond2 outop_brcond2 = { 1071 .base.static_constraint = C_O0_I4(r, r, rz, rz), 1072 .out = tgen_brcond2, 1073}; 1074 1075static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 1076 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 1077 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 1078{ 1079 int tmpflags; 1080 bool eqz; 1081 1082 /* If one of the values is zero, put it last to match SEL*Z instructions */ 1083 if (use_mips32r6_instructions && v1 == 0) { 1084 v1 = v2; 1085 v2 = 0; 1086 cond = tcg_invert_cond(cond); 1087 } 1088 1089 tmpflags = tcg_out_setcond_int(s, cond, TCG_TMP0, c1, c2); 1090 c1 = tmpflags & ~SETCOND_FLAGS; 1091 eqz = tmpflags & SETCOND_INV; 1092 1093 if (use_mips32r6_instructions) { 1094 MIPSInsn m_opc_t = eqz ? OPC_SELEQZ : OPC_SELNEZ; 1095 MIPSInsn m_opc_f = eqz ? OPC_SELNEZ : OPC_SELEQZ; 1096 1097 if (v2 != 0) { 1098 tcg_out_opc_reg(s, m_opc_f, TCG_TMP1, v2, c1); 1099 } 1100 tcg_out_opc_reg(s, m_opc_t, ret, v1, c1); 1101 if (v2 != 0) { 1102 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP1); 1103 } 1104 return; 1105 } 1106 1107 /* This should be guaranteed via constraints */ 1108 tcg_debug_assert(v2 == ret); 1109 1110 if (use_movnz_instructions) { 1111 MIPSInsn m_opc = eqz ? OPC_MOVZ : OPC_MOVN; 1112 tcg_out_opc_reg(s, m_opc, ret, v1, c1); 1113 } else { 1114 /* Invert the condition in order to branch over the move. */ 1115 MIPSInsn b_opc = eqz ? OPC_BNE : OPC_BEQ; 1116 tcg_out_opc_imm(s, b_opc, c1, TCG_REG_ZERO, 2); 1117 tcg_out_nop(s); 1118 /* Open-code tcg_out_mov, without the nop-move check. */ 1119 tcg_out_opc_reg(s, OPC_OR, ret, v1, TCG_REG_ZERO); 1120 } 1121} 1122 1123static const TCGOutOpMovcond outop_movcond = { 1124 .base.static_constraint = (use_mips32r6_instructions 1125 ? C_O1_I4(r, r, rz, rz, rz) 1126 : C_O1_I4(r, r, rz, rz, 0)), 1127 .out = tgen_movcond, 1128}; 1129 1130static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 1131{ 1132 /* 1133 * Note that __mips_abicalls requires the called function's address 1134 * to be loaded into $25 (t9), even if a direct branch is in range. 1135 * 1136 * For n64, always drop the pointer into the constant pool. 1137 * We can re-use helper addresses often and do not want any 1138 * of the longer sequences tcg_out_movi may try. 1139 */ 1140 if (sizeof(uintptr_t) == 8) { 1141 tcg_out_movi_pool(s, TCG_REG_T9, (uintptr_t)arg, TCG_REG_TB); 1142 } else { 1143 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_T9, (uintptr_t)arg); 1144 } 1145 1146 /* But do try a direct branch, allowing the cpu better insn prefetch. */ 1147 if (tail) { 1148 if (!tcg_out_opc_jmp(s, OPC_J, arg)) { 1149 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_T9, 0); 1150 } 1151 } else { 1152 if (!tcg_out_opc_jmp(s, OPC_JAL, arg)) { 1153 tcg_out_opc_reg(s, OPC_JALR, TCG_REG_RA, TCG_REG_T9, 0); 1154 } 1155 } 1156} 1157 1158static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 1159 const TCGHelperInfo *info) 1160{ 1161 tcg_out_call_int(s, arg, false); 1162 tcg_out_nop(s); 1163} 1164 1165/* We have four temps, we might as well expose three of them. */ 1166static const TCGLdstHelperParam ldst_helper_param = { 1167 .ntmp = 3, .tmp = { TCG_TMP0, TCG_TMP1, TCG_TMP2 } 1168}; 1169 1170static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1171{ 1172 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1173 MemOp opc = get_memop(l->oi); 1174 1175 /* resolve label address */ 1176 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1177 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1178 return false; 1179 } 1180 1181 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1182 1183 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SSIZE], false); 1184 /* delay slot */ 1185 tcg_out_nop(s); 1186 1187 tcg_out_ld_helper_ret(s, l, true, &ldst_helper_param); 1188 1189 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1190 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1191 return false; 1192 } 1193 1194 /* delay slot */ 1195 tcg_out_nop(s); 1196 return true; 1197} 1198 1199static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1200{ 1201 const tcg_insn_unit *tgt_rx = tcg_splitwx_to_rx(s->code_ptr); 1202 MemOp opc = get_memop(l->oi); 1203 1204 /* resolve label address */ 1205 if (!reloc_pc16(l->label_ptr[0], tgt_rx) 1206 || (l->label_ptr[1] && !reloc_pc16(l->label_ptr[1], tgt_rx))) { 1207 return false; 1208 } 1209 1210 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1211 1212 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1213 /* delay slot */ 1214 tcg_out_nop(s); 1215 1216 tcg_out_opc_br(s, OPC_BEQ, TCG_REG_ZERO, TCG_REG_ZERO); 1217 if (!reloc_pc16(s->code_ptr - 1, l->raddr)) { 1218 return false; 1219 } 1220 1221 /* delay slot */ 1222 tcg_out_nop(s); 1223 return true; 1224} 1225 1226typedef struct { 1227 TCGReg base; 1228 TCGAtomAlign aa; 1229} HostAddress; 1230 1231bool tcg_target_has_memory_bswap(MemOp memop) 1232{ 1233 return false; 1234} 1235 1236/* We expect to use a 16-bit negative offset from ENV. */ 1237#define MIN_TLB_MASK_TABLE_OFS -32768 1238 1239/* 1240 * For system-mode, perform the TLB load and compare. 1241 * For user-mode, perform any required alignment tests. 1242 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1243 * is required and fill in @h with the host address for the fast path. 1244 */ 1245static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1246 TCGReg addr, MemOpIdx oi, bool is_ld) 1247{ 1248 TCGType addr_type = s->addr_type; 1249 TCGLabelQemuLdst *ldst = NULL; 1250 MemOp opc = get_memop(oi); 1251 MemOp a_bits; 1252 unsigned s_bits = opc & MO_SIZE; 1253 unsigned a_mask; 1254 TCGReg base; 1255 1256 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1257 a_bits = h->aa.align; 1258 a_mask = (1 << a_bits) - 1; 1259 1260 if (tcg_use_softmmu) { 1261 unsigned s_mask = (1 << s_bits) - 1; 1262 int mem_index = get_mmuidx(oi); 1263 int fast_off = tlb_mask_table_ofs(s, mem_index); 1264 int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); 1265 int table_off = fast_off + offsetof(CPUTLBDescFast, table); 1266 int add_off = offsetof(CPUTLBEntry, addend); 1267 int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) 1268 : offsetof(CPUTLBEntry, addr_write); 1269 1270 ldst = new_ldst_label(s); 1271 ldst->is_ld = is_ld; 1272 ldst->oi = oi; 1273 ldst->addr_reg = addr; 1274 1275 /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ 1276 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); 1277 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); 1278 1279 /* Extract the TLB index from the address into TMP3. */ 1280 if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { 1281 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, addr, 1282 s->page_bits - CPU_TLB_ENTRY_BITS); 1283 } else { 1284 tcg_out_dsrl(s, TCG_TMP3, addr, s->page_bits - CPU_TLB_ENTRY_BITS); 1285 } 1286 tcg_out_opc_reg(s, OPC_AND, TCG_TMP3, TCG_TMP3, TCG_TMP0); 1287 1288 /* Add the tlb_table pointer, creating the CPUTLBEntry address. */ 1289 tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); 1290 1291 /* Load the tlb comparator. */ 1292 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1293 tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, 1294 cmp_off + HOST_BIG_ENDIAN * 4); 1295 } else { 1296 tcg_out_ld(s, TCG_TYPE_REG, TCG_TMP0, TCG_TMP3, cmp_off); 1297 } 1298 1299 /* Load the tlb addend for the fast path. */ 1300 tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); 1301 1302 /* 1303 * Mask the page bits, keeping the alignment bits to compare against. 1304 * For unaligned accesses, compare against the end of the access to 1305 * verify that it does not cross a page boundary. 1306 */ 1307 tcg_out_movi(s, addr_type, TCG_TMP1, s->page_mask | a_mask); 1308 if (a_mask < s_mask) { 1309 tcg_out_opc_imm(s, (TCG_TARGET_REG_BITS == 32 1310 || addr_type == TCG_TYPE_I32 1311 ? OPC_ADDIU : OPC_DADDIU), 1312 TCG_TMP2, addr, s_mask - a_mask); 1313 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, TCG_TMP2); 1314 } else { 1315 tcg_out_opc_reg(s, OPC_AND, TCG_TMP1, TCG_TMP1, addr); 1316 } 1317 1318 /* Zero extend a 32-bit guest address for a 64-bit host. */ 1319 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1320 tcg_out_ext32u(s, TCG_TMP2, addr); 1321 addr = TCG_TMP2; 1322 } 1323 1324 ldst->label_ptr[0] = s->code_ptr; 1325 tcg_out_opc_br(s, OPC_BNE, TCG_TMP1, TCG_TMP0); 1326 1327 /* delay slot */ 1328 base = TCG_TMP3; 1329 tcg_out_opc_reg(s, ALIAS_PADD, base, TCG_TMP3, addr); 1330 } else { 1331 if (a_mask && (use_mips32r6_instructions || a_bits != s_bits)) { 1332 ldst = new_ldst_label(s); 1333 1334 ldst->is_ld = is_ld; 1335 ldst->oi = oi; 1336 ldst->addr_reg = addr; 1337 1338 /* We are expecting a_bits to max out at 7, much lower than ANDI. */ 1339 tcg_debug_assert(a_bits < 16); 1340 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, addr, a_mask); 1341 1342 ldst->label_ptr[0] = s->code_ptr; 1343 if (use_mips32r6_instructions) { 1344 tcg_out_opc_br(s, OPC_BNEZALC_R6, TCG_REG_ZERO, TCG_TMP0); 1345 } else { 1346 tcg_out_opc_br(s, OPC_BNEL, TCG_TMP0, TCG_REG_ZERO); 1347 tcg_out_nop(s); 1348 } 1349 } 1350 1351 base = addr; 1352 if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { 1353 tcg_out_ext32u(s, TCG_REG_A0, base); 1354 base = TCG_REG_A0; 1355 } 1356 if (guest_base) { 1357 if (guest_base == (int16_t)guest_base) { 1358 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_A0, base, guest_base); 1359 } else { 1360 tcg_out_opc_reg(s, ALIAS_PADD, TCG_REG_A0, base, 1361 TCG_GUEST_BASE_REG); 1362 } 1363 base = TCG_REG_A0; 1364 } 1365 } 1366 1367 h->base = base; 1368 return ldst; 1369} 1370 1371static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1372 TCGReg base, MemOp opc, TCGType type) 1373{ 1374 switch (opc & MO_SSIZE) { 1375 case MO_UB: 1376 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1377 break; 1378 case MO_SB: 1379 tcg_out_opc_imm(s, OPC_LB, lo, base, 0); 1380 break; 1381 case MO_UW: 1382 tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); 1383 break; 1384 case MO_SW: 1385 tcg_out_opc_imm(s, OPC_LH, lo, base, 0); 1386 break; 1387 case MO_UL: 1388 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64) { 1389 tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); 1390 break; 1391 } 1392 /* FALLTHRU */ 1393 case MO_SL: 1394 tcg_out_opc_imm(s, OPC_LW, lo, base, 0); 1395 break; 1396 case MO_UQ: 1397 /* Prefer to load from offset 0 first, but allow for overlap. */ 1398 if (TCG_TARGET_REG_BITS == 64) { 1399 tcg_out_opc_imm(s, OPC_LD, lo, base, 0); 1400 } else if (HOST_BIG_ENDIAN ? hi != base : lo == base) { 1401 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1402 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1403 } else { 1404 tcg_out_opc_imm(s, OPC_LW, lo, base, LO_OFF); 1405 tcg_out_opc_imm(s, OPC_LW, hi, base, HI_OFF); 1406 } 1407 break; 1408 default: 1409 g_assert_not_reached(); 1410 } 1411} 1412 1413static void tcg_out_qemu_ld_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1414 TCGReg base, MemOp opc, TCGType type) 1415{ 1416 const MIPSInsn lw1 = HOST_BIG_ENDIAN ? OPC_LWL : OPC_LWR; 1417 const MIPSInsn lw2 = HOST_BIG_ENDIAN ? OPC_LWR : OPC_LWL; 1418 const MIPSInsn ld1 = HOST_BIG_ENDIAN ? OPC_LDL : OPC_LDR; 1419 const MIPSInsn ld2 = HOST_BIG_ENDIAN ? OPC_LDR : OPC_LDL; 1420 bool sgn = opc & MO_SIGN; 1421 1422 switch (opc & MO_SIZE) { 1423 case MO_16: 1424 if (HOST_BIG_ENDIAN) { 1425 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 0); 1426 tcg_out_opc_imm(s, OPC_LBU, lo, base, 1); 1427 if (use_mips32r2_instructions) { 1428 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1429 } else { 1430 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP0, TCG_TMP0, 8); 1431 tcg_out_opc_reg(s, OPC_OR, lo, lo, TCG_TMP0); 1432 } 1433 } else if (use_mips32r2_instructions && lo != base) { 1434 tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); 1435 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP0, base, 1); 1436 tcg_out_opc_bf(s, OPC_INS, lo, TCG_TMP0, 31, 8); 1437 } else { 1438 tcg_out_opc_imm(s, OPC_LBU, TCG_TMP0, base, 0); 1439 tcg_out_opc_imm(s, sgn ? OPC_LB : OPC_LBU, TCG_TMP1, base, 1); 1440 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP1, TCG_TMP1, 8); 1441 tcg_out_opc_reg(s, OPC_OR, lo, TCG_TMP0, TCG_TMP1); 1442 } 1443 break; 1444 1445 case MO_32: 1446 tcg_out_opc_imm(s, lw1, lo, base, 0); 1447 tcg_out_opc_imm(s, lw2, lo, base, 3); 1448 if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I64 && !sgn) { 1449 tcg_out_ext32u(s, lo, lo); 1450 } 1451 break; 1452 1453 case MO_64: 1454 if (TCG_TARGET_REG_BITS == 64) { 1455 tcg_out_opc_imm(s, ld1, lo, base, 0); 1456 tcg_out_opc_imm(s, ld2, lo, base, 7); 1457 } else { 1458 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1459 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1460 tcg_out_opc_imm(s, lw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1461 tcg_out_opc_imm(s, lw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1462 } 1463 break; 1464 1465 default: 1466 g_assert_not_reached(); 1467 } 1468} 1469 1470static void tcg_out_qemu_ld(TCGContext *s, TCGReg datalo, TCGReg datahi, 1471 TCGReg addr, MemOpIdx oi, TCGType data_type) 1472{ 1473 MemOp opc = get_memop(oi); 1474 TCGLabelQemuLdst *ldst; 1475 HostAddress h; 1476 1477 ldst = prepare_host_addr(s, &h, addr, oi, true); 1478 1479 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1480 tcg_out_qemu_ld_direct(s, datalo, datahi, h.base, opc, data_type); 1481 } else { 1482 tcg_out_qemu_ld_unalign(s, datalo, datahi, h.base, opc, data_type); 1483 } 1484 1485 if (ldst) { 1486 ldst->type = data_type; 1487 ldst->datalo_reg = datalo; 1488 ldst->datahi_reg = datahi; 1489 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1490 } 1491} 1492 1493static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, 1494 TCGReg base, MemOp opc) 1495{ 1496 switch (opc & MO_SIZE) { 1497 case MO_8: 1498 tcg_out_opc_imm(s, OPC_SB, lo, base, 0); 1499 break; 1500 case MO_16: 1501 tcg_out_opc_imm(s, OPC_SH, lo, base, 0); 1502 break; 1503 case MO_32: 1504 tcg_out_opc_imm(s, OPC_SW, lo, base, 0); 1505 break; 1506 case MO_64: 1507 if (TCG_TARGET_REG_BITS == 64) { 1508 tcg_out_opc_imm(s, OPC_SD, lo, base, 0); 1509 } else { 1510 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? hi : lo, base, 0); 1511 tcg_out_opc_imm(s, OPC_SW, HOST_BIG_ENDIAN ? lo : hi, base, 4); 1512 } 1513 break; 1514 default: 1515 g_assert_not_reached(); 1516 } 1517} 1518 1519static void tcg_out_qemu_st_unalign(TCGContext *s, TCGReg lo, TCGReg hi, 1520 TCGReg base, MemOp opc) 1521{ 1522 const MIPSInsn sw1 = HOST_BIG_ENDIAN ? OPC_SWL : OPC_SWR; 1523 const MIPSInsn sw2 = HOST_BIG_ENDIAN ? OPC_SWR : OPC_SWL; 1524 const MIPSInsn sd1 = HOST_BIG_ENDIAN ? OPC_SDL : OPC_SDR; 1525 const MIPSInsn sd2 = HOST_BIG_ENDIAN ? OPC_SDR : OPC_SDL; 1526 1527 switch (opc & MO_SIZE) { 1528 case MO_16: 1529 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, lo, 8); 1530 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? TCG_TMP0 : lo, base, 0); 1531 tcg_out_opc_imm(s, OPC_SB, HOST_BIG_ENDIAN ? lo : TCG_TMP0, base, 1); 1532 break; 1533 1534 case MO_32: 1535 tcg_out_opc_imm(s, sw1, lo, base, 0); 1536 tcg_out_opc_imm(s, sw2, lo, base, 3); 1537 break; 1538 1539 case MO_64: 1540 if (TCG_TARGET_REG_BITS == 64) { 1541 tcg_out_opc_imm(s, sd1, lo, base, 0); 1542 tcg_out_opc_imm(s, sd2, lo, base, 7); 1543 } else { 1544 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 0); 1545 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? hi : lo, base, 0 + 3); 1546 tcg_out_opc_imm(s, sw1, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 0); 1547 tcg_out_opc_imm(s, sw2, HOST_BIG_ENDIAN ? lo : hi, base, 4 + 3); 1548 } 1549 break; 1550 1551 default: 1552 g_assert_not_reached(); 1553 } 1554} 1555 1556static void tcg_out_qemu_st(TCGContext *s, TCGReg datalo, TCGReg datahi, 1557 TCGReg addr, MemOpIdx oi, TCGType data_type) 1558{ 1559 MemOp opc = get_memop(oi); 1560 TCGLabelQemuLdst *ldst; 1561 HostAddress h; 1562 1563 ldst = prepare_host_addr(s, &h, addr, oi, false); 1564 1565 if (use_mips32r6_instructions || h.aa.align >= (opc & MO_SIZE)) { 1566 tcg_out_qemu_st_direct(s, datalo, datahi, h.base, opc); 1567 } else { 1568 tcg_out_qemu_st_unalign(s, datalo, datahi, h.base, opc); 1569 } 1570 1571 if (ldst) { 1572 ldst->type = data_type; 1573 ldst->datalo_reg = datalo; 1574 ldst->datahi_reg = datahi; 1575 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1576 } 1577} 1578 1579static void tcg_out_mb(TCGContext *s, TCGArg a0) 1580{ 1581 static const MIPSInsn sync[] = { 1582 /* Note that SYNC_MB is a slightly weaker than SYNC 0, 1583 as the former is an ordering barrier and the latter 1584 is a completion barrier. */ 1585 [0 ... TCG_MO_ALL] = OPC_SYNC_MB, 1586 [TCG_MO_LD_LD] = OPC_SYNC_RMB, 1587 [TCG_MO_ST_ST] = OPC_SYNC_WMB, 1588 [TCG_MO_LD_ST] = OPC_SYNC_RELEASE, 1589 [TCG_MO_LD_ST | TCG_MO_ST_ST] = OPC_SYNC_RELEASE, 1590 [TCG_MO_LD_ST | TCG_MO_LD_LD] = OPC_SYNC_ACQUIRE, 1591 }; 1592 tcg_out32(s, sync[a0 & TCG_MO_ALL]); 1593} 1594 1595static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1596{ 1597 TCGReg base = TCG_REG_ZERO; 1598 int16_t lo = 0; 1599 1600 if (a0) { 1601 intptr_t ofs; 1602 if (TCG_TARGET_REG_BITS == 64) { 1603 ofs = tcg_tbrel_diff(s, (void *)a0); 1604 lo = ofs; 1605 if (ofs == lo) { 1606 base = TCG_REG_TB; 1607 } else { 1608 base = TCG_REG_V0; 1609 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1610 tcg_out_opc_reg(s, ALIAS_PADD, base, base, TCG_REG_TB); 1611 } 1612 } else { 1613 ofs = a0; 1614 lo = ofs; 1615 base = TCG_REG_V0; 1616 tcg_out_movi(s, TCG_TYPE_PTR, base, ofs - lo); 1617 } 1618 } 1619 if (!tcg_out_opc_jmp(s, OPC_J, tb_ret_addr)) { 1620 tcg_out_movi(s, TCG_TYPE_PTR, TCG_TMP0, (uintptr_t)tb_ret_addr); 1621 tcg_out_opc_reg(s, OPC_JR, 0, TCG_TMP0, 0); 1622 } 1623 /* delay slot */ 1624 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_V0, base, lo); 1625} 1626 1627static void tcg_out_goto_tb(TCGContext *s, int which) 1628{ 1629 intptr_t ofs = get_jmp_target_addr(s, which); 1630 TCGReg base, dest; 1631 1632 /* indirect jump method */ 1633 if (TCG_TARGET_REG_BITS == 64) { 1634 dest = TCG_REG_TB; 1635 base = TCG_REG_TB; 1636 ofs = tcg_tbrel_diff(s, (void *)ofs); 1637 } else { 1638 dest = TCG_TMP0; 1639 base = TCG_REG_ZERO; 1640 } 1641 tcg_out_ld(s, TCG_TYPE_PTR, dest, base, ofs); 1642 tcg_out_opc_reg(s, OPC_JR, 0, dest, 0); 1643 /* delay slot */ 1644 tcg_out_nop(s); 1645 1646 set_jmp_reset_offset(s, which); 1647 if (TCG_TARGET_REG_BITS == 64) { 1648 /* For the unlinked case, need to reset TCG_REG_TB. */ 1649 tcg_out_ldst(s, ALIAS_PADDI, TCG_REG_TB, TCG_REG_TB, 1650 -tcg_current_code_size(s)); 1651 } 1652} 1653 1654void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1655 uintptr_t jmp_rx, uintptr_t jmp_rw) 1656{ 1657 /* Always indirect, nothing to do */ 1658} 1659 1660 1661static void tgen_add(TCGContext *s, TCGType type, 1662 TCGReg a0, TCGReg a1, TCGReg a2) 1663{ 1664 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDU : OPC_DADDU; 1665 tcg_out_opc_reg(s, insn, a0, a1, a2); 1666} 1667 1668static void tgen_addi(TCGContext *s, TCGType type, 1669 TCGReg a0, TCGReg a1, tcg_target_long a2) 1670{ 1671 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ADDIU : OPC_DADDIU; 1672 tcg_out_opc_imm(s, insn, a0, a1, a2); 1673} 1674 1675static const TCGOutOpBinary outop_add = { 1676 .base.static_constraint = C_O1_I2(r, r, rJ), 1677 .out_rrr = tgen_add, 1678 .out_rri = tgen_addi, 1679}; 1680 1681static void tgen_and(TCGContext *s, TCGType type, 1682 TCGReg a0, TCGReg a1, TCGReg a2) 1683{ 1684 tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); 1685} 1686 1687static void tgen_andi(TCGContext *s, TCGType type, 1688 TCGReg a0, TCGReg a1, tcg_target_long a2) 1689{ 1690 int msb; 1691 1692 if (a2 == (uint16_t)a2) { 1693 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); 1694 return; 1695 } 1696 1697 tcg_debug_assert(use_mips32r2_instructions); 1698 tcg_debug_assert(is_p2m1(a2)); 1699 msb = ctz64(~a2) - 1; 1700 if (type == TCG_TYPE_I32) { 1701 tcg_out_opc_bf(s, OPC_EXT, a0, a1, msb, 0); 1702 } else { 1703 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, a0, a1, msb, 0); 1704 } 1705} 1706 1707static const TCGOutOpBinary outop_and = { 1708 .base.static_constraint = C_O1_I2(r, r, rIK), 1709 .out_rrr = tgen_and, 1710 .out_rri = tgen_andi, 1711}; 1712 1713static const TCGOutOpBinary outop_andc = { 1714 .base.static_constraint = C_NotImplemented, 1715}; 1716 1717static void tgen_clz(TCGContext *s, TCGType type, 1718 TCGReg a0, TCGReg a1, TCGReg a2) 1719{ 1720 if (use_mips32r6_instructions) { 1721 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1722 tcg_out_opc_reg(s, opcv6, TCG_TMP0, a1, 0); 1723 tgen_movcond(s, TCG_TYPE_REG, TCG_COND_EQ, a0, a1, a2, false, 1724 TCG_TMP0, false, TCG_REG_ZERO, false); 1725 } else { 1726 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1727 if (a0 == a2) { 1728 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1729 tcg_out_opc_reg(s, OPC_MOVN, a0, TCG_TMP0, a1); 1730 } else if (a0 != a1) { 1731 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1732 tcg_out_opc_reg(s, OPC_MOVZ, a0, a2, a1); 1733 } else { 1734 tcg_out_opc_reg(s, opcv2, TCG_TMP0, a1, a1); 1735 tcg_out_opc_reg(s, OPC_MOVZ, TCG_TMP0, a2, a1); 1736 tcg_out_mov(s, type, a0, TCG_TMP0); 1737 } 1738 } 1739} 1740 1741static void tgen_clzi(TCGContext *s, TCGType type, 1742 TCGReg a0, TCGReg a1, tcg_target_long a2) 1743{ 1744 if (a2 == 0) { 1745 tgen_clz(s, type, a0, a1, TCG_REG_ZERO); 1746 } else if (use_mips32r6_instructions) { 1747 MIPSInsn opcv6 = type == TCG_TYPE_I32 ? OPC_CLZ_R6 : OPC_DCLZ_R6; 1748 tcg_out_opc_reg(s, opcv6, a0, a1, 0); 1749 } else { 1750 MIPSInsn opcv2 = type == TCG_TYPE_I32 ? OPC_CLZ : OPC_DCLZ; 1751 tcg_out_opc_reg(s, opcv2, a0, a1, a1); 1752 } 1753} 1754 1755static TCGConstraintSetIndex cset_clz(TCGType type, unsigned flags) 1756{ 1757 return use_mips32r2_instructions ? C_O1_I2(r, r, rzW) : C_NotImplemented; 1758} 1759 1760static const TCGOutOpBinary outop_clz = { 1761 .base.static_constraint = C_Dynamic, 1762 .base.dynamic_constraint = cset_clz, 1763 .out_rrr = tgen_clz, 1764 .out_rri = tgen_clzi, 1765}; 1766 1767static const TCGOutOpUnary outop_ctpop = { 1768 .base.static_constraint = C_NotImplemented, 1769}; 1770 1771static const TCGOutOpBinary outop_ctz = { 1772 .base.static_constraint = C_NotImplemented, 1773}; 1774 1775static void tgen_divs(TCGContext *s, TCGType type, 1776 TCGReg a0, TCGReg a1, TCGReg a2) 1777{ 1778 if (use_mips32r6_instructions) { 1779 if (type == TCG_TYPE_I32) { 1780 tcg_out_opc_reg(s, OPC_DIV_R6, a0, a1, a2); 1781 } else { 1782 tcg_out_opc_reg(s, OPC_DDIV_R6, a0, a1, a2); 1783 } 1784 } else { 1785 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1786 tcg_out_opc_reg(s, insn, 0, a1, a2); 1787 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1788 } 1789} 1790 1791static const TCGOutOpBinary outop_divs = { 1792 .base.static_constraint = C_O1_I2(r, r, r), 1793 .out_rrr = tgen_divs, 1794}; 1795 1796static const TCGOutOpDivRem outop_divs2 = { 1797 .base.static_constraint = C_NotImplemented, 1798}; 1799 1800static void tgen_divu(TCGContext *s, TCGType type, 1801 TCGReg a0, TCGReg a1, TCGReg a2) 1802{ 1803 if (use_mips32r6_instructions) { 1804 if (type == TCG_TYPE_I32) { 1805 tcg_out_opc_reg(s, OPC_DIVU_R6, a0, a1, a2); 1806 } else { 1807 tcg_out_opc_reg(s, OPC_DDIVU_R6, a0, a1, a2); 1808 } 1809 } else { 1810 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1811 tcg_out_opc_reg(s, insn, 0, a1, a2); 1812 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1813 } 1814} 1815 1816static const TCGOutOpBinary outop_divu = { 1817 .base.static_constraint = C_O1_I2(r, r, r), 1818 .out_rrr = tgen_divu, 1819}; 1820 1821static const TCGOutOpDivRem outop_divu2 = { 1822 .base.static_constraint = C_NotImplemented, 1823}; 1824 1825static const TCGOutOpBinary outop_eqv = { 1826 .base.static_constraint = C_NotImplemented, 1827}; 1828 1829static void tgen_mul(TCGContext *s, TCGType type, 1830 TCGReg a0, TCGReg a1, TCGReg a2) 1831{ 1832 MIPSInsn insn; 1833 1834 if (type == TCG_TYPE_I32) { 1835 if (use_mips32_instructions) { 1836 tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); 1837 return; 1838 } 1839 insn = OPC_MULT; 1840 } else { 1841 if (use_mips32r6_instructions) { 1842 tcg_out_opc_reg(s, OPC_DMUL, a0, a1, a2); 1843 return; 1844 } 1845 insn = OPC_DMULT; 1846 } 1847 tcg_out_opc_reg(s, insn, 0, a1, a2); 1848 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1849} 1850 1851static const TCGOutOpBinary outop_mul = { 1852 .base.static_constraint = C_O1_I2(r, r, r), 1853 .out_rrr = tgen_mul, 1854}; 1855 1856static void tgen_muls2(TCGContext *s, TCGType type, 1857 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1858{ 1859 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1860 tcg_out_opc_reg(s, insn, 0, a2, a3); 1861 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1862 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1863} 1864 1865static TCGConstraintSetIndex cset_mul2(TCGType type, unsigned flags) 1866{ 1867 return use_mips32r6_instructions ? C_NotImplemented : C_O2_I2(r, r, r, r); 1868} 1869 1870static const TCGOutOpMul2 outop_muls2 = { 1871 .base.static_constraint = C_Dynamic, 1872 .base.dynamic_constraint = cset_mul2, 1873 .out_rrrr = tgen_muls2, 1874}; 1875 1876static void tgen_mulsh(TCGContext *s, TCGType type, 1877 TCGReg a0, TCGReg a1, TCGReg a2) 1878{ 1879 if (use_mips32r6_instructions) { 1880 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUH : OPC_DMUH; 1881 tcg_out_opc_reg(s, insn, a0, a1, a2); 1882 } else { 1883 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULT : OPC_DMULT; 1884 tcg_out_opc_reg(s, insn, 0, a1, a2); 1885 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1886 } 1887} 1888 1889static const TCGOutOpBinary outop_mulsh = { 1890 .base.static_constraint = C_O1_I2(r, r, r), 1891 .out_rrr = tgen_mulsh, 1892}; 1893 1894static void tgen_mulu2(TCGContext *s, TCGType type, 1895 TCGReg a0, TCGReg a1, TCGReg a2, TCGReg a3) 1896{ 1897 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1898 tcg_out_opc_reg(s, insn, 0, a2, a3); 1899 tcg_out_opc_reg(s, OPC_MFLO, a0, 0, 0); 1900 tcg_out_opc_reg(s, OPC_MFHI, a1, 0, 0); 1901} 1902 1903static const TCGOutOpMul2 outop_mulu2 = { 1904 .base.static_constraint = C_Dynamic, 1905 .base.dynamic_constraint = cset_mul2, 1906 .out_rrrr = tgen_mulu2, 1907}; 1908 1909static void tgen_muluh(TCGContext *s, TCGType type, 1910 TCGReg a0, TCGReg a1, TCGReg a2) 1911{ 1912 if (use_mips32r6_instructions) { 1913 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MUHU : OPC_DMUHU; 1914 tcg_out_opc_reg(s, insn, a0, a1, a2); 1915 } else { 1916 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_MULTU : OPC_DMULTU; 1917 tcg_out_opc_reg(s, insn, 0, a1, a2); 1918 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1919 } 1920} 1921 1922static const TCGOutOpBinary outop_muluh = { 1923 .base.static_constraint = C_O1_I2(r, r, r), 1924 .out_rrr = tgen_muluh, 1925}; 1926 1927static const TCGOutOpBinary outop_nand = { 1928 .base.static_constraint = C_NotImplemented, 1929}; 1930 1931static void tgen_nor(TCGContext *s, TCGType type, 1932 TCGReg a0, TCGReg a1, TCGReg a2) 1933{ 1934 tcg_out_opc_reg(s, OPC_NOR, a0, a1, a2); 1935} 1936 1937static const TCGOutOpBinary outop_nor = { 1938 .base.static_constraint = C_O1_I2(r, r, r), 1939 .out_rrr = tgen_nor, 1940}; 1941 1942static void tgen_or(TCGContext *s, TCGType type, 1943 TCGReg a0, TCGReg a1, TCGReg a2) 1944{ 1945 tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); 1946} 1947 1948static void tgen_ori(TCGContext *s, TCGType type, 1949 TCGReg a0, TCGReg a1, tcg_target_long a2) 1950{ 1951 tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); 1952} 1953 1954static const TCGOutOpBinary outop_or = { 1955 .base.static_constraint = C_O1_I2(r, r, rI), 1956 .out_rrr = tgen_or, 1957 .out_rri = tgen_ori, 1958}; 1959 1960static const TCGOutOpBinary outop_orc = { 1961 .base.static_constraint = C_NotImplemented, 1962}; 1963 1964static void tgen_rems(TCGContext *s, TCGType type, 1965 TCGReg a0, TCGReg a1, TCGReg a2) 1966{ 1967 if (use_mips32r6_instructions) { 1968 if (type == TCG_TYPE_I32) { 1969 tcg_out_opc_reg(s, OPC_MOD, a0, a1, a2); 1970 } else { 1971 tcg_out_opc_reg(s, OPC_DMOD, a0, a1, a2); 1972 } 1973 } else { 1974 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIV : OPC_DDIV; 1975 tcg_out_opc_reg(s, insn, 0, a1, a2); 1976 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1977 } 1978} 1979 1980static const TCGOutOpBinary outop_rems = { 1981 .base.static_constraint = C_O1_I2(r, r, r), 1982 .out_rrr = tgen_rems, 1983}; 1984 1985static void tgen_remu(TCGContext *s, TCGType type, 1986 TCGReg a0, TCGReg a1, TCGReg a2) 1987{ 1988 if (use_mips32r6_instructions) { 1989 if (type == TCG_TYPE_I32) { 1990 tcg_out_opc_reg(s, OPC_MODU, a0, a1, a2); 1991 } else { 1992 tcg_out_opc_reg(s, OPC_DMODU, a0, a1, a2); 1993 } 1994 } else { 1995 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_DIVU : OPC_DDIVU; 1996 tcg_out_opc_reg(s, insn, 0, a1, a2); 1997 tcg_out_opc_reg(s, OPC_MFHI, a0, 0, 0); 1998 } 1999} 2000 2001static const TCGOutOpBinary outop_remu = { 2002 .base.static_constraint = C_O1_I2(r, r, r), 2003 .out_rrr = tgen_remu, 2004}; 2005 2006static const TCGOutOpBinary outop_rotl = { 2007 .base.static_constraint = C_NotImplemented, 2008}; 2009 2010static TCGConstraintSetIndex cset_rotr(TCGType type, unsigned flags) 2011{ 2012 return use_mips32r2_instructions ? C_O1_I2(r, r, ri) : C_NotImplemented; 2013} 2014 2015static void tgen_rotr(TCGContext *s, TCGType type, 2016 TCGReg a0, TCGReg a1, TCGReg a2) 2017{ 2018 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_ROTRV : OPC_DROTRV; 2019 tcg_out_opc_reg(s, insn, a0, a1, a2); 2020} 2021 2022static void tgen_rotri(TCGContext *s, TCGType type, 2023 TCGReg a0, TCGReg a1, tcg_target_long a2) 2024{ 2025 if (type == TCG_TYPE_I32) { 2026 tcg_out_opc_sa(s, OPC_ROTR, a0, a1, a2); 2027 } else { 2028 tcg_out_opc_sa64(s, OPC_DROTR, OPC_DROTR32, a0, a1, a2); 2029 } 2030} 2031 2032static const TCGOutOpBinary outop_rotr = { 2033 .base.static_constraint = C_Dynamic, 2034 .base.dynamic_constraint = cset_rotr, 2035 .out_rrr = tgen_rotr, 2036 .out_rri = tgen_rotri, 2037}; 2038 2039static void tgen_sar(TCGContext *s, TCGType type, 2040 TCGReg a0, TCGReg a1, TCGReg a2) 2041{ 2042 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRAV : OPC_DSRAV; 2043 tcg_out_opc_reg(s, insn, a0, a1, a2); 2044} 2045 2046static void tgen_sari(TCGContext *s, TCGType type, 2047 TCGReg a0, TCGReg a1, tcg_target_long a2) 2048{ 2049 if (type == TCG_TYPE_I32) { 2050 tcg_out_opc_sa(s, OPC_SRA, a0, a1, a2); 2051 } else { 2052 tcg_out_dsra(s, a0, a1, a2); 2053 } 2054} 2055 2056static const TCGOutOpBinary outop_sar = { 2057 .base.static_constraint = C_O1_I2(r, r, ri), 2058 .out_rrr = tgen_sar, 2059 .out_rri = tgen_sari, 2060}; 2061 2062static void tgen_shl(TCGContext *s, TCGType type, 2063 TCGReg a0, TCGReg a1, TCGReg a2) 2064{ 2065 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SLLV : OPC_DSLLV; 2066 tcg_out_opc_reg(s, insn, a0, a1, a2); 2067} 2068 2069static void tgen_shli(TCGContext *s, TCGType type, 2070 TCGReg a0, TCGReg a1, tcg_target_long a2) 2071{ 2072 if (type == TCG_TYPE_I32) { 2073 tcg_out_opc_sa(s, OPC_SLL, a0, a1, a2); 2074 } else { 2075 tcg_out_dsll(s, a0, a1, a2); 2076 } 2077} 2078 2079static const TCGOutOpBinary outop_shl = { 2080 .base.static_constraint = C_O1_I2(r, r, ri), 2081 .out_rrr = tgen_shl, 2082 .out_rri = tgen_shli, 2083}; 2084 2085static void tgen_shr(TCGContext *s, TCGType type, 2086 TCGReg a0, TCGReg a1, TCGReg a2) 2087{ 2088 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SRLV : OPC_DSRLV; 2089 tcg_out_opc_reg(s, insn, a0, a1, a2); 2090} 2091 2092static void tgen_shri(TCGContext *s, TCGType type, 2093 TCGReg a0, TCGReg a1, tcg_target_long a2) 2094{ 2095 if (type == TCG_TYPE_I32) { 2096 tcg_out_opc_sa(s, OPC_SRL, a0, a1, a2); 2097 } else { 2098 tcg_out_dsrl(s, a0, a1, a2); 2099 } 2100} 2101 2102static const TCGOutOpBinary outop_shr = { 2103 .base.static_constraint = C_O1_I2(r, r, ri), 2104 .out_rrr = tgen_shr, 2105 .out_rri = tgen_shri, 2106}; 2107 2108static void tgen_sub(TCGContext *s, TCGType type, 2109 TCGReg a0, TCGReg a1, TCGReg a2) 2110{ 2111 MIPSInsn insn = type == TCG_TYPE_I32 ? OPC_SUBU : OPC_DSUBU; 2112 tcg_out_opc_reg(s, insn, a0, a1, a2); 2113} 2114 2115static const TCGOutOpSubtract outop_sub = { 2116 .base.static_constraint = C_O1_I2(r, r, r), 2117 .out_rrr = tgen_sub, 2118}; 2119 2120static void tgen_xor(TCGContext *s, TCGType type, 2121 TCGReg a0, TCGReg a1, TCGReg a2) 2122{ 2123 tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); 2124} 2125 2126static void tgen_xori(TCGContext *s, TCGType type, 2127 TCGReg a0, TCGReg a1, tcg_target_long a2) 2128{ 2129 tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); 2130} 2131 2132static const TCGOutOpBinary outop_xor = { 2133 .base.static_constraint = C_O1_I2(r, r, rI), 2134 .out_rrr = tgen_xor, 2135 .out_rri = tgen_xori, 2136}; 2137 2138static void tgen_bswap16(TCGContext *s, TCGType type, 2139 TCGReg ret, TCGReg arg, unsigned flags) 2140{ 2141 /* With arg = abcd: */ 2142 if (use_mips32r2_instructions) { 2143 tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); /* badc */ 2144 if (flags & TCG_BSWAP_OS) { 2145 tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); /* ssdc */ 2146 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 2147 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xffff); /* 00dc */ 2148 } 2149 return; 2150 } 2151 2152 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP0, arg, 8); /* 0abc */ 2153 if (!(flags & TCG_BSWAP_IZ)) { 2154 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP0, TCG_TMP0, 0x00ff); /* 000c */ 2155 } 2156 if (flags & TCG_BSWAP_OS) { 2157 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); /* d000 */ 2158 tcg_out_opc_sa(s, OPC_SRA, ret, ret, 16); /* ssd0 */ 2159 } else { 2160 tcg_out_opc_sa(s, OPC_SLL, ret, arg, 8); /* bcd0 */ 2161 if (flags & TCG_BSWAP_OZ) { 2162 tcg_out_opc_imm(s, OPC_ANDI, ret, ret, 0xff00); /* 00d0 */ 2163 } 2164 } 2165 tcg_out_opc_reg(s, OPC_OR, ret, ret, TCG_TMP0); /* ssdc */ 2166} 2167 2168static const TCGOutOpBswap outop_bswap16 = { 2169 .base.static_constraint = C_O1_I1(r, r), 2170 .out_rr = tgen_bswap16, 2171}; 2172 2173static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2174{ 2175 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 2176} 2177 2178static const TCGOutOpUnary outop_neg = { 2179 .base.static_constraint = C_O1_I1(r, r), 2180 .out_rr = tgen_neg, 2181}; 2182 2183static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 2184{ 2185 tgen_nor(s, type, a0, TCG_REG_ZERO, a1); 2186} 2187 2188static const TCGOutOpUnary outop_not = { 2189 .base.static_constraint = C_O1_I1(r, r), 2190 .out_rr = tgen_not, 2191}; 2192 2193 2194static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2195 const TCGArg args[TCG_MAX_OP_ARGS], 2196 const int const_args[TCG_MAX_OP_ARGS]) 2197{ 2198 MIPSInsn i1; 2199 TCGArg a0, a1, a2; 2200 2201 a0 = args[0]; 2202 a1 = args[1]; 2203 a2 = args[2]; 2204 2205 switch (opc) { 2206 case INDEX_op_goto_ptr: 2207 /* jmp to the given host address (could be epilogue) */ 2208 tcg_out_opc_reg(s, OPC_JR, 0, a0, 0); 2209 if (TCG_TARGET_REG_BITS == 64) { 2210 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, a0); 2211 } else { 2212 tcg_out_nop(s); 2213 } 2214 break; 2215 case INDEX_op_br: 2216 tgen_brcond(s, TCG_TYPE_I32, TCG_COND_EQ, 2217 TCG_REG_ZERO, TCG_REG_ZERO, arg_label(a0)); 2218 break; 2219 2220 case INDEX_op_ld8u_i32: 2221 case INDEX_op_ld8u_i64: 2222 i1 = OPC_LBU; 2223 goto do_ldst; 2224 case INDEX_op_ld8s_i32: 2225 case INDEX_op_ld8s_i64: 2226 i1 = OPC_LB; 2227 goto do_ldst; 2228 case INDEX_op_ld16u_i32: 2229 case INDEX_op_ld16u_i64: 2230 i1 = OPC_LHU; 2231 goto do_ldst; 2232 case INDEX_op_ld16s_i32: 2233 case INDEX_op_ld16s_i64: 2234 i1 = OPC_LH; 2235 goto do_ldst; 2236 case INDEX_op_ld_i32: 2237 case INDEX_op_ld32s_i64: 2238 i1 = OPC_LW; 2239 goto do_ldst; 2240 case INDEX_op_ld32u_i64: 2241 i1 = OPC_LWU; 2242 goto do_ldst; 2243 case INDEX_op_ld_i64: 2244 i1 = OPC_LD; 2245 goto do_ldst; 2246 case INDEX_op_st8_i32: 2247 case INDEX_op_st8_i64: 2248 i1 = OPC_SB; 2249 goto do_ldst; 2250 case INDEX_op_st16_i32: 2251 case INDEX_op_st16_i64: 2252 i1 = OPC_SH; 2253 goto do_ldst; 2254 case INDEX_op_st_i32: 2255 case INDEX_op_st32_i64: 2256 i1 = OPC_SW; 2257 goto do_ldst; 2258 case INDEX_op_st_i64: 2259 i1 = OPC_SD; 2260 do_ldst: 2261 tcg_out_ldst(s, i1, a0, a1, a2); 2262 break; 2263 2264 case INDEX_op_bswap32_i32: 2265 tcg_out_bswap32(s, a0, a1, 0); 2266 break; 2267 case INDEX_op_bswap32_i64: 2268 tcg_out_bswap32(s, a0, a1, a2); 2269 break; 2270 case INDEX_op_bswap64_i64: 2271 tcg_out_bswap64(s, a0, a1); 2272 break; 2273 case INDEX_op_extrh_i64_i32: 2274 tcg_out_dsra(s, a0, a1, 32); 2275 break; 2276 2277 case INDEX_op_deposit_i32: 2278 tcg_out_opc_bf(s, OPC_INS, a0, a2, args[3] + args[4] - 1, args[3]); 2279 break; 2280 case INDEX_op_deposit_i64: 2281 tcg_out_opc_bf64(s, OPC_DINS, OPC_DINSM, OPC_DINSU, a0, a2, 2282 args[3] + args[4] - 1, args[3]); 2283 break; 2284 2285 case INDEX_op_extract_i32: 2286 if (a2 == 0 && args[3] <= 16) { 2287 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2288 } else { 2289 tcg_out_opc_bf(s, OPC_EXT, a0, a1, args[3] - 1, a2); 2290 } 2291 break; 2292 case INDEX_op_extract_i64: 2293 if (a2 == 0 && args[3] <= 16) { 2294 tcg_out_opc_imm(s, OPC_ANDI, a0, a1, (1 << args[3]) - 1); 2295 } else { 2296 tcg_out_opc_bf64(s, OPC_DEXT, OPC_DEXTM, OPC_DEXTU, 2297 a0, a1, args[3] - 1, a2); 2298 } 2299 break; 2300 2301 case INDEX_op_sextract_i64: 2302 if (a2 == 0 && args[3] == 32) { 2303 tcg_out_ext32s(s, a0, a1); 2304 break; 2305 } 2306 /* FALLTHRU */ 2307 case INDEX_op_sextract_i32: 2308 if (a2 == 0 && args[3] == 8) { 2309 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 2310 } else if (a2 == 0 && args[3] == 16) { 2311 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 2312 } else { 2313 g_assert_not_reached(); 2314 } 2315 break; 2316 2317 case INDEX_op_qemu_ld_i32: 2318 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I32); 2319 break; 2320 case INDEX_op_qemu_ld_i64: 2321 if (TCG_TARGET_REG_BITS == 64) { 2322 tcg_out_qemu_ld(s, a0, 0, a1, a2, TCG_TYPE_I64); 2323 } else { 2324 tcg_out_qemu_ld(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2325 } 2326 break; 2327 2328 case INDEX_op_qemu_st_i32: 2329 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I32); 2330 break; 2331 case INDEX_op_qemu_st_i64: 2332 if (TCG_TARGET_REG_BITS == 64) { 2333 tcg_out_qemu_st(s, a0, 0, a1, a2, TCG_TYPE_I64); 2334 } else { 2335 tcg_out_qemu_st(s, a0, a1, a2, args[3], TCG_TYPE_I64); 2336 } 2337 break; 2338 2339 case INDEX_op_add2_i32: 2340 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2341 const_args[4], const_args[5], false); 2342 break; 2343 case INDEX_op_sub2_i32: 2344 tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], 2345 const_args[4], const_args[5], true); 2346 break; 2347 2348 case INDEX_op_mb: 2349 tcg_out_mb(s, a0); 2350 break; 2351 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2352 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2353 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2354 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 2355 case INDEX_op_extu_i32_i64: 2356 case INDEX_op_extrl_i64_i32: 2357 default: 2358 g_assert_not_reached(); 2359 } 2360} 2361 2362static TCGConstraintSetIndex 2363tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2364{ 2365 switch (op) { 2366 case INDEX_op_goto_ptr: 2367 return C_O0_I1(r); 2368 2369 case INDEX_op_ld8u_i32: 2370 case INDEX_op_ld8s_i32: 2371 case INDEX_op_ld16u_i32: 2372 case INDEX_op_ld16s_i32: 2373 case INDEX_op_ld_i32: 2374 case INDEX_op_bswap32_i32: 2375 case INDEX_op_extract_i32: 2376 case INDEX_op_sextract_i32: 2377 case INDEX_op_ld8u_i64: 2378 case INDEX_op_ld8s_i64: 2379 case INDEX_op_ld16u_i64: 2380 case INDEX_op_ld16s_i64: 2381 case INDEX_op_ld32s_i64: 2382 case INDEX_op_ld32u_i64: 2383 case INDEX_op_ld_i64: 2384 case INDEX_op_bswap32_i64: 2385 case INDEX_op_bswap64_i64: 2386 case INDEX_op_ext_i32_i64: 2387 case INDEX_op_extu_i32_i64: 2388 case INDEX_op_extrl_i64_i32: 2389 case INDEX_op_extrh_i64_i32: 2390 case INDEX_op_extract_i64: 2391 case INDEX_op_sextract_i64: 2392 return C_O1_I1(r, r); 2393 2394 case INDEX_op_st8_i32: 2395 case INDEX_op_st16_i32: 2396 case INDEX_op_st_i32: 2397 case INDEX_op_st8_i64: 2398 case INDEX_op_st16_i64: 2399 case INDEX_op_st32_i64: 2400 case INDEX_op_st_i64: 2401 return C_O0_I2(rz, r); 2402 2403 case INDEX_op_deposit_i32: 2404 case INDEX_op_deposit_i64: 2405 return C_O1_I2(r, 0, rz); 2406 case INDEX_op_add2_i32: 2407 case INDEX_op_sub2_i32: 2408 return C_O2_I4(r, r, rz, rz, rN, rN); 2409 2410 case INDEX_op_qemu_ld_i32: 2411 return C_O1_I1(r, r); 2412 case INDEX_op_qemu_st_i32: 2413 return C_O0_I2(rz, r); 2414 case INDEX_op_qemu_ld_i64: 2415 return TCG_TARGET_REG_BITS == 64 ? C_O1_I1(r, r) : C_O2_I1(r, r, r); 2416 case INDEX_op_qemu_st_i64: 2417 return TCG_TARGET_REG_BITS == 64 ? C_O0_I2(rz, r) : C_O0_I3(rz, rz, r); 2418 2419 default: 2420 return C_NotImplemented; 2421 } 2422} 2423 2424static const int tcg_target_callee_save_regs[] = { 2425 TCG_REG_S0, 2426 TCG_REG_S1, 2427 TCG_REG_S2, 2428 TCG_REG_S3, 2429 TCG_REG_S4, 2430 TCG_REG_S5, 2431 TCG_REG_S6, /* used for the tb base (TCG_REG_TB) */ 2432 TCG_REG_S7, /* used for guest_base */ 2433 TCG_REG_S8, /* used for the global env (TCG_AREG0) */ 2434 TCG_REG_RA, /* should be last for ABI compliance */ 2435}; 2436 2437/* The Linux kernel doesn't provide any information about the available 2438 instruction set. Probe it using a signal handler. */ 2439 2440 2441#ifndef use_movnz_instructions 2442bool use_movnz_instructions = false; 2443#endif 2444 2445#ifndef use_mips32_instructions 2446bool use_mips32_instructions = false; 2447#endif 2448 2449#ifndef use_mips32r2_instructions 2450bool use_mips32r2_instructions = false; 2451#endif 2452 2453static volatile sig_atomic_t got_sigill; 2454 2455static void sigill_handler(int signo, siginfo_t *si, void *data) 2456{ 2457 /* Skip the faulty instruction */ 2458 ucontext_t *uc = (ucontext_t *)data; 2459 uc->uc_mcontext.pc += 4; 2460 2461 got_sigill = 1; 2462} 2463 2464static void tcg_target_detect_isa(void) 2465{ 2466 struct sigaction sa_old, sa_new; 2467 2468 memset(&sa_new, 0, sizeof(sa_new)); 2469 sa_new.sa_flags = SA_SIGINFO; 2470 sa_new.sa_sigaction = sigill_handler; 2471 sigaction(SIGILL, &sa_new, &sa_old); 2472 2473 /* Probe for movn/movz, necessary to implement movcond. */ 2474#ifndef use_movnz_instructions 2475 got_sigill = 0; 2476 asm volatile(".set push\n" 2477 ".set mips32\n" 2478 "movn $zero, $zero, $zero\n" 2479 "movz $zero, $zero, $zero\n" 2480 ".set pop\n" 2481 : : : ); 2482 use_movnz_instructions = !got_sigill; 2483#endif 2484 2485 /* Probe for MIPS32 instructions. As no subsetting is allowed 2486 by the specification, it is only necessary to probe for one 2487 of the instructions. */ 2488#ifndef use_mips32_instructions 2489 got_sigill = 0; 2490 asm volatile(".set push\n" 2491 ".set mips32\n" 2492 "mul $zero, $zero\n" 2493 ".set pop\n" 2494 : : : ); 2495 use_mips32_instructions = !got_sigill; 2496#endif 2497 2498 /* Probe for MIPS32r2 instructions if MIPS32 instructions are 2499 available. As no subsetting is allowed by the specification, 2500 it is only necessary to probe for one of the instructions. */ 2501#ifndef use_mips32r2_instructions 2502 if (use_mips32_instructions) { 2503 got_sigill = 0; 2504 asm volatile(".set push\n" 2505 ".set mips32r2\n" 2506 "seb $zero, $zero\n" 2507 ".set pop\n" 2508 : : : ); 2509 use_mips32r2_instructions = !got_sigill; 2510 } 2511#endif 2512 2513 sigaction(SIGILL, &sa_old, NULL); 2514} 2515 2516static tcg_insn_unit *align_code_ptr(TCGContext *s) 2517{ 2518 uintptr_t p = (uintptr_t)s->code_ptr; 2519 if (p & 15) { 2520 p = (p + 15) & -16; 2521 s->code_ptr = (void *)p; 2522 } 2523 return s->code_ptr; 2524} 2525 2526/* Stack frame parameters. */ 2527#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2528#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2529#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2530 2531#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2532 + TCG_TARGET_STACK_ALIGN - 1) \ 2533 & -TCG_TARGET_STACK_ALIGN) 2534#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2535 2536/* We're expecting to be able to use an immediate for frame allocation. */ 2537QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7fff); 2538 2539/* Generate global QEMU prologue and epilogue code */ 2540static void tcg_target_qemu_prologue(TCGContext *s) 2541{ 2542 int i; 2543 2544 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2545 2546 /* TB prologue */ 2547 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2548 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2549 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2550 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2551 } 2552 2553 if (!tcg_use_softmmu && guest_base != (int16_t)guest_base) { 2554 /* 2555 * The function call abi for n32 and n64 will have loaded $25 (t9) 2556 * with the address of the prologue, so we can use that instead 2557 * of TCG_REG_TB. 2558 */ 2559#if TCG_TARGET_REG_BITS == 64 && !defined(__mips_abicalls) 2560# error "Unknown mips abi" 2561#endif 2562 tcg_out_movi_int(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base, 2563 TCG_TARGET_REG_BITS == 64 ? TCG_REG_T9 : 0); 2564 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2565 } 2566 2567 if (TCG_TARGET_REG_BITS == 64) { 2568 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_TB, tcg_target_call_iarg_regs[1]); 2569 } 2570 2571 /* Call generated code */ 2572 tcg_out_opc_reg(s, OPC_JR, 0, tcg_target_call_iarg_regs[1], 0); 2573 /* delay slot */ 2574 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2575 2576 /* 2577 * Return path for goto_ptr. Set return value to 0, a-la exit_tb, 2578 * and fall through to the rest of the epilogue. 2579 */ 2580 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2581 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_V0, TCG_REG_ZERO); 2582 2583 /* TB epilogue */ 2584 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2585 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2586 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2587 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2588 } 2589 2590 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2591 /* delay slot */ 2592 tcg_out_opc_imm(s, ALIAS_PADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2593 2594 if (use_mips32r2_instructions) { 2595 return; 2596 } 2597 2598 /* Bswap subroutines: Input in TCG_TMP0, output in TCG_TMP3; 2599 clobbers TCG_TMP1, TCG_TMP2. */ 2600 2601 /* 2602 * bswap32 -- 32-bit swap (signed result for mips64). a0 = abcd. 2603 */ 2604 bswap32_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2605 /* t3 = (ssss)d000 */ 2606 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP3, TCG_TMP0, 24); 2607 /* t1 = 000a */ 2608 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 24); 2609 /* t2 = 00c0 */ 2610 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2611 /* t3 = d00a */ 2612 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2613 /* t1 = 0abc */ 2614 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2615 /* t2 = 0c00 */ 2616 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2617 /* t1 = 00b0 */ 2618 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2619 /* t3 = dc0a */ 2620 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2621 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2622 /* t3 = dcba -- delay slot */ 2623 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2624 2625 if (TCG_TARGET_REG_BITS == 32) { 2626 return; 2627 } 2628 2629 /* 2630 * bswap32u -- unsigned 32-bit swap. a0 = ....abcd. 2631 */ 2632 bswap32u_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2633 /* t1 = (0000)000d */ 2634 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP0, 0xff); 2635 /* t3 = 000a */ 2636 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP3, TCG_TMP0, 24); 2637 /* t1 = (0000)d000 */ 2638 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2639 /* t2 = 00c0 */ 2640 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2641 /* t3 = d00a */ 2642 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2643 /* t1 = 0abc */ 2644 tcg_out_opc_sa(s, OPC_SRL, TCG_TMP1, TCG_TMP0, 8); 2645 /* t2 = 0c00 */ 2646 tcg_out_opc_sa(s, OPC_SLL, TCG_TMP2, TCG_TMP2, 8); 2647 /* t1 = 00b0 */ 2648 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2649 /* t3 = dc0a */ 2650 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2651 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2652 /* t3 = dcba -- delay slot */ 2653 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2654 2655 /* 2656 * bswap64 -- 64-bit swap. a0 = abcdefgh 2657 */ 2658 bswap64_addr = tcg_splitwx_to_rx(align_code_ptr(s)); 2659 /* t3 = h0000000 */ 2660 tcg_out_dsll(s, TCG_TMP3, TCG_TMP0, 56); 2661 /* t1 = 0000000a */ 2662 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 56); 2663 2664 /* t2 = 000000g0 */ 2665 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP0, 0xff00); 2666 /* t3 = h000000a */ 2667 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2668 /* t1 = 00000abc */ 2669 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 40); 2670 /* t2 = 0g000000 */ 2671 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2672 /* t1 = 000000b0 */ 2673 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2674 2675 /* t3 = hg00000a */ 2676 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2677 /* t2 = 0000abcd */ 2678 tcg_out_dsrl(s, TCG_TMP2, TCG_TMP0, 32); 2679 /* t3 = hg0000ba */ 2680 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2681 2682 /* t1 = 000000c0 */ 2683 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP2, 0xff00); 2684 /* t2 = 0000000d */ 2685 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP2, 0x00ff); 2686 /* t1 = 00000c00 */ 2687 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 8); 2688 /* t2 = 0000d000 */ 2689 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 24); 2690 2691 /* t3 = hg000cba */ 2692 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2693 /* t1 = 00abcdef */ 2694 tcg_out_dsrl(s, TCG_TMP1, TCG_TMP0, 16); 2695 /* t3 = hg00dcba */ 2696 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2697 2698 /* t2 = 0000000f */ 2699 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP2, TCG_TMP1, 0x00ff); 2700 /* t1 = 000000e0 */ 2701 tcg_out_opc_imm(s, OPC_ANDI, TCG_TMP1, TCG_TMP1, 0xff00); 2702 /* t2 = 00f00000 */ 2703 tcg_out_dsll(s, TCG_TMP2, TCG_TMP2, 40); 2704 /* t1 = 000e0000 */ 2705 tcg_out_dsll(s, TCG_TMP1, TCG_TMP1, 24); 2706 2707 /* t3 = hgf0dcba */ 2708 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP2); 2709 tcg_out_opc_reg(s, OPC_JR, 0, TCG_REG_RA, 0); 2710 /* t3 = hgfedcba -- delay slot */ 2711 tcg_out_opc_reg(s, OPC_OR, TCG_TMP3, TCG_TMP3, TCG_TMP1); 2712} 2713 2714static void tcg_out_tb_start(TCGContext *s) 2715{ 2716 /* nothing to do */ 2717} 2718 2719static void tcg_target_init(TCGContext *s) 2720{ 2721 tcg_target_detect_isa(); 2722 tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; 2723 if (TCG_TARGET_REG_BITS == 64) { 2724 tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; 2725 } 2726 2727 tcg_target_call_clobber_regs = 0; 2728 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V0); 2729 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_V1); 2730 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A0); 2731 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A1); 2732 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A2); 2733 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_A3); 2734 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T0); 2735 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T1); 2736 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T2); 2737 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T3); 2738 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T4); 2739 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T5); 2740 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T6); 2741 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T7); 2742 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T8); 2743 tcg_regset_set_reg(tcg_target_call_clobber_regs, TCG_REG_T9); 2744 2745 s->reserved_regs = 0; 2746 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); /* zero register */ 2747 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K0); /* kernel use only */ 2748 tcg_regset_set_reg(s->reserved_regs, TCG_REG_K1); /* kernel use only */ 2749 tcg_regset_set_reg(s->reserved_regs, TCG_TMP0); /* internal use */ 2750 tcg_regset_set_reg(s->reserved_regs, TCG_TMP1); /* internal use */ 2751 tcg_regset_set_reg(s->reserved_regs, TCG_TMP2); /* internal use */ 2752 tcg_regset_set_reg(s->reserved_regs, TCG_TMP3); /* internal use */ 2753 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RA); /* return address */ 2754 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); /* stack pointer */ 2755 tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); /* global pointer */ 2756 if (TCG_TARGET_REG_BITS == 64) { 2757 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TB); /* tc->tc_ptr */ 2758 } 2759} 2760 2761typedef struct { 2762 DebugFrameHeader h; 2763 uint8_t fde_def_cfa[4]; 2764 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2765} DebugFrame; 2766 2767#define ELF_HOST_MACHINE EM_MIPS 2768/* GDB doesn't appear to require proper setting of ELF_HOST_FLAGS, 2769 which is good because they're really quite complicated for MIPS. */ 2770 2771static const DebugFrame debug_frame = { 2772 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2773 .h.cie.id = -1, 2774 .h.cie.version = 1, 2775 .h.cie.code_align = 1, 2776 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2777 .h.cie.return_column = TCG_REG_RA, 2778 2779 /* Total FDE size does not include the "len" member. */ 2780 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2781 2782 .fde_def_cfa = { 2783 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2784 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2785 (FRAME_SIZE >> 7) 2786 }, 2787 .fde_reg_ofs = { 2788 0x80 + 16, 9, /* DW_CFA_offset, s0, -72 */ 2789 0x80 + 17, 8, /* DW_CFA_offset, s2, -64 */ 2790 0x80 + 18, 7, /* DW_CFA_offset, s3, -56 */ 2791 0x80 + 19, 6, /* DW_CFA_offset, s4, -48 */ 2792 0x80 + 20, 5, /* DW_CFA_offset, s5, -40 */ 2793 0x80 + 21, 4, /* DW_CFA_offset, s6, -32 */ 2794 0x80 + 22, 3, /* DW_CFA_offset, s7, -24 */ 2795 0x80 + 30, 2, /* DW_CFA_offset, s8, -16 */ 2796 0x80 + 31, 1, /* DW_CFA_offset, ra, -8 */ 2797 } 2798}; 2799 2800void tcg_register_jit(const void *buf, size_t buf_size) 2801{ 2802 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2803} 2804