1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 */ 7 8 #ifndef TCG_TARGET_HAS_H 9 #define TCG_TARGET_HAS_H 10 11 /* MOVN/MOVZ instructions detection */ 12 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ 13 defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \ 14 defined(_MIPS_ARCH_MIPS4) 15 #define use_movnz_instructions 1 16 #else 17 extern bool use_movnz_instructions; 18 #endif 19 20 /* MIPS32 instruction set detection */ 21 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1) 22 #define use_mips32_instructions 1 23 #else 24 extern bool use_mips32_instructions; 25 #endif 26 27 /* MIPS32R2 instruction set detection */ 28 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 29 #define use_mips32r2_instructions 1 30 #else 31 extern bool use_mips32r2_instructions; 32 #endif 33 34 /* MIPS32R6 instruction set detection */ 35 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 6) 36 #define use_mips32r6_instructions 1 37 #else 38 #define use_mips32r6_instructions 0 39 #endif 40 41 /* optional instructions */ 42 #define TCG_TARGET_HAS_div_i32 1 43 #define TCG_TARGET_HAS_rem_i32 1 44 #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions) 45 #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions) 46 #define TCG_TARGET_HAS_bswap16_i32 1 47 #define TCG_TARGET_HAS_bswap32_i32 1 48 #define TCG_TARGET_HAS_negsetcond_i32 0 49 50 #if TCG_TARGET_REG_BITS == 64 51 #define TCG_TARGET_HAS_add2_i32 0 52 #define TCG_TARGET_HAS_sub2_i32 0 53 #define TCG_TARGET_HAS_extr_i64_i32 1 54 #define TCG_TARGET_HAS_div_i64 1 55 #define TCG_TARGET_HAS_rem_i64 1 56 #define TCG_TARGET_HAS_add2_i64 0 57 #define TCG_TARGET_HAS_sub2_i64 0 58 #define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions) 59 #define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions) 60 #define TCG_TARGET_HAS_ext32s_i64 1 61 #define TCG_TARGET_HAS_ext32u_i64 1 62 #define TCG_TARGET_HAS_negsetcond_i64 0 63 #endif 64 65 /* optional instructions detected at runtime */ 66 #define TCG_TARGET_HAS_extract2_i32 0 67 #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions 68 #define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions 69 #define TCG_TARGET_HAS_ctz_i32 0 70 #define TCG_TARGET_HAS_ctpop_i32 0 71 #define TCG_TARGET_HAS_qemu_st8_i32 0 72 73 #if TCG_TARGET_REG_BITS == 64 74 #define TCG_TARGET_HAS_bswap16_i64 1 75 #define TCG_TARGET_HAS_bswap32_i64 1 76 #define TCG_TARGET_HAS_bswap64_i64 1 77 #define TCG_TARGET_HAS_extract2_i64 0 78 #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions 79 #define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions 80 #define TCG_TARGET_HAS_ctz_i64 0 81 #define TCG_TARGET_HAS_ctpop_i64 0 82 #endif 83 84 #define TCG_TARGET_HAS_qemu_ldst_i128 0 85 #define TCG_TARGET_HAS_tst 0 86 87 #define TCG_TARGET_extract_valid(type, ofs, len) use_mips32r2_instructions 88 #define TCG_TARGET_deposit_valid(type, ofs, len) use_mips32r2_instructions 89 90 static inline bool 91 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 92 { 93 if (ofs == 0) { 94 switch (len) { 95 case 8: 96 case 16: 97 return use_mips32r2_instructions; 98 case 32: 99 return type == TCG_TYPE_I64; 100 } 101 } 102 return false; 103 } 104 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 105 106 #endif 107