1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 6 */ 7 8 #ifndef TCG_TARGET_HAS_H 9 #define TCG_TARGET_HAS_H 10 11 /* MOVN/MOVZ instructions detection */ 12 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ 13 defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \ 14 defined(_MIPS_ARCH_MIPS4) 15 #define use_movnz_instructions 1 16 #else 17 extern bool use_movnz_instructions; 18 #endif 19 20 /* MIPS32 instruction set detection */ 21 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1) 22 #define use_mips32_instructions 1 23 #else 24 extern bool use_mips32_instructions; 25 #endif 26 27 /* MIPS32R2 instruction set detection */ 28 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) 29 #define use_mips32r2_instructions 1 30 #else 31 extern bool use_mips32r2_instructions; 32 #endif 33 34 /* MIPS32R6 instruction set detection */ 35 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 6) 36 #define use_mips32r6_instructions 1 37 #else 38 #define use_mips32r6_instructions 0 39 #endif 40 41 /* optional instructions */ 42 #define TCG_TARGET_HAS_rem_i32 1 43 #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions) 44 #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions) 45 #define TCG_TARGET_HAS_bswap16_i32 1 46 #define TCG_TARGET_HAS_bswap32_i32 1 47 #define TCG_TARGET_HAS_negsetcond_i32 0 48 49 #if TCG_TARGET_REG_BITS == 64 50 #define TCG_TARGET_HAS_add2_i32 0 51 #define TCG_TARGET_HAS_sub2_i32 0 52 #define TCG_TARGET_HAS_extr_i64_i32 1 53 #define TCG_TARGET_HAS_rem_i64 1 54 #define TCG_TARGET_HAS_add2_i64 0 55 #define TCG_TARGET_HAS_sub2_i64 0 56 #define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions) 57 #define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions) 58 #define TCG_TARGET_HAS_ext32s_i64 1 59 #define TCG_TARGET_HAS_ext32u_i64 1 60 #define TCG_TARGET_HAS_negsetcond_i64 0 61 #endif 62 63 /* optional instructions detected at runtime */ 64 #define TCG_TARGET_HAS_extract2_i32 0 65 #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions 66 #define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions 67 #define TCG_TARGET_HAS_ctz_i32 0 68 #define TCG_TARGET_HAS_ctpop_i32 0 69 #define TCG_TARGET_HAS_qemu_st8_i32 0 70 71 #if TCG_TARGET_REG_BITS == 64 72 #define TCG_TARGET_HAS_bswap16_i64 1 73 #define TCG_TARGET_HAS_bswap32_i64 1 74 #define TCG_TARGET_HAS_bswap64_i64 1 75 #define TCG_TARGET_HAS_extract2_i64 0 76 #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions 77 #define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions 78 #define TCG_TARGET_HAS_ctz_i64 0 79 #define TCG_TARGET_HAS_ctpop_i64 0 80 #endif 81 82 #define TCG_TARGET_HAS_qemu_ldst_i128 0 83 #define TCG_TARGET_HAS_tst 0 84 85 #define TCG_TARGET_extract_valid(type, ofs, len) use_mips32r2_instructions 86 #define TCG_TARGET_deposit_valid(type, ofs, len) use_mips32r2_instructions 87 88 static inline bool 89 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 90 { 91 if (ofs == 0) { 92 switch (len) { 93 case 8: 94 case 16: 95 return use_mips32r2_instructions; 96 case 32: 97 return type == TCG_TYPE_I64; 98 } 99 } 100 return false; 101 } 102 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 103 104 #endif 105