1 /* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.h 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a copy 11 * of this software and associated documentation files (the "Software"), to deal 12 * in the Software without restriction, including without limitation the rights 13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 14 * copies of the Software, and to permit persons to whom the Software is 15 * furnished to do so, subject to the following conditions: 16 * 17 * The above copyright notice and this permission notice shall be included in 18 * all copies or substantial portions of the Software. 19 * 20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 26 * THE SOFTWARE. 27 */ 28 29 #ifndef LOONGARCH_TCG_TARGET_H 30 #define LOONGARCH_TCG_TARGET_H 31 32 #define TCG_TARGET_INSN_UNIT_SIZE 4 33 #define TCG_TARGET_NB_REGS 32 34 35 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) 36 37 typedef enum { 38 TCG_REG_ZERO, 39 TCG_REG_RA, 40 TCG_REG_TP, 41 TCG_REG_SP, 42 TCG_REG_A0, 43 TCG_REG_A1, 44 TCG_REG_A2, 45 TCG_REG_A3, 46 TCG_REG_A4, 47 TCG_REG_A5, 48 TCG_REG_A6, 49 TCG_REG_A7, 50 TCG_REG_T0, 51 TCG_REG_T1, 52 TCG_REG_T2, 53 TCG_REG_T3, 54 TCG_REG_T4, 55 TCG_REG_T5, 56 TCG_REG_T6, 57 TCG_REG_T7, 58 TCG_REG_T8, 59 TCG_REG_RESERVED, 60 TCG_REG_S9, 61 TCG_REG_S0, 62 TCG_REG_S1, 63 TCG_REG_S2, 64 TCG_REG_S3, 65 TCG_REG_S4, 66 TCG_REG_S5, 67 TCG_REG_S6, 68 TCG_REG_S7, 69 TCG_REG_S8, 70 71 /* aliases */ 72 TCG_AREG0 = TCG_REG_S0, 73 TCG_REG_TMP0 = TCG_REG_T8, 74 TCG_REG_TMP1 = TCG_REG_T7, 75 TCG_REG_TMP2 = TCG_REG_T6, 76 } TCGReg; 77 78 /* used for function call generation */ 79 #define TCG_REG_CALL_STACK TCG_REG_SP 80 #define TCG_TARGET_STACK_ALIGN 16 81 #define TCG_TARGET_CALL_STACK_OFFSET 0 82 #define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 83 #define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 84 #define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 85 #define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 86 87 /* optional instructions */ 88 #define TCG_TARGET_HAS_movcond_i32 1 89 #define TCG_TARGET_HAS_div_i32 1 90 #define TCG_TARGET_HAS_rem_i32 1 91 #define TCG_TARGET_HAS_div2_i32 0 92 #define TCG_TARGET_HAS_rot_i32 1 93 #define TCG_TARGET_HAS_deposit_i32 1 94 #define TCG_TARGET_HAS_extract_i32 1 95 #define TCG_TARGET_HAS_sextract_i32 0 96 #define TCG_TARGET_HAS_extract2_i32 0 97 #define TCG_TARGET_HAS_add2_i32 0 98 #define TCG_TARGET_HAS_sub2_i32 0 99 #define TCG_TARGET_HAS_mulu2_i32 0 100 #define TCG_TARGET_HAS_muls2_i32 0 101 #define TCG_TARGET_HAS_muluh_i32 1 102 #define TCG_TARGET_HAS_mulsh_i32 1 103 #define TCG_TARGET_HAS_ext8s_i32 1 104 #define TCG_TARGET_HAS_ext16s_i32 1 105 #define TCG_TARGET_HAS_ext8u_i32 1 106 #define TCG_TARGET_HAS_ext16u_i32 1 107 #define TCG_TARGET_HAS_bswap16_i32 1 108 #define TCG_TARGET_HAS_bswap32_i32 1 109 #define TCG_TARGET_HAS_not_i32 1 110 #define TCG_TARGET_HAS_neg_i32 0 111 #define TCG_TARGET_HAS_andc_i32 1 112 #define TCG_TARGET_HAS_orc_i32 1 113 #define TCG_TARGET_HAS_eqv_i32 0 114 #define TCG_TARGET_HAS_nand_i32 0 115 #define TCG_TARGET_HAS_nor_i32 1 116 #define TCG_TARGET_HAS_clz_i32 1 117 #define TCG_TARGET_HAS_ctz_i32 1 118 #define TCG_TARGET_HAS_ctpop_i32 0 119 #define TCG_TARGET_HAS_brcond2 0 120 #define TCG_TARGET_HAS_setcond2 0 121 #define TCG_TARGET_HAS_qemu_st8_i32 0 122 123 /* 64-bit operations */ 124 #define TCG_TARGET_HAS_movcond_i64 1 125 #define TCG_TARGET_HAS_div_i64 1 126 #define TCG_TARGET_HAS_rem_i64 1 127 #define TCG_TARGET_HAS_div2_i64 0 128 #define TCG_TARGET_HAS_rot_i64 1 129 #define TCG_TARGET_HAS_deposit_i64 1 130 #define TCG_TARGET_HAS_extract_i64 1 131 #define TCG_TARGET_HAS_sextract_i64 0 132 #define TCG_TARGET_HAS_extract2_i64 0 133 #define TCG_TARGET_HAS_extrl_i64_i32 1 134 #define TCG_TARGET_HAS_extrh_i64_i32 1 135 #define TCG_TARGET_HAS_ext8s_i64 1 136 #define TCG_TARGET_HAS_ext16s_i64 1 137 #define TCG_TARGET_HAS_ext32s_i64 1 138 #define TCG_TARGET_HAS_ext8u_i64 1 139 #define TCG_TARGET_HAS_ext16u_i64 1 140 #define TCG_TARGET_HAS_ext32u_i64 1 141 #define TCG_TARGET_HAS_bswap16_i64 1 142 #define TCG_TARGET_HAS_bswap32_i64 1 143 #define TCG_TARGET_HAS_bswap64_i64 1 144 #define TCG_TARGET_HAS_not_i64 1 145 #define TCG_TARGET_HAS_neg_i64 0 146 #define TCG_TARGET_HAS_andc_i64 1 147 #define TCG_TARGET_HAS_orc_i64 1 148 #define TCG_TARGET_HAS_eqv_i64 0 149 #define TCG_TARGET_HAS_nand_i64 0 150 #define TCG_TARGET_HAS_nor_i64 1 151 #define TCG_TARGET_HAS_clz_i64 1 152 #define TCG_TARGET_HAS_ctz_i64 1 153 #define TCG_TARGET_HAS_ctpop_i64 0 154 #define TCG_TARGET_HAS_add2_i64 0 155 #define TCG_TARGET_HAS_sub2_i64 0 156 #define TCG_TARGET_HAS_mulu2_i64 0 157 #define TCG_TARGET_HAS_muls2_i64 0 158 #define TCG_TARGET_HAS_muluh_i64 1 159 #define TCG_TARGET_HAS_mulsh_i64 1 160 #define TCG_TARGET_HAS_qemu_ldst_i128 0 161 162 #define TCG_TARGET_DEFAULT_MO (0) 163 164 #define TCG_TARGET_NEED_LDST_LABELS 165 166 #endif /* LOONGARCH_TCG_TARGET_H */ 167