1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include <asm/hwcap.h> 33 34/* used for function call generation */ 35#define TCG_REG_CALL_STACK TCG_REG_SP 36#define TCG_TARGET_STACK_ALIGN 16 37#define TCG_TARGET_CALL_STACK_OFFSET 0 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 41#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 42 43#ifdef CONFIG_DEBUG_TCG 44static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 45 "zero", 46 "ra", 47 "tp", 48 "sp", 49 "a0", 50 "a1", 51 "a2", 52 "a3", 53 "a4", 54 "a5", 55 "a6", 56 "a7", 57 "t0", 58 "t1", 59 "t2", 60 "t3", 61 "t4", 62 "t5", 63 "t6", 64 "t7", 65 "t8", 66 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 67 "s9", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "s8", 77 "vr0", 78 "vr1", 79 "vr2", 80 "vr3", 81 "vr4", 82 "vr5", 83 "vr6", 84 "vr7", 85 "vr8", 86 "vr9", 87 "vr10", 88 "vr11", 89 "vr12", 90 "vr13", 91 "vr14", 92 "vr15", 93 "vr16", 94 "vr17", 95 "vr18", 96 "vr19", 97 "vr20", 98 "vr21", 99 "vr22", 100 "vr23", 101 "vr24", 102 "vr25", 103 "vr26", 104 "vr27", 105 "vr28", 106 "vr29", 107 "vr30", 108 "vr31", 109}; 110#endif 111 112static const int tcg_target_reg_alloc_order[] = { 113 /* Registers preserved across calls */ 114 /* TCG_REG_S0 reserved for TCG_AREG0 */ 115 TCG_REG_S1, 116 TCG_REG_S2, 117 TCG_REG_S3, 118 TCG_REG_S4, 119 TCG_REG_S5, 120 TCG_REG_S6, 121 TCG_REG_S7, 122 TCG_REG_S8, 123 TCG_REG_S9, 124 125 /* Registers (potentially) clobbered across calls */ 126 TCG_REG_T0, 127 TCG_REG_T1, 128 TCG_REG_T2, 129 TCG_REG_T3, 130 TCG_REG_T4, 131 TCG_REG_T5, 132 TCG_REG_T6, 133 TCG_REG_T7, 134 TCG_REG_T8, 135 136 /* Argument registers, opposite order of allocation. */ 137 TCG_REG_A7, 138 TCG_REG_A6, 139 TCG_REG_A5, 140 TCG_REG_A4, 141 TCG_REG_A3, 142 TCG_REG_A2, 143 TCG_REG_A1, 144 TCG_REG_A0, 145 146 /* Vector registers */ 147 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 148 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 149 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 150 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 151 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 152 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 153 /* V24 - V31 are caller-saved, and skipped. */ 154}; 155 156static const int tcg_target_call_iarg_regs[] = { 157 TCG_REG_A0, 158 TCG_REG_A1, 159 TCG_REG_A2, 160 TCG_REG_A3, 161 TCG_REG_A4, 162 TCG_REG_A5, 163 TCG_REG_A6, 164 TCG_REG_A7, 165}; 166 167static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 168{ 169 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 170 tcg_debug_assert(slot >= 0 && slot <= 1); 171 return TCG_REG_A0 + slot; 172} 173 174#define TCG_GUEST_BASE_REG TCG_REG_S1 175 176#define TCG_CT_CONST_S12 0x100 177#define TCG_CT_CONST_S32 0x200 178#define TCG_CT_CONST_U12 0x400 179#define TCG_CT_CONST_WSZ 0x800 180#define TCG_CT_CONST_VCMP 0x1000 181#define TCG_CT_CONST_VADD 0x2000 182 183#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 184#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 185 186static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 187{ 188 return sextract64(val, pos, len); 189} 190 191/* test if a constant matches the constraint */ 192static bool tcg_target_const_match(int64_t val, int ct, 193 TCGType type, TCGCond cond, int vece) 194{ 195 if (ct & TCG_CT_CONST) { 196 return true; 197 } 198 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 199 return true; 200 } 201 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 202 return true; 203 } 204 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 205 return true; 206 } 207 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return true; 209 } 210 if (ct & (TCG_CT_CONST_VCMP | TCG_CT_CONST_VADD)) { 211 int64_t vec_val = sextract64(val, 0, 8 << vece); 212 if (ct & TCG_CT_CONST_VCMP) { 213 switch (cond) { 214 case TCG_COND_EQ: 215 case TCG_COND_LE: 216 case TCG_COND_LT: 217 return -0x10 <= vec_val && vec_val <= 0x0f; 218 case TCG_COND_LEU: 219 case TCG_COND_LTU: 220 return 0x00 <= vec_val && vec_val <= 0x1f; 221 default: 222 return false; 223 } 224 } 225 if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) { 226 return true; 227 } 228 } 229 return false; 230} 231 232/* 233 * Relocations 234 */ 235 236/* 237 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 238 * complicated; a whopping stack machine is needed to stuff the fields, at 239 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 240 * needed. 241 * 242 * Hence, define our own simpler relocation types. Numbers are chosen as to 243 * not collide with potential future additions to the true ELF relocation 244 * type enum. 245 */ 246 247/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 248#define R_LOONGARCH_BR_SK16 256 249/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 250#define R_LOONGARCH_BR_SD10K16 257 251 252static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 253{ 254 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 255 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 256 257 tcg_debug_assert((offset & 3) == 0); 258 offset >>= 2; 259 if (offset == sextreg(offset, 0, 16)) { 260 *src_rw = deposit64(*src_rw, 10, 16, offset); 261 return true; 262 } 263 264 return false; 265} 266 267static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 268 const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 272 273 tcg_debug_assert((offset & 3) == 0); 274 offset >>= 2; 275 if (offset == sextreg(offset, 0, 26)) { 276 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 277 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 278 return true; 279 } 280 281 return false; 282} 283 284static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 285 intptr_t value, intptr_t addend) 286{ 287 tcg_debug_assert(addend == 0); 288 switch (type) { 289 case R_LOONGARCH_BR_SK16: 290 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 291 case R_LOONGARCH_BR_SD10K16: 292 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 293 default: 294 g_assert_not_reached(); 295 } 296} 297 298#include "tcg-insn-defs.c.inc" 299 300/* 301 * TCG intrinsics 302 */ 303 304static void tcg_out_mb(TCGContext *s, TCGArg a0) 305{ 306 /* Baseline LoongArch only has the full barrier, unfortunately. */ 307 tcg_out_opc_dbar(s, 0); 308} 309 310static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 311{ 312 if (ret == arg) { 313 return true; 314 } 315 switch (type) { 316 case TCG_TYPE_I32: 317 case TCG_TYPE_I64: 318 if (ret < TCG_REG_V0) { 319 if (arg < TCG_REG_V0) { 320 /* 321 * Conventional register-register move used in LoongArch is 322 * `or dst, src, zero`. 323 */ 324 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 325 } else { 326 tcg_out_opc_movfr2gr_d(s, ret, arg); 327 } 328 } else { 329 if (arg < TCG_REG_V0) { 330 tcg_out_opc_movgr2fr_d(s, ret, arg); 331 } else { 332 tcg_out_opc_fmov_d(s, ret, arg); 333 } 334 } 335 break; 336 case TCG_TYPE_V64: 337 case TCG_TYPE_V128: 338 tcg_out_opc_vori_b(s, ret, arg, 0); 339 break; 340 case TCG_TYPE_V256: 341 tcg_out_opc_xvori_b(s, ret, arg, 0); 342 break; 343 default: 344 g_assert_not_reached(); 345 } 346 return true; 347} 348 349/* Loads a 32-bit immediate into rd, sign-extended. */ 350static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 351{ 352 tcg_target_long lo = sextreg(val, 0, 12); 353 tcg_target_long hi12 = sextreg(val, 12, 20); 354 355 /* Single-instruction cases. */ 356 if (hi12 == 0) { 357 /* val fits in uimm12: ori rd, zero, val */ 358 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 359 return; 360 } 361 if (hi12 == sextreg(lo, 12, 20)) { 362 /* val fits in simm12: addi.w rd, zero, val */ 363 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 364 return; 365 } 366 367 /* High bits must be set; load with lu12i.w + optional ori. */ 368 tcg_out_opc_lu12i_w(s, rd, hi12); 369 if (lo != 0) { 370 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 371 } 372} 373 374static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 375 tcg_target_long val) 376{ 377 /* 378 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 379 * with dedicated instructions for filling the respective bitfields 380 * below: 381 * 382 * 6 5 4 3 383 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 384 * +-----------------------+---------------------------------------+... 385 * | hi52 | hi32 | 386 * +-----------------------+---------------------------------------+... 387 * 3 2 1 388 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 389 * ...+-------------------------------------+-------------------------+ 390 * | hi12 | lo | 391 * ...+-------------------------------------+-------------------------+ 392 * 393 * Check if val belong to one of the several fast cases, before falling 394 * back to the slow path. 395 */ 396 397 intptr_t src_rx, pc_offset; 398 tcg_target_long hi12, hi32, hi52; 399 400 /* Value fits in signed i32. */ 401 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 402 tcg_out_movi_i32(s, rd, val); 403 return; 404 } 405 406 /* PC-relative cases. */ 407 src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr); 408 if ((val & 3) == 0) { 409 pc_offset = val - src_rx; 410 if (pc_offset == sextreg(pc_offset, 0, 22)) { 411 /* Single pcaddu2i. */ 412 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 413 return; 414 } 415 } 416 417 pc_offset = (val >> 12) - (src_rx >> 12); 418 if (pc_offset == sextreg(pc_offset, 0, 20)) { 419 /* Load with pcalau12i + ori. */ 420 tcg_target_long val_lo = val & 0xfff; 421 tcg_out_opc_pcalau12i(s, rd, pc_offset); 422 if (val_lo != 0) { 423 tcg_out_opc_ori(s, rd, rd, val_lo); 424 } 425 return; 426 } 427 428 hi12 = sextreg(val, 12, 20); 429 hi32 = sextreg(val, 32, 20); 430 hi52 = sextreg(val, 52, 12); 431 432 /* Single cu52i.d case. */ 433 if ((hi52 != 0) && (ctz64(val) >= 52)) { 434 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 435 return; 436 } 437 438 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 439 tcg_out_movi_i32(s, rd, val); 440 441 /* Load hi32 and hi52 explicitly when they are unexpected values. */ 442 if (hi32 != sextreg(hi12, 20, 20)) { 443 tcg_out_opc_cu32i_d(s, rd, hi32); 444 } 445 446 if (hi52 != sextreg(hi32, 20, 12)) { 447 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 448 } 449} 450 451static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, 452 TCGReg rs, tcg_target_long imm) 453{ 454 tcg_target_long lo12 = sextreg(imm, 0, 12); 455 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16); 456 457 /* 458 * Note that there's a hole in between hi16 and lo12: 459 * 460 * 3 2 1 0 461 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 462 * ...+-------------------------------+-------+-----------------------+ 463 * | hi16 | | lo12 | 464 * ...+-------------------------------+-------+-----------------------+ 465 * 466 * For bits within that hole, it's more efficient to use LU12I and ADD. 467 */ 468 if (imm == (hi16 << 16) + lo12) { 469 if (hi16) { 470 tcg_out_opc_addu16i_d(s, rd, rs, hi16); 471 rs = rd; 472 } 473 if (type == TCG_TYPE_I32) { 474 tcg_out_opc_addi_w(s, rd, rs, lo12); 475 } else if (lo12) { 476 tcg_out_opc_addi_d(s, rd, rs, lo12); 477 } else { 478 tcg_out_mov(s, type, rd, rs); 479 } 480 } else { 481 tcg_out_movi(s, type, TCG_REG_TMP0, imm); 482 if (type == TCG_TYPE_I32) { 483 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); 484 } else { 485 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); 486 } 487 } 488} 489 490static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 491{ 492 return false; 493} 494 495static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 496 tcg_target_long imm) 497{ 498 /* This function is only used for passing structs by reference. */ 499 g_assert_not_reached(); 500} 501 502static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 503{ 504 tcg_out_opc_andi(s, ret, arg, 0xff); 505} 506 507static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 508{ 509 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 510} 511 512static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 513{ 514 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 515} 516 517static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 518{ 519 tcg_out_opc_sext_b(s, ret, arg); 520} 521 522static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 523{ 524 tcg_out_opc_sext_h(s, ret, arg); 525} 526 527static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 528{ 529 tcg_out_opc_addi_w(s, ret, arg, 0); 530} 531 532static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 533{ 534 if (ret != arg) { 535 tcg_out_ext32s(s, ret, arg); 536 } 537} 538 539static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 540{ 541 tcg_out_ext32u(s, ret, arg); 542} 543 544static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 545{ 546 tcg_out_ext32s(s, ret, arg); 547} 548 549#define SETCOND_INV TCG_TARGET_NB_REGS 550#define SETCOND_NEZ (SETCOND_INV << 1) 551#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 552 553static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 554 TCGReg arg1, tcg_target_long arg2, bool c2) 555{ 556 int flags = 0; 557 558 switch (cond) { 559 case TCG_COND_EQ: /* -> NE */ 560 case TCG_COND_GE: /* -> LT */ 561 case TCG_COND_GEU: /* -> LTU */ 562 case TCG_COND_GT: /* -> LE */ 563 case TCG_COND_GTU: /* -> LEU */ 564 cond = tcg_invert_cond(cond); 565 flags ^= SETCOND_INV; 566 break; 567 default: 568 break; 569 } 570 571 switch (cond) { 572 case TCG_COND_LE: 573 case TCG_COND_LEU: 574 /* 575 * If we have a constant input, the most efficient way to implement 576 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 577 * We don't need to care for this for LE because the constant input 578 * is still constrained to int32_t, and INT32_MAX+1 is representable 579 * in the 64-bit temporary register. 580 */ 581 if (c2) { 582 if (cond == TCG_COND_LEU) { 583 /* unsigned <= -1 is true */ 584 if (arg2 == -1) { 585 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 586 return ret; 587 } 588 cond = TCG_COND_LTU; 589 } else { 590 cond = TCG_COND_LT; 591 } 592 arg2 += 1; 593 } else { 594 TCGReg tmp = arg2; 595 arg2 = arg1; 596 arg1 = tmp; 597 cond = tcg_swap_cond(cond); /* LE -> GE */ 598 cond = tcg_invert_cond(cond); /* GE -> LT */ 599 flags ^= SETCOND_INV; 600 } 601 break; 602 default: 603 break; 604 } 605 606 switch (cond) { 607 case TCG_COND_NE: 608 flags |= SETCOND_NEZ; 609 if (!c2) { 610 tcg_out_opc_xor(s, ret, arg1, arg2); 611 } else if (arg2 == 0) { 612 ret = arg1; 613 } else if (arg2 >= 0 && arg2 <= 0xfff) { 614 tcg_out_opc_xori(s, ret, arg1, arg2); 615 } else { 616 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2); 617 } 618 break; 619 620 case TCG_COND_LT: 621 case TCG_COND_LTU: 622 if (c2) { 623 if (arg2 >= -0x800 && arg2 <= 0x7ff) { 624 if (cond == TCG_COND_LT) { 625 tcg_out_opc_slti(s, ret, arg1, arg2); 626 } else { 627 tcg_out_opc_sltui(s, ret, arg1, arg2); 628 } 629 break; 630 } 631 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 632 arg2 = TCG_REG_TMP0; 633 } 634 if (cond == TCG_COND_LT) { 635 tcg_out_opc_slt(s, ret, arg1, arg2); 636 } else { 637 tcg_out_opc_sltu(s, ret, arg1, arg2); 638 } 639 break; 640 641 default: 642 g_assert_not_reached(); 643 } 644 645 return ret | flags; 646} 647 648static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 649 TCGReg arg1, tcg_target_long arg2, 650 bool c2, bool neg) 651{ 652 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 653 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 654 655 if (neg) { 656 /* If intermediate result is zero/non-zero: test != 0. */ 657 if (tmpflags & SETCOND_NEZ) { 658 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 659 tmp = ret; 660 } 661 /* Produce the 0/-1 result. */ 662 if (tmpflags & SETCOND_INV) { 663 tcg_out_opc_addi_d(s, ret, tmp, -1); 664 } else { 665 tcg_out_opc_sub_d(s, ret, TCG_REG_ZERO, tmp); 666 } 667 } else { 668 switch (tmpflags & SETCOND_FLAGS) { 669 case 0: 670 tcg_debug_assert(tmp == ret); 671 break; 672 case SETCOND_INV: 673 /* Intermediate result is boolean: simply invert. */ 674 tcg_out_opc_xori(s, ret, tmp, 1); 675 break; 676 case SETCOND_NEZ: 677 /* Intermediate result is zero/non-zero: test != 0. */ 678 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 679 break; 680 case SETCOND_NEZ | SETCOND_INV: 681 /* Intermediate result is zero/non-zero: test == 0. */ 682 tcg_out_opc_sltui(s, ret, tmp, 1); 683 break; 684 default: 685 g_assert_not_reached(); 686 } 687 } 688} 689 690static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 691 TCGReg dest, TCGReg arg1, TCGReg arg2) 692{ 693 tcg_out_setcond(s, cond, dest, arg1, arg2, false, false); 694} 695 696static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 697 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 698{ 699 tcg_out_setcond(s, cond, dest, arg1, arg2, true, false); 700} 701 702static const TCGOutOpSetcond outop_setcond = { 703 .base.static_constraint = C_O1_I2(r, r, rJ), 704 .out_rrr = tgen_setcond, 705 .out_rri = tgen_setcondi, 706}; 707 708static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 709 TCGReg dest, TCGReg arg1, TCGReg arg2) 710{ 711 tcg_out_setcond(s, cond, dest, arg1, arg2, false, true); 712} 713 714static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 715 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 716{ 717 tcg_out_setcond(s, cond, dest, arg1, arg2, true, true); 718} 719 720static const TCGOutOpSetcond outop_negsetcond = { 721 .base.static_constraint = C_O1_I2(r, r, rJ), 722 .out_rrr = tgen_negsetcond, 723 .out_rri = tgen_negsetcondi, 724}; 725 726static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 727 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 728 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 729{ 730 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const_c2); 731 TCGReg t; 732 733 /* Standardize the test below to t != 0. */ 734 if (tmpflags & SETCOND_INV) { 735 t = v1, v1 = v2, v2 = t; 736 } 737 738 t = tmpflags & ~SETCOND_FLAGS; 739 if (v1 == TCG_REG_ZERO) { 740 tcg_out_opc_masknez(s, ret, v2, t); 741 } else if (v2 == TCG_REG_ZERO) { 742 tcg_out_opc_maskeqz(s, ret, v1, t); 743 } else { 744 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */ 745 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */ 746 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2); 747 } 748} 749 750static const TCGOutOpMovcond outop_movcond = { 751 .base.static_constraint = C_O1_I4(r, r, rJ, rz, rz), 752 .out = tgen_movcond, 753}; 754 755/* 756 * Branch helpers 757 */ 758 759static const struct { 760 LoongArchInsn op; 761 bool swap; 762} tcg_brcond_to_loongarch[] = { 763 [TCG_COND_EQ] = { OPC_BEQ, false }, 764 [TCG_COND_NE] = { OPC_BNE, false }, 765 [TCG_COND_LT] = { OPC_BGT, true }, 766 [TCG_COND_GE] = { OPC_BLE, true }, 767 [TCG_COND_LE] = { OPC_BLE, false }, 768 [TCG_COND_GT] = { OPC_BGT, false }, 769 [TCG_COND_LTU] = { OPC_BGTU, true }, 770 [TCG_COND_GEU] = { OPC_BLEU, true }, 771 [TCG_COND_LEU] = { OPC_BLEU, false }, 772 [TCG_COND_GTU] = { OPC_BGTU, false } 773}; 774 775static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 776 TCGReg arg1, TCGReg arg2, TCGLabel *l) 777{ 778 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 779 780 tcg_debug_assert(op != 0); 781 782 if (tcg_brcond_to_loongarch[cond].swap) { 783 TCGReg t = arg1; 784 arg1 = arg2; 785 arg2 = t; 786 } 787 788 /* all conditional branch insns belong to DJSk16-format */ 789 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 790 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 791} 792 793static const TCGOutOpBrcond outop_brcond = { 794 .base.static_constraint = C_O0_I2(r, rz), 795 .out_rr = tgen_brcond, 796}; 797 798static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 799{ 800 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 801 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 802 803 tcg_debug_assert((offset & 3) == 0); 804 if (offset == sextreg(offset, 0, 28)) { 805 /* short jump: +/- 256MiB */ 806 if (tail) { 807 tcg_out_opc_b(s, offset >> 2); 808 } else { 809 tcg_out_opc_bl(s, offset >> 2); 810 } 811 } else if (offset == sextreg(offset, 0, 38)) { 812 /* long jump: +/- 256GiB */ 813 tcg_target_long lo = sextreg(offset, 0, 18); 814 tcg_target_long hi = offset - lo; 815 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 816 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 817 } else { 818 /* far jump: 64-bit */ 819 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 820 tcg_target_long hi = (tcg_target_long)arg - lo; 821 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 822 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 823 } 824} 825 826static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 827 const TCGHelperInfo *info) 828{ 829 tcg_out_call_int(s, arg, false); 830} 831 832/* 833 * Load/store helpers 834 */ 835 836static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 837 TCGReg addr, intptr_t offset) 838{ 839 intptr_t imm12 = sextreg(offset, 0, 12); 840 841 if (offset != imm12) { 842 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 843 844 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 845 imm12 = sextreg(diff, 0, 12); 846 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 847 } else { 848 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 849 if (addr != TCG_REG_ZERO) { 850 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 851 } 852 } 853 addr = TCG_REG_TMP2; 854 } 855 856 switch (opc) { 857 case OPC_LD_B: 858 case OPC_LD_BU: 859 case OPC_LD_H: 860 case OPC_LD_HU: 861 case OPC_LD_W: 862 case OPC_LD_WU: 863 case OPC_LD_D: 864 case OPC_ST_B: 865 case OPC_ST_H: 866 case OPC_ST_W: 867 case OPC_ST_D: 868 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 869 break; 870 case OPC_FLD_S: 871 case OPC_FLD_D: 872 case OPC_FST_S: 873 case OPC_FST_D: 874 tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12)); 875 break; 876 default: 877 g_assert_not_reached(); 878 } 879} 880 881static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest, 882 TCGReg base, intptr_t offset) 883{ 884 switch (type) { 885 case TCG_TYPE_I32: 886 if (dest < TCG_REG_V0) { 887 tcg_out_ldst(s, OPC_LD_W, dest, base, offset); 888 } else { 889 tcg_out_ldst(s, OPC_FLD_S, dest, base, offset); 890 } 891 break; 892 case TCG_TYPE_I64: 893 case TCG_TYPE_V64: 894 if (dest < TCG_REG_V0) { 895 tcg_out_ldst(s, OPC_LD_D, dest, base, offset); 896 } else { 897 tcg_out_ldst(s, OPC_FLD_D, dest, base, offset); 898 } 899 break; 900 case TCG_TYPE_V128: 901 if (-0x800 <= offset && offset <= 0x7ff) { 902 tcg_out_opc_vld(s, dest, base, offset); 903 } else { 904 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 905 tcg_out_opc_vldx(s, dest, base, TCG_REG_TMP0); 906 } 907 break; 908 case TCG_TYPE_V256: 909 if (-0x800 <= offset && offset <= 0x7ff) { 910 tcg_out_opc_xvld(s, dest, base, offset); 911 } else { 912 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 913 tcg_out_opc_xvldx(s, dest, base, TCG_REG_TMP0); 914 } 915 break; 916 default: 917 g_assert_not_reached(); 918 } 919} 920 921static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, 922 TCGReg base, intptr_t offset) 923{ 924 switch (type) { 925 case TCG_TYPE_I32: 926 if (src < TCG_REG_V0) { 927 tcg_out_ldst(s, OPC_ST_W, src, base, offset); 928 } else { 929 tcg_out_ldst(s, OPC_FST_S, src, base, offset); 930 } 931 break; 932 case TCG_TYPE_I64: 933 case TCG_TYPE_V64: 934 if (src < TCG_REG_V0) { 935 tcg_out_ldst(s, OPC_ST_D, src, base, offset); 936 } else { 937 tcg_out_ldst(s, OPC_FST_D, src, base, offset); 938 } 939 break; 940 case TCG_TYPE_V128: 941 if (-0x800 <= offset && offset <= 0x7ff) { 942 tcg_out_opc_vst(s, src, base, offset); 943 } else { 944 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 945 tcg_out_opc_vstx(s, src, base, TCG_REG_TMP0); 946 } 947 break; 948 case TCG_TYPE_V256: 949 if (-0x800 <= offset && offset <= 0x7ff) { 950 tcg_out_opc_xvst(s, src, base, offset); 951 } else { 952 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 953 tcg_out_opc_xvstx(s, src, base, TCG_REG_TMP0); 954 } 955 break; 956 default: 957 g_assert_not_reached(); 958 } 959} 960 961static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 962 TCGReg base, intptr_t ofs) 963{ 964 if (val == 0) { 965 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 966 return true; 967 } 968 return false; 969} 970 971/* 972 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 973 */ 974 975static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 976{ 977 tcg_out_opc_b(s, 0); 978 return reloc_br_sd10k16(s->code_ptr - 1, target); 979} 980 981static const TCGLdstHelperParam ldst_helper_param = { 982 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 983}; 984 985static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 986{ 987 MemOp opc = get_memop(l->oi); 988 989 /* resolve label address */ 990 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 991 return false; 992 } 993 994 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 995 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); 996 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 997 return tcg_out_goto(s, l->raddr); 998} 999 1000static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1001{ 1002 MemOp opc = get_memop(l->oi); 1003 1004 /* resolve label address */ 1005 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1006 return false; 1007 } 1008 1009 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1010 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1011 return tcg_out_goto(s, l->raddr); 1012} 1013 1014typedef struct { 1015 TCGReg base; 1016 TCGReg index; 1017 TCGAtomAlign aa; 1018} HostAddress; 1019 1020bool tcg_target_has_memory_bswap(MemOp memop) 1021{ 1022 return false; 1023} 1024 1025/* We expect to use a 12-bit negative offset from ENV. */ 1026#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 1027 1028/* 1029 * For system-mode, perform the TLB load and compare. 1030 * For user-mode, perform any required alignment tests. 1031 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1032 * is required and fill in @h with the host address for the fast path. 1033 */ 1034static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1035 TCGReg addr_reg, MemOpIdx oi, 1036 bool is_ld) 1037{ 1038 TCGType addr_type = s->addr_type; 1039 TCGLabelQemuLdst *ldst = NULL; 1040 MemOp opc = get_memop(oi); 1041 MemOp a_bits; 1042 1043 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1044 a_bits = h->aa.align; 1045 1046 if (tcg_use_softmmu) { 1047 unsigned s_bits = opc & MO_SIZE; 1048 int mem_index = get_mmuidx(oi); 1049 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 1050 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 1051 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 1052 1053 ldst = new_ldst_label(s); 1054 ldst->is_ld = is_ld; 1055 ldst->oi = oi; 1056 ldst->addr_reg = addr_reg; 1057 1058 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 1059 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 1060 1061 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, 1062 s->page_bits - CPU_TLB_ENTRY_BITS); 1063 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 1064 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 1065 1066 /* Load the tlb comparator and the addend. */ 1067 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 1068 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 1069 is_ld ? offsetof(CPUTLBEntry, addr_read) 1070 : offsetof(CPUTLBEntry, addr_write)); 1071 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 1072 offsetof(CPUTLBEntry, addend)); 1073 1074 /* 1075 * For aligned accesses, we check the first byte and include the 1076 * alignment bits within the address. For unaligned access, we 1077 * check that we don't cross pages using the address of the last 1078 * byte of the access. 1079 */ 1080 if (a_bits < s_bits) { 1081 unsigned a_mask = (1u << a_bits) - 1; 1082 unsigned s_mask = (1u << s_bits) - 1; 1083 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask); 1084 } else { 1085 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); 1086 } 1087 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, 1088 a_bits, s->page_bits - 1); 1089 1090 /* Compare masked address with the TLB entry. */ 1091 ldst->label_ptr[0] = s->code_ptr; 1092 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1093 1094 h->index = TCG_REG_TMP2; 1095 } else { 1096 if (a_bits) { 1097 ldst = new_ldst_label(s); 1098 1099 ldst->is_ld = is_ld; 1100 ldst->oi = oi; 1101 ldst->addr_reg = addr_reg; 1102 1103 /* 1104 * Without micro-architecture details, we don't know which of 1105 * bstrpick or andi is faster, so use bstrpick as it's not 1106 * constrained by imm field width. Not to say alignments >= 2^12 1107 * are going to happen any time soon. 1108 */ 1109 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 1110 1111 ldst->label_ptr[0] = s->code_ptr; 1112 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1113 } 1114 1115 h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1116 } 1117 1118 if (addr_type == TCG_TYPE_I32) { 1119 h->base = TCG_REG_TMP0; 1120 tcg_out_ext32u(s, h->base, addr_reg); 1121 } else { 1122 h->base = addr_reg; 1123 } 1124 1125 return ldst; 1126} 1127 1128static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, 1129 TCGReg rd, HostAddress h) 1130{ 1131 /* Byte swapping is left to middle-end expansion. */ 1132 tcg_debug_assert((opc & MO_BSWAP) == 0); 1133 1134 switch (opc & MO_SSIZE) { 1135 case MO_UB: 1136 tcg_out_opc_ldx_bu(s, rd, h.base, h.index); 1137 break; 1138 case MO_SB: 1139 tcg_out_opc_ldx_b(s, rd, h.base, h.index); 1140 break; 1141 case MO_UW: 1142 tcg_out_opc_ldx_hu(s, rd, h.base, h.index); 1143 break; 1144 case MO_SW: 1145 tcg_out_opc_ldx_h(s, rd, h.base, h.index); 1146 break; 1147 case MO_UL: 1148 if (type == TCG_TYPE_I64) { 1149 tcg_out_opc_ldx_wu(s, rd, h.base, h.index); 1150 break; 1151 } 1152 /* fallthrough */ 1153 case MO_SL: 1154 tcg_out_opc_ldx_w(s, rd, h.base, h.index); 1155 break; 1156 case MO_UQ: 1157 tcg_out_opc_ldx_d(s, rd, h.base, h.index); 1158 break; 1159 default: 1160 g_assert_not_reached(); 1161 } 1162} 1163 1164static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1165 MemOpIdx oi, TCGType data_type) 1166{ 1167 TCGLabelQemuLdst *ldst; 1168 HostAddress h; 1169 1170 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1171 tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); 1172 1173 if (ldst) { 1174 ldst->type = data_type; 1175 ldst->datalo_reg = data_reg; 1176 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1177 } 1178} 1179 1180static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, 1181 TCGReg rd, HostAddress h) 1182{ 1183 /* Byte swapping is left to middle-end expansion. */ 1184 tcg_debug_assert((opc & MO_BSWAP) == 0); 1185 1186 switch (opc & MO_SIZE) { 1187 case MO_8: 1188 tcg_out_opc_stx_b(s, rd, h.base, h.index); 1189 break; 1190 case MO_16: 1191 tcg_out_opc_stx_h(s, rd, h.base, h.index); 1192 break; 1193 case MO_32: 1194 tcg_out_opc_stx_w(s, rd, h.base, h.index); 1195 break; 1196 case MO_64: 1197 tcg_out_opc_stx_d(s, rd, h.base, h.index); 1198 break; 1199 default: 1200 g_assert_not_reached(); 1201 } 1202} 1203 1204static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1205 MemOpIdx oi, TCGType data_type) 1206{ 1207 TCGLabelQemuLdst *ldst; 1208 HostAddress h; 1209 1210 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1211 tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); 1212 1213 if (ldst) { 1214 ldst->type = data_type; 1215 ldst->datalo_reg = data_reg; 1216 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1217 } 1218} 1219 1220static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi, 1221 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1222{ 1223 TCGLabelQemuLdst *ldst; 1224 HostAddress h; 1225 1226 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1227 1228 if (h.aa.atom == MO_128) { 1229 /* 1230 * Use VLDX/VSTX when 128-bit atomicity is required. 1231 * If address is aligned to 16-bytes, the 128-bit load/store is atomic. 1232 */ 1233 if (is_ld) { 1234 tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index); 1235 tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0); 1236 tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1); 1237 } else { 1238 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0); 1239 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1); 1240 tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index); 1241 } 1242 } else { 1243 /* Otherwise use a pair of LD/ST. */ 1244 TCGReg base = h.base; 1245 if (h.index != TCG_REG_ZERO) { 1246 base = TCG_REG_TMP0; 1247 tcg_out_opc_add_d(s, base, h.base, h.index); 1248 } 1249 if (is_ld) { 1250 tcg_debug_assert(base != data_lo); 1251 tcg_out_opc_ld_d(s, data_lo, base, 0); 1252 tcg_out_opc_ld_d(s, data_hi, base, 8); 1253 } else { 1254 tcg_out_opc_st_d(s, data_lo, base, 0); 1255 tcg_out_opc_st_d(s, data_hi, base, 8); 1256 } 1257 } 1258 1259 if (ldst) { 1260 ldst->type = TCG_TYPE_I128; 1261 ldst->datalo_reg = data_lo; 1262 ldst->datahi_reg = data_hi; 1263 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1264 } 1265} 1266 1267/* 1268 * Entry-points 1269 */ 1270 1271static const tcg_insn_unit *tb_ret_addr; 1272 1273static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1274{ 1275 /* Reuse the zeroing that exists for goto_ptr. */ 1276 if (a0 == 0) { 1277 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1278 } else { 1279 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1280 tcg_out_call_int(s, tb_ret_addr, true); 1281 } 1282} 1283 1284static void tcg_out_goto_tb(TCGContext *s, int which) 1285{ 1286 /* 1287 * Direct branch, or load indirect address, to be patched 1288 * by tb_target_set_jmp_target. Check indirect load offset 1289 * in range early, regardless of direct branch distance, 1290 * via assert within tcg_out_opc_pcaddu2i. 1291 */ 1292 uintptr_t i_addr = get_jmp_target_addr(s, which); 1293 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr); 1294 1295 set_jmp_insn_offset(s, which); 1296 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2); 1297 1298 /* Finish the load and indirect branch. */ 1299 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); 1300 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1301 set_jmp_reset_offset(s, which); 1302} 1303 1304void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1305 uintptr_t jmp_rx, uintptr_t jmp_rw) 1306{ 1307 uintptr_t d_addr = tb->jmp_target_addr[n]; 1308 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2; 1309 tcg_insn_unit insn; 1310 1311 /* Either directly branch, or load slot address for indirect branch. */ 1312 if (d_disp == sextreg(d_disp, 0, 26)) { 1313 insn = encode_sd10k16_insn(OPC_B, d_disp); 1314 } else { 1315 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 1316 intptr_t i_disp = i_addr - jmp_rx; 1317 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2); 1318 } 1319 1320 qatomic_set((tcg_insn_unit *)jmp_rw, insn); 1321 flush_idcache_range(jmp_rx, jmp_rw, 4); 1322} 1323 1324 1325static void tgen_add(TCGContext *s, TCGType type, 1326 TCGReg a0, TCGReg a1, TCGReg a2) 1327{ 1328 if (type == TCG_TYPE_I32) { 1329 tcg_out_opc_add_w(s, a0, a1, a2); 1330 } else { 1331 tcg_out_opc_add_d(s, a0, a1, a2); 1332 } 1333} 1334 1335static const TCGOutOpBinary outop_add = { 1336 .base.static_constraint = C_O1_I2(r, r, rJ), 1337 .out_rrr = tgen_add, 1338 .out_rri = tcg_out_addi, 1339}; 1340 1341static void tgen_and(TCGContext *s, TCGType type, 1342 TCGReg a0, TCGReg a1, TCGReg a2) 1343{ 1344 tcg_out_opc_and(s, a0, a1, a2); 1345} 1346 1347static void tgen_andi(TCGContext *s, TCGType type, 1348 TCGReg a0, TCGReg a1, tcg_target_long a2) 1349{ 1350 tcg_out_opc_andi(s, a0, a1, a2); 1351} 1352 1353static const TCGOutOpBinary outop_and = { 1354 .base.static_constraint = C_O1_I2(r, r, rU), 1355 .out_rrr = tgen_and, 1356 .out_rri = tgen_andi, 1357}; 1358 1359static void tgen_andc(TCGContext *s, TCGType type, 1360 TCGReg a0, TCGReg a1, TCGReg a2) 1361{ 1362 tcg_out_opc_andn(s, a0, a1, a2); 1363} 1364 1365static const TCGOutOpBinary outop_andc = { 1366 .base.static_constraint = C_O1_I2(r, r, r), 1367 .out_rrr = tgen_andc, 1368}; 1369 1370static void tgen_clzi(TCGContext *s, TCGType type, 1371 TCGReg a0, TCGReg a1, tcg_target_long a2) 1372{ 1373 /* a2 is constrained to exactly the type width. */ 1374 if (type == TCG_TYPE_I32) { 1375 tcg_out_opc_clz_w(s, a0, a1); 1376 } else { 1377 tcg_out_opc_clz_d(s, a0, a1); 1378 } 1379} 1380 1381static void tgen_clz(TCGContext *s, TCGType type, 1382 TCGReg a0, TCGReg a1, TCGReg a2) 1383{ 1384 tgen_clzi(s, type, TCG_REG_TMP0, a1, /* ignored */ 0); 1385 /* a0 = a1 ? REG_TMP0 : a2 */ 1386 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 1387 tcg_out_opc_masknez(s, a0, a2, a1); 1388 tcg_out_opc_or(s, a0, a0, TCG_REG_TMP0); 1389} 1390 1391static const TCGOutOpBinary outop_clz = { 1392 .base.static_constraint = C_O1_I2(r, r, rW), 1393 .out_rrr = tgen_clz, 1394 .out_rri = tgen_clzi, 1395}; 1396 1397static const TCGOutOpUnary outop_ctpop = { 1398 .base.static_constraint = C_NotImplemented, 1399}; 1400 1401static void tgen_ctzi(TCGContext *s, TCGType type, 1402 TCGReg a0, TCGReg a1, tcg_target_long a2) 1403{ 1404 /* a2 is constrained to exactly the type width. */ 1405 if (type == TCG_TYPE_I32) { 1406 tcg_out_opc_ctz_w(s, a0, a1); 1407 } else { 1408 tcg_out_opc_ctz_d(s, a0, a1); 1409 } 1410} 1411 1412static void tgen_ctz(TCGContext *s, TCGType type, 1413 TCGReg a0, TCGReg a1, TCGReg a2) 1414{ 1415 tgen_ctzi(s, type, TCG_REG_TMP0, a1, /* ignored */ 0); 1416 /* a0 = a1 ? REG_TMP0 : a2 */ 1417 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 1418 tcg_out_opc_masknez(s, a0, a2, a1); 1419 tcg_out_opc_or(s, a0, a0, TCG_REG_TMP0); 1420} 1421 1422static const TCGOutOpBinary outop_ctz = { 1423 .base.static_constraint = C_O1_I2(r, r, rW), 1424 .out_rrr = tgen_ctz, 1425 .out_rri = tgen_ctzi, 1426}; 1427 1428static void tgen_divs(TCGContext *s, TCGType type, 1429 TCGReg a0, TCGReg a1, TCGReg a2) 1430{ 1431 if (type == TCG_TYPE_I32) { 1432 tcg_out_opc_div_w(s, a0, a1, a2); 1433 } else { 1434 tcg_out_opc_div_d(s, a0, a1, a2); 1435 } 1436} 1437 1438static const TCGOutOpBinary outop_divs = { 1439 .base.static_constraint = C_O1_I2(r, r, r), 1440 .out_rrr = tgen_divs, 1441}; 1442 1443static const TCGOutOpDivRem outop_divs2 = { 1444 .base.static_constraint = C_NotImplemented, 1445}; 1446 1447static void tgen_divu(TCGContext *s, TCGType type, 1448 TCGReg a0, TCGReg a1, TCGReg a2) 1449{ 1450 if (type == TCG_TYPE_I32) { 1451 tcg_out_opc_div_wu(s, a0, a1, a2); 1452 } else { 1453 tcg_out_opc_div_du(s, a0, a1, a2); 1454 } 1455} 1456 1457static const TCGOutOpBinary outop_divu = { 1458 .base.static_constraint = C_O1_I2(r, r, r), 1459 .out_rrr = tgen_divu, 1460}; 1461 1462static const TCGOutOpDivRem outop_divu2 = { 1463 .base.static_constraint = C_NotImplemented, 1464}; 1465 1466static const TCGOutOpBinary outop_eqv = { 1467 .base.static_constraint = C_NotImplemented, 1468}; 1469 1470static void tgen_mul(TCGContext *s, TCGType type, 1471 TCGReg a0, TCGReg a1, TCGReg a2) 1472{ 1473 if (type == TCG_TYPE_I32) { 1474 tcg_out_opc_mul_w(s, a0, a1, a2); 1475 } else { 1476 tcg_out_opc_mul_d(s, a0, a1, a2); 1477 } 1478} 1479 1480static const TCGOutOpBinary outop_mul = { 1481 .base.static_constraint = C_O1_I2(r, r, r), 1482 .out_rrr = tgen_mul, 1483}; 1484 1485static const TCGOutOpMul2 outop_muls2 = { 1486 .base.static_constraint = C_NotImplemented, 1487}; 1488 1489static void tgen_mulsh(TCGContext *s, TCGType type, 1490 TCGReg a0, TCGReg a1, TCGReg a2) 1491{ 1492 if (type == TCG_TYPE_I32) { 1493 tcg_out_opc_mulh_w(s, a0, a1, a2); 1494 } else { 1495 tcg_out_opc_mulh_d(s, a0, a1, a2); 1496 } 1497} 1498 1499static const TCGOutOpBinary outop_mulsh = { 1500 .base.static_constraint = C_O1_I2(r, r, r), 1501 .out_rrr = tgen_mulsh, 1502}; 1503 1504static const TCGOutOpMul2 outop_mulu2 = { 1505 .base.static_constraint = C_NotImplemented, 1506}; 1507 1508static void tgen_muluh(TCGContext *s, TCGType type, 1509 TCGReg a0, TCGReg a1, TCGReg a2) 1510{ 1511 if (type == TCG_TYPE_I32) { 1512 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1513 } else { 1514 tcg_out_opc_mulh_du(s, a0, a1, a2); 1515 } 1516} 1517 1518static const TCGOutOpBinary outop_muluh = { 1519 .base.static_constraint = C_O1_I2(r, r, r), 1520 .out_rrr = tgen_muluh, 1521}; 1522 1523static const TCGOutOpBinary outop_nand = { 1524 .base.static_constraint = C_NotImplemented, 1525}; 1526 1527static void tgen_nor(TCGContext *s, TCGType type, 1528 TCGReg a0, TCGReg a1, TCGReg a2) 1529{ 1530 tcg_out_opc_nor(s, a0, a1, a2); 1531} 1532 1533static const TCGOutOpBinary outop_nor = { 1534 .base.static_constraint = C_O1_I2(r, r, r), 1535 .out_rrr = tgen_nor, 1536}; 1537 1538static void tgen_or(TCGContext *s, TCGType type, 1539 TCGReg a0, TCGReg a1, TCGReg a2) 1540{ 1541 tcg_out_opc_or(s, a0, a1, a2); 1542} 1543 1544static void tgen_ori(TCGContext *s, TCGType type, 1545 TCGReg a0, TCGReg a1, tcg_target_long a2) 1546{ 1547 tcg_out_opc_ori(s, a0, a1, a2); 1548} 1549 1550static const TCGOutOpBinary outop_or = { 1551 .base.static_constraint = C_O1_I2(r, r, rU), 1552 .out_rrr = tgen_or, 1553 .out_rri = tgen_ori, 1554}; 1555 1556static void tgen_orc(TCGContext *s, TCGType type, 1557 TCGReg a0, TCGReg a1, TCGReg a2) 1558{ 1559 tcg_out_opc_orn(s, a0, a1, a2); 1560} 1561 1562static const TCGOutOpBinary outop_orc = { 1563 .base.static_constraint = C_O1_I2(r, r, r), 1564 .out_rrr = tgen_orc, 1565}; 1566 1567static void tgen_rems(TCGContext *s, TCGType type, 1568 TCGReg a0, TCGReg a1, TCGReg a2) 1569{ 1570 if (type == TCG_TYPE_I32) { 1571 tcg_out_opc_mod_w(s, a0, a1, a2); 1572 } else { 1573 tcg_out_opc_mod_d(s, a0, a1, a2); 1574 } 1575} 1576 1577static const TCGOutOpBinary outop_rems = { 1578 .base.static_constraint = C_O1_I2(r, r, r), 1579 .out_rrr = tgen_rems, 1580}; 1581 1582static void tgen_remu(TCGContext *s, TCGType type, 1583 TCGReg a0, TCGReg a1, TCGReg a2) 1584{ 1585 if (type == TCG_TYPE_I32) { 1586 tcg_out_opc_mod_wu(s, a0, a1, a2); 1587 } else { 1588 tcg_out_opc_mod_du(s, a0, a1, a2); 1589 } 1590} 1591 1592static const TCGOutOpBinary outop_remu = { 1593 .base.static_constraint = C_O1_I2(r, r, r), 1594 .out_rrr = tgen_remu, 1595}; 1596 1597static const TCGOutOpBinary outop_rotl = { 1598 .base.static_constraint = C_NotImplemented, 1599}; 1600 1601static void tgen_rotr(TCGContext *s, TCGType type, 1602 TCGReg a0, TCGReg a1, TCGReg a2) 1603{ 1604 if (type == TCG_TYPE_I32) { 1605 tcg_out_opc_rotr_w(s, a0, a1, a2); 1606 } else { 1607 tcg_out_opc_rotr_d(s, a0, a1, a2); 1608 } 1609} 1610 1611static void tgen_rotri(TCGContext *s, TCGType type, 1612 TCGReg a0, TCGReg a1, tcg_target_long a2) 1613{ 1614 if (type == TCG_TYPE_I32) { 1615 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1616 } else { 1617 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1618 } 1619} 1620 1621static const TCGOutOpBinary outop_rotr = { 1622 .base.static_constraint = C_O1_I2(r, r, ri), 1623 .out_rrr = tgen_rotr, 1624 .out_rri = tgen_rotri, 1625}; 1626 1627static void tgen_sar(TCGContext *s, TCGType type, 1628 TCGReg a0, TCGReg a1, TCGReg a2) 1629{ 1630 if (type == TCG_TYPE_I32) { 1631 tcg_out_opc_sra_w(s, a0, a1, a2); 1632 } else { 1633 tcg_out_opc_sra_d(s, a0, a1, a2); 1634 } 1635} 1636 1637static void tgen_sari(TCGContext *s, TCGType type, 1638 TCGReg a0, TCGReg a1, tcg_target_long a2) 1639{ 1640 if (type == TCG_TYPE_I32) { 1641 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1642 } else { 1643 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1644 } 1645} 1646 1647static const TCGOutOpBinary outop_sar = { 1648 .base.static_constraint = C_O1_I2(r, r, ri), 1649 .out_rrr = tgen_sar, 1650 .out_rri = tgen_sari, 1651}; 1652 1653static void tgen_shl(TCGContext *s, TCGType type, 1654 TCGReg a0, TCGReg a1, TCGReg a2) 1655{ 1656 if (type == TCG_TYPE_I32) { 1657 tcg_out_opc_sll_w(s, a0, a1, a2); 1658 } else { 1659 tcg_out_opc_sll_d(s, a0, a1, a2); 1660 } 1661} 1662 1663static void tgen_shli(TCGContext *s, TCGType type, 1664 TCGReg a0, TCGReg a1, tcg_target_long a2) 1665{ 1666 if (type == TCG_TYPE_I32) { 1667 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1668 } else { 1669 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1670 } 1671} 1672 1673static const TCGOutOpBinary outop_shl = { 1674 .base.static_constraint = C_O1_I2(r, r, ri), 1675 .out_rrr = tgen_shl, 1676 .out_rri = tgen_shli, 1677}; 1678 1679static void tgen_shr(TCGContext *s, TCGType type, 1680 TCGReg a0, TCGReg a1, TCGReg a2) 1681{ 1682 if (type == TCG_TYPE_I32) { 1683 tcg_out_opc_srl_w(s, a0, a1, a2); 1684 } else { 1685 tcg_out_opc_srl_d(s, a0, a1, a2); 1686 } 1687} 1688 1689static void tgen_shri(TCGContext *s, TCGType type, 1690 TCGReg a0, TCGReg a1, tcg_target_long a2) 1691{ 1692 if (type == TCG_TYPE_I32) { 1693 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1694 } else { 1695 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1696 } 1697} 1698 1699static const TCGOutOpBinary outop_shr = { 1700 .base.static_constraint = C_O1_I2(r, r, ri), 1701 .out_rrr = tgen_shr, 1702 .out_rri = tgen_shri, 1703}; 1704 1705static void tgen_sub(TCGContext *s, TCGType type, 1706 TCGReg a0, TCGReg a1, TCGReg a2) 1707{ 1708 if (type == TCG_TYPE_I32) { 1709 tcg_out_opc_sub_w(s, a0, a1, a2); 1710 } else { 1711 tcg_out_opc_sub_d(s, a0, a1, a2); 1712 } 1713} 1714 1715static const TCGOutOpSubtract outop_sub = { 1716 .base.static_constraint = C_O1_I2(r, r, r), 1717 .out_rrr = tgen_sub, 1718}; 1719 1720static void tgen_xor(TCGContext *s, TCGType type, 1721 TCGReg a0, TCGReg a1, TCGReg a2) 1722{ 1723 tcg_out_opc_xor(s, a0, a1, a2); 1724} 1725 1726static void tgen_xori(TCGContext *s, TCGType type, 1727 TCGReg a0, TCGReg a1, tcg_target_long a2) 1728{ 1729 tcg_out_opc_xori(s, a0, a1, a2); 1730} 1731 1732static const TCGOutOpBinary outop_xor = { 1733 .base.static_constraint = C_O1_I2(r, r, rU), 1734 .out_rrr = tgen_xor, 1735 .out_rri = tgen_xori, 1736}; 1737 1738static void tgen_bswap16(TCGContext *s, TCGType type, 1739 TCGReg a0, TCGReg a1, unsigned flags) 1740{ 1741 tcg_out_opc_revb_2h(s, a0, a1); 1742 if (flags & TCG_BSWAP_OS) { 1743 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); 1744 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1745 tcg_out_ext16u(s, a0, a0); 1746 } 1747} 1748 1749static const TCGOutOpBswap outop_bswap16 = { 1750 .base.static_constraint = C_O1_I1(r, r), 1751 .out_rr = tgen_bswap16, 1752}; 1753 1754static void tgen_bswap32(TCGContext *s, TCGType type, 1755 TCGReg a0, TCGReg a1, unsigned flags) 1756{ 1757 tcg_out_opc_revb_2w(s, a0, a1); 1758 1759 /* All 32-bit values are computed sign-extended in the register. */ 1760 if (type == TCG_TYPE_I32 || (flags & TCG_BSWAP_OS)) { 1761 tcg_out_ext32s(s, a0, a0); 1762 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1763 tcg_out_ext32u(s, a0, a0); 1764 } 1765} 1766 1767static const TCGOutOpBswap outop_bswap32 = { 1768 .base.static_constraint = C_O1_I1(r, r), 1769 .out_rr = tgen_bswap32, 1770}; 1771 1772static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1773{ 1774 tcg_out_opc_revb_d(s, a0, a1); 1775} 1776 1777static const TCGOutOpUnary outop_bswap64 = { 1778 .base.static_constraint = C_O1_I1(r, r), 1779 .out_rr = tgen_bswap64, 1780}; 1781 1782static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1783{ 1784 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 1785} 1786 1787static const TCGOutOpUnary outop_neg = { 1788 .base.static_constraint = C_O1_I1(r, r), 1789 .out_rr = tgen_neg, 1790}; 1791 1792static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1793{ 1794 tgen_nor(s, type, a0, a1, TCG_REG_ZERO); 1795} 1796 1797static const TCGOutOpUnary outop_not = { 1798 .base.static_constraint = C_O1_I1(r, r), 1799 .out_rr = tgen_not, 1800}; 1801 1802static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1803 unsigned ofs, unsigned len) 1804{ 1805 if (ofs == 0 && len <= 12) { 1806 tcg_out_opc_andi(s, a0, a1, (1 << len) - 1); 1807 } else if (type == TCG_TYPE_I32) { 1808 tcg_out_opc_bstrpick_w(s, a0, a1, ofs, ofs + len - 1); 1809 } else { 1810 tcg_out_opc_bstrpick_d(s, a0, a1, ofs, ofs + len - 1); 1811 } 1812} 1813 1814static const TCGOutOpExtract outop_extract = { 1815 .base.static_constraint = C_O1_I1(r, r), 1816 .out_rr = tgen_extract, 1817}; 1818 1819static void tgen_sextract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1820 unsigned ofs, unsigned len) 1821{ 1822 if (ofs == 0) { 1823 switch (len) { 1824 case 8: 1825 tcg_out_ext8s(s, type, a0, a1); 1826 return; 1827 case 16: 1828 tcg_out_ext16s(s, type, a0, a1); 1829 return; 1830 case 32: 1831 tcg_out_ext32s(s, a0, a1); 1832 return; 1833 } 1834 } else if (ofs + len == 32) { 1835 tcg_out_opc_srai_w(s, a0, a1, ofs); 1836 return; 1837 } 1838 g_assert_not_reached(); 1839} 1840 1841static const TCGOutOpExtract outop_sextract = { 1842 .base.static_constraint = C_O1_I1(r, r), 1843 .out_rr = tgen_sextract, 1844}; 1845 1846static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1847 const TCGArg args[TCG_MAX_OP_ARGS], 1848 const int const_args[TCG_MAX_OP_ARGS]) 1849{ 1850 TCGArg a0 = args[0]; 1851 TCGArg a1 = args[1]; 1852 TCGArg a2 = args[2]; 1853 TCGArg a3 = args[3]; 1854 1855 switch (opc) { 1856 case INDEX_op_mb: 1857 tcg_out_mb(s, a0); 1858 break; 1859 1860 case INDEX_op_goto_ptr: 1861 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1862 break; 1863 1864 case INDEX_op_br: 1865 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), 1866 0); 1867 tcg_out_opc_b(s, 0); 1868 break; 1869 1870 case INDEX_op_extrh_i64_i32: 1871 tcg_out_opc_srai_d(s, a0, a1, 32); 1872 break; 1873 1874 case INDEX_op_deposit_i32: 1875 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); 1876 break; 1877 case INDEX_op_deposit_i64: 1878 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); 1879 break; 1880 1881 case INDEX_op_ld8s_i32: 1882 case INDEX_op_ld8s_i64: 1883 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); 1884 break; 1885 case INDEX_op_ld8u_i32: 1886 case INDEX_op_ld8u_i64: 1887 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); 1888 break; 1889 case INDEX_op_ld16s_i32: 1890 case INDEX_op_ld16s_i64: 1891 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); 1892 break; 1893 case INDEX_op_ld16u_i32: 1894 case INDEX_op_ld16u_i64: 1895 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); 1896 break; 1897 case INDEX_op_ld_i32: 1898 case INDEX_op_ld32s_i64: 1899 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); 1900 break; 1901 case INDEX_op_ld32u_i64: 1902 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); 1903 break; 1904 case INDEX_op_ld_i64: 1905 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); 1906 break; 1907 1908 case INDEX_op_st8_i32: 1909 case INDEX_op_st8_i64: 1910 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); 1911 break; 1912 case INDEX_op_st16_i32: 1913 case INDEX_op_st16_i64: 1914 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); 1915 break; 1916 case INDEX_op_st_i32: 1917 case INDEX_op_st32_i64: 1918 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); 1919 break; 1920 case INDEX_op_st_i64: 1921 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); 1922 break; 1923 1924 case INDEX_op_qemu_ld_i32: 1925 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1926 break; 1927 case INDEX_op_qemu_ld_i64: 1928 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1929 break; 1930 case INDEX_op_qemu_ld_i128: 1931 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true); 1932 break; 1933 case INDEX_op_qemu_st_i32: 1934 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1935 break; 1936 case INDEX_op_qemu_st_i64: 1937 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1938 break; 1939 case INDEX_op_qemu_st_i128: 1940 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false); 1941 break; 1942 1943 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1944 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1945 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1946 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 1947 case INDEX_op_extu_i32_i64: 1948 case INDEX_op_extrl_i64_i32: 1949 default: 1950 g_assert_not_reached(); 1951 } 1952} 1953 1954static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1955 TCGReg rd, TCGReg rs) 1956{ 1957 static const LoongArchInsn repl_insn[2][4] = { 1958 { OPC_VREPLGR2VR_B, OPC_VREPLGR2VR_H, 1959 OPC_VREPLGR2VR_W, OPC_VREPLGR2VR_D }, 1960 { OPC_XVREPLGR2VR_B, OPC_XVREPLGR2VR_H, 1961 OPC_XVREPLGR2VR_W, OPC_XVREPLGR2VR_D }, 1962 }; 1963 bool lasx = type == TCG_TYPE_V256; 1964 1965 tcg_debug_assert(vece <= MO_64); 1966 tcg_out32(s, encode_vdj_insn(repl_insn[lasx][vece], rd, rs)); 1967 return true; 1968} 1969 1970static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1971 TCGReg r, TCGReg base, intptr_t offset) 1972{ 1973 bool lasx = type == TCG_TYPE_V256; 1974 1975 /* Handle imm overflow and division (vldrepl.d imm is divided by 8). */ 1976 if (offset < -0x800 || offset > 0x7ff || 1977 (offset & ((1 << vece) - 1)) != 0) { 1978 tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset); 1979 base = TCG_REG_TMP0; 1980 offset = 0; 1981 } 1982 offset >>= vece; 1983 1984 switch (vece) { 1985 case MO_8: 1986 if (lasx) { 1987 tcg_out_opc_xvldrepl_b(s, r, base, offset); 1988 } else { 1989 tcg_out_opc_vldrepl_b(s, r, base, offset); 1990 } 1991 break; 1992 case MO_16: 1993 if (lasx) { 1994 tcg_out_opc_xvldrepl_h(s, r, base, offset); 1995 } else { 1996 tcg_out_opc_vldrepl_h(s, r, base, offset); 1997 } 1998 break; 1999 case MO_32: 2000 if (lasx) { 2001 tcg_out_opc_xvldrepl_w(s, r, base, offset); 2002 } else { 2003 tcg_out_opc_vldrepl_w(s, r, base, offset); 2004 } 2005 break; 2006 case MO_64: 2007 if (lasx) { 2008 tcg_out_opc_xvldrepl_d(s, r, base, offset); 2009 } else { 2010 tcg_out_opc_vldrepl_d(s, r, base, offset); 2011 } 2012 break; 2013 default: 2014 g_assert_not_reached(); 2015 } 2016 return true; 2017} 2018 2019static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2020 TCGReg rd, int64_t v64) 2021{ 2022 /* Try vldi if imm can fit */ 2023 int64_t value = sextract64(v64, 0, 8 << vece); 2024 if (-0x200 <= value && value <= 0x1FF) { 2025 uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF); 2026 2027 if (type == TCG_TYPE_V256) { 2028 tcg_out_opc_xvldi(s, rd, imm); 2029 } else { 2030 tcg_out_opc_vldi(s, rd, imm); 2031 } 2032 return; 2033 } 2034 2035 /* TODO: vldi patterns when imm 12 is set */ 2036 2037 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value); 2038 tcg_out_dup_vec(s, type, vece, rd, TCG_REG_TMP0); 2039} 2040 2041static void tcg_out_addsub_vec(TCGContext *s, bool lasx, unsigned vece, 2042 TCGArg a0, TCGArg a1, TCGArg a2, 2043 bool a2_is_const, bool is_add) 2044{ 2045 static const LoongArchInsn add_vec_insn[2][4] = { 2046 { OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D }, 2047 { OPC_XVADD_B, OPC_XVADD_H, OPC_XVADD_W, OPC_XVADD_D }, 2048 }; 2049 static const LoongArchInsn add_vec_imm_insn[2][4] = { 2050 { OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU }, 2051 { OPC_XVADDI_BU, OPC_XVADDI_HU, OPC_XVADDI_WU, OPC_XVADDI_DU }, 2052 }; 2053 static const LoongArchInsn sub_vec_insn[2][4] = { 2054 { OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D }, 2055 { OPC_XVSUB_B, OPC_XVSUB_H, OPC_XVSUB_W, OPC_XVSUB_D }, 2056 }; 2057 static const LoongArchInsn sub_vec_imm_insn[2][4] = { 2058 { OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU }, 2059 { OPC_XVSUBI_BU, OPC_XVSUBI_HU, OPC_XVSUBI_WU, OPC_XVSUBI_DU }, 2060 }; 2061 LoongArchInsn insn; 2062 2063 if (a2_is_const) { 2064 int64_t value = sextract64(a2, 0, 8 << vece); 2065 2066 if (!is_add) { 2067 value = -value; 2068 } 2069 if (value < 0) { 2070 insn = sub_vec_imm_insn[lasx][vece]; 2071 value = -value; 2072 } else { 2073 insn = add_vec_imm_insn[lasx][vece]; 2074 } 2075 2076 /* Constraint TCG_CT_CONST_VADD ensures validity. */ 2077 tcg_debug_assert(0 <= value && value <= 0x1f); 2078 2079 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, value)); 2080 return; 2081 } 2082 2083 if (is_add) { 2084 insn = add_vec_insn[lasx][vece]; 2085 } else { 2086 insn = sub_vec_insn[lasx][vece]; 2087 } 2088 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 2089} 2090 2091static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2092 unsigned vecl, unsigned vece, 2093 const TCGArg args[TCG_MAX_OP_ARGS], 2094 const int const_args[TCG_MAX_OP_ARGS]) 2095{ 2096 TCGType type = vecl + TCG_TYPE_V64; 2097 bool lasx = type == TCG_TYPE_V256; 2098 TCGArg a0, a1, a2, a3; 2099 LoongArchInsn insn; 2100 2101 static const LoongArchInsn cmp_vec_insn[16][2][4] = { 2102 [TCG_COND_EQ] = { 2103 { OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D }, 2104 { OPC_XVSEQ_B, OPC_XVSEQ_H, OPC_XVSEQ_W, OPC_XVSEQ_D }, 2105 }, 2106 [TCG_COND_LE] = { 2107 { OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D }, 2108 { OPC_XVSLE_B, OPC_XVSLE_H, OPC_XVSLE_W, OPC_XVSLE_D }, 2109 }, 2110 [TCG_COND_LEU] = { 2111 { OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU }, 2112 { OPC_XVSLE_BU, OPC_XVSLE_HU, OPC_XVSLE_WU, OPC_XVSLE_DU }, 2113 }, 2114 [TCG_COND_LT] = { 2115 { OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D }, 2116 { OPC_XVSLT_B, OPC_XVSLT_H, OPC_XVSLT_W, OPC_XVSLT_D }, 2117 }, 2118 [TCG_COND_LTU] = { 2119 { OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU }, 2120 { OPC_XVSLT_BU, OPC_XVSLT_HU, OPC_XVSLT_WU, OPC_XVSLT_DU }, 2121 } 2122 }; 2123 static const LoongArchInsn cmp_vec_imm_insn[16][2][4] = { 2124 [TCG_COND_EQ] = { 2125 { OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D }, 2126 { OPC_XVSEQI_B, OPC_XVSEQI_H, OPC_XVSEQI_W, OPC_XVSEQI_D }, 2127 }, 2128 [TCG_COND_LE] = { 2129 { OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D }, 2130 { OPC_XVSLEI_B, OPC_XVSLEI_H, OPC_XVSLEI_W, OPC_XVSLEI_D }, 2131 }, 2132 [TCG_COND_LEU] = { 2133 { OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU }, 2134 { OPC_XVSLEI_BU, OPC_XVSLEI_HU, OPC_XVSLEI_WU, OPC_XVSLEI_DU }, 2135 }, 2136 [TCG_COND_LT] = { 2137 { OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D }, 2138 { OPC_XVSLTI_B, OPC_XVSLTI_H, OPC_XVSLTI_W, OPC_XVSLTI_D }, 2139 }, 2140 [TCG_COND_LTU] = { 2141 { OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU }, 2142 { OPC_XVSLTI_BU, OPC_XVSLTI_HU, OPC_XVSLTI_WU, OPC_XVSLTI_DU }, 2143 } 2144 }; 2145 static const LoongArchInsn neg_vec_insn[2][4] = { 2146 { OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D }, 2147 { OPC_XVNEG_B, OPC_XVNEG_H, OPC_XVNEG_W, OPC_XVNEG_D }, 2148 }; 2149 static const LoongArchInsn mul_vec_insn[2][4] = { 2150 { OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D }, 2151 { OPC_XVMUL_B, OPC_XVMUL_H, OPC_XVMUL_W, OPC_XVMUL_D }, 2152 }; 2153 static const LoongArchInsn smin_vec_insn[2][4] = { 2154 { OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D }, 2155 { OPC_XVMIN_B, OPC_XVMIN_H, OPC_XVMIN_W, OPC_XVMIN_D }, 2156 }; 2157 static const LoongArchInsn umin_vec_insn[2][4] = { 2158 { OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU }, 2159 { OPC_XVMIN_BU, OPC_XVMIN_HU, OPC_XVMIN_WU, OPC_XVMIN_DU }, 2160 }; 2161 static const LoongArchInsn smax_vec_insn[2][4] = { 2162 { OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D }, 2163 { OPC_XVMAX_B, OPC_XVMAX_H, OPC_XVMAX_W, OPC_XVMAX_D }, 2164 }; 2165 static const LoongArchInsn umax_vec_insn[2][4] = { 2166 { OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU }, 2167 { OPC_XVMAX_BU, OPC_XVMAX_HU, OPC_XVMAX_WU, OPC_XVMAX_DU }, 2168 }; 2169 static const LoongArchInsn ssadd_vec_insn[2][4] = { 2170 { OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D }, 2171 { OPC_XVSADD_B, OPC_XVSADD_H, OPC_XVSADD_W, OPC_XVSADD_D }, 2172 }; 2173 static const LoongArchInsn usadd_vec_insn[2][4] = { 2174 { OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU }, 2175 { OPC_XVSADD_BU, OPC_XVSADD_HU, OPC_XVSADD_WU, OPC_XVSADD_DU }, 2176 }; 2177 static const LoongArchInsn sssub_vec_insn[2][4] = { 2178 { OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D }, 2179 { OPC_XVSSUB_B, OPC_XVSSUB_H, OPC_XVSSUB_W, OPC_XVSSUB_D }, 2180 }; 2181 static const LoongArchInsn ussub_vec_insn[2][4] = { 2182 { OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU }, 2183 { OPC_XVSSUB_BU, OPC_XVSSUB_HU, OPC_XVSSUB_WU, OPC_XVSSUB_DU }, 2184 }; 2185 static const LoongArchInsn shlv_vec_insn[2][4] = { 2186 { OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D }, 2187 { OPC_XVSLL_B, OPC_XVSLL_H, OPC_XVSLL_W, OPC_XVSLL_D }, 2188 }; 2189 static const LoongArchInsn shrv_vec_insn[2][4] = { 2190 { OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D }, 2191 { OPC_XVSRL_B, OPC_XVSRL_H, OPC_XVSRL_W, OPC_XVSRL_D }, 2192 }; 2193 static const LoongArchInsn sarv_vec_insn[2][4] = { 2194 { OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D }, 2195 { OPC_XVSRA_B, OPC_XVSRA_H, OPC_XVSRA_W, OPC_XVSRA_D }, 2196 }; 2197 static const LoongArchInsn shli_vec_insn[2][4] = { 2198 { OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D }, 2199 { OPC_XVSLLI_B, OPC_XVSLLI_H, OPC_XVSLLI_W, OPC_XVSLLI_D }, 2200 }; 2201 static const LoongArchInsn shri_vec_insn[2][4] = { 2202 { OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D }, 2203 { OPC_XVSRLI_B, OPC_XVSRLI_H, OPC_XVSRLI_W, OPC_XVSRLI_D }, 2204 }; 2205 static const LoongArchInsn sari_vec_insn[2][4] = { 2206 { OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D }, 2207 { OPC_XVSRAI_B, OPC_XVSRAI_H, OPC_XVSRAI_W, OPC_XVSRAI_D }, 2208 }; 2209 static const LoongArchInsn rotrv_vec_insn[2][4] = { 2210 { OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D }, 2211 { OPC_XVROTR_B, OPC_XVROTR_H, OPC_XVROTR_W, OPC_XVROTR_D }, 2212 }; 2213 static const LoongArchInsn rotri_vec_insn[2][4] = { 2214 { OPC_VROTRI_B, OPC_VROTRI_H, OPC_VROTRI_W, OPC_VROTRI_D }, 2215 { OPC_XVROTRI_B, OPC_XVROTRI_H, OPC_XVROTRI_W, OPC_XVROTRI_D }, 2216 }; 2217 2218 a0 = args[0]; 2219 a1 = args[1]; 2220 a2 = args[2]; 2221 a3 = args[3]; 2222 2223 switch (opc) { 2224 case INDEX_op_st_vec: 2225 tcg_out_st(s, type, a0, a1, a2); 2226 break; 2227 case INDEX_op_ld_vec: 2228 tcg_out_ld(s, type, a0, a1, a2); 2229 break; 2230 case INDEX_op_and_vec: 2231 insn = lasx ? OPC_XVAND_V : OPC_VAND_V; 2232 goto vdvjvk; 2233 case INDEX_op_andc_vec: 2234 /* 2235 * vandn vd, vj, vk: vd = vk & ~vj 2236 * andc_vec vd, vj, vk: vd = vj & ~vk 2237 * vj and vk are swapped 2238 */ 2239 a1 = a2; 2240 a2 = args[1]; 2241 insn = lasx ? OPC_XVANDN_V : OPC_VANDN_V; 2242 goto vdvjvk; 2243 case INDEX_op_or_vec: 2244 insn = lasx ? OPC_XVOR_V : OPC_VOR_V; 2245 goto vdvjvk; 2246 case INDEX_op_orc_vec: 2247 insn = lasx ? OPC_XVORN_V : OPC_VORN_V; 2248 goto vdvjvk; 2249 case INDEX_op_xor_vec: 2250 insn = lasx ? OPC_XVXOR_V : OPC_VXOR_V; 2251 goto vdvjvk; 2252 case INDEX_op_not_vec: 2253 a2 = a1; 2254 /* fall through */ 2255 case INDEX_op_nor_vec: 2256 insn = lasx ? OPC_XVNOR_V : OPC_VNOR_V; 2257 goto vdvjvk; 2258 case INDEX_op_cmp_vec: 2259 { 2260 TCGCond cond = args[3]; 2261 2262 if (const_args[2]) { 2263 /* 2264 * cmp_vec dest, src, value 2265 * Try vseqi/vslei/vslti 2266 */ 2267 int64_t value = sextract64(a2, 0, 8 << vece); 2268 switch (cond) { 2269 case TCG_COND_EQ: 2270 case TCG_COND_LE: 2271 case TCG_COND_LT: 2272 insn = cmp_vec_imm_insn[cond][lasx][vece]; 2273 tcg_out32(s, encode_vdvjsk5_insn(insn, a0, a1, value)); 2274 break; 2275 case TCG_COND_LEU: 2276 case TCG_COND_LTU: 2277 insn = cmp_vec_imm_insn[cond][lasx][vece]; 2278 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, value)); 2279 break; 2280 default: 2281 g_assert_not_reached(); 2282 } 2283 break; 2284 } 2285 2286 insn = cmp_vec_insn[cond][lasx][vece]; 2287 if (insn == 0) { 2288 TCGArg t; 2289 t = a1, a1 = a2, a2 = t; 2290 cond = tcg_swap_cond(cond); 2291 insn = cmp_vec_insn[cond][lasx][vece]; 2292 tcg_debug_assert(insn != 0); 2293 } 2294 } 2295 goto vdvjvk; 2296 case INDEX_op_add_vec: 2297 tcg_out_addsub_vec(s, lasx, vece, a0, a1, a2, const_args[2], true); 2298 break; 2299 case INDEX_op_sub_vec: 2300 tcg_out_addsub_vec(s, lasx, vece, a0, a1, a2, const_args[2], false); 2301 break; 2302 case INDEX_op_neg_vec: 2303 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[lasx][vece], a0, a1)); 2304 break; 2305 case INDEX_op_mul_vec: 2306 insn = mul_vec_insn[lasx][vece]; 2307 goto vdvjvk; 2308 case INDEX_op_smin_vec: 2309 insn = smin_vec_insn[lasx][vece]; 2310 goto vdvjvk; 2311 case INDEX_op_smax_vec: 2312 insn = smax_vec_insn[lasx][vece]; 2313 goto vdvjvk; 2314 case INDEX_op_umin_vec: 2315 insn = umin_vec_insn[lasx][vece]; 2316 goto vdvjvk; 2317 case INDEX_op_umax_vec: 2318 insn = umax_vec_insn[lasx][vece]; 2319 goto vdvjvk; 2320 case INDEX_op_ssadd_vec: 2321 insn = ssadd_vec_insn[lasx][vece]; 2322 goto vdvjvk; 2323 case INDEX_op_usadd_vec: 2324 insn = usadd_vec_insn[lasx][vece]; 2325 goto vdvjvk; 2326 case INDEX_op_sssub_vec: 2327 insn = sssub_vec_insn[lasx][vece]; 2328 goto vdvjvk; 2329 case INDEX_op_ussub_vec: 2330 insn = ussub_vec_insn[lasx][vece]; 2331 goto vdvjvk; 2332 case INDEX_op_shlv_vec: 2333 insn = shlv_vec_insn[lasx][vece]; 2334 goto vdvjvk; 2335 case INDEX_op_shrv_vec: 2336 insn = shrv_vec_insn[lasx][vece]; 2337 goto vdvjvk; 2338 case INDEX_op_sarv_vec: 2339 insn = sarv_vec_insn[lasx][vece]; 2340 goto vdvjvk; 2341 case INDEX_op_rotlv_vec: 2342 /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */ 2343 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[lasx][vece], 2344 TCG_VEC_TMP0, a2)); 2345 a2 = TCG_VEC_TMP0; 2346 /* fall through */ 2347 case INDEX_op_rotrv_vec: 2348 insn = rotrv_vec_insn[lasx][vece]; 2349 goto vdvjvk; 2350 case INDEX_op_shli_vec: 2351 insn = shli_vec_insn[lasx][vece]; 2352 goto vdvjukN; 2353 case INDEX_op_shri_vec: 2354 insn = shri_vec_insn[lasx][vece]; 2355 goto vdvjukN; 2356 case INDEX_op_sari_vec: 2357 insn = sari_vec_insn[lasx][vece]; 2358 goto vdvjukN; 2359 case INDEX_op_rotli_vec: 2360 /* rotli_vec a1, a2 = rotri_vec a1, -a2 */ 2361 a2 = extract32(-a2, 0, 3 + vece); 2362 insn = rotri_vec_insn[lasx][vece]; 2363 goto vdvjukN; 2364 case INDEX_op_bitsel_vec: 2365 /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */ 2366 if (lasx) { 2367 tcg_out_opc_xvbitsel_v(s, a0, a3, a2, a1); 2368 } else { 2369 tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1); 2370 } 2371 break; 2372 case INDEX_op_dupm_vec: 2373 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2374 break; 2375 default: 2376 g_assert_not_reached(); 2377 vdvjvk: 2378 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 2379 break; 2380 vdvjukN: 2381 switch (vece) { 2382 case MO_8: 2383 tcg_out32(s, encode_vdvjuk3_insn(insn, a0, a1, a2)); 2384 break; 2385 case MO_16: 2386 tcg_out32(s, encode_vdvjuk4_insn(insn, a0, a1, a2)); 2387 break; 2388 case MO_32: 2389 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, a2)); 2390 break; 2391 case MO_64: 2392 tcg_out32(s, encode_vdvjuk6_insn(insn, a0, a1, a2)); 2393 break; 2394 default: 2395 g_assert_not_reached(); 2396 } 2397 break; 2398 } 2399} 2400 2401int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2402{ 2403 switch (opc) { 2404 case INDEX_op_ld_vec: 2405 case INDEX_op_st_vec: 2406 case INDEX_op_dup_vec: 2407 case INDEX_op_dupm_vec: 2408 case INDEX_op_cmp_vec: 2409 case INDEX_op_add_vec: 2410 case INDEX_op_sub_vec: 2411 case INDEX_op_and_vec: 2412 case INDEX_op_andc_vec: 2413 case INDEX_op_or_vec: 2414 case INDEX_op_orc_vec: 2415 case INDEX_op_xor_vec: 2416 case INDEX_op_nor_vec: 2417 case INDEX_op_not_vec: 2418 case INDEX_op_neg_vec: 2419 case INDEX_op_mul_vec: 2420 case INDEX_op_smin_vec: 2421 case INDEX_op_smax_vec: 2422 case INDEX_op_umin_vec: 2423 case INDEX_op_umax_vec: 2424 case INDEX_op_ssadd_vec: 2425 case INDEX_op_usadd_vec: 2426 case INDEX_op_sssub_vec: 2427 case INDEX_op_ussub_vec: 2428 case INDEX_op_shlv_vec: 2429 case INDEX_op_shrv_vec: 2430 case INDEX_op_sarv_vec: 2431 case INDEX_op_bitsel_vec: 2432 return 1; 2433 default: 2434 return 0; 2435 } 2436} 2437 2438void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2439 TCGArg a0, ...) 2440{ 2441 g_assert_not_reached(); 2442} 2443 2444static TCGConstraintSetIndex 2445tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2446{ 2447 switch (op) { 2448 case INDEX_op_goto_ptr: 2449 return C_O0_I1(r); 2450 2451 case INDEX_op_st8_i32: 2452 case INDEX_op_st8_i64: 2453 case INDEX_op_st16_i32: 2454 case INDEX_op_st16_i64: 2455 case INDEX_op_st32_i64: 2456 case INDEX_op_st_i32: 2457 case INDEX_op_st_i64: 2458 case INDEX_op_qemu_st_i32: 2459 case INDEX_op_qemu_st_i64: 2460 return C_O0_I2(rz, r); 2461 2462 case INDEX_op_qemu_ld_i128: 2463 return C_N2_I1(r, r, r); 2464 2465 case INDEX_op_qemu_st_i128: 2466 return C_O0_I3(r, r, r); 2467 2468 case INDEX_op_extu_i32_i64: 2469 case INDEX_op_extrl_i64_i32: 2470 case INDEX_op_extrh_i64_i32: 2471 case INDEX_op_ext_i32_i64: 2472 case INDEX_op_ld8s_i32: 2473 case INDEX_op_ld8s_i64: 2474 case INDEX_op_ld8u_i32: 2475 case INDEX_op_ld8u_i64: 2476 case INDEX_op_ld16s_i32: 2477 case INDEX_op_ld16s_i64: 2478 case INDEX_op_ld16u_i32: 2479 case INDEX_op_ld16u_i64: 2480 case INDEX_op_ld32s_i64: 2481 case INDEX_op_ld32u_i64: 2482 case INDEX_op_ld_i32: 2483 case INDEX_op_ld_i64: 2484 case INDEX_op_qemu_ld_i32: 2485 case INDEX_op_qemu_ld_i64: 2486 return C_O1_I1(r, r); 2487 2488 case INDEX_op_deposit_i32: 2489 case INDEX_op_deposit_i64: 2490 /* Must deposit into the same register as input */ 2491 return C_O1_I2(r, 0, rz); 2492 2493 case INDEX_op_ld_vec: 2494 case INDEX_op_dupm_vec: 2495 case INDEX_op_dup_vec: 2496 return C_O1_I1(w, r); 2497 2498 case INDEX_op_st_vec: 2499 return C_O0_I2(w, r); 2500 2501 case INDEX_op_cmp_vec: 2502 return C_O1_I2(w, w, wM); 2503 2504 case INDEX_op_add_vec: 2505 case INDEX_op_sub_vec: 2506 return C_O1_I2(w, w, wA); 2507 2508 case INDEX_op_and_vec: 2509 case INDEX_op_andc_vec: 2510 case INDEX_op_or_vec: 2511 case INDEX_op_orc_vec: 2512 case INDEX_op_xor_vec: 2513 case INDEX_op_nor_vec: 2514 case INDEX_op_mul_vec: 2515 case INDEX_op_smin_vec: 2516 case INDEX_op_smax_vec: 2517 case INDEX_op_umin_vec: 2518 case INDEX_op_umax_vec: 2519 case INDEX_op_ssadd_vec: 2520 case INDEX_op_usadd_vec: 2521 case INDEX_op_sssub_vec: 2522 case INDEX_op_ussub_vec: 2523 case INDEX_op_shlv_vec: 2524 case INDEX_op_shrv_vec: 2525 case INDEX_op_sarv_vec: 2526 case INDEX_op_rotrv_vec: 2527 case INDEX_op_rotlv_vec: 2528 return C_O1_I2(w, w, w); 2529 2530 case INDEX_op_not_vec: 2531 case INDEX_op_neg_vec: 2532 case INDEX_op_shli_vec: 2533 case INDEX_op_shri_vec: 2534 case INDEX_op_sari_vec: 2535 case INDEX_op_rotli_vec: 2536 return C_O1_I1(w, w); 2537 2538 case INDEX_op_bitsel_vec: 2539 return C_O1_I3(w, w, w, w); 2540 2541 default: 2542 return C_NotImplemented; 2543 } 2544} 2545 2546static const int tcg_target_callee_save_regs[] = { 2547 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2548 TCG_REG_S1, 2549 TCG_REG_S2, 2550 TCG_REG_S3, 2551 TCG_REG_S4, 2552 TCG_REG_S5, 2553 TCG_REG_S6, 2554 TCG_REG_S7, 2555 TCG_REG_S8, 2556 TCG_REG_S9, 2557 TCG_REG_RA, /* should be last for ABI compliance */ 2558}; 2559 2560/* Stack frame parameters. */ 2561#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2562#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2563#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2564#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2565 + TCG_TARGET_STACK_ALIGN - 1) \ 2566 & -TCG_TARGET_STACK_ALIGN) 2567#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2568 2569/* We're expecting to be able to use an immediate for frame allocation. */ 2570QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2571 2572/* Generate global QEMU prologue and epilogue code */ 2573static void tcg_target_qemu_prologue(TCGContext *s) 2574{ 2575 int i; 2576 2577 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2578 2579 /* TB prologue */ 2580 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2581 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2582 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2583 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2584 } 2585 2586 if (!tcg_use_softmmu && guest_base) { 2587 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2588 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2589 } 2590 2591 /* Call generated code */ 2592 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2593 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2594 2595 /* Return path for goto_ptr. Set return value to 0 */ 2596 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2597 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2598 2599 /* TB epilogue */ 2600 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2601 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2602 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2603 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2604 } 2605 2606 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2607 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 2608} 2609 2610static void tcg_out_tb_start(TCGContext *s) 2611{ 2612 /* nothing to do */ 2613} 2614 2615static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2616{ 2617 for (int i = 0; i < count; ++i) { 2618 /* Canonical nop is andi r0,r0,0 */ 2619 p[i] = OPC_ANDI; 2620 } 2621} 2622 2623static void tcg_target_init(TCGContext *s) 2624{ 2625 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2626 2627 /* Server and desktop class cpus have UAL; embedded cpus do not. */ 2628 if (!(hwcap & HWCAP_LOONGARCH_UAL)) { 2629 error_report("TCG: unaligned access support required; exiting"); 2630 exit(EXIT_FAILURE); 2631 } 2632 2633 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2634 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 2635 2636 tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; 2637 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2638 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2639 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2640 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2641 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2642 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2643 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2644 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2645 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2646 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2647 2648 if (cpuinfo & CPUINFO_LSX) { 2649 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2650 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2651 if (cpuinfo & CPUINFO_LASX) { 2652 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 2653 } 2654 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 2655 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 2656 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 2657 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 2658 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 2659 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 2660 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 2661 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 2662 } 2663 2664 s->reserved_regs = 0; 2665 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2666 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2667 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2668 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2669 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2670 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2671 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 2672 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 2673} 2674 2675typedef struct { 2676 DebugFrameHeader h; 2677 uint8_t fde_def_cfa[4]; 2678 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2679} DebugFrame; 2680 2681#define ELF_HOST_MACHINE EM_LOONGARCH 2682 2683static const DebugFrame debug_frame = { 2684 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2685 .h.cie.id = -1, 2686 .h.cie.version = 1, 2687 .h.cie.code_align = 1, 2688 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2689 .h.cie.return_column = TCG_REG_RA, 2690 2691 /* Total FDE size does not include the "len" member. */ 2692 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2693 2694 .fde_def_cfa = { 2695 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2696 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2697 (FRAME_SIZE >> 7) 2698 }, 2699 .fde_reg_ofs = { 2700 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 2701 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 2702 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 2703 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 2704 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 2705 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 2706 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 2707 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 2708 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 2709 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 2710 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 2711 } 2712}; 2713 2714void tcg_register_jit(const void *buf, size_t buf_size) 2715{ 2716 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2717} 2718