1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include <asm/hwcap.h> 33 34/* used for function call generation */ 35#define TCG_REG_CALL_STACK TCG_REG_SP 36#define TCG_TARGET_STACK_ALIGN 16 37#define TCG_TARGET_CALL_STACK_OFFSET 0 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 41#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 42 43#ifdef CONFIG_DEBUG_TCG 44static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 45 "zero", 46 "ra", 47 "tp", 48 "sp", 49 "a0", 50 "a1", 51 "a2", 52 "a3", 53 "a4", 54 "a5", 55 "a6", 56 "a7", 57 "t0", 58 "t1", 59 "t2", 60 "t3", 61 "t4", 62 "t5", 63 "t6", 64 "t7", 65 "t8", 66 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 67 "s9", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "s8", 77 "vr0", 78 "vr1", 79 "vr2", 80 "vr3", 81 "vr4", 82 "vr5", 83 "vr6", 84 "vr7", 85 "vr8", 86 "vr9", 87 "vr10", 88 "vr11", 89 "vr12", 90 "vr13", 91 "vr14", 92 "vr15", 93 "vr16", 94 "vr17", 95 "vr18", 96 "vr19", 97 "vr20", 98 "vr21", 99 "vr22", 100 "vr23", 101 "vr24", 102 "vr25", 103 "vr26", 104 "vr27", 105 "vr28", 106 "vr29", 107 "vr30", 108 "vr31", 109}; 110#endif 111 112static const int tcg_target_reg_alloc_order[] = { 113 /* Registers preserved across calls */ 114 /* TCG_REG_S0 reserved for TCG_AREG0 */ 115 TCG_REG_S1, 116 TCG_REG_S2, 117 TCG_REG_S3, 118 TCG_REG_S4, 119 TCG_REG_S5, 120 TCG_REG_S6, 121 TCG_REG_S7, 122 TCG_REG_S8, 123 TCG_REG_S9, 124 125 /* Registers (potentially) clobbered across calls */ 126 TCG_REG_T0, 127 TCG_REG_T1, 128 TCG_REG_T2, 129 TCG_REG_T3, 130 TCG_REG_T4, 131 TCG_REG_T5, 132 TCG_REG_T6, 133 TCG_REG_T7, 134 TCG_REG_T8, 135 136 /* Argument registers, opposite order of allocation. */ 137 TCG_REG_A7, 138 TCG_REG_A6, 139 TCG_REG_A5, 140 TCG_REG_A4, 141 TCG_REG_A3, 142 TCG_REG_A2, 143 TCG_REG_A1, 144 TCG_REG_A0, 145 146 /* Vector registers */ 147 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 148 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 149 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 150 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 151 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 152 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 153 /* V24 - V31 are caller-saved, and skipped. */ 154}; 155 156static const int tcg_target_call_iarg_regs[] = { 157 TCG_REG_A0, 158 TCG_REG_A1, 159 TCG_REG_A2, 160 TCG_REG_A3, 161 TCG_REG_A4, 162 TCG_REG_A5, 163 TCG_REG_A6, 164 TCG_REG_A7, 165}; 166 167static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 168{ 169 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 170 tcg_debug_assert(slot >= 0 && slot <= 1); 171 return TCG_REG_A0 + slot; 172} 173 174#define TCG_GUEST_BASE_REG TCG_REG_S1 175 176#define TCG_CT_CONST_S12 0x100 177#define TCG_CT_CONST_S32 0x200 178#define TCG_CT_CONST_U12 0x400 179#define TCG_CT_CONST_WSZ 0x800 180#define TCG_CT_CONST_VCMP 0x1000 181#define TCG_CT_CONST_VADD 0x2000 182 183#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 184#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 185 186static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 187{ 188 return sextract64(val, pos, len); 189} 190 191/* test if a constant matches the constraint */ 192static bool tcg_target_const_match(int64_t val, int ct, 193 TCGType type, TCGCond cond, int vece) 194{ 195 if (ct & TCG_CT_CONST) { 196 return true; 197 } 198 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 199 return true; 200 } 201 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 202 return true; 203 } 204 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 205 return true; 206 } 207 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return true; 209 } 210 if (ct & (TCG_CT_CONST_VCMP | TCG_CT_CONST_VADD)) { 211 int64_t vec_val = sextract64(val, 0, 8 << vece); 212 if (ct & TCG_CT_CONST_VCMP) { 213 switch (cond) { 214 case TCG_COND_EQ: 215 case TCG_COND_LE: 216 case TCG_COND_LT: 217 return -0x10 <= vec_val && vec_val <= 0x0f; 218 case TCG_COND_LEU: 219 case TCG_COND_LTU: 220 return 0x00 <= vec_val && vec_val <= 0x1f; 221 default: 222 return false; 223 } 224 } 225 if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) { 226 return true; 227 } 228 } 229 return false; 230} 231 232/* 233 * Relocations 234 */ 235 236/* 237 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 238 * complicated; a whopping stack machine is needed to stuff the fields, at 239 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 240 * needed. 241 * 242 * Hence, define our own simpler relocation types. Numbers are chosen as to 243 * not collide with potential future additions to the true ELF relocation 244 * type enum. 245 */ 246 247/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 248#define R_LOONGARCH_BR_SK16 256 249/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 250#define R_LOONGARCH_BR_SD10K16 257 251 252static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 253{ 254 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 255 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 256 257 tcg_debug_assert((offset & 3) == 0); 258 offset >>= 2; 259 if (offset == sextreg(offset, 0, 16)) { 260 *src_rw = deposit64(*src_rw, 10, 16, offset); 261 return true; 262 } 263 264 return false; 265} 266 267static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 268 const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 272 273 tcg_debug_assert((offset & 3) == 0); 274 offset >>= 2; 275 if (offset == sextreg(offset, 0, 26)) { 276 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 277 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 278 return true; 279 } 280 281 return false; 282} 283 284static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 285 intptr_t value, intptr_t addend) 286{ 287 tcg_debug_assert(addend == 0); 288 switch (type) { 289 case R_LOONGARCH_BR_SK16: 290 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 291 case R_LOONGARCH_BR_SD10K16: 292 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 293 default: 294 g_assert_not_reached(); 295 } 296} 297 298#include "tcg-insn-defs.c.inc" 299 300/* 301 * TCG intrinsics 302 */ 303 304static void tcg_out_mb(TCGContext *s, TCGArg a0) 305{ 306 /* Baseline LoongArch only has the full barrier, unfortunately. */ 307 tcg_out_opc_dbar(s, 0); 308} 309 310static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 311{ 312 if (ret == arg) { 313 return true; 314 } 315 switch (type) { 316 case TCG_TYPE_I32: 317 case TCG_TYPE_I64: 318 if (ret < TCG_REG_V0) { 319 if (arg < TCG_REG_V0) { 320 /* 321 * Conventional register-register move used in LoongArch is 322 * `or dst, src, zero`. 323 */ 324 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 325 } else { 326 tcg_out_opc_movfr2gr_d(s, ret, arg); 327 } 328 } else { 329 if (arg < TCG_REG_V0) { 330 tcg_out_opc_movgr2fr_d(s, ret, arg); 331 } else { 332 tcg_out_opc_fmov_d(s, ret, arg); 333 } 334 } 335 break; 336 case TCG_TYPE_V64: 337 case TCG_TYPE_V128: 338 tcg_out_opc_vori_b(s, ret, arg, 0); 339 break; 340 case TCG_TYPE_V256: 341 tcg_out_opc_xvori_b(s, ret, arg, 0); 342 break; 343 default: 344 g_assert_not_reached(); 345 } 346 return true; 347} 348 349/* Loads a 32-bit immediate into rd, sign-extended. */ 350static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 351{ 352 tcg_target_long lo = sextreg(val, 0, 12); 353 tcg_target_long hi12 = sextreg(val, 12, 20); 354 355 /* Single-instruction cases. */ 356 if (hi12 == 0) { 357 /* val fits in uimm12: ori rd, zero, val */ 358 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 359 return; 360 } 361 if (hi12 == sextreg(lo, 12, 20)) { 362 /* val fits in simm12: addi.w rd, zero, val */ 363 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 364 return; 365 } 366 367 /* High bits must be set; load with lu12i.w + optional ori. */ 368 tcg_out_opc_lu12i_w(s, rd, hi12); 369 if (lo != 0) { 370 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 371 } 372} 373 374static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 375 tcg_target_long val) 376{ 377 /* 378 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 379 * with dedicated instructions for filling the respective bitfields 380 * below: 381 * 382 * 6 5 4 3 383 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 384 * +-----------------------+---------------------------------------+... 385 * | hi52 | hi32 | 386 * +-----------------------+---------------------------------------+... 387 * 3 2 1 388 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 389 * ...+-------------------------------------+-------------------------+ 390 * | hi12 | lo | 391 * ...+-------------------------------------+-------------------------+ 392 * 393 * Check if val belong to one of the several fast cases, before falling 394 * back to the slow path. 395 */ 396 397 intptr_t src_rx, pc_offset; 398 tcg_target_long hi12, hi32, hi52; 399 400 /* Value fits in signed i32. */ 401 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 402 tcg_out_movi_i32(s, rd, val); 403 return; 404 } 405 406 /* PC-relative cases. */ 407 src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr); 408 if ((val & 3) == 0) { 409 pc_offset = val - src_rx; 410 if (pc_offset == sextreg(pc_offset, 0, 22)) { 411 /* Single pcaddu2i. */ 412 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 413 return; 414 } 415 } 416 417 pc_offset = (val >> 12) - (src_rx >> 12); 418 if (pc_offset == sextreg(pc_offset, 0, 20)) { 419 /* Load with pcalau12i + ori. */ 420 tcg_target_long val_lo = val & 0xfff; 421 tcg_out_opc_pcalau12i(s, rd, pc_offset); 422 if (val_lo != 0) { 423 tcg_out_opc_ori(s, rd, rd, val_lo); 424 } 425 return; 426 } 427 428 hi12 = sextreg(val, 12, 20); 429 hi32 = sextreg(val, 32, 20); 430 hi52 = sextreg(val, 52, 12); 431 432 /* Single cu52i.d case. */ 433 if ((hi52 != 0) && (ctz64(val) >= 52)) { 434 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 435 return; 436 } 437 438 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 439 tcg_out_movi_i32(s, rd, val); 440 441 /* Load hi32 and hi52 explicitly when they are unexpected values. */ 442 if (hi32 != sextreg(hi12, 20, 20)) { 443 tcg_out_opc_cu32i_d(s, rd, hi32); 444 } 445 446 if (hi52 != sextreg(hi32, 20, 12)) { 447 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 448 } 449} 450 451static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, 452 TCGReg rs, tcg_target_long imm) 453{ 454 tcg_target_long lo12 = sextreg(imm, 0, 12); 455 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16); 456 457 /* 458 * Note that there's a hole in between hi16 and lo12: 459 * 460 * 3 2 1 0 461 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 462 * ...+-------------------------------+-------+-----------------------+ 463 * | hi16 | | lo12 | 464 * ...+-------------------------------+-------+-----------------------+ 465 * 466 * For bits within that hole, it's more efficient to use LU12I and ADD. 467 */ 468 if (imm == (hi16 << 16) + lo12) { 469 if (hi16) { 470 tcg_out_opc_addu16i_d(s, rd, rs, hi16); 471 rs = rd; 472 } 473 if (type == TCG_TYPE_I32) { 474 tcg_out_opc_addi_w(s, rd, rs, lo12); 475 } else if (lo12) { 476 tcg_out_opc_addi_d(s, rd, rs, lo12); 477 } else { 478 tcg_out_mov(s, type, rd, rs); 479 } 480 } else { 481 tcg_out_movi(s, type, TCG_REG_TMP0, imm); 482 if (type == TCG_TYPE_I32) { 483 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); 484 } else { 485 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); 486 } 487 } 488} 489 490static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 491{ 492 return false; 493} 494 495static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 496 tcg_target_long imm) 497{ 498 /* This function is only used for passing structs by reference. */ 499 g_assert_not_reached(); 500} 501 502static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 503{ 504 tcg_out_opc_andi(s, ret, arg, 0xff); 505} 506 507static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 508{ 509 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 510} 511 512static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 513{ 514 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 515} 516 517static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 518{ 519 tcg_out_opc_sext_b(s, ret, arg); 520} 521 522static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 523{ 524 tcg_out_opc_sext_h(s, ret, arg); 525} 526 527static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 528{ 529 tcg_out_opc_addi_w(s, ret, arg, 0); 530} 531 532static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 533{ 534 if (ret != arg) { 535 tcg_out_ext32s(s, ret, arg); 536 } 537} 538 539static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 540{ 541 tcg_out_ext32u(s, ret, arg); 542} 543 544static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 545{ 546 tcg_out_ext32s(s, ret, arg); 547} 548 549#define SETCOND_INV TCG_TARGET_NB_REGS 550#define SETCOND_NEZ (SETCOND_INV << 1) 551#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 552 553static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 554 TCGReg arg1, tcg_target_long arg2, bool c2) 555{ 556 int flags = 0; 557 558 switch (cond) { 559 case TCG_COND_EQ: /* -> NE */ 560 case TCG_COND_GE: /* -> LT */ 561 case TCG_COND_GEU: /* -> LTU */ 562 case TCG_COND_GT: /* -> LE */ 563 case TCG_COND_GTU: /* -> LEU */ 564 cond = tcg_invert_cond(cond); 565 flags ^= SETCOND_INV; 566 break; 567 default: 568 break; 569 } 570 571 switch (cond) { 572 case TCG_COND_LE: 573 case TCG_COND_LEU: 574 /* 575 * If we have a constant input, the most efficient way to implement 576 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 577 * We don't need to care for this for LE because the constant input 578 * is still constrained to int32_t, and INT32_MAX+1 is representable 579 * in the 64-bit temporary register. 580 */ 581 if (c2) { 582 if (cond == TCG_COND_LEU) { 583 /* unsigned <= -1 is true */ 584 if (arg2 == -1) { 585 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 586 return ret; 587 } 588 cond = TCG_COND_LTU; 589 } else { 590 cond = TCG_COND_LT; 591 } 592 arg2 += 1; 593 } else { 594 TCGReg tmp = arg2; 595 arg2 = arg1; 596 arg1 = tmp; 597 cond = tcg_swap_cond(cond); /* LE -> GE */ 598 cond = tcg_invert_cond(cond); /* GE -> LT */ 599 flags ^= SETCOND_INV; 600 } 601 break; 602 default: 603 break; 604 } 605 606 switch (cond) { 607 case TCG_COND_NE: 608 flags |= SETCOND_NEZ; 609 if (!c2) { 610 tcg_out_opc_xor(s, ret, arg1, arg2); 611 } else if (arg2 == 0) { 612 ret = arg1; 613 } else if (arg2 >= 0 && arg2 <= 0xfff) { 614 tcg_out_opc_xori(s, ret, arg1, arg2); 615 } else { 616 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2); 617 } 618 break; 619 620 case TCG_COND_LT: 621 case TCG_COND_LTU: 622 if (c2) { 623 if (arg2 >= -0x800 && arg2 <= 0x7ff) { 624 if (cond == TCG_COND_LT) { 625 tcg_out_opc_slti(s, ret, arg1, arg2); 626 } else { 627 tcg_out_opc_sltui(s, ret, arg1, arg2); 628 } 629 break; 630 } 631 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 632 arg2 = TCG_REG_TMP0; 633 } 634 if (cond == TCG_COND_LT) { 635 tcg_out_opc_slt(s, ret, arg1, arg2); 636 } else { 637 tcg_out_opc_sltu(s, ret, arg1, arg2); 638 } 639 break; 640 641 default: 642 g_assert_not_reached(); 643 } 644 645 return ret | flags; 646} 647 648static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 649 TCGReg arg1, tcg_target_long arg2, bool c2) 650{ 651 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 652 653 if (tmpflags != ret) { 654 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 655 656 switch (tmpflags & SETCOND_FLAGS) { 657 case SETCOND_INV: 658 /* Intermediate result is boolean: simply invert. */ 659 tcg_out_opc_xori(s, ret, tmp, 1); 660 break; 661 case SETCOND_NEZ: 662 /* Intermediate result is zero/non-zero: test != 0. */ 663 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 664 break; 665 case SETCOND_NEZ | SETCOND_INV: 666 /* Intermediate result is zero/non-zero: test == 0. */ 667 tcg_out_opc_sltui(s, ret, tmp, 1); 668 break; 669 default: 670 g_assert_not_reached(); 671 } 672 } 673} 674 675static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 676 TCGReg c1, tcg_target_long c2, bool const2, 677 TCGReg v1, TCGReg v2) 678{ 679 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2); 680 TCGReg t; 681 682 /* Standardize the test below to t != 0. */ 683 if (tmpflags & SETCOND_INV) { 684 t = v1, v1 = v2, v2 = t; 685 } 686 687 t = tmpflags & ~SETCOND_FLAGS; 688 if (v1 == TCG_REG_ZERO) { 689 tcg_out_opc_masknez(s, ret, v2, t); 690 } else if (v2 == TCG_REG_ZERO) { 691 tcg_out_opc_maskeqz(s, ret, v1, t); 692 } else { 693 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */ 694 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */ 695 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2); 696 } 697} 698 699/* 700 * Branch helpers 701 */ 702 703static const struct { 704 LoongArchInsn op; 705 bool swap; 706} tcg_brcond_to_loongarch[] = { 707 [TCG_COND_EQ] = { OPC_BEQ, false }, 708 [TCG_COND_NE] = { OPC_BNE, false }, 709 [TCG_COND_LT] = { OPC_BGT, true }, 710 [TCG_COND_GE] = { OPC_BLE, true }, 711 [TCG_COND_LE] = { OPC_BLE, false }, 712 [TCG_COND_GT] = { OPC_BGT, false }, 713 [TCG_COND_LTU] = { OPC_BGTU, true }, 714 [TCG_COND_GEU] = { OPC_BLEU, true }, 715 [TCG_COND_LEU] = { OPC_BLEU, false }, 716 [TCG_COND_GTU] = { OPC_BGTU, false } 717}; 718 719static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 720 TCGReg arg2, TCGLabel *l) 721{ 722 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 723 724 tcg_debug_assert(op != 0); 725 726 if (tcg_brcond_to_loongarch[cond].swap) { 727 TCGReg t = arg1; 728 arg1 = arg2; 729 arg2 = t; 730 } 731 732 /* all conditional branch insns belong to DJSk16-format */ 733 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 734 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 735} 736 737static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 738{ 739 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 740 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 741 742 tcg_debug_assert((offset & 3) == 0); 743 if (offset == sextreg(offset, 0, 28)) { 744 /* short jump: +/- 256MiB */ 745 if (tail) { 746 tcg_out_opc_b(s, offset >> 2); 747 } else { 748 tcg_out_opc_bl(s, offset >> 2); 749 } 750 } else if (offset == sextreg(offset, 0, 38)) { 751 /* long jump: +/- 256GiB */ 752 tcg_target_long lo = sextreg(offset, 0, 18); 753 tcg_target_long hi = offset - lo; 754 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 755 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 756 } else { 757 /* far jump: 64-bit */ 758 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 759 tcg_target_long hi = (tcg_target_long)arg - lo; 760 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 761 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 762 } 763} 764 765static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 766 const TCGHelperInfo *info) 767{ 768 tcg_out_call_int(s, arg, false); 769} 770 771/* 772 * Load/store helpers 773 */ 774 775static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 776 TCGReg addr, intptr_t offset) 777{ 778 intptr_t imm12 = sextreg(offset, 0, 12); 779 780 if (offset != imm12) { 781 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 782 783 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 784 imm12 = sextreg(diff, 0, 12); 785 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 786 } else { 787 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 788 if (addr != TCG_REG_ZERO) { 789 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 790 } 791 } 792 addr = TCG_REG_TMP2; 793 } 794 795 switch (opc) { 796 case OPC_LD_B: 797 case OPC_LD_BU: 798 case OPC_LD_H: 799 case OPC_LD_HU: 800 case OPC_LD_W: 801 case OPC_LD_WU: 802 case OPC_LD_D: 803 case OPC_ST_B: 804 case OPC_ST_H: 805 case OPC_ST_W: 806 case OPC_ST_D: 807 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 808 break; 809 case OPC_FLD_S: 810 case OPC_FLD_D: 811 case OPC_FST_S: 812 case OPC_FST_D: 813 tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12)); 814 break; 815 default: 816 g_assert_not_reached(); 817 } 818} 819 820static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest, 821 TCGReg base, intptr_t offset) 822{ 823 switch (type) { 824 case TCG_TYPE_I32: 825 if (dest < TCG_REG_V0) { 826 tcg_out_ldst(s, OPC_LD_W, dest, base, offset); 827 } else { 828 tcg_out_ldst(s, OPC_FLD_S, dest, base, offset); 829 } 830 break; 831 case TCG_TYPE_I64: 832 case TCG_TYPE_V64: 833 if (dest < TCG_REG_V0) { 834 tcg_out_ldst(s, OPC_LD_D, dest, base, offset); 835 } else { 836 tcg_out_ldst(s, OPC_FLD_D, dest, base, offset); 837 } 838 break; 839 case TCG_TYPE_V128: 840 if (-0x800 <= offset && offset <= 0x7ff) { 841 tcg_out_opc_vld(s, dest, base, offset); 842 } else { 843 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 844 tcg_out_opc_vldx(s, dest, base, TCG_REG_TMP0); 845 } 846 break; 847 case TCG_TYPE_V256: 848 if (-0x800 <= offset && offset <= 0x7ff) { 849 tcg_out_opc_xvld(s, dest, base, offset); 850 } else { 851 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 852 tcg_out_opc_xvldx(s, dest, base, TCG_REG_TMP0); 853 } 854 break; 855 default: 856 g_assert_not_reached(); 857 } 858} 859 860static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, 861 TCGReg base, intptr_t offset) 862{ 863 switch (type) { 864 case TCG_TYPE_I32: 865 if (src < TCG_REG_V0) { 866 tcg_out_ldst(s, OPC_ST_W, src, base, offset); 867 } else { 868 tcg_out_ldst(s, OPC_FST_S, src, base, offset); 869 } 870 break; 871 case TCG_TYPE_I64: 872 case TCG_TYPE_V64: 873 if (src < TCG_REG_V0) { 874 tcg_out_ldst(s, OPC_ST_D, src, base, offset); 875 } else { 876 tcg_out_ldst(s, OPC_FST_D, src, base, offset); 877 } 878 break; 879 case TCG_TYPE_V128: 880 if (-0x800 <= offset && offset <= 0x7ff) { 881 tcg_out_opc_vst(s, src, base, offset); 882 } else { 883 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 884 tcg_out_opc_vstx(s, src, base, TCG_REG_TMP0); 885 } 886 break; 887 case TCG_TYPE_V256: 888 if (-0x800 <= offset && offset <= 0x7ff) { 889 tcg_out_opc_xvst(s, src, base, offset); 890 } else { 891 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 892 tcg_out_opc_xvstx(s, src, base, TCG_REG_TMP0); 893 } 894 break; 895 default: 896 g_assert_not_reached(); 897 } 898} 899 900static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 901 TCGReg base, intptr_t ofs) 902{ 903 if (val == 0) { 904 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 905 return true; 906 } 907 return false; 908} 909 910/* 911 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 912 */ 913 914static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 915{ 916 tcg_out_opc_b(s, 0); 917 return reloc_br_sd10k16(s->code_ptr - 1, target); 918} 919 920static const TCGLdstHelperParam ldst_helper_param = { 921 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 922}; 923 924static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 925{ 926 MemOp opc = get_memop(l->oi); 927 928 /* resolve label address */ 929 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 930 return false; 931 } 932 933 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 934 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); 935 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 936 return tcg_out_goto(s, l->raddr); 937} 938 939static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 940{ 941 MemOp opc = get_memop(l->oi); 942 943 /* resolve label address */ 944 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 945 return false; 946 } 947 948 tcg_out_st_helper_args(s, l, &ldst_helper_param); 949 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 950 return tcg_out_goto(s, l->raddr); 951} 952 953typedef struct { 954 TCGReg base; 955 TCGReg index; 956 TCGAtomAlign aa; 957} HostAddress; 958 959bool tcg_target_has_memory_bswap(MemOp memop) 960{ 961 return false; 962} 963 964/* We expect to use a 12-bit negative offset from ENV. */ 965#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 966 967/* 968 * For system-mode, perform the TLB load and compare. 969 * For user-mode, perform any required alignment tests. 970 * In both cases, return a TCGLabelQemuLdst structure if the slow path 971 * is required and fill in @h with the host address for the fast path. 972 */ 973static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 974 TCGReg addr_reg, MemOpIdx oi, 975 bool is_ld) 976{ 977 TCGType addr_type = s->addr_type; 978 TCGLabelQemuLdst *ldst = NULL; 979 MemOp opc = get_memop(oi); 980 MemOp a_bits; 981 982 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 983 a_bits = h->aa.align; 984 985 if (tcg_use_softmmu) { 986 unsigned s_bits = opc & MO_SIZE; 987 int mem_index = get_mmuidx(oi); 988 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 989 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 990 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 991 992 ldst = new_ldst_label(s); 993 ldst->is_ld = is_ld; 994 ldst->oi = oi; 995 ldst->addr_reg = addr_reg; 996 997 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 998 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 999 1000 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, 1001 s->page_bits - CPU_TLB_ENTRY_BITS); 1002 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 1003 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 1004 1005 /* Load the tlb comparator and the addend. */ 1006 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 1007 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 1008 is_ld ? offsetof(CPUTLBEntry, addr_read) 1009 : offsetof(CPUTLBEntry, addr_write)); 1010 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 1011 offsetof(CPUTLBEntry, addend)); 1012 1013 /* 1014 * For aligned accesses, we check the first byte and include the 1015 * alignment bits within the address. For unaligned access, we 1016 * check that we don't cross pages using the address of the last 1017 * byte of the access. 1018 */ 1019 if (a_bits < s_bits) { 1020 unsigned a_mask = (1u << a_bits) - 1; 1021 unsigned s_mask = (1u << s_bits) - 1; 1022 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask); 1023 } else { 1024 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); 1025 } 1026 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, 1027 a_bits, s->page_bits - 1); 1028 1029 /* Compare masked address with the TLB entry. */ 1030 ldst->label_ptr[0] = s->code_ptr; 1031 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1032 1033 h->index = TCG_REG_TMP2; 1034 } else { 1035 if (a_bits) { 1036 ldst = new_ldst_label(s); 1037 1038 ldst->is_ld = is_ld; 1039 ldst->oi = oi; 1040 ldst->addr_reg = addr_reg; 1041 1042 /* 1043 * Without micro-architecture details, we don't know which of 1044 * bstrpick or andi is faster, so use bstrpick as it's not 1045 * constrained by imm field width. Not to say alignments >= 2^12 1046 * are going to happen any time soon. 1047 */ 1048 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 1049 1050 ldst->label_ptr[0] = s->code_ptr; 1051 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1052 } 1053 1054 h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1055 } 1056 1057 if (addr_type == TCG_TYPE_I32) { 1058 h->base = TCG_REG_TMP0; 1059 tcg_out_ext32u(s, h->base, addr_reg); 1060 } else { 1061 h->base = addr_reg; 1062 } 1063 1064 return ldst; 1065} 1066 1067static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, 1068 TCGReg rd, HostAddress h) 1069{ 1070 /* Byte swapping is left to middle-end expansion. */ 1071 tcg_debug_assert((opc & MO_BSWAP) == 0); 1072 1073 switch (opc & MO_SSIZE) { 1074 case MO_UB: 1075 tcg_out_opc_ldx_bu(s, rd, h.base, h.index); 1076 break; 1077 case MO_SB: 1078 tcg_out_opc_ldx_b(s, rd, h.base, h.index); 1079 break; 1080 case MO_UW: 1081 tcg_out_opc_ldx_hu(s, rd, h.base, h.index); 1082 break; 1083 case MO_SW: 1084 tcg_out_opc_ldx_h(s, rd, h.base, h.index); 1085 break; 1086 case MO_UL: 1087 if (type == TCG_TYPE_I64) { 1088 tcg_out_opc_ldx_wu(s, rd, h.base, h.index); 1089 break; 1090 } 1091 /* fallthrough */ 1092 case MO_SL: 1093 tcg_out_opc_ldx_w(s, rd, h.base, h.index); 1094 break; 1095 case MO_UQ: 1096 tcg_out_opc_ldx_d(s, rd, h.base, h.index); 1097 break; 1098 default: 1099 g_assert_not_reached(); 1100 } 1101} 1102 1103static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1104 MemOpIdx oi, TCGType data_type) 1105{ 1106 TCGLabelQemuLdst *ldst; 1107 HostAddress h; 1108 1109 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1110 tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); 1111 1112 if (ldst) { 1113 ldst->type = data_type; 1114 ldst->datalo_reg = data_reg; 1115 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1116 } 1117} 1118 1119static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, 1120 TCGReg rd, HostAddress h) 1121{ 1122 /* Byte swapping is left to middle-end expansion. */ 1123 tcg_debug_assert((opc & MO_BSWAP) == 0); 1124 1125 switch (opc & MO_SIZE) { 1126 case MO_8: 1127 tcg_out_opc_stx_b(s, rd, h.base, h.index); 1128 break; 1129 case MO_16: 1130 tcg_out_opc_stx_h(s, rd, h.base, h.index); 1131 break; 1132 case MO_32: 1133 tcg_out_opc_stx_w(s, rd, h.base, h.index); 1134 break; 1135 case MO_64: 1136 tcg_out_opc_stx_d(s, rd, h.base, h.index); 1137 break; 1138 default: 1139 g_assert_not_reached(); 1140 } 1141} 1142 1143static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1144 MemOpIdx oi, TCGType data_type) 1145{ 1146 TCGLabelQemuLdst *ldst; 1147 HostAddress h; 1148 1149 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1150 tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); 1151 1152 if (ldst) { 1153 ldst->type = data_type; 1154 ldst->datalo_reg = data_reg; 1155 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1156 } 1157} 1158 1159static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi, 1160 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1161{ 1162 TCGLabelQemuLdst *ldst; 1163 HostAddress h; 1164 1165 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1166 1167 if (h.aa.atom == MO_128) { 1168 /* 1169 * Use VLDX/VSTX when 128-bit atomicity is required. 1170 * If address is aligned to 16-bytes, the 128-bit load/store is atomic. 1171 */ 1172 if (is_ld) { 1173 tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index); 1174 tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0); 1175 tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1); 1176 } else { 1177 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0); 1178 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1); 1179 tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index); 1180 } 1181 } else { 1182 /* Otherwise use a pair of LD/ST. */ 1183 TCGReg base = h.base; 1184 if (h.index != TCG_REG_ZERO) { 1185 base = TCG_REG_TMP0; 1186 tcg_out_opc_add_d(s, base, h.base, h.index); 1187 } 1188 if (is_ld) { 1189 tcg_debug_assert(base != data_lo); 1190 tcg_out_opc_ld_d(s, data_lo, base, 0); 1191 tcg_out_opc_ld_d(s, data_hi, base, 8); 1192 } else { 1193 tcg_out_opc_st_d(s, data_lo, base, 0); 1194 tcg_out_opc_st_d(s, data_hi, base, 8); 1195 } 1196 } 1197 1198 if (ldst) { 1199 ldst->type = TCG_TYPE_I128; 1200 ldst->datalo_reg = data_lo; 1201 ldst->datahi_reg = data_hi; 1202 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1203 } 1204} 1205 1206/* 1207 * Entry-points 1208 */ 1209 1210static const tcg_insn_unit *tb_ret_addr; 1211 1212static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1213{ 1214 /* Reuse the zeroing that exists for goto_ptr. */ 1215 if (a0 == 0) { 1216 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1217 } else { 1218 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1219 tcg_out_call_int(s, tb_ret_addr, true); 1220 } 1221} 1222 1223static void tcg_out_goto_tb(TCGContext *s, int which) 1224{ 1225 /* 1226 * Direct branch, or load indirect address, to be patched 1227 * by tb_target_set_jmp_target. Check indirect load offset 1228 * in range early, regardless of direct branch distance, 1229 * via assert within tcg_out_opc_pcaddu2i. 1230 */ 1231 uintptr_t i_addr = get_jmp_target_addr(s, which); 1232 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr); 1233 1234 set_jmp_insn_offset(s, which); 1235 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2); 1236 1237 /* Finish the load and indirect branch. */ 1238 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); 1239 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1240 set_jmp_reset_offset(s, which); 1241} 1242 1243void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1244 uintptr_t jmp_rx, uintptr_t jmp_rw) 1245{ 1246 uintptr_t d_addr = tb->jmp_target_addr[n]; 1247 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2; 1248 tcg_insn_unit insn; 1249 1250 /* Either directly branch, or load slot address for indirect branch. */ 1251 if (d_disp == sextreg(d_disp, 0, 26)) { 1252 insn = encode_sd10k16_insn(OPC_B, d_disp); 1253 } else { 1254 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 1255 intptr_t i_disp = i_addr - jmp_rx; 1256 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2); 1257 } 1258 1259 qatomic_set((tcg_insn_unit *)jmp_rw, insn); 1260 flush_idcache_range(jmp_rx, jmp_rw, 4); 1261} 1262 1263 1264static void tgen_add(TCGContext *s, TCGType type, 1265 TCGReg a0, TCGReg a1, TCGReg a2) 1266{ 1267 if (type == TCG_TYPE_I32) { 1268 tcg_out_opc_add_w(s, a0, a1, a2); 1269 } else { 1270 tcg_out_opc_add_d(s, a0, a1, a2); 1271 } 1272} 1273 1274static const TCGOutOpBinary outop_add = { 1275 .base.static_constraint = C_O1_I2(r, r, rJ), 1276 .out_rrr = tgen_add, 1277 .out_rri = tcg_out_addi, 1278}; 1279 1280static void tgen_and(TCGContext *s, TCGType type, 1281 TCGReg a0, TCGReg a1, TCGReg a2) 1282{ 1283 tcg_out_opc_and(s, a0, a1, a2); 1284} 1285 1286static void tgen_andi(TCGContext *s, TCGType type, 1287 TCGReg a0, TCGReg a1, tcg_target_long a2) 1288{ 1289 tcg_out_opc_andi(s, a0, a1, a2); 1290} 1291 1292static const TCGOutOpBinary outop_and = { 1293 .base.static_constraint = C_O1_I2(r, r, rU), 1294 .out_rrr = tgen_and, 1295 .out_rri = tgen_andi, 1296}; 1297 1298static void tgen_andc(TCGContext *s, TCGType type, 1299 TCGReg a0, TCGReg a1, TCGReg a2) 1300{ 1301 tcg_out_opc_andn(s, a0, a1, a2); 1302} 1303 1304static const TCGOutOpBinary outop_andc = { 1305 .base.static_constraint = C_O1_I2(r, r, r), 1306 .out_rrr = tgen_andc, 1307}; 1308 1309static void tgen_clzi(TCGContext *s, TCGType type, 1310 TCGReg a0, TCGReg a1, tcg_target_long a2) 1311{ 1312 /* a2 is constrained to exactly the type width. */ 1313 if (type == TCG_TYPE_I32) { 1314 tcg_out_opc_clz_w(s, a0, a1); 1315 } else { 1316 tcg_out_opc_clz_d(s, a0, a1); 1317 } 1318} 1319 1320static void tgen_clz(TCGContext *s, TCGType type, 1321 TCGReg a0, TCGReg a1, TCGReg a2) 1322{ 1323 tgen_clzi(s, type, TCG_REG_TMP0, a1, /* ignored */ 0); 1324 /* a0 = a1 ? REG_TMP0 : a2 */ 1325 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 1326 tcg_out_opc_masknez(s, a0, a2, a1); 1327 tcg_out_opc_or(s, a0, a0, TCG_REG_TMP0); 1328} 1329 1330static const TCGOutOpBinary outop_clz = { 1331 .base.static_constraint = C_O1_I2(r, r, rW), 1332 .out_rrr = tgen_clz, 1333 .out_rri = tgen_clzi, 1334}; 1335 1336static void tgen_ctzi(TCGContext *s, TCGType type, 1337 TCGReg a0, TCGReg a1, tcg_target_long a2) 1338{ 1339 /* a2 is constrained to exactly the type width. */ 1340 if (type == TCG_TYPE_I32) { 1341 tcg_out_opc_ctz_w(s, a0, a1); 1342 } else { 1343 tcg_out_opc_ctz_d(s, a0, a1); 1344 } 1345} 1346 1347static void tgen_ctz(TCGContext *s, TCGType type, 1348 TCGReg a0, TCGReg a1, TCGReg a2) 1349{ 1350 tgen_ctzi(s, type, TCG_REG_TMP0, a1, /* ignored */ 0); 1351 /* a0 = a1 ? REG_TMP0 : a2 */ 1352 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 1353 tcg_out_opc_masknez(s, a0, a2, a1); 1354 tcg_out_opc_or(s, a0, a0, TCG_REG_TMP0); 1355} 1356 1357static const TCGOutOpBinary outop_ctz = { 1358 .base.static_constraint = C_O1_I2(r, r, rW), 1359 .out_rrr = tgen_ctz, 1360 .out_rri = tgen_ctzi, 1361}; 1362 1363static void tgen_divs(TCGContext *s, TCGType type, 1364 TCGReg a0, TCGReg a1, TCGReg a2) 1365{ 1366 if (type == TCG_TYPE_I32) { 1367 tcg_out_opc_div_w(s, a0, a1, a2); 1368 } else { 1369 tcg_out_opc_div_d(s, a0, a1, a2); 1370 } 1371} 1372 1373static const TCGOutOpBinary outop_divs = { 1374 .base.static_constraint = C_O1_I2(r, r, r), 1375 .out_rrr = tgen_divs, 1376}; 1377 1378static const TCGOutOpDivRem outop_divs2 = { 1379 .base.static_constraint = C_NotImplemented, 1380}; 1381 1382static void tgen_divu(TCGContext *s, TCGType type, 1383 TCGReg a0, TCGReg a1, TCGReg a2) 1384{ 1385 if (type == TCG_TYPE_I32) { 1386 tcg_out_opc_div_wu(s, a0, a1, a2); 1387 } else { 1388 tcg_out_opc_div_du(s, a0, a1, a2); 1389 } 1390} 1391 1392static const TCGOutOpBinary outop_divu = { 1393 .base.static_constraint = C_O1_I2(r, r, r), 1394 .out_rrr = tgen_divu, 1395}; 1396 1397static const TCGOutOpDivRem outop_divu2 = { 1398 .base.static_constraint = C_NotImplemented, 1399}; 1400 1401static const TCGOutOpBinary outop_eqv = { 1402 .base.static_constraint = C_NotImplemented, 1403}; 1404 1405static void tgen_mul(TCGContext *s, TCGType type, 1406 TCGReg a0, TCGReg a1, TCGReg a2) 1407{ 1408 if (type == TCG_TYPE_I32) { 1409 tcg_out_opc_mul_w(s, a0, a1, a2); 1410 } else { 1411 tcg_out_opc_mul_d(s, a0, a1, a2); 1412 } 1413} 1414 1415static const TCGOutOpBinary outop_mul = { 1416 .base.static_constraint = C_O1_I2(r, r, r), 1417 .out_rrr = tgen_mul, 1418}; 1419 1420static void tgen_mulsh(TCGContext *s, TCGType type, 1421 TCGReg a0, TCGReg a1, TCGReg a2) 1422{ 1423 if (type == TCG_TYPE_I32) { 1424 tcg_out_opc_mulh_w(s, a0, a1, a2); 1425 } else { 1426 tcg_out_opc_mulh_d(s, a0, a1, a2); 1427 } 1428} 1429 1430static const TCGOutOpBinary outop_mulsh = { 1431 .base.static_constraint = C_O1_I2(r, r, r), 1432 .out_rrr = tgen_mulsh, 1433}; 1434 1435static void tgen_muluh(TCGContext *s, TCGType type, 1436 TCGReg a0, TCGReg a1, TCGReg a2) 1437{ 1438 if (type == TCG_TYPE_I32) { 1439 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1440 } else { 1441 tcg_out_opc_mulh_du(s, a0, a1, a2); 1442 } 1443} 1444 1445static const TCGOutOpBinary outop_muluh = { 1446 .base.static_constraint = C_O1_I2(r, r, r), 1447 .out_rrr = tgen_muluh, 1448}; 1449 1450static const TCGOutOpBinary outop_nand = { 1451 .base.static_constraint = C_NotImplemented, 1452}; 1453 1454static void tgen_nor(TCGContext *s, TCGType type, 1455 TCGReg a0, TCGReg a1, TCGReg a2) 1456{ 1457 tcg_out_opc_nor(s, a0, a1, a2); 1458} 1459 1460static const TCGOutOpBinary outop_nor = { 1461 .base.static_constraint = C_O1_I2(r, r, r), 1462 .out_rrr = tgen_nor, 1463}; 1464 1465static void tgen_or(TCGContext *s, TCGType type, 1466 TCGReg a0, TCGReg a1, TCGReg a2) 1467{ 1468 tcg_out_opc_or(s, a0, a1, a2); 1469} 1470 1471static void tgen_ori(TCGContext *s, TCGType type, 1472 TCGReg a0, TCGReg a1, tcg_target_long a2) 1473{ 1474 tcg_out_opc_ori(s, a0, a1, a2); 1475} 1476 1477static const TCGOutOpBinary outop_or = { 1478 .base.static_constraint = C_O1_I2(r, r, rU), 1479 .out_rrr = tgen_or, 1480 .out_rri = tgen_ori, 1481}; 1482 1483static void tgen_orc(TCGContext *s, TCGType type, 1484 TCGReg a0, TCGReg a1, TCGReg a2) 1485{ 1486 tcg_out_opc_orn(s, a0, a1, a2); 1487} 1488 1489static const TCGOutOpBinary outop_orc = { 1490 .base.static_constraint = C_O1_I2(r, r, r), 1491 .out_rrr = tgen_orc, 1492}; 1493 1494static void tgen_rems(TCGContext *s, TCGType type, 1495 TCGReg a0, TCGReg a1, TCGReg a2) 1496{ 1497 if (type == TCG_TYPE_I32) { 1498 tcg_out_opc_mod_w(s, a0, a1, a2); 1499 } else { 1500 tcg_out_opc_mod_d(s, a0, a1, a2); 1501 } 1502} 1503 1504static const TCGOutOpBinary outop_rems = { 1505 .base.static_constraint = C_O1_I2(r, r, r), 1506 .out_rrr = tgen_rems, 1507}; 1508 1509static void tgen_remu(TCGContext *s, TCGType type, 1510 TCGReg a0, TCGReg a1, TCGReg a2) 1511{ 1512 if (type == TCG_TYPE_I32) { 1513 tcg_out_opc_mod_wu(s, a0, a1, a2); 1514 } else { 1515 tcg_out_opc_mod_du(s, a0, a1, a2); 1516 } 1517} 1518 1519static const TCGOutOpBinary outop_remu = { 1520 .base.static_constraint = C_O1_I2(r, r, r), 1521 .out_rrr = tgen_remu, 1522}; 1523 1524static const TCGOutOpBinary outop_rotl = { 1525 .base.static_constraint = C_NotImplemented, 1526}; 1527 1528static void tgen_rotr(TCGContext *s, TCGType type, 1529 TCGReg a0, TCGReg a1, TCGReg a2) 1530{ 1531 if (type == TCG_TYPE_I32) { 1532 tcg_out_opc_rotr_w(s, a0, a1, a2); 1533 } else { 1534 tcg_out_opc_rotr_d(s, a0, a1, a2); 1535 } 1536} 1537 1538static void tgen_rotri(TCGContext *s, TCGType type, 1539 TCGReg a0, TCGReg a1, tcg_target_long a2) 1540{ 1541 if (type == TCG_TYPE_I32) { 1542 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1543 } else { 1544 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1545 } 1546} 1547 1548static const TCGOutOpBinary outop_rotr = { 1549 .base.static_constraint = C_O1_I2(r, r, ri), 1550 .out_rrr = tgen_rotr, 1551 .out_rri = tgen_rotri, 1552}; 1553 1554static void tgen_sar(TCGContext *s, TCGType type, 1555 TCGReg a0, TCGReg a1, TCGReg a2) 1556{ 1557 if (type == TCG_TYPE_I32) { 1558 tcg_out_opc_sra_w(s, a0, a1, a2); 1559 } else { 1560 tcg_out_opc_sra_d(s, a0, a1, a2); 1561 } 1562} 1563 1564static void tgen_sari(TCGContext *s, TCGType type, 1565 TCGReg a0, TCGReg a1, tcg_target_long a2) 1566{ 1567 if (type == TCG_TYPE_I32) { 1568 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1569 } else { 1570 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1571 } 1572} 1573 1574static const TCGOutOpBinary outop_sar = { 1575 .base.static_constraint = C_O1_I2(r, r, ri), 1576 .out_rrr = tgen_sar, 1577 .out_rri = tgen_sari, 1578}; 1579 1580static void tgen_shl(TCGContext *s, TCGType type, 1581 TCGReg a0, TCGReg a1, TCGReg a2) 1582{ 1583 if (type == TCG_TYPE_I32) { 1584 tcg_out_opc_sll_w(s, a0, a1, a2); 1585 } else { 1586 tcg_out_opc_sll_d(s, a0, a1, a2); 1587 } 1588} 1589 1590static void tgen_shli(TCGContext *s, TCGType type, 1591 TCGReg a0, TCGReg a1, tcg_target_long a2) 1592{ 1593 if (type == TCG_TYPE_I32) { 1594 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1595 } else { 1596 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1597 } 1598} 1599 1600static const TCGOutOpBinary outop_shl = { 1601 .base.static_constraint = C_O1_I2(r, r, ri), 1602 .out_rrr = tgen_shl, 1603 .out_rri = tgen_shli, 1604}; 1605 1606static void tgen_shr(TCGContext *s, TCGType type, 1607 TCGReg a0, TCGReg a1, TCGReg a2) 1608{ 1609 if (type == TCG_TYPE_I32) { 1610 tcg_out_opc_srl_w(s, a0, a1, a2); 1611 } else { 1612 tcg_out_opc_srl_d(s, a0, a1, a2); 1613 } 1614} 1615 1616static void tgen_shri(TCGContext *s, TCGType type, 1617 TCGReg a0, TCGReg a1, tcg_target_long a2) 1618{ 1619 if (type == TCG_TYPE_I32) { 1620 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1621 } else { 1622 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1623 } 1624} 1625 1626static const TCGOutOpBinary outop_shr = { 1627 .base.static_constraint = C_O1_I2(r, r, ri), 1628 .out_rrr = tgen_shr, 1629 .out_rri = tgen_shri, 1630}; 1631 1632static void tgen_sub(TCGContext *s, TCGType type, 1633 TCGReg a0, TCGReg a1, TCGReg a2) 1634{ 1635 if (type == TCG_TYPE_I32) { 1636 tcg_out_opc_sub_w(s, a0, a1, a2); 1637 } else { 1638 tcg_out_opc_sub_d(s, a0, a1, a2); 1639 } 1640} 1641 1642static const TCGOutOpSubtract outop_sub = { 1643 .base.static_constraint = C_O1_I2(r, r, r), 1644 .out_rrr = tgen_sub, 1645}; 1646 1647static void tgen_xor(TCGContext *s, TCGType type, 1648 TCGReg a0, TCGReg a1, TCGReg a2) 1649{ 1650 tcg_out_opc_xor(s, a0, a1, a2); 1651} 1652 1653static void tgen_xori(TCGContext *s, TCGType type, 1654 TCGReg a0, TCGReg a1, tcg_target_long a2) 1655{ 1656 tcg_out_opc_xori(s, a0, a1, a2); 1657} 1658 1659static const TCGOutOpBinary outop_xor = { 1660 .base.static_constraint = C_O1_I2(r, r, rU), 1661 .out_rrr = tgen_xor, 1662 .out_rri = tgen_xori, 1663}; 1664 1665static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1666{ 1667 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 1668} 1669 1670static const TCGOutOpUnary outop_neg = { 1671 .base.static_constraint = C_O1_I1(r, r), 1672 .out_rr = tgen_neg, 1673}; 1674 1675static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1676{ 1677 tgen_nor(s, type, a0, a1, TCG_REG_ZERO); 1678} 1679 1680static const TCGOutOpUnary outop_not = { 1681 .base.static_constraint = C_O1_I1(r, r), 1682 .out_rr = tgen_not, 1683}; 1684 1685 1686static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 1687 const TCGArg args[TCG_MAX_OP_ARGS], 1688 const int const_args[TCG_MAX_OP_ARGS]) 1689{ 1690 TCGArg a0 = args[0]; 1691 TCGArg a1 = args[1]; 1692 TCGArg a2 = args[2]; 1693 TCGArg a3 = args[3]; 1694 int c2 = const_args[2]; 1695 1696 switch (opc) { 1697 case INDEX_op_mb: 1698 tcg_out_mb(s, a0); 1699 break; 1700 1701 case INDEX_op_goto_ptr: 1702 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1703 break; 1704 1705 case INDEX_op_br: 1706 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), 1707 0); 1708 tcg_out_opc_b(s, 0); 1709 break; 1710 1711 case INDEX_op_brcond_i32: 1712 case INDEX_op_brcond_i64: 1713 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1714 break; 1715 1716 case INDEX_op_extrh_i64_i32: 1717 tcg_out_opc_srai_d(s, a0, a1, 32); 1718 break; 1719 1720 case INDEX_op_extract_i32: 1721 if (a2 == 0 && args[3] <= 12) { 1722 tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1); 1723 } else { 1724 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); 1725 } 1726 break; 1727 case INDEX_op_extract_i64: 1728 if (a2 == 0 && args[3] <= 12) { 1729 tcg_out_opc_andi(s, a0, a1, (1 << args[3]) - 1); 1730 } else { 1731 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); 1732 } 1733 break; 1734 1735 case INDEX_op_sextract_i64: 1736 if (a2 + args[3] == 32) { 1737 if (a2 == 0) { 1738 tcg_out_ext32s(s, a0, a1); 1739 } else { 1740 tcg_out_opc_srai_w(s, a0, a1, a2); 1741 } 1742 break; 1743 } 1744 /* FALLTHRU */ 1745 case INDEX_op_sextract_i32: 1746 if (a2 == 0 && args[3] == 8) { 1747 tcg_out_ext8s(s, TCG_TYPE_REG, a0, a1); 1748 } else if (a2 == 0 && args[3] == 16) { 1749 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a1); 1750 } else { 1751 g_assert_not_reached(); 1752 } 1753 break; 1754 1755 case INDEX_op_deposit_i32: 1756 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); 1757 break; 1758 case INDEX_op_deposit_i64: 1759 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); 1760 break; 1761 1762 case INDEX_op_bswap16_i32: 1763 case INDEX_op_bswap16_i64: 1764 tcg_out_opc_revb_2h(s, a0, a1); 1765 if (a2 & TCG_BSWAP_OS) { 1766 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); 1767 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1768 tcg_out_ext16u(s, a0, a0); 1769 } 1770 break; 1771 1772 case INDEX_op_bswap32_i32: 1773 /* All 32-bit values are computed sign-extended in the register. */ 1774 a2 = TCG_BSWAP_OS; 1775 /* fallthrough */ 1776 case INDEX_op_bswap32_i64: 1777 tcg_out_opc_revb_2w(s, a0, a1); 1778 if (a2 & TCG_BSWAP_OS) { 1779 tcg_out_ext32s(s, a0, a0); 1780 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1781 tcg_out_ext32u(s, a0, a0); 1782 } 1783 break; 1784 1785 case INDEX_op_bswap64_i64: 1786 tcg_out_opc_revb_d(s, a0, a1); 1787 break; 1788 1789 case INDEX_op_setcond_i32: 1790 case INDEX_op_setcond_i64: 1791 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 1792 break; 1793 1794 case INDEX_op_movcond_i32: 1795 case INDEX_op_movcond_i64: 1796 tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]); 1797 break; 1798 1799 case INDEX_op_ld8s_i32: 1800 case INDEX_op_ld8s_i64: 1801 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); 1802 break; 1803 case INDEX_op_ld8u_i32: 1804 case INDEX_op_ld8u_i64: 1805 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); 1806 break; 1807 case INDEX_op_ld16s_i32: 1808 case INDEX_op_ld16s_i64: 1809 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); 1810 break; 1811 case INDEX_op_ld16u_i32: 1812 case INDEX_op_ld16u_i64: 1813 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); 1814 break; 1815 case INDEX_op_ld_i32: 1816 case INDEX_op_ld32s_i64: 1817 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); 1818 break; 1819 case INDEX_op_ld32u_i64: 1820 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); 1821 break; 1822 case INDEX_op_ld_i64: 1823 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); 1824 break; 1825 1826 case INDEX_op_st8_i32: 1827 case INDEX_op_st8_i64: 1828 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); 1829 break; 1830 case INDEX_op_st16_i32: 1831 case INDEX_op_st16_i64: 1832 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); 1833 break; 1834 case INDEX_op_st_i32: 1835 case INDEX_op_st32_i64: 1836 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); 1837 break; 1838 case INDEX_op_st_i64: 1839 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); 1840 break; 1841 1842 case INDEX_op_qemu_ld_i32: 1843 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1844 break; 1845 case INDEX_op_qemu_ld_i64: 1846 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1847 break; 1848 case INDEX_op_qemu_ld_i128: 1849 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true); 1850 break; 1851 case INDEX_op_qemu_st_i32: 1852 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1853 break; 1854 case INDEX_op_qemu_st_i64: 1855 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1856 break; 1857 case INDEX_op_qemu_st_i128: 1858 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false); 1859 break; 1860 1861 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1862 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1863 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1864 case INDEX_op_ext_i32_i64: /* Always emitted via tcg_reg_alloc_op. */ 1865 case INDEX_op_extu_i32_i64: 1866 case INDEX_op_extrl_i64_i32: 1867 default: 1868 g_assert_not_reached(); 1869 } 1870} 1871 1872static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1873 TCGReg rd, TCGReg rs) 1874{ 1875 static const LoongArchInsn repl_insn[2][4] = { 1876 { OPC_VREPLGR2VR_B, OPC_VREPLGR2VR_H, 1877 OPC_VREPLGR2VR_W, OPC_VREPLGR2VR_D }, 1878 { OPC_XVREPLGR2VR_B, OPC_XVREPLGR2VR_H, 1879 OPC_XVREPLGR2VR_W, OPC_XVREPLGR2VR_D }, 1880 }; 1881 bool lasx = type == TCG_TYPE_V256; 1882 1883 tcg_debug_assert(vece <= MO_64); 1884 tcg_out32(s, encode_vdj_insn(repl_insn[lasx][vece], rd, rs)); 1885 return true; 1886} 1887 1888static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1889 TCGReg r, TCGReg base, intptr_t offset) 1890{ 1891 bool lasx = type == TCG_TYPE_V256; 1892 1893 /* Handle imm overflow and division (vldrepl.d imm is divided by 8). */ 1894 if (offset < -0x800 || offset > 0x7ff || 1895 (offset & ((1 << vece) - 1)) != 0) { 1896 tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset); 1897 base = TCG_REG_TMP0; 1898 offset = 0; 1899 } 1900 offset >>= vece; 1901 1902 switch (vece) { 1903 case MO_8: 1904 if (lasx) { 1905 tcg_out_opc_xvldrepl_b(s, r, base, offset); 1906 } else { 1907 tcg_out_opc_vldrepl_b(s, r, base, offset); 1908 } 1909 break; 1910 case MO_16: 1911 if (lasx) { 1912 tcg_out_opc_xvldrepl_h(s, r, base, offset); 1913 } else { 1914 tcg_out_opc_vldrepl_h(s, r, base, offset); 1915 } 1916 break; 1917 case MO_32: 1918 if (lasx) { 1919 tcg_out_opc_xvldrepl_w(s, r, base, offset); 1920 } else { 1921 tcg_out_opc_vldrepl_w(s, r, base, offset); 1922 } 1923 break; 1924 case MO_64: 1925 if (lasx) { 1926 tcg_out_opc_xvldrepl_d(s, r, base, offset); 1927 } else { 1928 tcg_out_opc_vldrepl_d(s, r, base, offset); 1929 } 1930 break; 1931 default: 1932 g_assert_not_reached(); 1933 } 1934 return true; 1935} 1936 1937static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1938 TCGReg rd, int64_t v64) 1939{ 1940 /* Try vldi if imm can fit */ 1941 int64_t value = sextract64(v64, 0, 8 << vece); 1942 if (-0x200 <= value && value <= 0x1FF) { 1943 uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF); 1944 1945 if (type == TCG_TYPE_V256) { 1946 tcg_out_opc_xvldi(s, rd, imm); 1947 } else { 1948 tcg_out_opc_vldi(s, rd, imm); 1949 } 1950 return; 1951 } 1952 1953 /* TODO: vldi patterns when imm 12 is set */ 1954 1955 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value); 1956 tcg_out_dup_vec(s, type, vece, rd, TCG_REG_TMP0); 1957} 1958 1959static void tcg_out_addsub_vec(TCGContext *s, bool lasx, unsigned vece, 1960 TCGArg a0, TCGArg a1, TCGArg a2, 1961 bool a2_is_const, bool is_add) 1962{ 1963 static const LoongArchInsn add_vec_insn[2][4] = { 1964 { OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D }, 1965 { OPC_XVADD_B, OPC_XVADD_H, OPC_XVADD_W, OPC_XVADD_D }, 1966 }; 1967 static const LoongArchInsn add_vec_imm_insn[2][4] = { 1968 { OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU }, 1969 { OPC_XVADDI_BU, OPC_XVADDI_HU, OPC_XVADDI_WU, OPC_XVADDI_DU }, 1970 }; 1971 static const LoongArchInsn sub_vec_insn[2][4] = { 1972 { OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D }, 1973 { OPC_XVSUB_B, OPC_XVSUB_H, OPC_XVSUB_W, OPC_XVSUB_D }, 1974 }; 1975 static const LoongArchInsn sub_vec_imm_insn[2][4] = { 1976 { OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU }, 1977 { OPC_XVSUBI_BU, OPC_XVSUBI_HU, OPC_XVSUBI_WU, OPC_XVSUBI_DU }, 1978 }; 1979 LoongArchInsn insn; 1980 1981 if (a2_is_const) { 1982 int64_t value = sextract64(a2, 0, 8 << vece); 1983 1984 if (!is_add) { 1985 value = -value; 1986 } 1987 if (value < 0) { 1988 insn = sub_vec_imm_insn[lasx][vece]; 1989 value = -value; 1990 } else { 1991 insn = add_vec_imm_insn[lasx][vece]; 1992 } 1993 1994 /* Constraint TCG_CT_CONST_VADD ensures validity. */ 1995 tcg_debug_assert(0 <= value && value <= 0x1f); 1996 1997 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, value)); 1998 return; 1999 } 2000 2001 if (is_add) { 2002 insn = add_vec_insn[lasx][vece]; 2003 } else { 2004 insn = sub_vec_insn[lasx][vece]; 2005 } 2006 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 2007} 2008 2009static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2010 unsigned vecl, unsigned vece, 2011 const TCGArg args[TCG_MAX_OP_ARGS], 2012 const int const_args[TCG_MAX_OP_ARGS]) 2013{ 2014 TCGType type = vecl + TCG_TYPE_V64; 2015 bool lasx = type == TCG_TYPE_V256; 2016 TCGArg a0, a1, a2, a3; 2017 LoongArchInsn insn; 2018 2019 static const LoongArchInsn cmp_vec_insn[16][2][4] = { 2020 [TCG_COND_EQ] = { 2021 { OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D }, 2022 { OPC_XVSEQ_B, OPC_XVSEQ_H, OPC_XVSEQ_W, OPC_XVSEQ_D }, 2023 }, 2024 [TCG_COND_LE] = { 2025 { OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D }, 2026 { OPC_XVSLE_B, OPC_XVSLE_H, OPC_XVSLE_W, OPC_XVSLE_D }, 2027 }, 2028 [TCG_COND_LEU] = { 2029 { OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU }, 2030 { OPC_XVSLE_BU, OPC_XVSLE_HU, OPC_XVSLE_WU, OPC_XVSLE_DU }, 2031 }, 2032 [TCG_COND_LT] = { 2033 { OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D }, 2034 { OPC_XVSLT_B, OPC_XVSLT_H, OPC_XVSLT_W, OPC_XVSLT_D }, 2035 }, 2036 [TCG_COND_LTU] = { 2037 { OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU }, 2038 { OPC_XVSLT_BU, OPC_XVSLT_HU, OPC_XVSLT_WU, OPC_XVSLT_DU }, 2039 } 2040 }; 2041 static const LoongArchInsn cmp_vec_imm_insn[16][2][4] = { 2042 [TCG_COND_EQ] = { 2043 { OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D }, 2044 { OPC_XVSEQI_B, OPC_XVSEQI_H, OPC_XVSEQI_W, OPC_XVSEQI_D }, 2045 }, 2046 [TCG_COND_LE] = { 2047 { OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D }, 2048 { OPC_XVSLEI_B, OPC_XVSLEI_H, OPC_XVSLEI_W, OPC_XVSLEI_D }, 2049 }, 2050 [TCG_COND_LEU] = { 2051 { OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU }, 2052 { OPC_XVSLEI_BU, OPC_XVSLEI_HU, OPC_XVSLEI_WU, OPC_XVSLEI_DU }, 2053 }, 2054 [TCG_COND_LT] = { 2055 { OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D }, 2056 { OPC_XVSLTI_B, OPC_XVSLTI_H, OPC_XVSLTI_W, OPC_XVSLTI_D }, 2057 }, 2058 [TCG_COND_LTU] = { 2059 { OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU }, 2060 { OPC_XVSLTI_BU, OPC_XVSLTI_HU, OPC_XVSLTI_WU, OPC_XVSLTI_DU }, 2061 } 2062 }; 2063 static const LoongArchInsn neg_vec_insn[2][4] = { 2064 { OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D }, 2065 { OPC_XVNEG_B, OPC_XVNEG_H, OPC_XVNEG_W, OPC_XVNEG_D }, 2066 }; 2067 static const LoongArchInsn mul_vec_insn[2][4] = { 2068 { OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D }, 2069 { OPC_XVMUL_B, OPC_XVMUL_H, OPC_XVMUL_W, OPC_XVMUL_D }, 2070 }; 2071 static const LoongArchInsn smin_vec_insn[2][4] = { 2072 { OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D }, 2073 { OPC_XVMIN_B, OPC_XVMIN_H, OPC_XVMIN_W, OPC_XVMIN_D }, 2074 }; 2075 static const LoongArchInsn umin_vec_insn[2][4] = { 2076 { OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU }, 2077 { OPC_XVMIN_BU, OPC_XVMIN_HU, OPC_XVMIN_WU, OPC_XVMIN_DU }, 2078 }; 2079 static const LoongArchInsn smax_vec_insn[2][4] = { 2080 { OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D }, 2081 { OPC_XVMAX_B, OPC_XVMAX_H, OPC_XVMAX_W, OPC_XVMAX_D }, 2082 }; 2083 static const LoongArchInsn umax_vec_insn[2][4] = { 2084 { OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU }, 2085 { OPC_XVMAX_BU, OPC_XVMAX_HU, OPC_XVMAX_WU, OPC_XVMAX_DU }, 2086 }; 2087 static const LoongArchInsn ssadd_vec_insn[2][4] = { 2088 { OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D }, 2089 { OPC_XVSADD_B, OPC_XVSADD_H, OPC_XVSADD_W, OPC_XVSADD_D }, 2090 }; 2091 static const LoongArchInsn usadd_vec_insn[2][4] = { 2092 { OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU }, 2093 { OPC_XVSADD_BU, OPC_XVSADD_HU, OPC_XVSADD_WU, OPC_XVSADD_DU }, 2094 }; 2095 static const LoongArchInsn sssub_vec_insn[2][4] = { 2096 { OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D }, 2097 { OPC_XVSSUB_B, OPC_XVSSUB_H, OPC_XVSSUB_W, OPC_XVSSUB_D }, 2098 }; 2099 static const LoongArchInsn ussub_vec_insn[2][4] = { 2100 { OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU }, 2101 { OPC_XVSSUB_BU, OPC_XVSSUB_HU, OPC_XVSSUB_WU, OPC_XVSSUB_DU }, 2102 }; 2103 static const LoongArchInsn shlv_vec_insn[2][4] = { 2104 { OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D }, 2105 { OPC_XVSLL_B, OPC_XVSLL_H, OPC_XVSLL_W, OPC_XVSLL_D }, 2106 }; 2107 static const LoongArchInsn shrv_vec_insn[2][4] = { 2108 { OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D }, 2109 { OPC_XVSRL_B, OPC_XVSRL_H, OPC_XVSRL_W, OPC_XVSRL_D }, 2110 }; 2111 static const LoongArchInsn sarv_vec_insn[2][4] = { 2112 { OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D }, 2113 { OPC_XVSRA_B, OPC_XVSRA_H, OPC_XVSRA_W, OPC_XVSRA_D }, 2114 }; 2115 static const LoongArchInsn shli_vec_insn[2][4] = { 2116 { OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D }, 2117 { OPC_XVSLLI_B, OPC_XVSLLI_H, OPC_XVSLLI_W, OPC_XVSLLI_D }, 2118 }; 2119 static const LoongArchInsn shri_vec_insn[2][4] = { 2120 { OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D }, 2121 { OPC_XVSRLI_B, OPC_XVSRLI_H, OPC_XVSRLI_W, OPC_XVSRLI_D }, 2122 }; 2123 static const LoongArchInsn sari_vec_insn[2][4] = { 2124 { OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D }, 2125 { OPC_XVSRAI_B, OPC_XVSRAI_H, OPC_XVSRAI_W, OPC_XVSRAI_D }, 2126 }; 2127 static const LoongArchInsn rotrv_vec_insn[2][4] = { 2128 { OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D }, 2129 { OPC_XVROTR_B, OPC_XVROTR_H, OPC_XVROTR_W, OPC_XVROTR_D }, 2130 }; 2131 static const LoongArchInsn rotri_vec_insn[2][4] = { 2132 { OPC_VROTRI_B, OPC_VROTRI_H, OPC_VROTRI_W, OPC_VROTRI_D }, 2133 { OPC_XVROTRI_B, OPC_XVROTRI_H, OPC_XVROTRI_W, OPC_XVROTRI_D }, 2134 }; 2135 2136 a0 = args[0]; 2137 a1 = args[1]; 2138 a2 = args[2]; 2139 a3 = args[3]; 2140 2141 switch (opc) { 2142 case INDEX_op_st_vec: 2143 tcg_out_st(s, type, a0, a1, a2); 2144 break; 2145 case INDEX_op_ld_vec: 2146 tcg_out_ld(s, type, a0, a1, a2); 2147 break; 2148 case INDEX_op_and_vec: 2149 insn = lasx ? OPC_XVAND_V : OPC_VAND_V; 2150 goto vdvjvk; 2151 case INDEX_op_andc_vec: 2152 /* 2153 * vandn vd, vj, vk: vd = vk & ~vj 2154 * andc_vec vd, vj, vk: vd = vj & ~vk 2155 * vj and vk are swapped 2156 */ 2157 a1 = a2; 2158 a2 = args[1]; 2159 insn = lasx ? OPC_XVANDN_V : OPC_VANDN_V; 2160 goto vdvjvk; 2161 case INDEX_op_or_vec: 2162 insn = lasx ? OPC_XVOR_V : OPC_VOR_V; 2163 goto vdvjvk; 2164 case INDEX_op_orc_vec: 2165 insn = lasx ? OPC_XVORN_V : OPC_VORN_V; 2166 goto vdvjvk; 2167 case INDEX_op_xor_vec: 2168 insn = lasx ? OPC_XVXOR_V : OPC_VXOR_V; 2169 goto vdvjvk; 2170 case INDEX_op_not_vec: 2171 a2 = a1; 2172 /* fall through */ 2173 case INDEX_op_nor_vec: 2174 insn = lasx ? OPC_XVNOR_V : OPC_VNOR_V; 2175 goto vdvjvk; 2176 case INDEX_op_cmp_vec: 2177 { 2178 TCGCond cond = args[3]; 2179 2180 if (const_args[2]) { 2181 /* 2182 * cmp_vec dest, src, value 2183 * Try vseqi/vslei/vslti 2184 */ 2185 int64_t value = sextract64(a2, 0, 8 << vece); 2186 switch (cond) { 2187 case TCG_COND_EQ: 2188 case TCG_COND_LE: 2189 case TCG_COND_LT: 2190 insn = cmp_vec_imm_insn[cond][lasx][vece]; 2191 tcg_out32(s, encode_vdvjsk5_insn(insn, a0, a1, value)); 2192 break; 2193 case TCG_COND_LEU: 2194 case TCG_COND_LTU: 2195 insn = cmp_vec_imm_insn[cond][lasx][vece]; 2196 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, value)); 2197 break; 2198 default: 2199 g_assert_not_reached(); 2200 } 2201 break; 2202 } 2203 2204 insn = cmp_vec_insn[cond][lasx][vece]; 2205 if (insn == 0) { 2206 TCGArg t; 2207 t = a1, a1 = a2, a2 = t; 2208 cond = tcg_swap_cond(cond); 2209 insn = cmp_vec_insn[cond][lasx][vece]; 2210 tcg_debug_assert(insn != 0); 2211 } 2212 } 2213 goto vdvjvk; 2214 case INDEX_op_add_vec: 2215 tcg_out_addsub_vec(s, lasx, vece, a0, a1, a2, const_args[2], true); 2216 break; 2217 case INDEX_op_sub_vec: 2218 tcg_out_addsub_vec(s, lasx, vece, a0, a1, a2, const_args[2], false); 2219 break; 2220 case INDEX_op_neg_vec: 2221 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[lasx][vece], a0, a1)); 2222 break; 2223 case INDEX_op_mul_vec: 2224 insn = mul_vec_insn[lasx][vece]; 2225 goto vdvjvk; 2226 case INDEX_op_smin_vec: 2227 insn = smin_vec_insn[lasx][vece]; 2228 goto vdvjvk; 2229 case INDEX_op_smax_vec: 2230 insn = smax_vec_insn[lasx][vece]; 2231 goto vdvjvk; 2232 case INDEX_op_umin_vec: 2233 insn = umin_vec_insn[lasx][vece]; 2234 goto vdvjvk; 2235 case INDEX_op_umax_vec: 2236 insn = umax_vec_insn[lasx][vece]; 2237 goto vdvjvk; 2238 case INDEX_op_ssadd_vec: 2239 insn = ssadd_vec_insn[lasx][vece]; 2240 goto vdvjvk; 2241 case INDEX_op_usadd_vec: 2242 insn = usadd_vec_insn[lasx][vece]; 2243 goto vdvjvk; 2244 case INDEX_op_sssub_vec: 2245 insn = sssub_vec_insn[lasx][vece]; 2246 goto vdvjvk; 2247 case INDEX_op_ussub_vec: 2248 insn = ussub_vec_insn[lasx][vece]; 2249 goto vdvjvk; 2250 case INDEX_op_shlv_vec: 2251 insn = shlv_vec_insn[lasx][vece]; 2252 goto vdvjvk; 2253 case INDEX_op_shrv_vec: 2254 insn = shrv_vec_insn[lasx][vece]; 2255 goto vdvjvk; 2256 case INDEX_op_sarv_vec: 2257 insn = sarv_vec_insn[lasx][vece]; 2258 goto vdvjvk; 2259 case INDEX_op_rotlv_vec: 2260 /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */ 2261 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[lasx][vece], 2262 TCG_VEC_TMP0, a2)); 2263 a2 = TCG_VEC_TMP0; 2264 /* fall through */ 2265 case INDEX_op_rotrv_vec: 2266 insn = rotrv_vec_insn[lasx][vece]; 2267 goto vdvjvk; 2268 case INDEX_op_shli_vec: 2269 insn = shli_vec_insn[lasx][vece]; 2270 goto vdvjukN; 2271 case INDEX_op_shri_vec: 2272 insn = shri_vec_insn[lasx][vece]; 2273 goto vdvjukN; 2274 case INDEX_op_sari_vec: 2275 insn = sari_vec_insn[lasx][vece]; 2276 goto vdvjukN; 2277 case INDEX_op_rotli_vec: 2278 /* rotli_vec a1, a2 = rotri_vec a1, -a2 */ 2279 a2 = extract32(-a2, 0, 3 + vece); 2280 insn = rotri_vec_insn[lasx][vece]; 2281 goto vdvjukN; 2282 case INDEX_op_bitsel_vec: 2283 /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */ 2284 if (lasx) { 2285 tcg_out_opc_xvbitsel_v(s, a0, a3, a2, a1); 2286 } else { 2287 tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1); 2288 } 2289 break; 2290 case INDEX_op_dupm_vec: 2291 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2292 break; 2293 default: 2294 g_assert_not_reached(); 2295 vdvjvk: 2296 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 2297 break; 2298 vdvjukN: 2299 switch (vece) { 2300 case MO_8: 2301 tcg_out32(s, encode_vdvjuk3_insn(insn, a0, a1, a2)); 2302 break; 2303 case MO_16: 2304 tcg_out32(s, encode_vdvjuk4_insn(insn, a0, a1, a2)); 2305 break; 2306 case MO_32: 2307 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, a2)); 2308 break; 2309 case MO_64: 2310 tcg_out32(s, encode_vdvjuk6_insn(insn, a0, a1, a2)); 2311 break; 2312 default: 2313 g_assert_not_reached(); 2314 } 2315 break; 2316 } 2317} 2318 2319int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2320{ 2321 switch (opc) { 2322 case INDEX_op_ld_vec: 2323 case INDEX_op_st_vec: 2324 case INDEX_op_dup_vec: 2325 case INDEX_op_dupm_vec: 2326 case INDEX_op_cmp_vec: 2327 case INDEX_op_add_vec: 2328 case INDEX_op_sub_vec: 2329 case INDEX_op_and_vec: 2330 case INDEX_op_andc_vec: 2331 case INDEX_op_or_vec: 2332 case INDEX_op_orc_vec: 2333 case INDEX_op_xor_vec: 2334 case INDEX_op_nor_vec: 2335 case INDEX_op_not_vec: 2336 case INDEX_op_neg_vec: 2337 case INDEX_op_mul_vec: 2338 case INDEX_op_smin_vec: 2339 case INDEX_op_smax_vec: 2340 case INDEX_op_umin_vec: 2341 case INDEX_op_umax_vec: 2342 case INDEX_op_ssadd_vec: 2343 case INDEX_op_usadd_vec: 2344 case INDEX_op_sssub_vec: 2345 case INDEX_op_ussub_vec: 2346 case INDEX_op_shlv_vec: 2347 case INDEX_op_shrv_vec: 2348 case INDEX_op_sarv_vec: 2349 case INDEX_op_bitsel_vec: 2350 return 1; 2351 default: 2352 return 0; 2353 } 2354} 2355 2356void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2357 TCGArg a0, ...) 2358{ 2359 g_assert_not_reached(); 2360} 2361 2362static TCGConstraintSetIndex 2363tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2364{ 2365 switch (op) { 2366 case INDEX_op_goto_ptr: 2367 return C_O0_I1(r); 2368 2369 case INDEX_op_st8_i32: 2370 case INDEX_op_st8_i64: 2371 case INDEX_op_st16_i32: 2372 case INDEX_op_st16_i64: 2373 case INDEX_op_st32_i64: 2374 case INDEX_op_st_i32: 2375 case INDEX_op_st_i64: 2376 case INDEX_op_qemu_st_i32: 2377 case INDEX_op_qemu_st_i64: 2378 return C_O0_I2(rz, r); 2379 2380 case INDEX_op_qemu_ld_i128: 2381 return C_N2_I1(r, r, r); 2382 2383 case INDEX_op_qemu_st_i128: 2384 return C_O0_I3(r, r, r); 2385 2386 case INDEX_op_brcond_i32: 2387 case INDEX_op_brcond_i64: 2388 return C_O0_I2(rz, rz); 2389 2390 case INDEX_op_extu_i32_i64: 2391 case INDEX_op_extrl_i64_i32: 2392 case INDEX_op_extrh_i64_i32: 2393 case INDEX_op_ext_i32_i64: 2394 case INDEX_op_extract_i32: 2395 case INDEX_op_extract_i64: 2396 case INDEX_op_sextract_i32: 2397 case INDEX_op_sextract_i64: 2398 case INDEX_op_bswap16_i32: 2399 case INDEX_op_bswap16_i64: 2400 case INDEX_op_bswap32_i32: 2401 case INDEX_op_bswap32_i64: 2402 case INDEX_op_bswap64_i64: 2403 case INDEX_op_ld8s_i32: 2404 case INDEX_op_ld8s_i64: 2405 case INDEX_op_ld8u_i32: 2406 case INDEX_op_ld8u_i64: 2407 case INDEX_op_ld16s_i32: 2408 case INDEX_op_ld16s_i64: 2409 case INDEX_op_ld16u_i32: 2410 case INDEX_op_ld16u_i64: 2411 case INDEX_op_ld32s_i64: 2412 case INDEX_op_ld32u_i64: 2413 case INDEX_op_ld_i32: 2414 case INDEX_op_ld_i64: 2415 case INDEX_op_qemu_ld_i32: 2416 case INDEX_op_qemu_ld_i64: 2417 return C_O1_I1(r, r); 2418 2419 case INDEX_op_deposit_i32: 2420 case INDEX_op_deposit_i64: 2421 /* Must deposit into the same register as input */ 2422 return C_O1_I2(r, 0, rz); 2423 2424 case INDEX_op_setcond_i32: 2425 return C_O1_I2(r, rz, ri); 2426 case INDEX_op_setcond_i64: 2427 return C_O1_I2(r, rz, rJ); 2428 2429 case INDEX_op_movcond_i32: 2430 case INDEX_op_movcond_i64: 2431 return C_O1_I4(r, rz, rJ, rz, rz); 2432 2433 case INDEX_op_ld_vec: 2434 case INDEX_op_dupm_vec: 2435 case INDEX_op_dup_vec: 2436 return C_O1_I1(w, r); 2437 2438 case INDEX_op_st_vec: 2439 return C_O0_I2(w, r); 2440 2441 case INDEX_op_cmp_vec: 2442 return C_O1_I2(w, w, wM); 2443 2444 case INDEX_op_add_vec: 2445 case INDEX_op_sub_vec: 2446 return C_O1_I2(w, w, wA); 2447 2448 case INDEX_op_and_vec: 2449 case INDEX_op_andc_vec: 2450 case INDEX_op_or_vec: 2451 case INDEX_op_orc_vec: 2452 case INDEX_op_xor_vec: 2453 case INDEX_op_nor_vec: 2454 case INDEX_op_mul_vec: 2455 case INDEX_op_smin_vec: 2456 case INDEX_op_smax_vec: 2457 case INDEX_op_umin_vec: 2458 case INDEX_op_umax_vec: 2459 case INDEX_op_ssadd_vec: 2460 case INDEX_op_usadd_vec: 2461 case INDEX_op_sssub_vec: 2462 case INDEX_op_ussub_vec: 2463 case INDEX_op_shlv_vec: 2464 case INDEX_op_shrv_vec: 2465 case INDEX_op_sarv_vec: 2466 case INDEX_op_rotrv_vec: 2467 case INDEX_op_rotlv_vec: 2468 return C_O1_I2(w, w, w); 2469 2470 case INDEX_op_not_vec: 2471 case INDEX_op_neg_vec: 2472 case INDEX_op_shli_vec: 2473 case INDEX_op_shri_vec: 2474 case INDEX_op_sari_vec: 2475 case INDEX_op_rotli_vec: 2476 return C_O1_I1(w, w); 2477 2478 case INDEX_op_bitsel_vec: 2479 return C_O1_I3(w, w, w, w); 2480 2481 default: 2482 return C_NotImplemented; 2483 } 2484} 2485 2486static const int tcg_target_callee_save_regs[] = { 2487 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2488 TCG_REG_S1, 2489 TCG_REG_S2, 2490 TCG_REG_S3, 2491 TCG_REG_S4, 2492 TCG_REG_S5, 2493 TCG_REG_S6, 2494 TCG_REG_S7, 2495 TCG_REG_S8, 2496 TCG_REG_S9, 2497 TCG_REG_RA, /* should be last for ABI compliance */ 2498}; 2499 2500/* Stack frame parameters. */ 2501#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2502#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2503#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2504#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2505 + TCG_TARGET_STACK_ALIGN - 1) \ 2506 & -TCG_TARGET_STACK_ALIGN) 2507#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2508 2509/* We're expecting to be able to use an immediate for frame allocation. */ 2510QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2511 2512/* Generate global QEMU prologue and epilogue code */ 2513static void tcg_target_qemu_prologue(TCGContext *s) 2514{ 2515 int i; 2516 2517 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2518 2519 /* TB prologue */ 2520 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2521 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2522 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2523 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2524 } 2525 2526 if (!tcg_use_softmmu && guest_base) { 2527 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2528 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2529 } 2530 2531 /* Call generated code */ 2532 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2533 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2534 2535 /* Return path for goto_ptr. Set return value to 0 */ 2536 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2537 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2538 2539 /* TB epilogue */ 2540 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2541 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2542 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2543 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2544 } 2545 2546 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2547 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 2548} 2549 2550static void tcg_out_tb_start(TCGContext *s) 2551{ 2552 /* nothing to do */ 2553} 2554 2555static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2556{ 2557 for (int i = 0; i < count; ++i) { 2558 /* Canonical nop is andi r0,r0,0 */ 2559 p[i] = OPC_ANDI; 2560 } 2561} 2562 2563static void tcg_target_init(TCGContext *s) 2564{ 2565 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2566 2567 /* Server and desktop class cpus have UAL; embedded cpus do not. */ 2568 if (!(hwcap & HWCAP_LOONGARCH_UAL)) { 2569 error_report("TCG: unaligned access support required; exiting"); 2570 exit(EXIT_FAILURE); 2571 } 2572 2573 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2574 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 2575 2576 tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; 2577 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2578 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2579 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2580 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2581 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2582 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2583 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2584 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2585 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2586 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2587 2588 if (cpuinfo & CPUINFO_LSX) { 2589 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2590 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2591 if (cpuinfo & CPUINFO_LASX) { 2592 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 2593 } 2594 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 2595 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 2596 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 2597 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 2598 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 2599 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 2600 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 2601 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 2602 } 2603 2604 s->reserved_regs = 0; 2605 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2606 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2607 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2608 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2609 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2610 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2611 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 2612 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 2613} 2614 2615typedef struct { 2616 DebugFrameHeader h; 2617 uint8_t fde_def_cfa[4]; 2618 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2619} DebugFrame; 2620 2621#define ELF_HOST_MACHINE EM_LOONGARCH 2622 2623static const DebugFrame debug_frame = { 2624 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2625 .h.cie.id = -1, 2626 .h.cie.version = 1, 2627 .h.cie.code_align = 1, 2628 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2629 .h.cie.return_column = TCG_REG_RA, 2630 2631 /* Total FDE size does not include the "len" member. */ 2632 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2633 2634 .fde_def_cfa = { 2635 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2636 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2637 (FRAME_SIZE >> 7) 2638 }, 2639 .fde_reg_ofs = { 2640 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 2641 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 2642 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 2643 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 2644 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 2645 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 2646 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 2647 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 2648 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 2649 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 2650 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 2651 } 2652}; 2653 2654void tcg_register_jit(const void *buf, size_t buf_size) 2655{ 2656 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2657} 2658