1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include "../tcg-ldst.c.inc" 33#include <asm/hwcap.h> 34 35#ifdef CONFIG_DEBUG_TCG 36static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 37 "zero", 38 "ra", 39 "tp", 40 "sp", 41 "a0", 42 "a1", 43 "a2", 44 "a3", 45 "a4", 46 "a5", 47 "a6", 48 "a7", 49 "t0", 50 "t1", 51 "t2", 52 "t3", 53 "t4", 54 "t5", 55 "t6", 56 "t7", 57 "t8", 58 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 59 "s9", 60 "s0", 61 "s1", 62 "s2", 63 "s3", 64 "s4", 65 "s5", 66 "s6", 67 "s7", 68 "s8", 69 "vr0", 70 "vr1", 71 "vr2", 72 "vr3", 73 "vr4", 74 "vr5", 75 "vr6", 76 "vr7", 77 "vr8", 78 "vr9", 79 "vr10", 80 "vr11", 81 "vr12", 82 "vr13", 83 "vr14", 84 "vr15", 85 "vr16", 86 "vr17", 87 "vr18", 88 "vr19", 89 "vr20", 90 "vr21", 91 "vr22", 92 "vr23", 93 "vr24", 94 "vr25", 95 "vr26", 96 "vr27", 97 "vr28", 98 "vr29", 99 "vr30", 100 "vr31", 101}; 102#endif 103 104static const int tcg_target_reg_alloc_order[] = { 105 /* Registers preserved across calls */ 106 /* TCG_REG_S0 reserved for TCG_AREG0 */ 107 TCG_REG_S1, 108 TCG_REG_S2, 109 TCG_REG_S3, 110 TCG_REG_S4, 111 TCG_REG_S5, 112 TCG_REG_S6, 113 TCG_REG_S7, 114 TCG_REG_S8, 115 TCG_REG_S9, 116 117 /* Registers (potentially) clobbered across calls */ 118 TCG_REG_T0, 119 TCG_REG_T1, 120 TCG_REG_T2, 121 TCG_REG_T3, 122 TCG_REG_T4, 123 TCG_REG_T5, 124 TCG_REG_T6, 125 TCG_REG_T7, 126 TCG_REG_T8, 127 128 /* Argument registers, opposite order of allocation. */ 129 TCG_REG_A7, 130 TCG_REG_A6, 131 TCG_REG_A5, 132 TCG_REG_A4, 133 TCG_REG_A3, 134 TCG_REG_A2, 135 TCG_REG_A1, 136 TCG_REG_A0, 137 138 /* Vector registers */ 139 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 140 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 141 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 142 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 143 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 144 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 145 /* V24 - V31 are caller-saved, and skipped. */ 146}; 147 148static const int tcg_target_call_iarg_regs[] = { 149 TCG_REG_A0, 150 TCG_REG_A1, 151 TCG_REG_A2, 152 TCG_REG_A3, 153 TCG_REG_A4, 154 TCG_REG_A5, 155 TCG_REG_A6, 156 TCG_REG_A7, 157}; 158 159static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 160{ 161 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 162 tcg_debug_assert(slot >= 0 && slot <= 1); 163 return TCG_REG_A0 + slot; 164} 165 166#define TCG_GUEST_BASE_REG TCG_REG_S1 167 168#define TCG_CT_CONST_ZERO 0x100 169#define TCG_CT_CONST_S12 0x200 170#define TCG_CT_CONST_S32 0x400 171#define TCG_CT_CONST_U12 0x800 172#define TCG_CT_CONST_C12 0x1000 173#define TCG_CT_CONST_WSZ 0x2000 174#define TCG_CT_CONST_VCMP 0x4000 175#define TCG_CT_CONST_VADD 0x8000 176 177#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 178#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 179 180static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 181{ 182 return sextract64(val, pos, len); 183} 184 185/* test if a constant matches the constraint */ 186static bool tcg_target_const_match(int64_t val, int ct, 187 TCGType type, TCGCond cond, int vece) 188{ 189 if (ct & TCG_CT_CONST) { 190 return true; 191 } 192 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 193 return true; 194 } 195 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 196 return true; 197 } 198 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 199 return true; 200 } 201 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 202 return true; 203 } 204 if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { 205 return true; 206 } 207 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return true; 209 } 210 int64_t vec_val = sextract64(val, 0, 8 << vece); 211 if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) { 212 return true; 213 } 214 if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) { 215 return true; 216 } 217 return false; 218} 219 220/* 221 * Relocations 222 */ 223 224/* 225 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 226 * complicated; a whopping stack machine is needed to stuff the fields, at 227 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 228 * needed. 229 * 230 * Hence, define our own simpler relocation types. Numbers are chosen as to 231 * not collide with potential future additions to the true ELF relocation 232 * type enum. 233 */ 234 235/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 236#define R_LOONGARCH_BR_SK16 256 237/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 238#define R_LOONGARCH_BR_SD10K16 257 239 240static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 241{ 242 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 243 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 244 245 tcg_debug_assert((offset & 3) == 0); 246 offset >>= 2; 247 if (offset == sextreg(offset, 0, 16)) { 248 *src_rw = deposit64(*src_rw, 10, 16, offset); 249 return true; 250 } 251 252 return false; 253} 254 255static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 256 const tcg_insn_unit *target) 257{ 258 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 259 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 260 261 tcg_debug_assert((offset & 3) == 0); 262 offset >>= 2; 263 if (offset == sextreg(offset, 0, 26)) { 264 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 265 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 266 return true; 267 } 268 269 return false; 270} 271 272static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 273 intptr_t value, intptr_t addend) 274{ 275 tcg_debug_assert(addend == 0); 276 switch (type) { 277 case R_LOONGARCH_BR_SK16: 278 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 279 case R_LOONGARCH_BR_SD10K16: 280 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 281 default: 282 g_assert_not_reached(); 283 } 284} 285 286#include "tcg-insn-defs.c.inc" 287 288/* 289 * TCG intrinsics 290 */ 291 292static void tcg_out_mb(TCGContext *s, TCGArg a0) 293{ 294 /* Baseline LoongArch only has the full barrier, unfortunately. */ 295 tcg_out_opc_dbar(s, 0); 296} 297 298static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 299{ 300 if (ret == arg) { 301 return true; 302 } 303 switch (type) { 304 case TCG_TYPE_I32: 305 case TCG_TYPE_I64: 306 if (ret < TCG_REG_V0) { 307 if (arg < TCG_REG_V0) { 308 /* 309 * Conventional register-register move used in LoongArch is 310 * `or dst, src, zero`. 311 */ 312 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 313 } else { 314 tcg_out_opc_movfr2gr_d(s, ret, arg); 315 } 316 } else { 317 if (arg < TCG_REG_V0) { 318 tcg_out_opc_movgr2fr_d(s, ret, arg); 319 } else { 320 tcg_out_opc_fmov_d(s, ret, arg); 321 } 322 } 323 break; 324 case TCG_TYPE_V64: 325 case TCG_TYPE_V128: 326 tcg_out_opc_vori_b(s, ret, arg, 0); 327 break; 328 case TCG_TYPE_V256: 329 tcg_out_opc_xvori_b(s, ret, arg, 0); 330 break; 331 default: 332 g_assert_not_reached(); 333 } 334 return true; 335} 336 337/* Loads a 32-bit immediate into rd, sign-extended. */ 338static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 339{ 340 tcg_target_long lo = sextreg(val, 0, 12); 341 tcg_target_long hi12 = sextreg(val, 12, 20); 342 343 /* Single-instruction cases. */ 344 if (hi12 == 0) { 345 /* val fits in uimm12: ori rd, zero, val */ 346 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 347 return; 348 } 349 if (hi12 == sextreg(lo, 12, 20)) { 350 /* val fits in simm12: addi.w rd, zero, val */ 351 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 352 return; 353 } 354 355 /* High bits must be set; load with lu12i.w + optional ori. */ 356 tcg_out_opc_lu12i_w(s, rd, hi12); 357 if (lo != 0) { 358 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 359 } 360} 361 362static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 363 tcg_target_long val) 364{ 365 /* 366 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 367 * with dedicated instructions for filling the respective bitfields 368 * below: 369 * 370 * 6 5 4 3 371 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 372 * +-----------------------+---------------------------------------+... 373 * | hi52 | hi32 | 374 * +-----------------------+---------------------------------------+... 375 * 3 2 1 376 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 377 * ...+-------------------------------------+-------------------------+ 378 * | hi12 | lo | 379 * ...+-------------------------------------+-------------------------+ 380 * 381 * Check if val belong to one of the several fast cases, before falling 382 * back to the slow path. 383 */ 384 385 intptr_t pc_offset; 386 tcg_target_long val_lo, val_hi, pc_hi, offset_hi; 387 tcg_target_long hi12, hi32, hi52; 388 389 /* Value fits in signed i32. */ 390 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 391 tcg_out_movi_i32(s, rd, val); 392 return; 393 } 394 395 /* PC-relative cases. */ 396 pc_offset = tcg_pcrel_diff(s, (void *)val); 397 if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) { 398 /* Single pcaddu2i. */ 399 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 400 return; 401 } 402 403 if (pc_offset == (int32_t)pc_offset) { 404 /* Offset within 32 bits; load with pcalau12i + ori. */ 405 val_lo = sextreg(val, 0, 12); 406 val_hi = val >> 12; 407 pc_hi = (val - pc_offset) >> 12; 408 offset_hi = val_hi - pc_hi; 409 410 tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20)); 411 tcg_out_opc_pcalau12i(s, rd, offset_hi); 412 if (val_lo != 0) { 413 tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff); 414 } 415 return; 416 } 417 418 hi12 = sextreg(val, 12, 20); 419 hi32 = sextreg(val, 32, 20); 420 hi52 = sextreg(val, 52, 12); 421 422 /* Single cu52i.d case. */ 423 if ((hi52 != 0) && (ctz64(val) >= 52)) { 424 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 425 return; 426 } 427 428 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 429 tcg_out_movi_i32(s, rd, val); 430 431 /* Load hi32 and hi52 explicitly when they are unexpected values. */ 432 if (hi32 != sextreg(hi12, 20, 20)) { 433 tcg_out_opc_cu32i_d(s, rd, hi32); 434 } 435 436 if (hi52 != sextreg(hi32, 20, 12)) { 437 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 438 } 439} 440 441static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, 442 TCGReg rs, tcg_target_long imm) 443{ 444 tcg_target_long lo12 = sextreg(imm, 0, 12); 445 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16); 446 447 /* 448 * Note that there's a hole in between hi16 and lo12: 449 * 450 * 3 2 1 0 451 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 452 * ...+-------------------------------+-------+-----------------------+ 453 * | hi16 | | lo12 | 454 * ...+-------------------------------+-------+-----------------------+ 455 * 456 * For bits within that hole, it's more efficient to use LU12I and ADD. 457 */ 458 if (imm == (hi16 << 16) + lo12) { 459 if (hi16) { 460 tcg_out_opc_addu16i_d(s, rd, rs, hi16); 461 rs = rd; 462 } 463 if (type == TCG_TYPE_I32) { 464 tcg_out_opc_addi_w(s, rd, rs, lo12); 465 } else if (lo12) { 466 tcg_out_opc_addi_d(s, rd, rs, lo12); 467 } else { 468 tcg_out_mov(s, type, rd, rs); 469 } 470 } else { 471 tcg_out_movi(s, type, TCG_REG_TMP0, imm); 472 if (type == TCG_TYPE_I32) { 473 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); 474 } else { 475 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); 476 } 477 } 478} 479 480static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 481{ 482 return false; 483} 484 485static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 486 tcg_target_long imm) 487{ 488 /* This function is only used for passing structs by reference. */ 489 g_assert_not_reached(); 490} 491 492static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 493{ 494 tcg_out_opc_andi(s, ret, arg, 0xff); 495} 496 497static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 498{ 499 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 500} 501 502static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 503{ 504 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 505} 506 507static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 508{ 509 tcg_out_opc_sext_b(s, ret, arg); 510} 511 512static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 513{ 514 tcg_out_opc_sext_h(s, ret, arg); 515} 516 517static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 518{ 519 tcg_out_opc_addi_w(s, ret, arg, 0); 520} 521 522static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 523{ 524 if (ret != arg) { 525 tcg_out_ext32s(s, ret, arg); 526 } 527} 528 529static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 530{ 531 tcg_out_ext32u(s, ret, arg); 532} 533 534static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 535{ 536 tcg_out_ext32s(s, ret, arg); 537} 538 539static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, 540 TCGReg a0, TCGReg a1, TCGReg a2, 541 bool c2, bool is_32bit) 542{ 543 if (c2) { 544 /* 545 * Fast path: semantics already satisfied due to constraint and 546 * insn behavior, single instruction is enough. 547 */ 548 tcg_debug_assert(a2 == (is_32bit ? 32 : 64)); 549 /* all clz/ctz insns belong to DJ-format */ 550 tcg_out32(s, encode_dj_insn(opc, a0, a1)); 551 return; 552 } 553 554 tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); 555 /* a0 = a1 ? REG_TMP0 : a2 */ 556 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 557 tcg_out_opc_masknez(s, a0, a2, a1); 558 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); 559} 560 561#define SETCOND_INV TCG_TARGET_NB_REGS 562#define SETCOND_NEZ (SETCOND_INV << 1) 563#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 564 565static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 566 TCGReg arg1, tcg_target_long arg2, bool c2) 567{ 568 int flags = 0; 569 570 switch (cond) { 571 case TCG_COND_EQ: /* -> NE */ 572 case TCG_COND_GE: /* -> LT */ 573 case TCG_COND_GEU: /* -> LTU */ 574 case TCG_COND_GT: /* -> LE */ 575 case TCG_COND_GTU: /* -> LEU */ 576 cond = tcg_invert_cond(cond); 577 flags ^= SETCOND_INV; 578 break; 579 default: 580 break; 581 } 582 583 switch (cond) { 584 case TCG_COND_LE: 585 case TCG_COND_LEU: 586 /* 587 * If we have a constant input, the most efficient way to implement 588 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 589 * We don't need to care for this for LE because the constant input 590 * is still constrained to int32_t, and INT32_MAX+1 is representable 591 * in the 64-bit temporary register. 592 */ 593 if (c2) { 594 if (cond == TCG_COND_LEU) { 595 /* unsigned <= -1 is true */ 596 if (arg2 == -1) { 597 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 598 return ret; 599 } 600 cond = TCG_COND_LTU; 601 } else { 602 cond = TCG_COND_LT; 603 } 604 arg2 += 1; 605 } else { 606 TCGReg tmp = arg2; 607 arg2 = arg1; 608 arg1 = tmp; 609 cond = tcg_swap_cond(cond); /* LE -> GE */ 610 cond = tcg_invert_cond(cond); /* GE -> LT */ 611 flags ^= SETCOND_INV; 612 } 613 break; 614 default: 615 break; 616 } 617 618 switch (cond) { 619 case TCG_COND_NE: 620 flags |= SETCOND_NEZ; 621 if (!c2) { 622 tcg_out_opc_xor(s, ret, arg1, arg2); 623 } else if (arg2 == 0) { 624 ret = arg1; 625 } else if (arg2 >= 0 && arg2 <= 0xfff) { 626 tcg_out_opc_xori(s, ret, arg1, arg2); 627 } else { 628 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2); 629 } 630 break; 631 632 case TCG_COND_LT: 633 case TCG_COND_LTU: 634 if (c2) { 635 if (arg2 >= -0x800 && arg2 <= 0x7ff) { 636 if (cond == TCG_COND_LT) { 637 tcg_out_opc_slti(s, ret, arg1, arg2); 638 } else { 639 tcg_out_opc_sltui(s, ret, arg1, arg2); 640 } 641 break; 642 } 643 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 644 arg2 = TCG_REG_TMP0; 645 } 646 if (cond == TCG_COND_LT) { 647 tcg_out_opc_slt(s, ret, arg1, arg2); 648 } else { 649 tcg_out_opc_sltu(s, ret, arg1, arg2); 650 } 651 break; 652 653 default: 654 g_assert_not_reached(); 655 break; 656 } 657 658 return ret | flags; 659} 660 661static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 662 TCGReg arg1, tcg_target_long arg2, bool c2) 663{ 664 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 665 666 if (tmpflags != ret) { 667 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 668 669 switch (tmpflags & SETCOND_FLAGS) { 670 case SETCOND_INV: 671 /* Intermediate result is boolean: simply invert. */ 672 tcg_out_opc_xori(s, ret, tmp, 1); 673 break; 674 case SETCOND_NEZ: 675 /* Intermediate result is zero/non-zero: test != 0. */ 676 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 677 break; 678 case SETCOND_NEZ | SETCOND_INV: 679 /* Intermediate result is zero/non-zero: test == 0. */ 680 tcg_out_opc_sltui(s, ret, tmp, 1); 681 break; 682 default: 683 g_assert_not_reached(); 684 } 685 } 686} 687 688static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 689 TCGReg c1, tcg_target_long c2, bool const2, 690 TCGReg v1, TCGReg v2) 691{ 692 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2); 693 TCGReg t; 694 695 /* Standardize the test below to t != 0. */ 696 if (tmpflags & SETCOND_INV) { 697 t = v1, v1 = v2, v2 = t; 698 } 699 700 t = tmpflags & ~SETCOND_FLAGS; 701 if (v1 == TCG_REG_ZERO) { 702 tcg_out_opc_masknez(s, ret, v2, t); 703 } else if (v2 == TCG_REG_ZERO) { 704 tcg_out_opc_maskeqz(s, ret, v1, t); 705 } else { 706 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */ 707 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */ 708 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2); 709 } 710} 711 712/* 713 * Branch helpers 714 */ 715 716static const struct { 717 LoongArchInsn op; 718 bool swap; 719} tcg_brcond_to_loongarch[] = { 720 [TCG_COND_EQ] = { OPC_BEQ, false }, 721 [TCG_COND_NE] = { OPC_BNE, false }, 722 [TCG_COND_LT] = { OPC_BGT, true }, 723 [TCG_COND_GE] = { OPC_BLE, true }, 724 [TCG_COND_LE] = { OPC_BLE, false }, 725 [TCG_COND_GT] = { OPC_BGT, false }, 726 [TCG_COND_LTU] = { OPC_BGTU, true }, 727 [TCG_COND_GEU] = { OPC_BLEU, true }, 728 [TCG_COND_LEU] = { OPC_BLEU, false }, 729 [TCG_COND_GTU] = { OPC_BGTU, false } 730}; 731 732static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 733 TCGReg arg2, TCGLabel *l) 734{ 735 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 736 737 tcg_debug_assert(op != 0); 738 739 if (tcg_brcond_to_loongarch[cond].swap) { 740 TCGReg t = arg1; 741 arg1 = arg2; 742 arg2 = t; 743 } 744 745 /* all conditional branch insns belong to DJSk16-format */ 746 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 747 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 748} 749 750static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 751{ 752 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 753 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 754 755 tcg_debug_assert((offset & 3) == 0); 756 if (offset == sextreg(offset, 0, 28)) { 757 /* short jump: +/- 256MiB */ 758 if (tail) { 759 tcg_out_opc_b(s, offset >> 2); 760 } else { 761 tcg_out_opc_bl(s, offset >> 2); 762 } 763 } else if (offset == sextreg(offset, 0, 38)) { 764 /* long jump: +/- 256GiB */ 765 tcg_target_long lo = sextreg(offset, 0, 18); 766 tcg_target_long hi = offset - lo; 767 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 768 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 769 } else { 770 /* far jump: 64-bit */ 771 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 772 tcg_target_long hi = (tcg_target_long)arg - lo; 773 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 774 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 775 } 776} 777 778static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 779 const TCGHelperInfo *info) 780{ 781 tcg_out_call_int(s, arg, false); 782} 783 784/* 785 * Load/store helpers 786 */ 787 788static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 789 TCGReg addr, intptr_t offset) 790{ 791 intptr_t imm12 = sextreg(offset, 0, 12); 792 793 if (offset != imm12) { 794 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 795 796 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 797 imm12 = sextreg(diff, 0, 12); 798 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 799 } else { 800 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 801 if (addr != TCG_REG_ZERO) { 802 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 803 } 804 } 805 addr = TCG_REG_TMP2; 806 } 807 808 switch (opc) { 809 case OPC_LD_B: 810 case OPC_LD_BU: 811 case OPC_LD_H: 812 case OPC_LD_HU: 813 case OPC_LD_W: 814 case OPC_LD_WU: 815 case OPC_LD_D: 816 case OPC_ST_B: 817 case OPC_ST_H: 818 case OPC_ST_W: 819 case OPC_ST_D: 820 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 821 break; 822 case OPC_FLD_S: 823 case OPC_FLD_D: 824 case OPC_FST_S: 825 case OPC_FST_D: 826 tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12)); 827 break; 828 default: 829 g_assert_not_reached(); 830 } 831} 832 833static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest, 834 TCGReg base, intptr_t offset) 835{ 836 switch (type) { 837 case TCG_TYPE_I32: 838 if (dest < TCG_REG_V0) { 839 tcg_out_ldst(s, OPC_LD_W, dest, base, offset); 840 } else { 841 tcg_out_ldst(s, OPC_FLD_S, dest, base, offset); 842 } 843 break; 844 case TCG_TYPE_I64: 845 case TCG_TYPE_V64: 846 if (dest < TCG_REG_V0) { 847 tcg_out_ldst(s, OPC_LD_D, dest, base, offset); 848 } else { 849 tcg_out_ldst(s, OPC_FLD_D, dest, base, offset); 850 } 851 break; 852 case TCG_TYPE_V128: 853 if (-0x800 <= offset && offset <= 0x7ff) { 854 tcg_out_opc_vld(s, dest, base, offset); 855 } else { 856 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 857 tcg_out_opc_vldx(s, dest, base, TCG_REG_TMP0); 858 } 859 break; 860 case TCG_TYPE_V256: 861 if (-0x800 <= offset && offset <= 0x7ff) { 862 tcg_out_opc_xvld(s, dest, base, offset); 863 } else { 864 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 865 tcg_out_opc_xvldx(s, dest, base, TCG_REG_TMP0); 866 } 867 break; 868 default: 869 g_assert_not_reached(); 870 } 871} 872 873static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, 874 TCGReg base, intptr_t offset) 875{ 876 switch (type) { 877 case TCG_TYPE_I32: 878 if (src < TCG_REG_V0) { 879 tcg_out_ldst(s, OPC_ST_W, src, base, offset); 880 } else { 881 tcg_out_ldst(s, OPC_FST_S, src, base, offset); 882 } 883 break; 884 case TCG_TYPE_I64: 885 case TCG_TYPE_V64: 886 if (src < TCG_REG_V0) { 887 tcg_out_ldst(s, OPC_ST_D, src, base, offset); 888 } else { 889 tcg_out_ldst(s, OPC_FST_D, src, base, offset); 890 } 891 break; 892 case TCG_TYPE_V128: 893 if (-0x800 <= offset && offset <= 0x7ff) { 894 tcg_out_opc_vst(s, src, base, offset); 895 } else { 896 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 897 tcg_out_opc_vstx(s, src, base, TCG_REG_TMP0); 898 } 899 break; 900 case TCG_TYPE_V256: 901 if (-0x800 <= offset && offset <= 0x7ff) { 902 tcg_out_opc_xvst(s, src, base, offset); 903 } else { 904 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 905 tcg_out_opc_xvstx(s, src, base, TCG_REG_TMP0); 906 } 907 break; 908 default: 909 g_assert_not_reached(); 910 } 911} 912 913static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 914 TCGReg base, intptr_t ofs) 915{ 916 if (val == 0) { 917 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 918 return true; 919 } 920 return false; 921} 922 923/* 924 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 925 */ 926 927static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 928{ 929 tcg_out_opc_b(s, 0); 930 return reloc_br_sd10k16(s->code_ptr - 1, target); 931} 932 933static const TCGLdstHelperParam ldst_helper_param = { 934 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 935}; 936 937static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 938{ 939 MemOp opc = get_memop(l->oi); 940 941 /* resolve label address */ 942 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 943 return false; 944 } 945 946 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 947 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); 948 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 949 return tcg_out_goto(s, l->raddr); 950} 951 952static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 953{ 954 MemOp opc = get_memop(l->oi); 955 956 /* resolve label address */ 957 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 958 return false; 959 } 960 961 tcg_out_st_helper_args(s, l, &ldst_helper_param); 962 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 963 return tcg_out_goto(s, l->raddr); 964} 965 966typedef struct { 967 TCGReg base; 968 TCGReg index; 969 TCGAtomAlign aa; 970} HostAddress; 971 972bool tcg_target_has_memory_bswap(MemOp memop) 973{ 974 return false; 975} 976 977/* We expect to use a 12-bit negative offset from ENV. */ 978#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 979 980/* 981 * For system-mode, perform the TLB load and compare. 982 * For user-mode, perform any required alignment tests. 983 * In both cases, return a TCGLabelQemuLdst structure if the slow path 984 * is required and fill in @h with the host address for the fast path. 985 */ 986static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 987 TCGReg addr_reg, MemOpIdx oi, 988 bool is_ld) 989{ 990 TCGType addr_type = s->addr_type; 991 TCGLabelQemuLdst *ldst = NULL; 992 MemOp opc = get_memop(oi); 993 MemOp a_bits; 994 995 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 996 a_bits = h->aa.align; 997 998 if (tcg_use_softmmu) { 999 unsigned s_bits = opc & MO_SIZE; 1000 int mem_index = get_mmuidx(oi); 1001 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 1002 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 1003 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 1004 1005 ldst = new_ldst_label(s); 1006 ldst->is_ld = is_ld; 1007 ldst->oi = oi; 1008 ldst->addrlo_reg = addr_reg; 1009 1010 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 1011 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 1012 1013 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, 1014 s->page_bits - CPU_TLB_ENTRY_BITS); 1015 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 1016 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 1017 1018 /* Load the tlb comparator and the addend. */ 1019 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 1020 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 1021 is_ld ? offsetof(CPUTLBEntry, addr_read) 1022 : offsetof(CPUTLBEntry, addr_write)); 1023 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 1024 offsetof(CPUTLBEntry, addend)); 1025 1026 /* 1027 * For aligned accesses, we check the first byte and include the 1028 * alignment bits within the address. For unaligned access, we 1029 * check that we don't cross pages using the address of the last 1030 * byte of the access. 1031 */ 1032 if (a_bits < s_bits) { 1033 unsigned a_mask = (1u << a_bits) - 1; 1034 unsigned s_mask = (1u << s_bits) - 1; 1035 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask); 1036 } else { 1037 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); 1038 } 1039 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, 1040 a_bits, s->page_bits - 1); 1041 1042 /* Compare masked address with the TLB entry. */ 1043 ldst->label_ptr[0] = s->code_ptr; 1044 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1045 1046 h->index = TCG_REG_TMP2; 1047 } else { 1048 if (a_bits) { 1049 ldst = new_ldst_label(s); 1050 1051 ldst->is_ld = is_ld; 1052 ldst->oi = oi; 1053 ldst->addrlo_reg = addr_reg; 1054 1055 /* 1056 * Without micro-architecture details, we don't know which of 1057 * bstrpick or andi is faster, so use bstrpick as it's not 1058 * constrained by imm field width. Not to say alignments >= 2^12 1059 * are going to happen any time soon. 1060 */ 1061 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 1062 1063 ldst->label_ptr[0] = s->code_ptr; 1064 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1065 } 1066 1067 h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1068 } 1069 1070 if (addr_type == TCG_TYPE_I32) { 1071 h->base = TCG_REG_TMP0; 1072 tcg_out_ext32u(s, h->base, addr_reg); 1073 } else { 1074 h->base = addr_reg; 1075 } 1076 1077 return ldst; 1078} 1079 1080static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, 1081 TCGReg rd, HostAddress h) 1082{ 1083 /* Byte swapping is left to middle-end expansion. */ 1084 tcg_debug_assert((opc & MO_BSWAP) == 0); 1085 1086 switch (opc & MO_SSIZE) { 1087 case MO_UB: 1088 tcg_out_opc_ldx_bu(s, rd, h.base, h.index); 1089 break; 1090 case MO_SB: 1091 tcg_out_opc_ldx_b(s, rd, h.base, h.index); 1092 break; 1093 case MO_UW: 1094 tcg_out_opc_ldx_hu(s, rd, h.base, h.index); 1095 break; 1096 case MO_SW: 1097 tcg_out_opc_ldx_h(s, rd, h.base, h.index); 1098 break; 1099 case MO_UL: 1100 if (type == TCG_TYPE_I64) { 1101 tcg_out_opc_ldx_wu(s, rd, h.base, h.index); 1102 break; 1103 } 1104 /* fallthrough */ 1105 case MO_SL: 1106 tcg_out_opc_ldx_w(s, rd, h.base, h.index); 1107 break; 1108 case MO_UQ: 1109 tcg_out_opc_ldx_d(s, rd, h.base, h.index); 1110 break; 1111 default: 1112 g_assert_not_reached(); 1113 } 1114} 1115 1116static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1117 MemOpIdx oi, TCGType data_type) 1118{ 1119 TCGLabelQemuLdst *ldst; 1120 HostAddress h; 1121 1122 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1123 tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); 1124 1125 if (ldst) { 1126 ldst->type = data_type; 1127 ldst->datalo_reg = data_reg; 1128 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1129 } 1130} 1131 1132static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, 1133 TCGReg rd, HostAddress h) 1134{ 1135 /* Byte swapping is left to middle-end expansion. */ 1136 tcg_debug_assert((opc & MO_BSWAP) == 0); 1137 1138 switch (opc & MO_SIZE) { 1139 case MO_8: 1140 tcg_out_opc_stx_b(s, rd, h.base, h.index); 1141 break; 1142 case MO_16: 1143 tcg_out_opc_stx_h(s, rd, h.base, h.index); 1144 break; 1145 case MO_32: 1146 tcg_out_opc_stx_w(s, rd, h.base, h.index); 1147 break; 1148 case MO_64: 1149 tcg_out_opc_stx_d(s, rd, h.base, h.index); 1150 break; 1151 default: 1152 g_assert_not_reached(); 1153 } 1154} 1155 1156static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1157 MemOpIdx oi, TCGType data_type) 1158{ 1159 TCGLabelQemuLdst *ldst; 1160 HostAddress h; 1161 1162 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1163 tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); 1164 1165 if (ldst) { 1166 ldst->type = data_type; 1167 ldst->datalo_reg = data_reg; 1168 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1169 } 1170} 1171 1172static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi, 1173 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1174{ 1175 TCGLabelQemuLdst *ldst; 1176 HostAddress h; 1177 1178 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1179 1180 if (h.aa.atom == MO_128) { 1181 /* 1182 * Use VLDX/VSTX when 128-bit atomicity is required. 1183 * If address is aligned to 16-bytes, the 128-bit load/store is atomic. 1184 */ 1185 if (is_ld) { 1186 tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index); 1187 tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0); 1188 tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1); 1189 } else { 1190 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0); 1191 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1); 1192 tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index); 1193 } 1194 } else { 1195 /* Otherwise use a pair of LD/ST. */ 1196 TCGReg base = h.base; 1197 if (h.index != TCG_REG_ZERO) { 1198 base = TCG_REG_TMP0; 1199 tcg_out_opc_add_d(s, base, h.base, h.index); 1200 } 1201 if (is_ld) { 1202 tcg_debug_assert(base != data_lo); 1203 tcg_out_opc_ld_d(s, data_lo, base, 0); 1204 tcg_out_opc_ld_d(s, data_hi, base, 8); 1205 } else { 1206 tcg_out_opc_st_d(s, data_lo, base, 0); 1207 tcg_out_opc_st_d(s, data_hi, base, 8); 1208 } 1209 } 1210 1211 if (ldst) { 1212 ldst->type = TCG_TYPE_I128; 1213 ldst->datalo_reg = data_lo; 1214 ldst->datahi_reg = data_hi; 1215 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1216 } 1217} 1218 1219/* 1220 * Entry-points 1221 */ 1222 1223static const tcg_insn_unit *tb_ret_addr; 1224 1225static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1226{ 1227 /* Reuse the zeroing that exists for goto_ptr. */ 1228 if (a0 == 0) { 1229 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1230 } else { 1231 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1232 tcg_out_call_int(s, tb_ret_addr, true); 1233 } 1234} 1235 1236static void tcg_out_goto_tb(TCGContext *s, int which) 1237{ 1238 /* 1239 * Direct branch, or load indirect address, to be patched 1240 * by tb_target_set_jmp_target. Check indirect load offset 1241 * in range early, regardless of direct branch distance, 1242 * via assert within tcg_out_opc_pcaddu2i. 1243 */ 1244 uintptr_t i_addr = get_jmp_target_addr(s, which); 1245 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr); 1246 1247 set_jmp_insn_offset(s, which); 1248 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2); 1249 1250 /* Finish the load and indirect branch. */ 1251 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); 1252 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1253 set_jmp_reset_offset(s, which); 1254} 1255 1256void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1257 uintptr_t jmp_rx, uintptr_t jmp_rw) 1258{ 1259 uintptr_t d_addr = tb->jmp_target_addr[n]; 1260 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2; 1261 tcg_insn_unit insn; 1262 1263 /* Either directly branch, or load slot address for indirect branch. */ 1264 if (d_disp == sextreg(d_disp, 0, 26)) { 1265 insn = encode_sd10k16_insn(OPC_B, d_disp); 1266 } else { 1267 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 1268 intptr_t i_disp = i_addr - jmp_rx; 1269 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2); 1270 } 1271 1272 qatomic_set((tcg_insn_unit *)jmp_rw, insn); 1273 flush_idcache_range(jmp_rx, jmp_rw, 4); 1274} 1275 1276static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1277 const TCGArg args[TCG_MAX_OP_ARGS], 1278 const int const_args[TCG_MAX_OP_ARGS]) 1279{ 1280 TCGArg a0 = args[0]; 1281 TCGArg a1 = args[1]; 1282 TCGArg a2 = args[2]; 1283 TCGArg a3 = args[3]; 1284 int c2 = const_args[2]; 1285 1286 switch (opc) { 1287 case INDEX_op_mb: 1288 tcg_out_mb(s, a0); 1289 break; 1290 1291 case INDEX_op_goto_ptr: 1292 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1293 break; 1294 1295 case INDEX_op_br: 1296 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), 1297 0); 1298 tcg_out_opc_b(s, 0); 1299 break; 1300 1301 case INDEX_op_brcond_i32: 1302 case INDEX_op_brcond_i64: 1303 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1304 break; 1305 1306 case INDEX_op_extrh_i64_i32: 1307 tcg_out_opc_srai_d(s, a0, a1, 32); 1308 break; 1309 1310 case INDEX_op_not_i32: 1311 case INDEX_op_not_i64: 1312 tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); 1313 break; 1314 1315 case INDEX_op_nor_i32: 1316 case INDEX_op_nor_i64: 1317 if (c2) { 1318 tcg_out_opc_ori(s, a0, a1, a2); 1319 tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO); 1320 } else { 1321 tcg_out_opc_nor(s, a0, a1, a2); 1322 } 1323 break; 1324 1325 case INDEX_op_andc_i32: 1326 case INDEX_op_andc_i64: 1327 if (c2) { 1328 /* guaranteed to fit due to constraint */ 1329 tcg_out_opc_andi(s, a0, a1, ~a2); 1330 } else { 1331 tcg_out_opc_andn(s, a0, a1, a2); 1332 } 1333 break; 1334 1335 case INDEX_op_orc_i32: 1336 case INDEX_op_orc_i64: 1337 if (c2) { 1338 /* guaranteed to fit due to constraint */ 1339 tcg_out_opc_ori(s, a0, a1, ~a2); 1340 } else { 1341 tcg_out_opc_orn(s, a0, a1, a2); 1342 } 1343 break; 1344 1345 case INDEX_op_and_i32: 1346 case INDEX_op_and_i64: 1347 if (c2) { 1348 tcg_out_opc_andi(s, a0, a1, a2); 1349 } else { 1350 tcg_out_opc_and(s, a0, a1, a2); 1351 } 1352 break; 1353 1354 case INDEX_op_or_i32: 1355 case INDEX_op_or_i64: 1356 if (c2) { 1357 tcg_out_opc_ori(s, a0, a1, a2); 1358 } else { 1359 tcg_out_opc_or(s, a0, a1, a2); 1360 } 1361 break; 1362 1363 case INDEX_op_xor_i32: 1364 case INDEX_op_xor_i64: 1365 if (c2) { 1366 tcg_out_opc_xori(s, a0, a1, a2); 1367 } else { 1368 tcg_out_opc_xor(s, a0, a1, a2); 1369 } 1370 break; 1371 1372 case INDEX_op_extract_i32: 1373 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); 1374 break; 1375 case INDEX_op_extract_i64: 1376 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); 1377 break; 1378 1379 case INDEX_op_deposit_i32: 1380 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); 1381 break; 1382 case INDEX_op_deposit_i64: 1383 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); 1384 break; 1385 1386 case INDEX_op_bswap16_i32: 1387 case INDEX_op_bswap16_i64: 1388 tcg_out_opc_revb_2h(s, a0, a1); 1389 if (a2 & TCG_BSWAP_OS) { 1390 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); 1391 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1392 tcg_out_ext16u(s, a0, a0); 1393 } 1394 break; 1395 1396 case INDEX_op_bswap32_i32: 1397 /* All 32-bit values are computed sign-extended in the register. */ 1398 a2 = TCG_BSWAP_OS; 1399 /* fallthrough */ 1400 case INDEX_op_bswap32_i64: 1401 tcg_out_opc_revb_2w(s, a0, a1); 1402 if (a2 & TCG_BSWAP_OS) { 1403 tcg_out_ext32s(s, a0, a0); 1404 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1405 tcg_out_ext32u(s, a0, a0); 1406 } 1407 break; 1408 1409 case INDEX_op_bswap64_i64: 1410 tcg_out_opc_revb_d(s, a0, a1); 1411 break; 1412 1413 case INDEX_op_clz_i32: 1414 tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true); 1415 break; 1416 case INDEX_op_clz_i64: 1417 tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false); 1418 break; 1419 1420 case INDEX_op_ctz_i32: 1421 tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true); 1422 break; 1423 case INDEX_op_ctz_i64: 1424 tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); 1425 break; 1426 1427 case INDEX_op_shl_i32: 1428 if (c2) { 1429 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1430 } else { 1431 tcg_out_opc_sll_w(s, a0, a1, a2); 1432 } 1433 break; 1434 case INDEX_op_shl_i64: 1435 if (c2) { 1436 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1437 } else { 1438 tcg_out_opc_sll_d(s, a0, a1, a2); 1439 } 1440 break; 1441 1442 case INDEX_op_shr_i32: 1443 if (c2) { 1444 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1445 } else { 1446 tcg_out_opc_srl_w(s, a0, a1, a2); 1447 } 1448 break; 1449 case INDEX_op_shr_i64: 1450 if (c2) { 1451 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1452 } else { 1453 tcg_out_opc_srl_d(s, a0, a1, a2); 1454 } 1455 break; 1456 1457 case INDEX_op_sar_i32: 1458 if (c2) { 1459 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1460 } else { 1461 tcg_out_opc_sra_w(s, a0, a1, a2); 1462 } 1463 break; 1464 case INDEX_op_sar_i64: 1465 if (c2) { 1466 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1467 } else { 1468 tcg_out_opc_sra_d(s, a0, a1, a2); 1469 } 1470 break; 1471 1472 case INDEX_op_rotl_i32: 1473 /* transform into equivalent rotr/rotri */ 1474 if (c2) { 1475 tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f); 1476 } else { 1477 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1478 tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0); 1479 } 1480 break; 1481 case INDEX_op_rotl_i64: 1482 /* transform into equivalent rotr/rotri */ 1483 if (c2) { 1484 tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f); 1485 } else { 1486 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1487 tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0); 1488 } 1489 break; 1490 1491 case INDEX_op_rotr_i32: 1492 if (c2) { 1493 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1494 } else { 1495 tcg_out_opc_rotr_w(s, a0, a1, a2); 1496 } 1497 break; 1498 case INDEX_op_rotr_i64: 1499 if (c2) { 1500 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1501 } else { 1502 tcg_out_opc_rotr_d(s, a0, a1, a2); 1503 } 1504 break; 1505 1506 case INDEX_op_add_i32: 1507 if (c2) { 1508 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2); 1509 } else { 1510 tcg_out_opc_add_w(s, a0, a1, a2); 1511 } 1512 break; 1513 case INDEX_op_add_i64: 1514 if (c2) { 1515 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2); 1516 } else { 1517 tcg_out_opc_add_d(s, a0, a1, a2); 1518 } 1519 break; 1520 1521 case INDEX_op_sub_i32: 1522 if (c2) { 1523 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2); 1524 } else { 1525 tcg_out_opc_sub_w(s, a0, a1, a2); 1526 } 1527 break; 1528 case INDEX_op_sub_i64: 1529 if (c2) { 1530 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2); 1531 } else { 1532 tcg_out_opc_sub_d(s, a0, a1, a2); 1533 } 1534 break; 1535 1536 case INDEX_op_neg_i32: 1537 tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1); 1538 break; 1539 case INDEX_op_neg_i64: 1540 tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1); 1541 break; 1542 1543 case INDEX_op_mul_i32: 1544 tcg_out_opc_mul_w(s, a0, a1, a2); 1545 break; 1546 case INDEX_op_mul_i64: 1547 tcg_out_opc_mul_d(s, a0, a1, a2); 1548 break; 1549 1550 case INDEX_op_mulsh_i32: 1551 tcg_out_opc_mulh_w(s, a0, a1, a2); 1552 break; 1553 case INDEX_op_mulsh_i64: 1554 tcg_out_opc_mulh_d(s, a0, a1, a2); 1555 break; 1556 1557 case INDEX_op_muluh_i32: 1558 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1559 break; 1560 case INDEX_op_muluh_i64: 1561 tcg_out_opc_mulh_du(s, a0, a1, a2); 1562 break; 1563 1564 case INDEX_op_div_i32: 1565 tcg_out_opc_div_w(s, a0, a1, a2); 1566 break; 1567 case INDEX_op_div_i64: 1568 tcg_out_opc_div_d(s, a0, a1, a2); 1569 break; 1570 1571 case INDEX_op_divu_i32: 1572 tcg_out_opc_div_wu(s, a0, a1, a2); 1573 break; 1574 case INDEX_op_divu_i64: 1575 tcg_out_opc_div_du(s, a0, a1, a2); 1576 break; 1577 1578 case INDEX_op_rem_i32: 1579 tcg_out_opc_mod_w(s, a0, a1, a2); 1580 break; 1581 case INDEX_op_rem_i64: 1582 tcg_out_opc_mod_d(s, a0, a1, a2); 1583 break; 1584 1585 case INDEX_op_remu_i32: 1586 tcg_out_opc_mod_wu(s, a0, a1, a2); 1587 break; 1588 case INDEX_op_remu_i64: 1589 tcg_out_opc_mod_du(s, a0, a1, a2); 1590 break; 1591 1592 case INDEX_op_setcond_i32: 1593 case INDEX_op_setcond_i64: 1594 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 1595 break; 1596 1597 case INDEX_op_movcond_i32: 1598 case INDEX_op_movcond_i64: 1599 tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]); 1600 break; 1601 1602 case INDEX_op_ld8s_i32: 1603 case INDEX_op_ld8s_i64: 1604 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); 1605 break; 1606 case INDEX_op_ld8u_i32: 1607 case INDEX_op_ld8u_i64: 1608 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); 1609 break; 1610 case INDEX_op_ld16s_i32: 1611 case INDEX_op_ld16s_i64: 1612 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); 1613 break; 1614 case INDEX_op_ld16u_i32: 1615 case INDEX_op_ld16u_i64: 1616 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); 1617 break; 1618 case INDEX_op_ld_i32: 1619 case INDEX_op_ld32s_i64: 1620 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); 1621 break; 1622 case INDEX_op_ld32u_i64: 1623 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); 1624 break; 1625 case INDEX_op_ld_i64: 1626 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); 1627 break; 1628 1629 case INDEX_op_st8_i32: 1630 case INDEX_op_st8_i64: 1631 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); 1632 break; 1633 case INDEX_op_st16_i32: 1634 case INDEX_op_st16_i64: 1635 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); 1636 break; 1637 case INDEX_op_st_i32: 1638 case INDEX_op_st32_i64: 1639 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); 1640 break; 1641 case INDEX_op_st_i64: 1642 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); 1643 break; 1644 1645 case INDEX_op_qemu_ld_a32_i32: 1646 case INDEX_op_qemu_ld_a64_i32: 1647 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1648 break; 1649 case INDEX_op_qemu_ld_a32_i64: 1650 case INDEX_op_qemu_ld_a64_i64: 1651 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1652 break; 1653 case INDEX_op_qemu_ld_a32_i128: 1654 case INDEX_op_qemu_ld_a64_i128: 1655 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true); 1656 break; 1657 case INDEX_op_qemu_st_a32_i32: 1658 case INDEX_op_qemu_st_a64_i32: 1659 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1660 break; 1661 case INDEX_op_qemu_st_a32_i64: 1662 case INDEX_op_qemu_st_a64_i64: 1663 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1664 break; 1665 case INDEX_op_qemu_st_a32_i128: 1666 case INDEX_op_qemu_st_a64_i128: 1667 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false); 1668 break; 1669 1670 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1671 case INDEX_op_mov_i64: 1672 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1673 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1674 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1675 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1676 case INDEX_op_ext8s_i64: 1677 case INDEX_op_ext8u_i32: 1678 case INDEX_op_ext8u_i64: 1679 case INDEX_op_ext16s_i32: 1680 case INDEX_op_ext16s_i64: 1681 case INDEX_op_ext16u_i32: 1682 case INDEX_op_ext16u_i64: 1683 case INDEX_op_ext32s_i64: 1684 case INDEX_op_ext32u_i64: 1685 case INDEX_op_ext_i32_i64: 1686 case INDEX_op_extu_i32_i64: 1687 case INDEX_op_extrl_i64_i32: 1688 default: 1689 g_assert_not_reached(); 1690 } 1691} 1692 1693static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1694 TCGReg rd, TCGReg rs) 1695{ 1696 static const LoongArchInsn repl_insn[2][4] = { 1697 { OPC_VREPLGR2VR_B, OPC_VREPLGR2VR_H, 1698 OPC_VREPLGR2VR_W, OPC_VREPLGR2VR_D }, 1699 { OPC_XVREPLGR2VR_B, OPC_XVREPLGR2VR_H, 1700 OPC_XVREPLGR2VR_W, OPC_XVREPLGR2VR_D }, 1701 }; 1702 bool lasx = type == TCG_TYPE_V256; 1703 1704 tcg_debug_assert(vece <= MO_64); 1705 tcg_out32(s, encode_vdj_insn(repl_insn[lasx][vece], rd, rs)); 1706 return true; 1707} 1708 1709static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1710 TCGReg r, TCGReg base, intptr_t offset) 1711{ 1712 bool lasx = type == TCG_TYPE_V256; 1713 1714 /* Handle imm overflow and division (vldrepl.d imm is divided by 8). */ 1715 if (offset < -0x800 || offset > 0x7ff || 1716 (offset & ((1 << vece) - 1)) != 0) { 1717 tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset); 1718 base = TCG_REG_TMP0; 1719 offset = 0; 1720 } 1721 offset >>= vece; 1722 1723 switch (vece) { 1724 case MO_8: 1725 if (lasx) { 1726 tcg_out_opc_xvldrepl_b(s, r, base, offset); 1727 } else { 1728 tcg_out_opc_vldrepl_b(s, r, base, offset); 1729 } 1730 break; 1731 case MO_16: 1732 if (lasx) { 1733 tcg_out_opc_xvldrepl_h(s, r, base, offset); 1734 } else { 1735 tcg_out_opc_vldrepl_h(s, r, base, offset); 1736 } 1737 break; 1738 case MO_32: 1739 if (lasx) { 1740 tcg_out_opc_xvldrepl_w(s, r, base, offset); 1741 } else { 1742 tcg_out_opc_vldrepl_w(s, r, base, offset); 1743 } 1744 break; 1745 case MO_64: 1746 if (lasx) { 1747 tcg_out_opc_xvldrepl_d(s, r, base, offset); 1748 } else { 1749 tcg_out_opc_vldrepl_d(s, r, base, offset); 1750 } 1751 break; 1752 default: 1753 g_assert_not_reached(); 1754 } 1755 return true; 1756} 1757 1758static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1759 TCGReg rd, int64_t v64) 1760{ 1761 /* Try vldi if imm can fit */ 1762 int64_t value = sextract64(v64, 0, 8 << vece); 1763 if (-0x200 <= value && value <= 0x1FF) { 1764 uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF); 1765 1766 if (type == TCG_TYPE_V256) { 1767 tcg_out_opc_xvldi(s, rd, imm); 1768 } else { 1769 tcg_out_opc_vldi(s, rd, imm); 1770 } 1771 return; 1772 } 1773 1774 /* TODO: vldi patterns when imm 12 is set */ 1775 1776 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value); 1777 tcg_out_dup_vec(s, type, vece, rd, TCG_REG_TMP0); 1778} 1779 1780static void tcg_out_addsub_vec(TCGContext *s, bool lasx, unsigned vece, 1781 TCGArg a0, TCGArg a1, TCGArg a2, 1782 bool a2_is_const, bool is_add) 1783{ 1784 static const LoongArchInsn add_vec_insn[2][4] = { 1785 { OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D }, 1786 { OPC_XVADD_B, OPC_XVADD_H, OPC_XVADD_W, OPC_XVADD_D }, 1787 }; 1788 static const LoongArchInsn add_vec_imm_insn[2][4] = { 1789 { OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU }, 1790 { OPC_XVADDI_BU, OPC_XVADDI_HU, OPC_XVADDI_WU, OPC_XVADDI_DU }, 1791 }; 1792 static const LoongArchInsn sub_vec_insn[2][4] = { 1793 { OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D }, 1794 { OPC_XVSUB_B, OPC_XVSUB_H, OPC_XVSUB_W, OPC_XVSUB_D }, 1795 }; 1796 static const LoongArchInsn sub_vec_imm_insn[2][4] = { 1797 { OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU }, 1798 { OPC_XVSUBI_BU, OPC_XVSUBI_HU, OPC_XVSUBI_WU, OPC_XVSUBI_DU }, 1799 }; 1800 LoongArchInsn insn; 1801 1802 if (a2_is_const) { 1803 int64_t value = sextract64(a2, 0, 8 << vece); 1804 1805 if (!is_add) { 1806 value = -value; 1807 } 1808 if (value < 0) { 1809 insn = sub_vec_imm_insn[lasx][vece]; 1810 value = -value; 1811 } else { 1812 insn = add_vec_imm_insn[lasx][vece]; 1813 } 1814 1815 /* Constraint TCG_CT_CONST_VADD ensures validity. */ 1816 tcg_debug_assert(0 <= value && value <= 0x1f); 1817 1818 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, value)); 1819 return; 1820 } 1821 1822 if (is_add) { 1823 insn = add_vec_insn[lasx][vece]; 1824 } else { 1825 insn = sub_vec_insn[lasx][vece]; 1826 } 1827 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 1828} 1829 1830static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 1831 unsigned vecl, unsigned vece, 1832 const TCGArg args[TCG_MAX_OP_ARGS], 1833 const int const_args[TCG_MAX_OP_ARGS]) 1834{ 1835 TCGType type = vecl + TCG_TYPE_V64; 1836 TCGArg a0, a1, a2, a3; 1837 TCGReg temp_vec = TCG_VEC_TMP0; 1838 1839 static const LoongArchInsn cmp_vec_insn[16][4] = { 1840 [TCG_COND_EQ] = {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D}, 1841 [TCG_COND_LE] = {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D}, 1842 [TCG_COND_LEU] = {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU}, 1843 [TCG_COND_LT] = {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D}, 1844 [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU}, 1845 }; 1846 static const LoongArchInsn cmp_vec_imm_insn[16][4] = { 1847 [TCG_COND_EQ] = {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D}, 1848 [TCG_COND_LE] = {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D}, 1849 [TCG_COND_LEU] = {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU}, 1850 [TCG_COND_LT] = {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D}, 1851 [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU}, 1852 }; 1853 LoongArchInsn insn; 1854 static const LoongArchInsn neg_vec_insn[4] = { 1855 OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D 1856 }; 1857 static const LoongArchInsn mul_vec_insn[4] = { 1858 OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D 1859 }; 1860 static const LoongArchInsn smin_vec_insn[4] = { 1861 OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D 1862 }; 1863 static const LoongArchInsn umin_vec_insn[4] = { 1864 OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU 1865 }; 1866 static const LoongArchInsn smax_vec_insn[4] = { 1867 OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D 1868 }; 1869 static const LoongArchInsn umax_vec_insn[4] = { 1870 OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU 1871 }; 1872 static const LoongArchInsn ssadd_vec_insn[4] = { 1873 OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D 1874 }; 1875 static const LoongArchInsn usadd_vec_insn[4] = { 1876 OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU 1877 }; 1878 static const LoongArchInsn sssub_vec_insn[4] = { 1879 OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D 1880 }; 1881 static const LoongArchInsn ussub_vec_insn[4] = { 1882 OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU 1883 }; 1884 static const LoongArchInsn shlv_vec_insn[4] = { 1885 OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D 1886 }; 1887 static const LoongArchInsn shrv_vec_insn[4] = { 1888 OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D 1889 }; 1890 static const LoongArchInsn sarv_vec_insn[4] = { 1891 OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D 1892 }; 1893 static const LoongArchInsn shli_vec_insn[4] = { 1894 OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D 1895 }; 1896 static const LoongArchInsn shri_vec_insn[4] = { 1897 OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D 1898 }; 1899 static const LoongArchInsn sari_vec_insn[4] = { 1900 OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D 1901 }; 1902 static const LoongArchInsn rotrv_vec_insn[4] = { 1903 OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D 1904 }; 1905 1906 a0 = args[0]; 1907 a1 = args[1]; 1908 a2 = args[2]; 1909 a3 = args[3]; 1910 1911 /* Currently only supports V64 & V128 */ 1912 tcg_debug_assert(type == TCG_TYPE_V64 || type == TCG_TYPE_V128); 1913 1914 switch (opc) { 1915 case INDEX_op_st_vec: 1916 tcg_out_st(s, type, a0, a1, a2); 1917 break; 1918 case INDEX_op_ld_vec: 1919 tcg_out_ld(s, type, a0, a1, a2); 1920 break; 1921 case INDEX_op_and_vec: 1922 insn = OPC_VAND_V; 1923 goto vdvjvk; 1924 case INDEX_op_andc_vec: 1925 /* 1926 * vandn vd, vj, vk: vd = vk & ~vj 1927 * andc_vec vd, vj, vk: vd = vj & ~vk 1928 * vj and vk are swapped 1929 */ 1930 a1 = a2; 1931 a2 = args[1]; 1932 insn = OPC_VANDN_V; 1933 goto vdvjvk; 1934 case INDEX_op_or_vec: 1935 insn = OPC_VOR_V; 1936 goto vdvjvk; 1937 case INDEX_op_orc_vec: 1938 insn = OPC_VORN_V; 1939 goto vdvjvk; 1940 case INDEX_op_xor_vec: 1941 insn = OPC_VXOR_V; 1942 goto vdvjvk; 1943 case INDEX_op_not_vec: 1944 a2 = a1; 1945 /* fall through */ 1946 case INDEX_op_nor_vec: 1947 insn = OPC_VNOR_V; 1948 goto vdvjvk; 1949 case INDEX_op_cmp_vec: 1950 { 1951 TCGCond cond = args[3]; 1952 1953 if (const_args[2]) { 1954 /* 1955 * cmp_vec dest, src, value 1956 * Try vseqi/vslei/vslti 1957 */ 1958 int64_t value = sextract64(a2, 0, 8 << vece); 1959 if ((cond == TCG_COND_EQ || 1960 cond == TCG_COND_LE || 1961 cond == TCG_COND_LT) && 1962 (-0x10 <= value && value <= 0x0f)) { 1963 insn = cmp_vec_imm_insn[cond][vece]; 1964 tcg_out32(s, encode_vdvjsk5_insn(insn, a0, a1, value)); 1965 break; 1966 } else if ((cond == TCG_COND_LEU || 1967 cond == TCG_COND_LTU) && 1968 (0x00 <= value && value <= 0x1f)) { 1969 insn = cmp_vec_imm_insn[cond][vece]; 1970 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, value)); 1971 break; 1972 } 1973 1974 /* 1975 * Fallback to: 1976 * dupi_vec temp, a2 1977 * cmp_vec a0, a1, temp, cond 1978 */ 1979 tcg_out_dupi_vec(s, type, vece, temp_vec, a2); 1980 a2 = temp_vec; 1981 } 1982 1983 insn = cmp_vec_insn[cond][vece]; 1984 if (insn == 0) { 1985 TCGArg t; 1986 t = a1, a1 = a2, a2 = t; 1987 cond = tcg_swap_cond(cond); 1988 insn = cmp_vec_insn[cond][vece]; 1989 tcg_debug_assert(insn != 0); 1990 } 1991 } 1992 goto vdvjvk; 1993 case INDEX_op_add_vec: 1994 tcg_out_addsub_vec(s, false, vece, a0, a1, a2, const_args[2], true); 1995 break; 1996 case INDEX_op_sub_vec: 1997 tcg_out_addsub_vec(s, false, vece, a0, a1, a2, const_args[2], false); 1998 break; 1999 case INDEX_op_neg_vec: 2000 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1)); 2001 break; 2002 case INDEX_op_mul_vec: 2003 insn = mul_vec_insn[vece]; 2004 goto vdvjvk; 2005 case INDEX_op_smin_vec: 2006 insn = smin_vec_insn[vece]; 2007 goto vdvjvk; 2008 case INDEX_op_smax_vec: 2009 insn = smax_vec_insn[vece]; 2010 goto vdvjvk; 2011 case INDEX_op_umin_vec: 2012 insn = umin_vec_insn[vece]; 2013 goto vdvjvk; 2014 case INDEX_op_umax_vec: 2015 insn = umax_vec_insn[vece]; 2016 goto vdvjvk; 2017 case INDEX_op_ssadd_vec: 2018 insn = ssadd_vec_insn[vece]; 2019 goto vdvjvk; 2020 case INDEX_op_usadd_vec: 2021 insn = usadd_vec_insn[vece]; 2022 goto vdvjvk; 2023 case INDEX_op_sssub_vec: 2024 insn = sssub_vec_insn[vece]; 2025 goto vdvjvk; 2026 case INDEX_op_ussub_vec: 2027 insn = ussub_vec_insn[vece]; 2028 goto vdvjvk; 2029 case INDEX_op_shlv_vec: 2030 insn = shlv_vec_insn[vece]; 2031 goto vdvjvk; 2032 case INDEX_op_shrv_vec: 2033 insn = shrv_vec_insn[vece]; 2034 goto vdvjvk; 2035 case INDEX_op_sarv_vec: 2036 insn = sarv_vec_insn[vece]; 2037 goto vdvjvk; 2038 case INDEX_op_shli_vec: 2039 tcg_out32(s, encode_vdvjuk3_insn(shli_vec_insn[vece], a0, a1, a2)); 2040 break; 2041 case INDEX_op_shri_vec: 2042 tcg_out32(s, encode_vdvjuk3_insn(shri_vec_insn[vece], a0, a1, a2)); 2043 break; 2044 case INDEX_op_sari_vec: 2045 tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2)); 2046 break; 2047 case INDEX_op_rotlv_vec: 2048 /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */ 2049 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], temp_vec, a2)); 2050 a2 = temp_vec; 2051 /* fall through */ 2052 case INDEX_op_rotrv_vec: 2053 insn = rotrv_vec_insn[vece]; 2054 goto vdvjvk; 2055 case INDEX_op_rotli_vec: 2056 /* rotli_vec a1, a2 = rotri_vec a1, -a2 */ 2057 a2 = extract32(-a2, 0, 3 + vece); 2058 switch (vece) { 2059 case MO_8: 2060 tcg_out_opc_vrotri_b(s, a0, a1, a2); 2061 break; 2062 case MO_16: 2063 tcg_out_opc_vrotri_h(s, a0, a1, a2); 2064 break; 2065 case MO_32: 2066 tcg_out_opc_vrotri_w(s, a0, a1, a2); 2067 break; 2068 case MO_64: 2069 tcg_out_opc_vrotri_d(s, a0, a1, a2); 2070 break; 2071 default: 2072 g_assert_not_reached(); 2073 } 2074 break; 2075 case INDEX_op_bitsel_vec: 2076 /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */ 2077 tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1); 2078 break; 2079 case INDEX_op_dupm_vec: 2080 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2081 break; 2082 default: 2083 g_assert_not_reached(); 2084 vdvjvk: 2085 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 2086 break; 2087 } 2088} 2089 2090int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2091{ 2092 switch (opc) { 2093 case INDEX_op_ld_vec: 2094 case INDEX_op_st_vec: 2095 case INDEX_op_dup_vec: 2096 case INDEX_op_dupm_vec: 2097 case INDEX_op_cmp_vec: 2098 case INDEX_op_add_vec: 2099 case INDEX_op_sub_vec: 2100 case INDEX_op_and_vec: 2101 case INDEX_op_andc_vec: 2102 case INDEX_op_or_vec: 2103 case INDEX_op_orc_vec: 2104 case INDEX_op_xor_vec: 2105 case INDEX_op_nor_vec: 2106 case INDEX_op_not_vec: 2107 case INDEX_op_neg_vec: 2108 case INDEX_op_mul_vec: 2109 case INDEX_op_smin_vec: 2110 case INDEX_op_smax_vec: 2111 case INDEX_op_umin_vec: 2112 case INDEX_op_umax_vec: 2113 case INDEX_op_ssadd_vec: 2114 case INDEX_op_usadd_vec: 2115 case INDEX_op_sssub_vec: 2116 case INDEX_op_ussub_vec: 2117 case INDEX_op_shlv_vec: 2118 case INDEX_op_shrv_vec: 2119 case INDEX_op_sarv_vec: 2120 case INDEX_op_bitsel_vec: 2121 return 1; 2122 default: 2123 return 0; 2124 } 2125} 2126 2127void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2128 TCGArg a0, ...) 2129{ 2130 g_assert_not_reached(); 2131} 2132 2133static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2134{ 2135 switch (op) { 2136 case INDEX_op_goto_ptr: 2137 return C_O0_I1(r); 2138 2139 case INDEX_op_st8_i32: 2140 case INDEX_op_st8_i64: 2141 case INDEX_op_st16_i32: 2142 case INDEX_op_st16_i64: 2143 case INDEX_op_st32_i64: 2144 case INDEX_op_st_i32: 2145 case INDEX_op_st_i64: 2146 case INDEX_op_qemu_st_a32_i32: 2147 case INDEX_op_qemu_st_a64_i32: 2148 case INDEX_op_qemu_st_a32_i64: 2149 case INDEX_op_qemu_st_a64_i64: 2150 return C_O0_I2(rZ, r); 2151 2152 case INDEX_op_qemu_ld_a32_i128: 2153 case INDEX_op_qemu_ld_a64_i128: 2154 return C_N2_I1(r, r, r); 2155 2156 case INDEX_op_qemu_st_a32_i128: 2157 case INDEX_op_qemu_st_a64_i128: 2158 return C_O0_I3(r, r, r); 2159 2160 case INDEX_op_brcond_i32: 2161 case INDEX_op_brcond_i64: 2162 return C_O0_I2(rZ, rZ); 2163 2164 case INDEX_op_ext8s_i32: 2165 case INDEX_op_ext8s_i64: 2166 case INDEX_op_ext8u_i32: 2167 case INDEX_op_ext8u_i64: 2168 case INDEX_op_ext16s_i32: 2169 case INDEX_op_ext16s_i64: 2170 case INDEX_op_ext16u_i32: 2171 case INDEX_op_ext16u_i64: 2172 case INDEX_op_ext32s_i64: 2173 case INDEX_op_ext32u_i64: 2174 case INDEX_op_extu_i32_i64: 2175 case INDEX_op_extrl_i64_i32: 2176 case INDEX_op_extrh_i64_i32: 2177 case INDEX_op_ext_i32_i64: 2178 case INDEX_op_neg_i32: 2179 case INDEX_op_neg_i64: 2180 case INDEX_op_not_i32: 2181 case INDEX_op_not_i64: 2182 case INDEX_op_extract_i32: 2183 case INDEX_op_extract_i64: 2184 case INDEX_op_bswap16_i32: 2185 case INDEX_op_bswap16_i64: 2186 case INDEX_op_bswap32_i32: 2187 case INDEX_op_bswap32_i64: 2188 case INDEX_op_bswap64_i64: 2189 case INDEX_op_ld8s_i32: 2190 case INDEX_op_ld8s_i64: 2191 case INDEX_op_ld8u_i32: 2192 case INDEX_op_ld8u_i64: 2193 case INDEX_op_ld16s_i32: 2194 case INDEX_op_ld16s_i64: 2195 case INDEX_op_ld16u_i32: 2196 case INDEX_op_ld16u_i64: 2197 case INDEX_op_ld32s_i64: 2198 case INDEX_op_ld32u_i64: 2199 case INDEX_op_ld_i32: 2200 case INDEX_op_ld_i64: 2201 case INDEX_op_qemu_ld_a32_i32: 2202 case INDEX_op_qemu_ld_a64_i32: 2203 case INDEX_op_qemu_ld_a32_i64: 2204 case INDEX_op_qemu_ld_a64_i64: 2205 return C_O1_I1(r, r); 2206 2207 case INDEX_op_andc_i32: 2208 case INDEX_op_andc_i64: 2209 case INDEX_op_orc_i32: 2210 case INDEX_op_orc_i64: 2211 /* 2212 * LoongArch insns for these ops don't have reg-imm forms, but we 2213 * can express using andi/ori if ~constant satisfies 2214 * TCG_CT_CONST_U12. 2215 */ 2216 return C_O1_I2(r, r, rC); 2217 2218 case INDEX_op_shl_i32: 2219 case INDEX_op_shl_i64: 2220 case INDEX_op_shr_i32: 2221 case INDEX_op_shr_i64: 2222 case INDEX_op_sar_i32: 2223 case INDEX_op_sar_i64: 2224 case INDEX_op_rotl_i32: 2225 case INDEX_op_rotl_i64: 2226 case INDEX_op_rotr_i32: 2227 case INDEX_op_rotr_i64: 2228 return C_O1_I2(r, r, ri); 2229 2230 case INDEX_op_add_i32: 2231 return C_O1_I2(r, r, ri); 2232 case INDEX_op_add_i64: 2233 return C_O1_I2(r, r, rJ); 2234 2235 case INDEX_op_and_i32: 2236 case INDEX_op_and_i64: 2237 case INDEX_op_nor_i32: 2238 case INDEX_op_nor_i64: 2239 case INDEX_op_or_i32: 2240 case INDEX_op_or_i64: 2241 case INDEX_op_xor_i32: 2242 case INDEX_op_xor_i64: 2243 /* LoongArch reg-imm bitops have their imms ZERO-extended */ 2244 return C_O1_I2(r, r, rU); 2245 2246 case INDEX_op_clz_i32: 2247 case INDEX_op_clz_i64: 2248 case INDEX_op_ctz_i32: 2249 case INDEX_op_ctz_i64: 2250 return C_O1_I2(r, r, rW); 2251 2252 case INDEX_op_deposit_i32: 2253 case INDEX_op_deposit_i64: 2254 /* Must deposit into the same register as input */ 2255 return C_O1_I2(r, 0, rZ); 2256 2257 case INDEX_op_sub_i32: 2258 case INDEX_op_setcond_i32: 2259 return C_O1_I2(r, rZ, ri); 2260 case INDEX_op_sub_i64: 2261 case INDEX_op_setcond_i64: 2262 return C_O1_I2(r, rZ, rJ); 2263 2264 case INDEX_op_mul_i32: 2265 case INDEX_op_mul_i64: 2266 case INDEX_op_mulsh_i32: 2267 case INDEX_op_mulsh_i64: 2268 case INDEX_op_muluh_i32: 2269 case INDEX_op_muluh_i64: 2270 case INDEX_op_div_i32: 2271 case INDEX_op_div_i64: 2272 case INDEX_op_divu_i32: 2273 case INDEX_op_divu_i64: 2274 case INDEX_op_rem_i32: 2275 case INDEX_op_rem_i64: 2276 case INDEX_op_remu_i32: 2277 case INDEX_op_remu_i64: 2278 return C_O1_I2(r, rZ, rZ); 2279 2280 case INDEX_op_movcond_i32: 2281 case INDEX_op_movcond_i64: 2282 return C_O1_I4(r, rZ, rJ, rZ, rZ); 2283 2284 case INDEX_op_ld_vec: 2285 case INDEX_op_dupm_vec: 2286 case INDEX_op_dup_vec: 2287 return C_O1_I1(w, r); 2288 2289 case INDEX_op_st_vec: 2290 return C_O0_I2(w, r); 2291 2292 case INDEX_op_cmp_vec: 2293 return C_O1_I2(w, w, wM); 2294 2295 case INDEX_op_add_vec: 2296 case INDEX_op_sub_vec: 2297 return C_O1_I2(w, w, wA); 2298 2299 case INDEX_op_and_vec: 2300 case INDEX_op_andc_vec: 2301 case INDEX_op_or_vec: 2302 case INDEX_op_orc_vec: 2303 case INDEX_op_xor_vec: 2304 case INDEX_op_nor_vec: 2305 case INDEX_op_mul_vec: 2306 case INDEX_op_smin_vec: 2307 case INDEX_op_smax_vec: 2308 case INDEX_op_umin_vec: 2309 case INDEX_op_umax_vec: 2310 case INDEX_op_ssadd_vec: 2311 case INDEX_op_usadd_vec: 2312 case INDEX_op_sssub_vec: 2313 case INDEX_op_ussub_vec: 2314 case INDEX_op_shlv_vec: 2315 case INDEX_op_shrv_vec: 2316 case INDEX_op_sarv_vec: 2317 case INDEX_op_rotrv_vec: 2318 case INDEX_op_rotlv_vec: 2319 return C_O1_I2(w, w, w); 2320 2321 case INDEX_op_not_vec: 2322 case INDEX_op_neg_vec: 2323 case INDEX_op_shli_vec: 2324 case INDEX_op_shri_vec: 2325 case INDEX_op_sari_vec: 2326 case INDEX_op_rotli_vec: 2327 return C_O1_I1(w, w); 2328 2329 case INDEX_op_bitsel_vec: 2330 return C_O1_I3(w, w, w, w); 2331 2332 default: 2333 g_assert_not_reached(); 2334 } 2335} 2336 2337static const int tcg_target_callee_save_regs[] = { 2338 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2339 TCG_REG_S1, 2340 TCG_REG_S2, 2341 TCG_REG_S3, 2342 TCG_REG_S4, 2343 TCG_REG_S5, 2344 TCG_REG_S6, 2345 TCG_REG_S7, 2346 TCG_REG_S8, 2347 TCG_REG_S9, 2348 TCG_REG_RA, /* should be last for ABI compliance */ 2349}; 2350 2351/* Stack frame parameters. */ 2352#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2353#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2354#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2355#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2356 + TCG_TARGET_STACK_ALIGN - 1) \ 2357 & -TCG_TARGET_STACK_ALIGN) 2358#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2359 2360/* We're expecting to be able to use an immediate for frame allocation. */ 2361QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2362 2363/* Generate global QEMU prologue and epilogue code */ 2364static void tcg_target_qemu_prologue(TCGContext *s) 2365{ 2366 int i; 2367 2368 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2369 2370 /* TB prologue */ 2371 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2372 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2373 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2374 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2375 } 2376 2377 if (!tcg_use_softmmu && guest_base) { 2378 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2379 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2380 } 2381 2382 /* Call generated code */ 2383 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2384 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2385 2386 /* Return path for goto_ptr. Set return value to 0 */ 2387 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2388 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2389 2390 /* TB epilogue */ 2391 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2392 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2393 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2394 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2395 } 2396 2397 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2398 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 2399} 2400 2401static void tcg_out_tb_start(TCGContext *s) 2402{ 2403 /* nothing to do */ 2404} 2405 2406static void tcg_target_init(TCGContext *s) 2407{ 2408 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2409 2410 /* Server and desktop class cpus have UAL; embedded cpus do not. */ 2411 if (!(hwcap & HWCAP_LOONGARCH_UAL)) { 2412 error_report("TCG: unaligned access support required; exiting"); 2413 exit(EXIT_FAILURE); 2414 } 2415 2416 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2417 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 2418 2419 tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; 2420 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2421 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2422 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2423 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2424 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2425 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2426 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2427 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2428 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2429 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2430 2431 if (cpuinfo & CPUINFO_LSX) { 2432 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2433 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2434 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 2435 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 2436 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 2437 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 2438 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 2439 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 2440 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 2441 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 2442 } 2443 2444 s->reserved_regs = 0; 2445 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2446 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2447 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2448 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2449 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2450 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2451 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 2452 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 2453} 2454 2455typedef struct { 2456 DebugFrameHeader h; 2457 uint8_t fde_def_cfa[4]; 2458 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2459} DebugFrame; 2460 2461#define ELF_HOST_MACHINE EM_LOONGARCH 2462 2463static const DebugFrame debug_frame = { 2464 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2465 .h.cie.id = -1, 2466 .h.cie.version = 1, 2467 .h.cie.code_align = 1, 2468 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2469 .h.cie.return_column = TCG_REG_RA, 2470 2471 /* Total FDE size does not include the "len" member. */ 2472 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2473 2474 .fde_def_cfa = { 2475 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2476 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2477 (FRAME_SIZE >> 7) 2478 }, 2479 .fde_reg_ofs = { 2480 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 2481 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 2482 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 2483 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 2484 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 2485 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 2486 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 2487 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 2488 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 2489 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 2490 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 2491 } 2492}; 2493 2494void tcg_register_jit(const void *buf, size_t buf_size) 2495{ 2496 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2497} 2498