1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include "../tcg-ldst.c.inc" 33#include <asm/hwcap.h> 34 35#ifdef CONFIG_DEBUG_TCG 36static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 37 "zero", 38 "ra", 39 "tp", 40 "sp", 41 "a0", 42 "a1", 43 "a2", 44 "a3", 45 "a4", 46 "a5", 47 "a6", 48 "a7", 49 "t0", 50 "t1", 51 "t2", 52 "t3", 53 "t4", 54 "t5", 55 "t6", 56 "t7", 57 "t8", 58 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 59 "s9", 60 "s0", 61 "s1", 62 "s2", 63 "s3", 64 "s4", 65 "s5", 66 "s6", 67 "s7", 68 "s8", 69 "vr0", 70 "vr1", 71 "vr2", 72 "vr3", 73 "vr4", 74 "vr5", 75 "vr6", 76 "vr7", 77 "vr8", 78 "vr9", 79 "vr10", 80 "vr11", 81 "vr12", 82 "vr13", 83 "vr14", 84 "vr15", 85 "vr16", 86 "vr17", 87 "vr18", 88 "vr19", 89 "vr20", 90 "vr21", 91 "vr22", 92 "vr23", 93 "vr24", 94 "vr25", 95 "vr26", 96 "vr27", 97 "vr28", 98 "vr29", 99 "vr30", 100 "vr31", 101}; 102#endif 103 104static const int tcg_target_reg_alloc_order[] = { 105 /* Registers preserved across calls */ 106 /* TCG_REG_S0 reserved for TCG_AREG0 */ 107 TCG_REG_S1, 108 TCG_REG_S2, 109 TCG_REG_S3, 110 TCG_REG_S4, 111 TCG_REG_S5, 112 TCG_REG_S6, 113 TCG_REG_S7, 114 TCG_REG_S8, 115 TCG_REG_S9, 116 117 /* Registers (potentially) clobbered across calls */ 118 TCG_REG_T0, 119 TCG_REG_T1, 120 TCG_REG_T2, 121 TCG_REG_T3, 122 TCG_REG_T4, 123 TCG_REG_T5, 124 TCG_REG_T6, 125 TCG_REG_T7, 126 TCG_REG_T8, 127 128 /* Argument registers, opposite order of allocation. */ 129 TCG_REG_A7, 130 TCG_REG_A6, 131 TCG_REG_A5, 132 TCG_REG_A4, 133 TCG_REG_A3, 134 TCG_REG_A2, 135 TCG_REG_A1, 136 TCG_REG_A0, 137 138 /* Vector registers */ 139 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 140 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 141 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 142 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 143 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 144 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 145 /* V24 - V31 are caller-saved, and skipped. */ 146}; 147 148static const int tcg_target_call_iarg_regs[] = { 149 TCG_REG_A0, 150 TCG_REG_A1, 151 TCG_REG_A2, 152 TCG_REG_A3, 153 TCG_REG_A4, 154 TCG_REG_A5, 155 TCG_REG_A6, 156 TCG_REG_A7, 157}; 158 159static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 160{ 161 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 162 tcg_debug_assert(slot >= 0 && slot <= 1); 163 return TCG_REG_A0 + slot; 164} 165 166#define TCG_GUEST_BASE_REG TCG_REG_S1 167 168#define TCG_CT_CONST_ZERO 0x100 169#define TCG_CT_CONST_S12 0x200 170#define TCG_CT_CONST_S32 0x400 171#define TCG_CT_CONST_U12 0x800 172#define TCG_CT_CONST_C12 0x1000 173#define TCG_CT_CONST_WSZ 0x2000 174#define TCG_CT_CONST_VCMP 0x4000 175#define TCG_CT_CONST_VADD 0x8000 176 177#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 178#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 179 180static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 181{ 182 return sextract64(val, pos, len); 183} 184 185/* test if a constant matches the constraint */ 186static bool tcg_target_const_match(int64_t val, int ct, 187 TCGType type, TCGCond cond, int vece) 188{ 189 if (ct & TCG_CT_CONST) { 190 return true; 191 } 192 if ((ct & TCG_CT_CONST_ZERO) && val == 0) { 193 return true; 194 } 195 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 196 return true; 197 } 198 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 199 return true; 200 } 201 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 202 return true; 203 } 204 if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) { 205 return true; 206 } 207 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return true; 209 } 210 int64_t vec_val = sextract64(val, 0, 8 << vece); 211 if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) { 212 return true; 213 } 214 if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) { 215 return true; 216 } 217 return false; 218} 219 220/* 221 * Relocations 222 */ 223 224/* 225 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 226 * complicated; a whopping stack machine is needed to stuff the fields, at 227 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 228 * needed. 229 * 230 * Hence, define our own simpler relocation types. Numbers are chosen as to 231 * not collide with potential future additions to the true ELF relocation 232 * type enum. 233 */ 234 235/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 236#define R_LOONGARCH_BR_SK16 256 237/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 238#define R_LOONGARCH_BR_SD10K16 257 239 240static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 241{ 242 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 243 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 244 245 tcg_debug_assert((offset & 3) == 0); 246 offset >>= 2; 247 if (offset == sextreg(offset, 0, 16)) { 248 *src_rw = deposit64(*src_rw, 10, 16, offset); 249 return true; 250 } 251 252 return false; 253} 254 255static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 256 const tcg_insn_unit *target) 257{ 258 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 259 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 260 261 tcg_debug_assert((offset & 3) == 0); 262 offset >>= 2; 263 if (offset == sextreg(offset, 0, 26)) { 264 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 265 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 266 return true; 267 } 268 269 return false; 270} 271 272static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 273 intptr_t value, intptr_t addend) 274{ 275 tcg_debug_assert(addend == 0); 276 switch (type) { 277 case R_LOONGARCH_BR_SK16: 278 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 279 case R_LOONGARCH_BR_SD10K16: 280 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 281 default: 282 g_assert_not_reached(); 283 } 284} 285 286#include "tcg-insn-defs.c.inc" 287 288/* 289 * TCG intrinsics 290 */ 291 292static void tcg_out_mb(TCGContext *s, TCGArg a0) 293{ 294 /* Baseline LoongArch only has the full barrier, unfortunately. */ 295 tcg_out_opc_dbar(s, 0); 296} 297 298static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 299{ 300 if (ret == arg) { 301 return true; 302 } 303 switch (type) { 304 case TCG_TYPE_I32: 305 case TCG_TYPE_I64: 306 /* 307 * Conventional register-register move used in LoongArch is 308 * `or dst, src, zero`. 309 */ 310 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 311 break; 312 case TCG_TYPE_V128: 313 tcg_out_opc_vori_b(s, ret, arg, 0); 314 break; 315 default: 316 g_assert_not_reached(); 317 } 318 return true; 319} 320 321/* Loads a 32-bit immediate into rd, sign-extended. */ 322static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 323{ 324 tcg_target_long lo = sextreg(val, 0, 12); 325 tcg_target_long hi12 = sextreg(val, 12, 20); 326 327 /* Single-instruction cases. */ 328 if (hi12 == 0) { 329 /* val fits in uimm12: ori rd, zero, val */ 330 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 331 return; 332 } 333 if (hi12 == sextreg(lo, 12, 20)) { 334 /* val fits in simm12: addi.w rd, zero, val */ 335 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 336 return; 337 } 338 339 /* High bits must be set; load with lu12i.w + optional ori. */ 340 tcg_out_opc_lu12i_w(s, rd, hi12); 341 if (lo != 0) { 342 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 343 } 344} 345 346static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 347 tcg_target_long val) 348{ 349 /* 350 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 351 * with dedicated instructions for filling the respective bitfields 352 * below: 353 * 354 * 6 5 4 3 355 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 356 * +-----------------------+---------------------------------------+... 357 * | hi52 | hi32 | 358 * +-----------------------+---------------------------------------+... 359 * 3 2 1 360 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 361 * ...+-------------------------------------+-------------------------+ 362 * | hi12 | lo | 363 * ...+-------------------------------------+-------------------------+ 364 * 365 * Check if val belong to one of the several fast cases, before falling 366 * back to the slow path. 367 */ 368 369 intptr_t pc_offset; 370 tcg_target_long val_lo, val_hi, pc_hi, offset_hi; 371 tcg_target_long hi12, hi32, hi52; 372 373 /* Value fits in signed i32. */ 374 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 375 tcg_out_movi_i32(s, rd, val); 376 return; 377 } 378 379 /* PC-relative cases. */ 380 pc_offset = tcg_pcrel_diff(s, (void *)val); 381 if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) { 382 /* Single pcaddu2i. */ 383 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 384 return; 385 } 386 387 if (pc_offset == (int32_t)pc_offset) { 388 /* Offset within 32 bits; load with pcalau12i + ori. */ 389 val_lo = sextreg(val, 0, 12); 390 val_hi = val >> 12; 391 pc_hi = (val - pc_offset) >> 12; 392 offset_hi = val_hi - pc_hi; 393 394 tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20)); 395 tcg_out_opc_pcalau12i(s, rd, offset_hi); 396 if (val_lo != 0) { 397 tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff); 398 } 399 return; 400 } 401 402 hi12 = sextreg(val, 12, 20); 403 hi32 = sextreg(val, 32, 20); 404 hi52 = sextreg(val, 52, 12); 405 406 /* Single cu52i.d case. */ 407 if ((hi52 != 0) && (ctz64(val) >= 52)) { 408 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 409 return; 410 } 411 412 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 413 tcg_out_movi_i32(s, rd, val); 414 415 /* Load hi32 and hi52 explicitly when they are unexpected values. */ 416 if (hi32 != sextreg(hi12, 20, 20)) { 417 tcg_out_opc_cu32i_d(s, rd, hi32); 418 } 419 420 if (hi52 != sextreg(hi32, 20, 12)) { 421 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 422 } 423} 424 425static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, 426 TCGReg rs, tcg_target_long imm) 427{ 428 tcg_target_long lo12 = sextreg(imm, 0, 12); 429 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16); 430 431 /* 432 * Note that there's a hole in between hi16 and lo12: 433 * 434 * 3 2 1 0 435 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 436 * ...+-------------------------------+-------+-----------------------+ 437 * | hi16 | | lo12 | 438 * ...+-------------------------------+-------+-----------------------+ 439 * 440 * For bits within that hole, it's more efficient to use LU12I and ADD. 441 */ 442 if (imm == (hi16 << 16) + lo12) { 443 if (hi16) { 444 tcg_out_opc_addu16i_d(s, rd, rs, hi16); 445 rs = rd; 446 } 447 if (type == TCG_TYPE_I32) { 448 tcg_out_opc_addi_w(s, rd, rs, lo12); 449 } else if (lo12) { 450 tcg_out_opc_addi_d(s, rd, rs, lo12); 451 } else { 452 tcg_out_mov(s, type, rd, rs); 453 } 454 } else { 455 tcg_out_movi(s, type, TCG_REG_TMP0, imm); 456 if (type == TCG_TYPE_I32) { 457 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); 458 } else { 459 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); 460 } 461 } 462} 463 464static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 465{ 466 return false; 467} 468 469static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 470 tcg_target_long imm) 471{ 472 /* This function is only used for passing structs by reference. */ 473 g_assert_not_reached(); 474} 475 476static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 477{ 478 tcg_out_opc_andi(s, ret, arg, 0xff); 479} 480 481static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 482{ 483 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 484} 485 486static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 487{ 488 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 489} 490 491static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 492{ 493 tcg_out_opc_sext_b(s, ret, arg); 494} 495 496static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 497{ 498 tcg_out_opc_sext_h(s, ret, arg); 499} 500 501static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 502{ 503 tcg_out_opc_addi_w(s, ret, arg, 0); 504} 505 506static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 507{ 508 if (ret != arg) { 509 tcg_out_ext32s(s, ret, arg); 510 } 511} 512 513static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 514{ 515 tcg_out_ext32u(s, ret, arg); 516} 517 518static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 519{ 520 tcg_out_ext32s(s, ret, arg); 521} 522 523static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc, 524 TCGReg a0, TCGReg a1, TCGReg a2, 525 bool c2, bool is_32bit) 526{ 527 if (c2) { 528 /* 529 * Fast path: semantics already satisfied due to constraint and 530 * insn behavior, single instruction is enough. 531 */ 532 tcg_debug_assert(a2 == (is_32bit ? 32 : 64)); 533 /* all clz/ctz insns belong to DJ-format */ 534 tcg_out32(s, encode_dj_insn(opc, a0, a1)); 535 return; 536 } 537 538 tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1)); 539 /* a0 = a1 ? REG_TMP0 : a2 */ 540 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 541 tcg_out_opc_masknez(s, a0, a2, a1); 542 tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0); 543} 544 545#define SETCOND_INV TCG_TARGET_NB_REGS 546#define SETCOND_NEZ (SETCOND_INV << 1) 547#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 548 549static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 550 TCGReg arg1, tcg_target_long arg2, bool c2) 551{ 552 int flags = 0; 553 554 switch (cond) { 555 case TCG_COND_EQ: /* -> NE */ 556 case TCG_COND_GE: /* -> LT */ 557 case TCG_COND_GEU: /* -> LTU */ 558 case TCG_COND_GT: /* -> LE */ 559 case TCG_COND_GTU: /* -> LEU */ 560 cond = tcg_invert_cond(cond); 561 flags ^= SETCOND_INV; 562 break; 563 default: 564 break; 565 } 566 567 switch (cond) { 568 case TCG_COND_LE: 569 case TCG_COND_LEU: 570 /* 571 * If we have a constant input, the most efficient way to implement 572 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 573 * We don't need to care for this for LE because the constant input 574 * is still constrained to int32_t, and INT32_MAX+1 is representable 575 * in the 64-bit temporary register. 576 */ 577 if (c2) { 578 if (cond == TCG_COND_LEU) { 579 /* unsigned <= -1 is true */ 580 if (arg2 == -1) { 581 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 582 return ret; 583 } 584 cond = TCG_COND_LTU; 585 } else { 586 cond = TCG_COND_LT; 587 } 588 arg2 += 1; 589 } else { 590 TCGReg tmp = arg2; 591 arg2 = arg1; 592 arg1 = tmp; 593 cond = tcg_swap_cond(cond); /* LE -> GE */ 594 cond = tcg_invert_cond(cond); /* GE -> LT */ 595 flags ^= SETCOND_INV; 596 } 597 break; 598 default: 599 break; 600 } 601 602 switch (cond) { 603 case TCG_COND_NE: 604 flags |= SETCOND_NEZ; 605 if (!c2) { 606 tcg_out_opc_xor(s, ret, arg1, arg2); 607 } else if (arg2 == 0) { 608 ret = arg1; 609 } else if (arg2 >= 0 && arg2 <= 0xfff) { 610 tcg_out_opc_xori(s, ret, arg1, arg2); 611 } else { 612 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2); 613 } 614 break; 615 616 case TCG_COND_LT: 617 case TCG_COND_LTU: 618 if (c2) { 619 if (arg2 >= -0x800 && arg2 <= 0x7ff) { 620 if (cond == TCG_COND_LT) { 621 tcg_out_opc_slti(s, ret, arg1, arg2); 622 } else { 623 tcg_out_opc_sltui(s, ret, arg1, arg2); 624 } 625 break; 626 } 627 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 628 arg2 = TCG_REG_TMP0; 629 } 630 if (cond == TCG_COND_LT) { 631 tcg_out_opc_slt(s, ret, arg1, arg2); 632 } else { 633 tcg_out_opc_sltu(s, ret, arg1, arg2); 634 } 635 break; 636 637 default: 638 g_assert_not_reached(); 639 break; 640 } 641 642 return ret | flags; 643} 644 645static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 646 TCGReg arg1, tcg_target_long arg2, bool c2) 647{ 648 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 649 650 if (tmpflags != ret) { 651 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 652 653 switch (tmpflags & SETCOND_FLAGS) { 654 case SETCOND_INV: 655 /* Intermediate result is boolean: simply invert. */ 656 tcg_out_opc_xori(s, ret, tmp, 1); 657 break; 658 case SETCOND_NEZ: 659 /* Intermediate result is zero/non-zero: test != 0. */ 660 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 661 break; 662 case SETCOND_NEZ | SETCOND_INV: 663 /* Intermediate result is zero/non-zero: test == 0. */ 664 tcg_out_opc_sltui(s, ret, tmp, 1); 665 break; 666 default: 667 g_assert_not_reached(); 668 } 669 } 670} 671 672static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret, 673 TCGReg c1, tcg_target_long c2, bool const2, 674 TCGReg v1, TCGReg v2) 675{ 676 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2); 677 TCGReg t; 678 679 /* Standardize the test below to t != 0. */ 680 if (tmpflags & SETCOND_INV) { 681 t = v1, v1 = v2, v2 = t; 682 } 683 684 t = tmpflags & ~SETCOND_FLAGS; 685 if (v1 == TCG_REG_ZERO) { 686 tcg_out_opc_masknez(s, ret, v2, t); 687 } else if (v2 == TCG_REG_ZERO) { 688 tcg_out_opc_maskeqz(s, ret, v1, t); 689 } else { 690 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */ 691 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */ 692 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2); 693 } 694} 695 696/* 697 * Branch helpers 698 */ 699 700static const struct { 701 LoongArchInsn op; 702 bool swap; 703} tcg_brcond_to_loongarch[] = { 704 [TCG_COND_EQ] = { OPC_BEQ, false }, 705 [TCG_COND_NE] = { OPC_BNE, false }, 706 [TCG_COND_LT] = { OPC_BGT, true }, 707 [TCG_COND_GE] = { OPC_BLE, true }, 708 [TCG_COND_LE] = { OPC_BLE, false }, 709 [TCG_COND_GT] = { OPC_BGT, false }, 710 [TCG_COND_LTU] = { OPC_BGTU, true }, 711 [TCG_COND_GEU] = { OPC_BLEU, true }, 712 [TCG_COND_LEU] = { OPC_BLEU, false }, 713 [TCG_COND_GTU] = { OPC_BGTU, false } 714}; 715 716static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, 717 TCGReg arg2, TCGLabel *l) 718{ 719 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 720 721 tcg_debug_assert(op != 0); 722 723 if (tcg_brcond_to_loongarch[cond].swap) { 724 TCGReg t = arg1; 725 arg1 = arg2; 726 arg2 = t; 727 } 728 729 /* all conditional branch insns belong to DJSk16-format */ 730 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 731 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 732} 733 734static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 735{ 736 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 737 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 738 739 tcg_debug_assert((offset & 3) == 0); 740 if (offset == sextreg(offset, 0, 28)) { 741 /* short jump: +/- 256MiB */ 742 if (tail) { 743 tcg_out_opc_b(s, offset >> 2); 744 } else { 745 tcg_out_opc_bl(s, offset >> 2); 746 } 747 } else if (offset == sextreg(offset, 0, 38)) { 748 /* long jump: +/- 256GiB */ 749 tcg_target_long lo = sextreg(offset, 0, 18); 750 tcg_target_long hi = offset - lo; 751 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 752 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 753 } else { 754 /* far jump: 64-bit */ 755 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 756 tcg_target_long hi = (tcg_target_long)arg - lo; 757 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 758 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 759 } 760} 761 762static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 763 const TCGHelperInfo *info) 764{ 765 tcg_out_call_int(s, arg, false); 766} 767 768/* 769 * Load/store helpers 770 */ 771 772static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 773 TCGReg addr, intptr_t offset) 774{ 775 intptr_t imm12 = sextreg(offset, 0, 12); 776 777 if (offset != imm12) { 778 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 779 780 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 781 imm12 = sextreg(diff, 0, 12); 782 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 783 } else { 784 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 785 if (addr != TCG_REG_ZERO) { 786 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 787 } 788 } 789 addr = TCG_REG_TMP2; 790 } 791 792 switch (opc) { 793 case OPC_LD_B: 794 case OPC_LD_BU: 795 case OPC_LD_H: 796 case OPC_LD_HU: 797 case OPC_LD_W: 798 case OPC_LD_WU: 799 case OPC_LD_D: 800 case OPC_ST_B: 801 case OPC_ST_H: 802 case OPC_ST_W: 803 case OPC_ST_D: 804 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 805 break; 806 default: 807 g_assert_not_reached(); 808 } 809} 810 811static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, 812 TCGReg arg1, intptr_t arg2) 813{ 814 bool is_32bit = type == TCG_TYPE_I32; 815 tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2); 816} 817 818static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, 819 TCGReg arg1, intptr_t arg2) 820{ 821 bool is_32bit = type == TCG_TYPE_I32; 822 tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2); 823} 824 825static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 826 TCGReg base, intptr_t ofs) 827{ 828 if (val == 0) { 829 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 830 return true; 831 } 832 return false; 833} 834 835/* 836 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 837 */ 838 839static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 840{ 841 tcg_out_opc_b(s, 0); 842 return reloc_br_sd10k16(s->code_ptr - 1, target); 843} 844 845static const TCGLdstHelperParam ldst_helper_param = { 846 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 847}; 848 849static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 850{ 851 MemOp opc = get_memop(l->oi); 852 853 /* resolve label address */ 854 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 855 return false; 856 } 857 858 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 859 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); 860 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 861 return tcg_out_goto(s, l->raddr); 862} 863 864static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 865{ 866 MemOp opc = get_memop(l->oi); 867 868 /* resolve label address */ 869 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 870 return false; 871 } 872 873 tcg_out_st_helper_args(s, l, &ldst_helper_param); 874 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 875 return tcg_out_goto(s, l->raddr); 876} 877 878typedef struct { 879 TCGReg base; 880 TCGReg index; 881 TCGAtomAlign aa; 882} HostAddress; 883 884bool tcg_target_has_memory_bswap(MemOp memop) 885{ 886 return false; 887} 888 889/* We expect to use a 12-bit negative offset from ENV. */ 890#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 891 892/* 893 * For system-mode, perform the TLB load and compare. 894 * For user-mode, perform any required alignment tests. 895 * In both cases, return a TCGLabelQemuLdst structure if the slow path 896 * is required and fill in @h with the host address for the fast path. 897 */ 898static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 899 TCGReg addr_reg, MemOpIdx oi, 900 bool is_ld) 901{ 902 TCGType addr_type = s->addr_type; 903 TCGLabelQemuLdst *ldst = NULL; 904 MemOp opc = get_memop(oi); 905 MemOp a_bits; 906 907 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 908 a_bits = h->aa.align; 909 910 if (tcg_use_softmmu) { 911 unsigned s_bits = opc & MO_SIZE; 912 int mem_index = get_mmuidx(oi); 913 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 914 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 915 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 916 917 ldst = new_ldst_label(s); 918 ldst->is_ld = is_ld; 919 ldst->oi = oi; 920 ldst->addrlo_reg = addr_reg; 921 922 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 923 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 924 925 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, 926 s->page_bits - CPU_TLB_ENTRY_BITS); 927 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 928 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 929 930 /* Load the tlb comparator and the addend. */ 931 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 932 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 933 is_ld ? offsetof(CPUTLBEntry, addr_read) 934 : offsetof(CPUTLBEntry, addr_write)); 935 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 936 offsetof(CPUTLBEntry, addend)); 937 938 /* 939 * For aligned accesses, we check the first byte and include the 940 * alignment bits within the address. For unaligned access, we 941 * check that we don't cross pages using the address of the last 942 * byte of the access. 943 */ 944 if (a_bits < s_bits) { 945 unsigned a_mask = (1u << a_bits) - 1; 946 unsigned s_mask = (1u << s_bits) - 1; 947 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask); 948 } else { 949 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); 950 } 951 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, 952 a_bits, s->page_bits - 1); 953 954 /* Compare masked address with the TLB entry. */ 955 ldst->label_ptr[0] = s->code_ptr; 956 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 957 958 h->index = TCG_REG_TMP2; 959 } else { 960 if (a_bits) { 961 ldst = new_ldst_label(s); 962 963 ldst->is_ld = is_ld; 964 ldst->oi = oi; 965 ldst->addrlo_reg = addr_reg; 966 967 /* 968 * Without micro-architecture details, we don't know which of 969 * bstrpick or andi is faster, so use bstrpick as it's not 970 * constrained by imm field width. Not to say alignments >= 2^12 971 * are going to happen any time soon. 972 */ 973 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 974 975 ldst->label_ptr[0] = s->code_ptr; 976 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 977 } 978 979 h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 980 } 981 982 if (addr_type == TCG_TYPE_I32) { 983 h->base = TCG_REG_TMP0; 984 tcg_out_ext32u(s, h->base, addr_reg); 985 } else { 986 h->base = addr_reg; 987 } 988 989 return ldst; 990} 991 992static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, 993 TCGReg rd, HostAddress h) 994{ 995 /* Byte swapping is left to middle-end expansion. */ 996 tcg_debug_assert((opc & MO_BSWAP) == 0); 997 998 switch (opc & MO_SSIZE) { 999 case MO_UB: 1000 tcg_out_opc_ldx_bu(s, rd, h.base, h.index); 1001 break; 1002 case MO_SB: 1003 tcg_out_opc_ldx_b(s, rd, h.base, h.index); 1004 break; 1005 case MO_UW: 1006 tcg_out_opc_ldx_hu(s, rd, h.base, h.index); 1007 break; 1008 case MO_SW: 1009 tcg_out_opc_ldx_h(s, rd, h.base, h.index); 1010 break; 1011 case MO_UL: 1012 if (type == TCG_TYPE_I64) { 1013 tcg_out_opc_ldx_wu(s, rd, h.base, h.index); 1014 break; 1015 } 1016 /* fallthrough */ 1017 case MO_SL: 1018 tcg_out_opc_ldx_w(s, rd, h.base, h.index); 1019 break; 1020 case MO_UQ: 1021 tcg_out_opc_ldx_d(s, rd, h.base, h.index); 1022 break; 1023 default: 1024 g_assert_not_reached(); 1025 } 1026} 1027 1028static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1029 MemOpIdx oi, TCGType data_type) 1030{ 1031 TCGLabelQemuLdst *ldst; 1032 HostAddress h; 1033 1034 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1035 tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); 1036 1037 if (ldst) { 1038 ldst->type = data_type; 1039 ldst->datalo_reg = data_reg; 1040 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1041 } 1042} 1043 1044static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, 1045 TCGReg rd, HostAddress h) 1046{ 1047 /* Byte swapping is left to middle-end expansion. */ 1048 tcg_debug_assert((opc & MO_BSWAP) == 0); 1049 1050 switch (opc & MO_SIZE) { 1051 case MO_8: 1052 tcg_out_opc_stx_b(s, rd, h.base, h.index); 1053 break; 1054 case MO_16: 1055 tcg_out_opc_stx_h(s, rd, h.base, h.index); 1056 break; 1057 case MO_32: 1058 tcg_out_opc_stx_w(s, rd, h.base, h.index); 1059 break; 1060 case MO_64: 1061 tcg_out_opc_stx_d(s, rd, h.base, h.index); 1062 break; 1063 default: 1064 g_assert_not_reached(); 1065 } 1066} 1067 1068static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1069 MemOpIdx oi, TCGType data_type) 1070{ 1071 TCGLabelQemuLdst *ldst; 1072 HostAddress h; 1073 1074 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1075 tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); 1076 1077 if (ldst) { 1078 ldst->type = data_type; 1079 ldst->datalo_reg = data_reg; 1080 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1081 } 1082} 1083 1084static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi, 1085 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1086{ 1087 TCGLabelQemuLdst *ldst; 1088 HostAddress h; 1089 1090 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1091 1092 if (h.aa.atom == MO_128) { 1093 /* 1094 * Use VLDX/VSTX when 128-bit atomicity is required. 1095 * If address is aligned to 16-bytes, the 128-bit load/store is atomic. 1096 */ 1097 if (is_ld) { 1098 tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index); 1099 tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0); 1100 tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1); 1101 } else { 1102 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0); 1103 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1); 1104 tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index); 1105 } 1106 } else { 1107 /* Otherwise use a pair of LD/ST. */ 1108 TCGReg base = h.base; 1109 if (h.index != TCG_REG_ZERO) { 1110 base = TCG_REG_TMP0; 1111 tcg_out_opc_add_d(s, base, h.base, h.index); 1112 } 1113 if (is_ld) { 1114 tcg_debug_assert(base != data_lo); 1115 tcg_out_opc_ld_d(s, data_lo, base, 0); 1116 tcg_out_opc_ld_d(s, data_hi, base, 8); 1117 } else { 1118 tcg_out_opc_st_d(s, data_lo, base, 0); 1119 tcg_out_opc_st_d(s, data_hi, base, 8); 1120 } 1121 } 1122 1123 if (ldst) { 1124 ldst->type = TCG_TYPE_I128; 1125 ldst->datalo_reg = data_lo; 1126 ldst->datahi_reg = data_hi; 1127 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1128 } 1129} 1130 1131/* 1132 * Entry-points 1133 */ 1134 1135static const tcg_insn_unit *tb_ret_addr; 1136 1137static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1138{ 1139 /* Reuse the zeroing that exists for goto_ptr. */ 1140 if (a0 == 0) { 1141 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1142 } else { 1143 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1144 tcg_out_call_int(s, tb_ret_addr, true); 1145 } 1146} 1147 1148static void tcg_out_goto_tb(TCGContext *s, int which) 1149{ 1150 /* 1151 * Direct branch, or load indirect address, to be patched 1152 * by tb_target_set_jmp_target. Check indirect load offset 1153 * in range early, regardless of direct branch distance, 1154 * via assert within tcg_out_opc_pcaddu2i. 1155 */ 1156 uintptr_t i_addr = get_jmp_target_addr(s, which); 1157 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr); 1158 1159 set_jmp_insn_offset(s, which); 1160 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2); 1161 1162 /* Finish the load and indirect branch. */ 1163 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); 1164 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1165 set_jmp_reset_offset(s, which); 1166} 1167 1168void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1169 uintptr_t jmp_rx, uintptr_t jmp_rw) 1170{ 1171 uintptr_t d_addr = tb->jmp_target_addr[n]; 1172 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2; 1173 tcg_insn_unit insn; 1174 1175 /* Either directly branch, or load slot address for indirect branch. */ 1176 if (d_disp == sextreg(d_disp, 0, 26)) { 1177 insn = encode_sd10k16_insn(OPC_B, d_disp); 1178 } else { 1179 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 1180 intptr_t i_disp = i_addr - jmp_rx; 1181 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2); 1182 } 1183 1184 qatomic_set((tcg_insn_unit *)jmp_rw, insn); 1185 flush_idcache_range(jmp_rx, jmp_rw, 4); 1186} 1187 1188static void tcg_out_op(TCGContext *s, TCGOpcode opc, 1189 const TCGArg args[TCG_MAX_OP_ARGS], 1190 const int const_args[TCG_MAX_OP_ARGS]) 1191{ 1192 TCGArg a0 = args[0]; 1193 TCGArg a1 = args[1]; 1194 TCGArg a2 = args[2]; 1195 TCGArg a3 = args[3]; 1196 int c2 = const_args[2]; 1197 1198 switch (opc) { 1199 case INDEX_op_mb: 1200 tcg_out_mb(s, a0); 1201 break; 1202 1203 case INDEX_op_goto_ptr: 1204 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1205 break; 1206 1207 case INDEX_op_br: 1208 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0), 1209 0); 1210 tcg_out_opc_b(s, 0); 1211 break; 1212 1213 case INDEX_op_brcond_i32: 1214 case INDEX_op_brcond_i64: 1215 tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); 1216 break; 1217 1218 case INDEX_op_extrh_i64_i32: 1219 tcg_out_opc_srai_d(s, a0, a1, 32); 1220 break; 1221 1222 case INDEX_op_not_i32: 1223 case INDEX_op_not_i64: 1224 tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO); 1225 break; 1226 1227 case INDEX_op_nor_i32: 1228 case INDEX_op_nor_i64: 1229 if (c2) { 1230 tcg_out_opc_ori(s, a0, a1, a2); 1231 tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO); 1232 } else { 1233 tcg_out_opc_nor(s, a0, a1, a2); 1234 } 1235 break; 1236 1237 case INDEX_op_andc_i32: 1238 case INDEX_op_andc_i64: 1239 if (c2) { 1240 /* guaranteed to fit due to constraint */ 1241 tcg_out_opc_andi(s, a0, a1, ~a2); 1242 } else { 1243 tcg_out_opc_andn(s, a0, a1, a2); 1244 } 1245 break; 1246 1247 case INDEX_op_orc_i32: 1248 case INDEX_op_orc_i64: 1249 if (c2) { 1250 /* guaranteed to fit due to constraint */ 1251 tcg_out_opc_ori(s, a0, a1, ~a2); 1252 } else { 1253 tcg_out_opc_orn(s, a0, a1, a2); 1254 } 1255 break; 1256 1257 case INDEX_op_and_i32: 1258 case INDEX_op_and_i64: 1259 if (c2) { 1260 tcg_out_opc_andi(s, a0, a1, a2); 1261 } else { 1262 tcg_out_opc_and(s, a0, a1, a2); 1263 } 1264 break; 1265 1266 case INDEX_op_or_i32: 1267 case INDEX_op_or_i64: 1268 if (c2) { 1269 tcg_out_opc_ori(s, a0, a1, a2); 1270 } else { 1271 tcg_out_opc_or(s, a0, a1, a2); 1272 } 1273 break; 1274 1275 case INDEX_op_xor_i32: 1276 case INDEX_op_xor_i64: 1277 if (c2) { 1278 tcg_out_opc_xori(s, a0, a1, a2); 1279 } else { 1280 tcg_out_opc_xor(s, a0, a1, a2); 1281 } 1282 break; 1283 1284 case INDEX_op_extract_i32: 1285 tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1); 1286 break; 1287 case INDEX_op_extract_i64: 1288 tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1); 1289 break; 1290 1291 case INDEX_op_deposit_i32: 1292 tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1); 1293 break; 1294 case INDEX_op_deposit_i64: 1295 tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1); 1296 break; 1297 1298 case INDEX_op_bswap16_i32: 1299 case INDEX_op_bswap16_i64: 1300 tcg_out_opc_revb_2h(s, a0, a1); 1301 if (a2 & TCG_BSWAP_OS) { 1302 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); 1303 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1304 tcg_out_ext16u(s, a0, a0); 1305 } 1306 break; 1307 1308 case INDEX_op_bswap32_i32: 1309 /* All 32-bit values are computed sign-extended in the register. */ 1310 a2 = TCG_BSWAP_OS; 1311 /* fallthrough */ 1312 case INDEX_op_bswap32_i64: 1313 tcg_out_opc_revb_2w(s, a0, a1); 1314 if (a2 & TCG_BSWAP_OS) { 1315 tcg_out_ext32s(s, a0, a0); 1316 } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1317 tcg_out_ext32u(s, a0, a0); 1318 } 1319 break; 1320 1321 case INDEX_op_bswap64_i64: 1322 tcg_out_opc_revb_d(s, a0, a1); 1323 break; 1324 1325 case INDEX_op_clz_i32: 1326 tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true); 1327 break; 1328 case INDEX_op_clz_i64: 1329 tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false); 1330 break; 1331 1332 case INDEX_op_ctz_i32: 1333 tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true); 1334 break; 1335 case INDEX_op_ctz_i64: 1336 tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false); 1337 break; 1338 1339 case INDEX_op_shl_i32: 1340 if (c2) { 1341 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1342 } else { 1343 tcg_out_opc_sll_w(s, a0, a1, a2); 1344 } 1345 break; 1346 case INDEX_op_shl_i64: 1347 if (c2) { 1348 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1349 } else { 1350 tcg_out_opc_sll_d(s, a0, a1, a2); 1351 } 1352 break; 1353 1354 case INDEX_op_shr_i32: 1355 if (c2) { 1356 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1357 } else { 1358 tcg_out_opc_srl_w(s, a0, a1, a2); 1359 } 1360 break; 1361 case INDEX_op_shr_i64: 1362 if (c2) { 1363 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1364 } else { 1365 tcg_out_opc_srl_d(s, a0, a1, a2); 1366 } 1367 break; 1368 1369 case INDEX_op_sar_i32: 1370 if (c2) { 1371 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1372 } else { 1373 tcg_out_opc_sra_w(s, a0, a1, a2); 1374 } 1375 break; 1376 case INDEX_op_sar_i64: 1377 if (c2) { 1378 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1379 } else { 1380 tcg_out_opc_sra_d(s, a0, a1, a2); 1381 } 1382 break; 1383 1384 case INDEX_op_rotl_i32: 1385 /* transform into equivalent rotr/rotri */ 1386 if (c2) { 1387 tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f); 1388 } else { 1389 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1390 tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0); 1391 } 1392 break; 1393 case INDEX_op_rotl_i64: 1394 /* transform into equivalent rotr/rotri */ 1395 if (c2) { 1396 tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f); 1397 } else { 1398 tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2); 1399 tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0); 1400 } 1401 break; 1402 1403 case INDEX_op_rotr_i32: 1404 if (c2) { 1405 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1406 } else { 1407 tcg_out_opc_rotr_w(s, a0, a1, a2); 1408 } 1409 break; 1410 case INDEX_op_rotr_i64: 1411 if (c2) { 1412 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1413 } else { 1414 tcg_out_opc_rotr_d(s, a0, a1, a2); 1415 } 1416 break; 1417 1418 case INDEX_op_add_i32: 1419 if (c2) { 1420 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2); 1421 } else { 1422 tcg_out_opc_add_w(s, a0, a1, a2); 1423 } 1424 break; 1425 case INDEX_op_add_i64: 1426 if (c2) { 1427 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2); 1428 } else { 1429 tcg_out_opc_add_d(s, a0, a1, a2); 1430 } 1431 break; 1432 1433 case INDEX_op_sub_i32: 1434 if (c2) { 1435 tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2); 1436 } else { 1437 tcg_out_opc_sub_w(s, a0, a1, a2); 1438 } 1439 break; 1440 case INDEX_op_sub_i64: 1441 if (c2) { 1442 tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2); 1443 } else { 1444 tcg_out_opc_sub_d(s, a0, a1, a2); 1445 } 1446 break; 1447 1448 case INDEX_op_neg_i32: 1449 tcg_out_opc_sub_w(s, a0, TCG_REG_ZERO, a1); 1450 break; 1451 case INDEX_op_neg_i64: 1452 tcg_out_opc_sub_d(s, a0, TCG_REG_ZERO, a1); 1453 break; 1454 1455 case INDEX_op_mul_i32: 1456 tcg_out_opc_mul_w(s, a0, a1, a2); 1457 break; 1458 case INDEX_op_mul_i64: 1459 tcg_out_opc_mul_d(s, a0, a1, a2); 1460 break; 1461 1462 case INDEX_op_mulsh_i32: 1463 tcg_out_opc_mulh_w(s, a0, a1, a2); 1464 break; 1465 case INDEX_op_mulsh_i64: 1466 tcg_out_opc_mulh_d(s, a0, a1, a2); 1467 break; 1468 1469 case INDEX_op_muluh_i32: 1470 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1471 break; 1472 case INDEX_op_muluh_i64: 1473 tcg_out_opc_mulh_du(s, a0, a1, a2); 1474 break; 1475 1476 case INDEX_op_div_i32: 1477 tcg_out_opc_div_w(s, a0, a1, a2); 1478 break; 1479 case INDEX_op_div_i64: 1480 tcg_out_opc_div_d(s, a0, a1, a2); 1481 break; 1482 1483 case INDEX_op_divu_i32: 1484 tcg_out_opc_div_wu(s, a0, a1, a2); 1485 break; 1486 case INDEX_op_divu_i64: 1487 tcg_out_opc_div_du(s, a0, a1, a2); 1488 break; 1489 1490 case INDEX_op_rem_i32: 1491 tcg_out_opc_mod_w(s, a0, a1, a2); 1492 break; 1493 case INDEX_op_rem_i64: 1494 tcg_out_opc_mod_d(s, a0, a1, a2); 1495 break; 1496 1497 case INDEX_op_remu_i32: 1498 tcg_out_opc_mod_wu(s, a0, a1, a2); 1499 break; 1500 case INDEX_op_remu_i64: 1501 tcg_out_opc_mod_du(s, a0, a1, a2); 1502 break; 1503 1504 case INDEX_op_setcond_i32: 1505 case INDEX_op_setcond_i64: 1506 tcg_out_setcond(s, args[3], a0, a1, a2, c2); 1507 break; 1508 1509 case INDEX_op_movcond_i32: 1510 case INDEX_op_movcond_i64: 1511 tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]); 1512 break; 1513 1514 case INDEX_op_ld8s_i32: 1515 case INDEX_op_ld8s_i64: 1516 tcg_out_ldst(s, OPC_LD_B, a0, a1, a2); 1517 break; 1518 case INDEX_op_ld8u_i32: 1519 case INDEX_op_ld8u_i64: 1520 tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2); 1521 break; 1522 case INDEX_op_ld16s_i32: 1523 case INDEX_op_ld16s_i64: 1524 tcg_out_ldst(s, OPC_LD_H, a0, a1, a2); 1525 break; 1526 case INDEX_op_ld16u_i32: 1527 case INDEX_op_ld16u_i64: 1528 tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2); 1529 break; 1530 case INDEX_op_ld_i32: 1531 case INDEX_op_ld32s_i64: 1532 tcg_out_ldst(s, OPC_LD_W, a0, a1, a2); 1533 break; 1534 case INDEX_op_ld32u_i64: 1535 tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2); 1536 break; 1537 case INDEX_op_ld_i64: 1538 tcg_out_ldst(s, OPC_LD_D, a0, a1, a2); 1539 break; 1540 1541 case INDEX_op_st8_i32: 1542 case INDEX_op_st8_i64: 1543 tcg_out_ldst(s, OPC_ST_B, a0, a1, a2); 1544 break; 1545 case INDEX_op_st16_i32: 1546 case INDEX_op_st16_i64: 1547 tcg_out_ldst(s, OPC_ST_H, a0, a1, a2); 1548 break; 1549 case INDEX_op_st_i32: 1550 case INDEX_op_st32_i64: 1551 tcg_out_ldst(s, OPC_ST_W, a0, a1, a2); 1552 break; 1553 case INDEX_op_st_i64: 1554 tcg_out_ldst(s, OPC_ST_D, a0, a1, a2); 1555 break; 1556 1557 case INDEX_op_qemu_ld_a32_i32: 1558 case INDEX_op_qemu_ld_a64_i32: 1559 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 1560 break; 1561 case INDEX_op_qemu_ld_a32_i64: 1562 case INDEX_op_qemu_ld_a64_i64: 1563 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 1564 break; 1565 case INDEX_op_qemu_ld_a32_i128: 1566 case INDEX_op_qemu_ld_a64_i128: 1567 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true); 1568 break; 1569 case INDEX_op_qemu_st_a32_i32: 1570 case INDEX_op_qemu_st_a64_i32: 1571 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 1572 break; 1573 case INDEX_op_qemu_st_a32_i64: 1574 case INDEX_op_qemu_st_a64_i64: 1575 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 1576 break; 1577 case INDEX_op_qemu_st_a32_i128: 1578 case INDEX_op_qemu_st_a64_i128: 1579 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false); 1580 break; 1581 1582 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ 1583 case INDEX_op_mov_i64: 1584 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 1585 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 1586 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 1587 case INDEX_op_ext8s_i32: /* Always emitted via tcg_reg_alloc_op. */ 1588 case INDEX_op_ext8s_i64: 1589 case INDEX_op_ext8u_i32: 1590 case INDEX_op_ext8u_i64: 1591 case INDEX_op_ext16s_i32: 1592 case INDEX_op_ext16s_i64: 1593 case INDEX_op_ext16u_i32: 1594 case INDEX_op_ext16u_i64: 1595 case INDEX_op_ext32s_i64: 1596 case INDEX_op_ext32u_i64: 1597 case INDEX_op_ext_i32_i64: 1598 case INDEX_op_extu_i32_i64: 1599 case INDEX_op_extrl_i64_i32: 1600 default: 1601 g_assert_not_reached(); 1602 } 1603} 1604 1605static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 1606 TCGReg rd, TCGReg rs) 1607{ 1608 switch (vece) { 1609 case MO_8: 1610 tcg_out_opc_vreplgr2vr_b(s, rd, rs); 1611 break; 1612 case MO_16: 1613 tcg_out_opc_vreplgr2vr_h(s, rd, rs); 1614 break; 1615 case MO_32: 1616 tcg_out_opc_vreplgr2vr_w(s, rd, rs); 1617 break; 1618 case MO_64: 1619 tcg_out_opc_vreplgr2vr_d(s, rd, rs); 1620 break; 1621 default: 1622 g_assert_not_reached(); 1623 } 1624 return true; 1625} 1626 1627static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 1628 TCGReg r, TCGReg base, intptr_t offset) 1629{ 1630 /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */ 1631 if (offset < -0x800 || offset > 0x7ff || \ 1632 (offset & ((1 << vece) - 1)) != 0) { 1633 tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset); 1634 base = TCG_REG_TMP0; 1635 offset = 0; 1636 } 1637 offset >>= vece; 1638 1639 switch (vece) { 1640 case MO_8: 1641 tcg_out_opc_vldrepl_b(s, r, base, offset); 1642 break; 1643 case MO_16: 1644 tcg_out_opc_vldrepl_h(s, r, base, offset); 1645 break; 1646 case MO_32: 1647 tcg_out_opc_vldrepl_w(s, r, base, offset); 1648 break; 1649 case MO_64: 1650 tcg_out_opc_vldrepl_d(s, r, base, offset); 1651 break; 1652 default: 1653 g_assert_not_reached(); 1654 } 1655 return true; 1656} 1657 1658static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 1659 TCGReg rd, int64_t v64) 1660{ 1661 /* Try vldi if imm can fit */ 1662 int64_t value = sextract64(v64, 0, 8 << vece); 1663 if (-0x200 <= value && value <= 0x1FF) { 1664 uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF); 1665 tcg_out_opc_vldi(s, rd, imm); 1666 return; 1667 } 1668 1669 /* TODO: vldi patterns when imm 12 is set */ 1670 1671 /* Fallback to vreplgr2vr */ 1672 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value); 1673 switch (vece) { 1674 case MO_8: 1675 tcg_out_opc_vreplgr2vr_b(s, rd, TCG_REG_TMP0); 1676 break; 1677 case MO_16: 1678 tcg_out_opc_vreplgr2vr_h(s, rd, TCG_REG_TMP0); 1679 break; 1680 case MO_32: 1681 tcg_out_opc_vreplgr2vr_w(s, rd, TCG_REG_TMP0); 1682 break; 1683 case MO_64: 1684 tcg_out_opc_vreplgr2vr_d(s, rd, TCG_REG_TMP0); 1685 break; 1686 default: 1687 g_assert_not_reached(); 1688 } 1689} 1690 1691static void tcg_out_addsub_vec(TCGContext *s, unsigned vece, const TCGArg a0, 1692 const TCGArg a1, const TCGArg a2, 1693 bool a2_is_const, bool is_add) 1694{ 1695 static const LoongArchInsn add_vec_insn[4] = { 1696 OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D 1697 }; 1698 static const LoongArchInsn add_vec_imm_insn[4] = { 1699 OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU 1700 }; 1701 static const LoongArchInsn sub_vec_insn[4] = { 1702 OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D 1703 }; 1704 static const LoongArchInsn sub_vec_imm_insn[4] = { 1705 OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU 1706 }; 1707 1708 if (a2_is_const) { 1709 int64_t value = sextract64(a2, 0, 8 << vece); 1710 if (!is_add) { 1711 value = -value; 1712 } 1713 1714 /* Try vaddi/vsubi */ 1715 if (0 <= value && value <= 0x1f) { 1716 tcg_out32(s, encode_vdvjuk5_insn(add_vec_imm_insn[vece], a0, \ 1717 a1, value)); 1718 return; 1719 } else if (-0x1f <= value && value < 0) { 1720 tcg_out32(s, encode_vdvjuk5_insn(sub_vec_imm_insn[vece], a0, \ 1721 a1, -value)); 1722 return; 1723 } 1724 1725 /* constraint TCG_CT_CONST_VADD ensures unreachable */ 1726 g_assert_not_reached(); 1727 } 1728 1729 if (is_add) { 1730 tcg_out32(s, encode_vdvjvk_insn(add_vec_insn[vece], a0, a1, a2)); 1731 } else { 1732 tcg_out32(s, encode_vdvjvk_insn(sub_vec_insn[vece], a0, a1, a2)); 1733 } 1734} 1735 1736static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 1737 unsigned vecl, unsigned vece, 1738 const TCGArg args[TCG_MAX_OP_ARGS], 1739 const int const_args[TCG_MAX_OP_ARGS]) 1740{ 1741 TCGType type = vecl + TCG_TYPE_V64; 1742 TCGArg a0, a1, a2, a3; 1743 TCGReg temp = TCG_REG_TMP0; 1744 TCGReg temp_vec = TCG_VEC_TMP0; 1745 1746 static const LoongArchInsn cmp_vec_insn[16][4] = { 1747 [TCG_COND_EQ] = {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D}, 1748 [TCG_COND_LE] = {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D}, 1749 [TCG_COND_LEU] = {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU}, 1750 [TCG_COND_LT] = {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D}, 1751 [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU}, 1752 }; 1753 static const LoongArchInsn cmp_vec_imm_insn[16][4] = { 1754 [TCG_COND_EQ] = {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D}, 1755 [TCG_COND_LE] = {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D}, 1756 [TCG_COND_LEU] = {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU}, 1757 [TCG_COND_LT] = {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D}, 1758 [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU}, 1759 }; 1760 LoongArchInsn insn; 1761 static const LoongArchInsn neg_vec_insn[4] = { 1762 OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D 1763 }; 1764 static const LoongArchInsn mul_vec_insn[4] = { 1765 OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D 1766 }; 1767 static const LoongArchInsn smin_vec_insn[4] = { 1768 OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D 1769 }; 1770 static const LoongArchInsn umin_vec_insn[4] = { 1771 OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU 1772 }; 1773 static const LoongArchInsn smax_vec_insn[4] = { 1774 OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D 1775 }; 1776 static const LoongArchInsn umax_vec_insn[4] = { 1777 OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU 1778 }; 1779 static const LoongArchInsn ssadd_vec_insn[4] = { 1780 OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D 1781 }; 1782 static const LoongArchInsn usadd_vec_insn[4] = { 1783 OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU 1784 }; 1785 static const LoongArchInsn sssub_vec_insn[4] = { 1786 OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D 1787 }; 1788 static const LoongArchInsn ussub_vec_insn[4] = { 1789 OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU 1790 }; 1791 static const LoongArchInsn shlv_vec_insn[4] = { 1792 OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D 1793 }; 1794 static const LoongArchInsn shrv_vec_insn[4] = { 1795 OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D 1796 }; 1797 static const LoongArchInsn sarv_vec_insn[4] = { 1798 OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D 1799 }; 1800 static const LoongArchInsn shli_vec_insn[4] = { 1801 OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D 1802 }; 1803 static const LoongArchInsn shri_vec_insn[4] = { 1804 OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D 1805 }; 1806 static const LoongArchInsn sari_vec_insn[4] = { 1807 OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D 1808 }; 1809 static const LoongArchInsn rotrv_vec_insn[4] = { 1810 OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D 1811 }; 1812 1813 a0 = args[0]; 1814 a1 = args[1]; 1815 a2 = args[2]; 1816 a3 = args[3]; 1817 1818 /* Currently only supports V128 */ 1819 tcg_debug_assert(type == TCG_TYPE_V128); 1820 1821 switch (opc) { 1822 case INDEX_op_st_vec: 1823 /* Try to fit vst imm */ 1824 if (-0x800 <= a2 && a2 <= 0x7ff) { 1825 tcg_out_opc_vst(s, a0, a1, a2); 1826 } else { 1827 tcg_out_movi(s, TCG_TYPE_I64, temp, a2); 1828 tcg_out_opc_vstx(s, a0, a1, temp); 1829 } 1830 break; 1831 case INDEX_op_ld_vec: 1832 /* Try to fit vld imm */ 1833 if (-0x800 <= a2 && a2 <= 0x7ff) { 1834 tcg_out_opc_vld(s, a0, a1, a2); 1835 } else { 1836 tcg_out_movi(s, TCG_TYPE_I64, temp, a2); 1837 tcg_out_opc_vldx(s, a0, a1, temp); 1838 } 1839 break; 1840 case INDEX_op_and_vec: 1841 tcg_out_opc_vand_v(s, a0, a1, a2); 1842 break; 1843 case INDEX_op_andc_vec: 1844 /* 1845 * vandn vd, vj, vk: vd = vk & ~vj 1846 * andc_vec vd, vj, vk: vd = vj & ~vk 1847 * vk and vk are swapped 1848 */ 1849 tcg_out_opc_vandn_v(s, a0, a2, a1); 1850 break; 1851 case INDEX_op_or_vec: 1852 tcg_out_opc_vor_v(s, a0, a1, a2); 1853 break; 1854 case INDEX_op_orc_vec: 1855 tcg_out_opc_vorn_v(s, a0, a1, a2); 1856 break; 1857 case INDEX_op_xor_vec: 1858 tcg_out_opc_vxor_v(s, a0, a1, a2); 1859 break; 1860 case INDEX_op_nor_vec: 1861 tcg_out_opc_vnor_v(s, a0, a1, a2); 1862 break; 1863 case INDEX_op_not_vec: 1864 tcg_out_opc_vnor_v(s, a0, a1, a1); 1865 break; 1866 case INDEX_op_cmp_vec: 1867 { 1868 TCGCond cond = args[3]; 1869 if (const_args[2]) { 1870 /* 1871 * cmp_vec dest, src, value 1872 * Try vseqi/vslei/vslti 1873 */ 1874 int64_t value = sextract64(a2, 0, 8 << vece); 1875 if ((cond == TCG_COND_EQ || cond == TCG_COND_LE || \ 1876 cond == TCG_COND_LT) && (-0x10 <= value && value <= 0x0f)) { 1877 tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][vece], \ 1878 a0, a1, value)); 1879 break; 1880 } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) && 1881 (0x00 <= value && value <= 0x1f)) { 1882 tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][vece], \ 1883 a0, a1, value)); 1884 break; 1885 } 1886 1887 /* 1888 * Fallback to: 1889 * dupi_vec temp, a2 1890 * cmp_vec a0, a1, temp, cond 1891 */ 1892 tcg_out_dupi_vec(s, type, vece, temp_vec, a2); 1893 a2 = temp_vec; 1894 } 1895 1896 insn = cmp_vec_insn[cond][vece]; 1897 if (insn == 0) { 1898 TCGArg t; 1899 t = a1, a1 = a2, a2 = t; 1900 cond = tcg_swap_cond(cond); 1901 insn = cmp_vec_insn[cond][vece]; 1902 tcg_debug_assert(insn != 0); 1903 } 1904 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 1905 } 1906 break; 1907 case INDEX_op_add_vec: 1908 tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], true); 1909 break; 1910 case INDEX_op_sub_vec: 1911 tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], false); 1912 break; 1913 case INDEX_op_neg_vec: 1914 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1)); 1915 break; 1916 case INDEX_op_mul_vec: 1917 tcg_out32(s, encode_vdvjvk_insn(mul_vec_insn[vece], a0, a1, a2)); 1918 break; 1919 case INDEX_op_smin_vec: 1920 tcg_out32(s, encode_vdvjvk_insn(smin_vec_insn[vece], a0, a1, a2)); 1921 break; 1922 case INDEX_op_smax_vec: 1923 tcg_out32(s, encode_vdvjvk_insn(smax_vec_insn[vece], a0, a1, a2)); 1924 break; 1925 case INDEX_op_umin_vec: 1926 tcg_out32(s, encode_vdvjvk_insn(umin_vec_insn[vece], a0, a1, a2)); 1927 break; 1928 case INDEX_op_umax_vec: 1929 tcg_out32(s, encode_vdvjvk_insn(umax_vec_insn[vece], a0, a1, a2)); 1930 break; 1931 case INDEX_op_ssadd_vec: 1932 tcg_out32(s, encode_vdvjvk_insn(ssadd_vec_insn[vece], a0, a1, a2)); 1933 break; 1934 case INDEX_op_usadd_vec: 1935 tcg_out32(s, encode_vdvjvk_insn(usadd_vec_insn[vece], a0, a1, a2)); 1936 break; 1937 case INDEX_op_sssub_vec: 1938 tcg_out32(s, encode_vdvjvk_insn(sssub_vec_insn[vece], a0, a1, a2)); 1939 break; 1940 case INDEX_op_ussub_vec: 1941 tcg_out32(s, encode_vdvjvk_insn(ussub_vec_insn[vece], a0, a1, a2)); 1942 break; 1943 case INDEX_op_shlv_vec: 1944 tcg_out32(s, encode_vdvjvk_insn(shlv_vec_insn[vece], a0, a1, a2)); 1945 break; 1946 case INDEX_op_shrv_vec: 1947 tcg_out32(s, encode_vdvjvk_insn(shrv_vec_insn[vece], a0, a1, a2)); 1948 break; 1949 case INDEX_op_sarv_vec: 1950 tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2)); 1951 break; 1952 case INDEX_op_shli_vec: 1953 tcg_out32(s, encode_vdvjuk3_insn(shli_vec_insn[vece], a0, a1, a2)); 1954 break; 1955 case INDEX_op_shri_vec: 1956 tcg_out32(s, encode_vdvjuk3_insn(shri_vec_insn[vece], a0, a1, a2)); 1957 break; 1958 case INDEX_op_sari_vec: 1959 tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2)); 1960 break; 1961 case INDEX_op_rotrv_vec: 1962 tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, a2)); 1963 break; 1964 case INDEX_op_rotlv_vec: 1965 /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */ 1966 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], temp_vec, a2)); 1967 tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, 1968 temp_vec)); 1969 break; 1970 case INDEX_op_rotli_vec: 1971 /* rotli_vec a1, a2 = rotri_vec a1, -a2 */ 1972 a2 = extract32(-a2, 0, 3 + vece); 1973 switch (vece) { 1974 case MO_8: 1975 tcg_out_opc_vrotri_b(s, a0, a1, a2); 1976 break; 1977 case MO_16: 1978 tcg_out_opc_vrotri_h(s, a0, a1, a2); 1979 break; 1980 case MO_32: 1981 tcg_out_opc_vrotri_w(s, a0, a1, a2); 1982 break; 1983 case MO_64: 1984 tcg_out_opc_vrotri_d(s, a0, a1, a2); 1985 break; 1986 default: 1987 g_assert_not_reached(); 1988 } 1989 break; 1990 case INDEX_op_bitsel_vec: 1991 /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */ 1992 tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1); 1993 break; 1994 case INDEX_op_dupm_vec: 1995 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 1996 break; 1997 default: 1998 g_assert_not_reached(); 1999 } 2000} 2001 2002int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2003{ 2004 switch (opc) { 2005 case INDEX_op_ld_vec: 2006 case INDEX_op_st_vec: 2007 case INDEX_op_dup_vec: 2008 case INDEX_op_dupm_vec: 2009 case INDEX_op_cmp_vec: 2010 case INDEX_op_add_vec: 2011 case INDEX_op_sub_vec: 2012 case INDEX_op_and_vec: 2013 case INDEX_op_andc_vec: 2014 case INDEX_op_or_vec: 2015 case INDEX_op_orc_vec: 2016 case INDEX_op_xor_vec: 2017 case INDEX_op_nor_vec: 2018 case INDEX_op_not_vec: 2019 case INDEX_op_neg_vec: 2020 case INDEX_op_mul_vec: 2021 case INDEX_op_smin_vec: 2022 case INDEX_op_smax_vec: 2023 case INDEX_op_umin_vec: 2024 case INDEX_op_umax_vec: 2025 case INDEX_op_ssadd_vec: 2026 case INDEX_op_usadd_vec: 2027 case INDEX_op_sssub_vec: 2028 case INDEX_op_ussub_vec: 2029 case INDEX_op_shlv_vec: 2030 case INDEX_op_shrv_vec: 2031 case INDEX_op_sarv_vec: 2032 case INDEX_op_bitsel_vec: 2033 return 1; 2034 default: 2035 return 0; 2036 } 2037} 2038 2039void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2040 TCGArg a0, ...) 2041{ 2042 g_assert_not_reached(); 2043} 2044 2045static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op) 2046{ 2047 switch (op) { 2048 case INDEX_op_goto_ptr: 2049 return C_O0_I1(r); 2050 2051 case INDEX_op_st8_i32: 2052 case INDEX_op_st8_i64: 2053 case INDEX_op_st16_i32: 2054 case INDEX_op_st16_i64: 2055 case INDEX_op_st32_i64: 2056 case INDEX_op_st_i32: 2057 case INDEX_op_st_i64: 2058 case INDEX_op_qemu_st_a32_i32: 2059 case INDEX_op_qemu_st_a64_i32: 2060 case INDEX_op_qemu_st_a32_i64: 2061 case INDEX_op_qemu_st_a64_i64: 2062 return C_O0_I2(rZ, r); 2063 2064 case INDEX_op_qemu_ld_a32_i128: 2065 case INDEX_op_qemu_ld_a64_i128: 2066 return C_N2_I1(r, r, r); 2067 2068 case INDEX_op_qemu_st_a32_i128: 2069 case INDEX_op_qemu_st_a64_i128: 2070 return C_O0_I3(r, r, r); 2071 2072 case INDEX_op_brcond_i32: 2073 case INDEX_op_brcond_i64: 2074 return C_O0_I2(rZ, rZ); 2075 2076 case INDEX_op_ext8s_i32: 2077 case INDEX_op_ext8s_i64: 2078 case INDEX_op_ext8u_i32: 2079 case INDEX_op_ext8u_i64: 2080 case INDEX_op_ext16s_i32: 2081 case INDEX_op_ext16s_i64: 2082 case INDEX_op_ext16u_i32: 2083 case INDEX_op_ext16u_i64: 2084 case INDEX_op_ext32s_i64: 2085 case INDEX_op_ext32u_i64: 2086 case INDEX_op_extu_i32_i64: 2087 case INDEX_op_extrl_i64_i32: 2088 case INDEX_op_extrh_i64_i32: 2089 case INDEX_op_ext_i32_i64: 2090 case INDEX_op_neg_i32: 2091 case INDEX_op_neg_i64: 2092 case INDEX_op_not_i32: 2093 case INDEX_op_not_i64: 2094 case INDEX_op_extract_i32: 2095 case INDEX_op_extract_i64: 2096 case INDEX_op_bswap16_i32: 2097 case INDEX_op_bswap16_i64: 2098 case INDEX_op_bswap32_i32: 2099 case INDEX_op_bswap32_i64: 2100 case INDEX_op_bswap64_i64: 2101 case INDEX_op_ld8s_i32: 2102 case INDEX_op_ld8s_i64: 2103 case INDEX_op_ld8u_i32: 2104 case INDEX_op_ld8u_i64: 2105 case INDEX_op_ld16s_i32: 2106 case INDEX_op_ld16s_i64: 2107 case INDEX_op_ld16u_i32: 2108 case INDEX_op_ld16u_i64: 2109 case INDEX_op_ld32s_i64: 2110 case INDEX_op_ld32u_i64: 2111 case INDEX_op_ld_i32: 2112 case INDEX_op_ld_i64: 2113 case INDEX_op_qemu_ld_a32_i32: 2114 case INDEX_op_qemu_ld_a64_i32: 2115 case INDEX_op_qemu_ld_a32_i64: 2116 case INDEX_op_qemu_ld_a64_i64: 2117 return C_O1_I1(r, r); 2118 2119 case INDEX_op_andc_i32: 2120 case INDEX_op_andc_i64: 2121 case INDEX_op_orc_i32: 2122 case INDEX_op_orc_i64: 2123 /* 2124 * LoongArch insns for these ops don't have reg-imm forms, but we 2125 * can express using andi/ori if ~constant satisfies 2126 * TCG_CT_CONST_U12. 2127 */ 2128 return C_O1_I2(r, r, rC); 2129 2130 case INDEX_op_shl_i32: 2131 case INDEX_op_shl_i64: 2132 case INDEX_op_shr_i32: 2133 case INDEX_op_shr_i64: 2134 case INDEX_op_sar_i32: 2135 case INDEX_op_sar_i64: 2136 case INDEX_op_rotl_i32: 2137 case INDEX_op_rotl_i64: 2138 case INDEX_op_rotr_i32: 2139 case INDEX_op_rotr_i64: 2140 return C_O1_I2(r, r, ri); 2141 2142 case INDEX_op_add_i32: 2143 return C_O1_I2(r, r, ri); 2144 case INDEX_op_add_i64: 2145 return C_O1_I2(r, r, rJ); 2146 2147 case INDEX_op_and_i32: 2148 case INDEX_op_and_i64: 2149 case INDEX_op_nor_i32: 2150 case INDEX_op_nor_i64: 2151 case INDEX_op_or_i32: 2152 case INDEX_op_or_i64: 2153 case INDEX_op_xor_i32: 2154 case INDEX_op_xor_i64: 2155 /* LoongArch reg-imm bitops have their imms ZERO-extended */ 2156 return C_O1_I2(r, r, rU); 2157 2158 case INDEX_op_clz_i32: 2159 case INDEX_op_clz_i64: 2160 case INDEX_op_ctz_i32: 2161 case INDEX_op_ctz_i64: 2162 return C_O1_I2(r, r, rW); 2163 2164 case INDEX_op_deposit_i32: 2165 case INDEX_op_deposit_i64: 2166 /* Must deposit into the same register as input */ 2167 return C_O1_I2(r, 0, rZ); 2168 2169 case INDEX_op_sub_i32: 2170 case INDEX_op_setcond_i32: 2171 return C_O1_I2(r, rZ, ri); 2172 case INDEX_op_sub_i64: 2173 case INDEX_op_setcond_i64: 2174 return C_O1_I2(r, rZ, rJ); 2175 2176 case INDEX_op_mul_i32: 2177 case INDEX_op_mul_i64: 2178 case INDEX_op_mulsh_i32: 2179 case INDEX_op_mulsh_i64: 2180 case INDEX_op_muluh_i32: 2181 case INDEX_op_muluh_i64: 2182 case INDEX_op_div_i32: 2183 case INDEX_op_div_i64: 2184 case INDEX_op_divu_i32: 2185 case INDEX_op_divu_i64: 2186 case INDEX_op_rem_i32: 2187 case INDEX_op_rem_i64: 2188 case INDEX_op_remu_i32: 2189 case INDEX_op_remu_i64: 2190 return C_O1_I2(r, rZ, rZ); 2191 2192 case INDEX_op_movcond_i32: 2193 case INDEX_op_movcond_i64: 2194 return C_O1_I4(r, rZ, rJ, rZ, rZ); 2195 2196 case INDEX_op_ld_vec: 2197 case INDEX_op_dupm_vec: 2198 case INDEX_op_dup_vec: 2199 return C_O1_I1(w, r); 2200 2201 case INDEX_op_st_vec: 2202 return C_O0_I2(w, r); 2203 2204 case INDEX_op_cmp_vec: 2205 return C_O1_I2(w, w, wM); 2206 2207 case INDEX_op_add_vec: 2208 case INDEX_op_sub_vec: 2209 return C_O1_I2(w, w, wA); 2210 2211 case INDEX_op_and_vec: 2212 case INDEX_op_andc_vec: 2213 case INDEX_op_or_vec: 2214 case INDEX_op_orc_vec: 2215 case INDEX_op_xor_vec: 2216 case INDEX_op_nor_vec: 2217 case INDEX_op_mul_vec: 2218 case INDEX_op_smin_vec: 2219 case INDEX_op_smax_vec: 2220 case INDEX_op_umin_vec: 2221 case INDEX_op_umax_vec: 2222 case INDEX_op_ssadd_vec: 2223 case INDEX_op_usadd_vec: 2224 case INDEX_op_sssub_vec: 2225 case INDEX_op_ussub_vec: 2226 case INDEX_op_shlv_vec: 2227 case INDEX_op_shrv_vec: 2228 case INDEX_op_sarv_vec: 2229 case INDEX_op_rotrv_vec: 2230 case INDEX_op_rotlv_vec: 2231 return C_O1_I2(w, w, w); 2232 2233 case INDEX_op_not_vec: 2234 case INDEX_op_neg_vec: 2235 case INDEX_op_shli_vec: 2236 case INDEX_op_shri_vec: 2237 case INDEX_op_sari_vec: 2238 case INDEX_op_rotli_vec: 2239 return C_O1_I1(w, w); 2240 2241 case INDEX_op_bitsel_vec: 2242 return C_O1_I3(w, w, w, w); 2243 2244 default: 2245 g_assert_not_reached(); 2246 } 2247} 2248 2249static const int tcg_target_callee_save_regs[] = { 2250 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2251 TCG_REG_S1, 2252 TCG_REG_S2, 2253 TCG_REG_S3, 2254 TCG_REG_S4, 2255 TCG_REG_S5, 2256 TCG_REG_S6, 2257 TCG_REG_S7, 2258 TCG_REG_S8, 2259 TCG_REG_S9, 2260 TCG_REG_RA, /* should be last for ABI compliance */ 2261}; 2262 2263/* Stack frame parameters. */ 2264#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2265#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2266#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2267#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2268 + TCG_TARGET_STACK_ALIGN - 1) \ 2269 & -TCG_TARGET_STACK_ALIGN) 2270#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2271 2272/* We're expecting to be able to use an immediate for frame allocation. */ 2273QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2274 2275/* Generate global QEMU prologue and epilogue code */ 2276static void tcg_target_qemu_prologue(TCGContext *s) 2277{ 2278 int i; 2279 2280 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2281 2282 /* TB prologue */ 2283 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2284 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2285 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2286 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2287 } 2288 2289 if (!tcg_use_softmmu && guest_base) { 2290 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2291 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2292 } 2293 2294 /* Call generated code */ 2295 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2296 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2297 2298 /* Return path for goto_ptr. Set return value to 0 */ 2299 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2300 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2301 2302 /* TB epilogue */ 2303 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2304 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2305 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2306 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2307 } 2308 2309 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2310 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 2311} 2312 2313static void tcg_out_tb_start(TCGContext *s) 2314{ 2315 /* nothing to do */ 2316} 2317 2318static void tcg_target_init(TCGContext *s) 2319{ 2320 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2321 2322 /* Server and desktop class cpus have UAL; embedded cpus do not. */ 2323 if (!(hwcap & HWCAP_LOONGARCH_UAL)) { 2324 error_report("TCG: unaligned access support required; exiting"); 2325 exit(EXIT_FAILURE); 2326 } 2327 2328 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2329 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 2330 2331 tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; 2332 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2333 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2334 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2335 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2336 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2337 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2338 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2339 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2340 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2341 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2342 2343 if (cpuinfo & CPUINFO_LSX) { 2344 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2345 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 2346 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 2347 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 2348 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 2349 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 2350 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 2351 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 2352 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 2353 } 2354 2355 s->reserved_regs = 0; 2356 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2357 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2358 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2359 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2360 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2361 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2362 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 2363 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 2364} 2365 2366typedef struct { 2367 DebugFrameHeader h; 2368 uint8_t fde_def_cfa[4]; 2369 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2370} DebugFrame; 2371 2372#define ELF_HOST_MACHINE EM_LOONGARCH 2373 2374static const DebugFrame debug_frame = { 2375 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2376 .h.cie.id = -1, 2377 .h.cie.version = 1, 2378 .h.cie.code_align = 1, 2379 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2380 .h.cie.return_column = TCG_REG_RA, 2381 2382 /* Total FDE size does not include the "len" member. */ 2383 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2384 2385 .fde_def_cfa = { 2386 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2387 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2388 (FRAME_SIZE >> 7) 2389 }, 2390 .fde_reg_ofs = { 2391 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 2392 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 2393 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 2394 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 2395 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 2396 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 2397 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 2398 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 2399 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 2400 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 2401 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 2402 } 2403}; 2404 2405void tcg_register_jit(const void *buf, size_t buf_size) 2406{ 2407 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2408} 2409