1/*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name>
5 *
6 * Based on tcg/riscv/tcg-target.c.inc
7 *
8 * Copyright (c) 2018 SiFive, Inc
9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
11 * Copyright (c) 2008 Fabrice Bellard
12 *
13 * Permission is hereby granted, free of charge, to any person obtaining a copy
14 * of this software and associated documentation files (the "Software"), to deal
15 * in the Software without restriction, including without limitation the rights
16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
17 * copies of the Software, and to permit persons to whom the Software is
18 * furnished to do so, subject to the following conditions:
19 *
20 * The above copyright notice and this permission notice shall be included in
21 * all copies or substantial portions of the Software.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
29 * THE SOFTWARE.
30 */
31
32#include "../tcg-ldst.c.inc"
33#include <asm/hwcap.h>
34
35bool use_lsx_instructions;
36
37#ifdef CONFIG_DEBUG_TCG
38static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
39    "zero",
40    "ra",
41    "tp",
42    "sp",
43    "a0",
44    "a1",
45    "a2",
46    "a3",
47    "a4",
48    "a5",
49    "a6",
50    "a7",
51    "t0",
52    "t1",
53    "t2",
54    "t3",
55    "t4",
56    "t5",
57    "t6",
58    "t7",
59    "t8",
60    "r21", /* reserved in the LP64* ABI, hence no ABI name */
61    "s9",
62    "s0",
63    "s1",
64    "s2",
65    "s3",
66    "s4",
67    "s5",
68    "s6",
69    "s7",
70    "s8",
71    "vr0",
72    "vr1",
73    "vr2",
74    "vr3",
75    "vr4",
76    "vr5",
77    "vr6",
78    "vr7",
79    "vr8",
80    "vr9",
81    "vr10",
82    "vr11",
83    "vr12",
84    "vr13",
85    "vr14",
86    "vr15",
87    "vr16",
88    "vr17",
89    "vr18",
90    "vr19",
91    "vr20",
92    "vr21",
93    "vr22",
94    "vr23",
95    "vr24",
96    "vr25",
97    "vr26",
98    "vr27",
99    "vr28",
100    "vr29",
101    "vr30",
102    "vr31",
103};
104#endif
105
106static const int tcg_target_reg_alloc_order[] = {
107    /* Registers preserved across calls */
108    /* TCG_REG_S0 reserved for TCG_AREG0 */
109    TCG_REG_S1,
110    TCG_REG_S2,
111    TCG_REG_S3,
112    TCG_REG_S4,
113    TCG_REG_S5,
114    TCG_REG_S6,
115    TCG_REG_S7,
116    TCG_REG_S8,
117    TCG_REG_S9,
118
119    /* Registers (potentially) clobbered across calls */
120    TCG_REG_T0,
121    TCG_REG_T1,
122    TCG_REG_T2,
123    TCG_REG_T3,
124    TCG_REG_T4,
125    TCG_REG_T5,
126    TCG_REG_T6,
127    TCG_REG_T7,
128    TCG_REG_T8,
129
130    /* Argument registers, opposite order of allocation.  */
131    TCG_REG_A7,
132    TCG_REG_A6,
133    TCG_REG_A5,
134    TCG_REG_A4,
135    TCG_REG_A3,
136    TCG_REG_A2,
137    TCG_REG_A1,
138    TCG_REG_A0,
139
140    /* Vector registers */
141    TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
142    TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
143    TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
144    TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
145    TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
146    TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
147    /* V24 - V31 are caller-saved, and skipped.  */
148};
149
150static const int tcg_target_call_iarg_regs[] = {
151    TCG_REG_A0,
152    TCG_REG_A1,
153    TCG_REG_A2,
154    TCG_REG_A3,
155    TCG_REG_A4,
156    TCG_REG_A5,
157    TCG_REG_A6,
158    TCG_REG_A7,
159};
160
161static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
162{
163    tcg_debug_assert(kind == TCG_CALL_RET_NORMAL);
164    tcg_debug_assert(slot >= 0 && slot <= 1);
165    return TCG_REG_A0 + slot;
166}
167
168#define TCG_GUEST_BASE_REG TCG_REG_S1
169
170#define TCG_CT_CONST_ZERO  0x100
171#define TCG_CT_CONST_S12   0x200
172#define TCG_CT_CONST_S32   0x400
173#define TCG_CT_CONST_U12   0x800
174#define TCG_CT_CONST_C12   0x1000
175#define TCG_CT_CONST_WSZ   0x2000
176#define TCG_CT_CONST_VCMP  0x4000
177#define TCG_CT_CONST_VADD  0x8000
178
179#define ALL_GENERAL_REGS   MAKE_64BIT_MASK(0, 32)
180#define ALL_VECTOR_REGS    MAKE_64BIT_MASK(32, 32)
181
182static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
183{
184    return sextract64(val, pos, len);
185}
186
187/* test if a constant matches the constraint */
188static bool tcg_target_const_match(int64_t val, TCGType type, int ct, int vece)
189{
190    if (ct & TCG_CT_CONST) {
191        return true;
192    }
193    if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
194        return true;
195    }
196    if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) {
197        return true;
198    }
199    if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
200        return true;
201    }
202    if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) {
203        return true;
204    }
205    if ((ct & TCG_CT_CONST_C12) && ~val >= 0 && ~val <= 0xfff) {
206        return true;
207    }
208    if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) {
209        return true;
210    }
211    int64_t vec_val = sextract64(val, 0, 8 << vece);
212    if ((ct & TCG_CT_CONST_VCMP) && -0x10 <= vec_val && vec_val <= 0x1f) {
213        return true;
214    }
215    if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) {
216        return true;
217    }
218    return false;
219}
220
221/*
222 * Relocations
223 */
224
225/*
226 * Relocation records defined in LoongArch ELF psABI v1.00 is way too
227 * complicated; a whopping stack machine is needed to stuff the fields, at
228 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are
229 * needed.
230 *
231 * Hence, define our own simpler relocation types. Numbers are chosen as to
232 * not collide with potential future additions to the true ELF relocation
233 * type enum.
234 */
235
236/* Field Sk16, shifted right by 2; suitable for conditional jumps */
237#define R_LOONGARCH_BR_SK16     256
238/* Field Sd10k16, shifted right by 2; suitable for B and BL */
239#define R_LOONGARCH_BR_SD10K16  257
240
241static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target)
242{
243    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
244    intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
245
246    tcg_debug_assert((offset & 3) == 0);
247    offset >>= 2;
248    if (offset == sextreg(offset, 0, 16)) {
249        *src_rw = deposit64(*src_rw, 10, 16, offset);
250        return true;
251    }
252
253    return false;
254}
255
256static bool reloc_br_sd10k16(tcg_insn_unit *src_rw,
257                             const tcg_insn_unit *target)
258{
259    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw);
260    intptr_t offset = (intptr_t)target - (intptr_t)src_rx;
261
262    tcg_debug_assert((offset & 3) == 0);
263    offset >>= 2;
264    if (offset == sextreg(offset, 0, 26)) {
265        *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */
266        *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */
267        return true;
268    }
269
270    return false;
271}
272
273static bool patch_reloc(tcg_insn_unit *code_ptr, int type,
274                        intptr_t value, intptr_t addend)
275{
276    tcg_debug_assert(addend == 0);
277    switch (type) {
278    case R_LOONGARCH_BR_SK16:
279        return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value);
280    case R_LOONGARCH_BR_SD10K16:
281        return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value);
282    default:
283        g_assert_not_reached();
284    }
285}
286
287#include "tcg-insn-defs.c.inc"
288
289/*
290 * TCG intrinsics
291 */
292
293static void tcg_out_mb(TCGContext *s, TCGArg a0)
294{
295    /* Baseline LoongArch only has the full barrier, unfortunately.  */
296    tcg_out_opc_dbar(s, 0);
297}
298
299static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
300{
301    if (ret == arg) {
302        return true;
303    }
304    switch (type) {
305    case TCG_TYPE_I32:
306    case TCG_TYPE_I64:
307        /*
308         * Conventional register-register move used in LoongArch is
309         * `or dst, src, zero`.
310         */
311        tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO);
312        break;
313    default:
314        g_assert_not_reached();
315    }
316    return true;
317}
318
319/* Loads a 32-bit immediate into rd, sign-extended.  */
320static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val)
321{
322    tcg_target_long lo = sextreg(val, 0, 12);
323    tcg_target_long hi12 = sextreg(val, 12, 20);
324
325    /* Single-instruction cases.  */
326    if (hi12 == 0) {
327        /* val fits in uimm12: ori rd, zero, val */
328        tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val);
329        return;
330    }
331    if (hi12 == sextreg(lo, 12, 20)) {
332        /* val fits in simm12: addi.w rd, zero, val */
333        tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val);
334        return;
335    }
336
337    /* High bits must be set; load with lu12i.w + optional ori.  */
338    tcg_out_opc_lu12i_w(s, rd, hi12);
339    if (lo != 0) {
340        tcg_out_opc_ori(s, rd, rd, lo & 0xfff);
341    }
342}
343
344static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
345                         tcg_target_long val)
346{
347    /*
348     * LoongArch conventionally loads 64-bit immediates in at most 4 steps,
349     * with dedicated instructions for filling the respective bitfields
350     * below:
351     *
352     *        6                   5                   4               3
353     *  3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2
354     * +-----------------------+---------------------------------------+...
355     * |          hi52         |                  hi32                 |
356     * +-----------------------+---------------------------------------+...
357     *       3                   2                   1
358     *     1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
359     * ...+-------------------------------------+-------------------------+
360     *    |                 hi12                |            lo           |
361     * ...+-------------------------------------+-------------------------+
362     *
363     * Check if val belong to one of the several fast cases, before falling
364     * back to the slow path.
365     */
366
367    intptr_t pc_offset;
368    tcg_target_long val_lo, val_hi, pc_hi, offset_hi;
369    tcg_target_long hi12, hi32, hi52;
370
371    /* Value fits in signed i32.  */
372    if (type == TCG_TYPE_I32 || val == (int32_t)val) {
373        tcg_out_movi_i32(s, rd, val);
374        return;
375    }
376
377    /* PC-relative cases.  */
378    pc_offset = tcg_pcrel_diff(s, (void *)val);
379    if (pc_offset == sextreg(pc_offset, 0, 22) && (pc_offset & 3) == 0) {
380        /* Single pcaddu2i.  */
381        tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2);
382        return;
383    }
384
385    if (pc_offset == (int32_t)pc_offset) {
386        /* Offset within 32 bits; load with pcalau12i + ori.  */
387        val_lo = sextreg(val, 0, 12);
388        val_hi = val >> 12;
389        pc_hi = (val - pc_offset) >> 12;
390        offset_hi = val_hi - pc_hi;
391
392        tcg_debug_assert(offset_hi == sextreg(offset_hi, 0, 20));
393        tcg_out_opc_pcalau12i(s, rd, offset_hi);
394        if (val_lo != 0) {
395            tcg_out_opc_ori(s, rd, rd, val_lo & 0xfff);
396        }
397        return;
398    }
399
400    hi12 = sextreg(val, 12, 20);
401    hi32 = sextreg(val, 32, 20);
402    hi52 = sextreg(val, 52, 12);
403
404    /* Single cu52i.d case.  */
405    if ((hi52 != 0) && (ctz64(val) >= 52)) {
406        tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52);
407        return;
408    }
409
410    /* Slow path.  Initialize the low 32 bits, then concat high bits.  */
411    tcg_out_movi_i32(s, rd, val);
412
413    /* Load hi32 and hi52 explicitly when they are unexpected values. */
414    if (hi32 != sextreg(hi12, 20, 20)) {
415        tcg_out_opc_cu32i_d(s, rd, hi32);
416    }
417
418    if (hi52 != sextreg(hi32, 20, 12)) {
419        tcg_out_opc_cu52i_d(s, rd, rd, hi52);
420    }
421}
422
423static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd,
424                         TCGReg rs, tcg_target_long imm)
425{
426    tcg_target_long lo12 = sextreg(imm, 0, 12);
427    tcg_target_long hi16 = sextreg(imm - lo12, 16, 16);
428
429    /*
430     * Note that there's a hole in between hi16 and lo12:
431     *
432     *       3                   2                   1                   0
433     *     1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
434     * ...+-------------------------------+-------+-----------------------+
435     *    |             hi16              |       |          lo12         |
436     * ...+-------------------------------+-------+-----------------------+
437     *
438     * For bits within that hole, it's more efficient to use LU12I and ADD.
439     */
440    if (imm == (hi16 << 16) + lo12) {
441        if (hi16) {
442            tcg_out_opc_addu16i_d(s, rd, rs, hi16);
443            rs = rd;
444        }
445        if (type == TCG_TYPE_I32) {
446            tcg_out_opc_addi_w(s, rd, rs, lo12);
447        } else if (lo12) {
448            tcg_out_opc_addi_d(s, rd, rs, lo12);
449        } else {
450            tcg_out_mov(s, type, rd, rs);
451        }
452    } else {
453        tcg_out_movi(s, type, TCG_REG_TMP0, imm);
454        if (type == TCG_TYPE_I32) {
455            tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0);
456        } else {
457            tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0);
458        }
459    }
460}
461
462static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2)
463{
464    return false;
465}
466
467static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs,
468                             tcg_target_long imm)
469{
470    /* This function is only used for passing structs by reference. */
471    g_assert_not_reached();
472}
473
474static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg)
475{
476    tcg_out_opc_andi(s, ret, arg, 0xff);
477}
478
479static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg)
480{
481    tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15);
482}
483
484static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg)
485{
486    tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31);
487}
488
489static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
490{
491    tcg_out_opc_sext_b(s, ret, arg);
492}
493
494static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
495{
496    tcg_out_opc_sext_h(s, ret, arg);
497}
498
499static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg)
500{
501    tcg_out_opc_addi_w(s, ret, arg, 0);
502}
503
504static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
505{
506    if (ret != arg) {
507        tcg_out_ext32s(s, ret, arg);
508    }
509}
510
511static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)
512{
513    tcg_out_ext32u(s, ret, arg);
514}
515
516static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg)
517{
518    tcg_out_ext32s(s, ret, arg);
519}
520
521static void tcg_out_clzctz(TCGContext *s, LoongArchInsn opc,
522                           TCGReg a0, TCGReg a1, TCGReg a2,
523                           bool c2, bool is_32bit)
524{
525    if (c2) {
526        /*
527         * Fast path: semantics already satisfied due to constraint and
528         * insn behavior, single instruction is enough.
529         */
530        tcg_debug_assert(a2 == (is_32bit ? 32 : 64));
531        /* all clz/ctz insns belong to DJ-format */
532        tcg_out32(s, encode_dj_insn(opc, a0, a1));
533        return;
534    }
535
536    tcg_out32(s, encode_dj_insn(opc, TCG_REG_TMP0, a1));
537    /* a0 = a1 ? REG_TMP0 : a2 */
538    tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1);
539    tcg_out_opc_masknez(s, a0, a2, a1);
540    tcg_out_opc_or(s, a0, TCG_REG_TMP0, a0);
541}
542
543#define SETCOND_INV    TCG_TARGET_NB_REGS
544#define SETCOND_NEZ    (SETCOND_INV << 1)
545#define SETCOND_FLAGS  (SETCOND_INV | SETCOND_NEZ)
546
547static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret,
548                               TCGReg arg1, tcg_target_long arg2, bool c2)
549{
550    int flags = 0;
551
552    switch (cond) {
553    case TCG_COND_EQ:    /* -> NE  */
554    case TCG_COND_GE:    /* -> LT  */
555    case TCG_COND_GEU:   /* -> LTU */
556    case TCG_COND_GT:    /* -> LE  */
557    case TCG_COND_GTU:   /* -> LEU */
558        cond = tcg_invert_cond(cond);
559        flags ^= SETCOND_INV;
560        break;
561    default:
562        break;
563    }
564
565    switch (cond) {
566    case TCG_COND_LE:
567    case TCG_COND_LEU:
568        /*
569         * If we have a constant input, the most efficient way to implement
570         * LE is by adding 1 and using LT.  Watch out for wrap around for LEU.
571         * We don't need to care for this for LE because the constant input
572         * is still constrained to int32_t, and INT32_MAX+1 is representable
573         * in the 64-bit temporary register.
574         */
575        if (c2) {
576            if (cond == TCG_COND_LEU) {
577                /* unsigned <= -1 is true */
578                if (arg2 == -1) {
579                    tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV));
580                    return ret;
581                }
582                cond = TCG_COND_LTU;
583            } else {
584                cond = TCG_COND_LT;
585            }
586            arg2 += 1;
587        } else {
588            TCGReg tmp = arg2;
589            arg2 = arg1;
590            arg1 = tmp;
591            cond = tcg_swap_cond(cond);    /* LE -> GE */
592            cond = tcg_invert_cond(cond);  /* GE -> LT */
593            flags ^= SETCOND_INV;
594        }
595        break;
596    default:
597        break;
598    }
599
600    switch (cond) {
601    case TCG_COND_NE:
602        flags |= SETCOND_NEZ;
603        if (!c2) {
604            tcg_out_opc_xor(s, ret, arg1, arg2);
605        } else if (arg2 == 0) {
606            ret = arg1;
607        } else if (arg2 >= 0 && arg2 <= 0xfff) {
608            tcg_out_opc_xori(s, ret, arg1, arg2);
609        } else {
610            tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2);
611        }
612        break;
613
614    case TCG_COND_LT:
615    case TCG_COND_LTU:
616        if (c2) {
617            if (arg2 >= -0x800 && arg2 <= 0x7ff) {
618                if (cond == TCG_COND_LT) {
619                    tcg_out_opc_slti(s, ret, arg1, arg2);
620                } else {
621                    tcg_out_opc_sltui(s, ret, arg1, arg2);
622                }
623                break;
624            }
625            tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2);
626            arg2 = TCG_REG_TMP0;
627        }
628        if (cond == TCG_COND_LT) {
629            tcg_out_opc_slt(s, ret, arg1, arg2);
630        } else {
631            tcg_out_opc_sltu(s, ret, arg1, arg2);
632        }
633        break;
634
635    default:
636        g_assert_not_reached();
637        break;
638    }
639
640    return ret | flags;
641}
642
643static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret,
644                            TCGReg arg1, tcg_target_long arg2, bool c2)
645{
646    int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2);
647
648    if (tmpflags != ret) {
649        TCGReg tmp = tmpflags & ~SETCOND_FLAGS;
650
651        switch (tmpflags & SETCOND_FLAGS) {
652        case SETCOND_INV:
653            /* Intermediate result is boolean: simply invert. */
654            tcg_out_opc_xori(s, ret, tmp, 1);
655            break;
656        case SETCOND_NEZ:
657            /* Intermediate result is zero/non-zero: test != 0. */
658            tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp);
659            break;
660        case SETCOND_NEZ | SETCOND_INV:
661            /* Intermediate result is zero/non-zero: test == 0. */
662            tcg_out_opc_sltui(s, ret, tmp, 1);
663            break;
664        default:
665            g_assert_not_reached();
666        }
667    }
668}
669
670static void tcg_out_movcond(TCGContext *s, TCGCond cond, TCGReg ret,
671                            TCGReg c1, tcg_target_long c2, bool const2,
672                            TCGReg v1, TCGReg v2)
673{
674    int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const2);
675    TCGReg t;
676
677    /* Standardize the test below to t != 0. */
678    if (tmpflags & SETCOND_INV) {
679        t = v1, v1 = v2, v2 = t;
680    }
681
682    t = tmpflags & ~SETCOND_FLAGS;
683    if (v1 == TCG_REG_ZERO) {
684        tcg_out_opc_masknez(s, ret, v2, t);
685    } else if (v2 == TCG_REG_ZERO) {
686        tcg_out_opc_maskeqz(s, ret, v1, t);
687    } else {
688        tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */
689        tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */
690        tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2);
691    }
692}
693
694/*
695 * Branch helpers
696 */
697
698static const struct {
699    LoongArchInsn op;
700    bool swap;
701} tcg_brcond_to_loongarch[] = {
702    [TCG_COND_EQ] =  { OPC_BEQ,  false },
703    [TCG_COND_NE] =  { OPC_BNE,  false },
704    [TCG_COND_LT] =  { OPC_BGT,  true  },
705    [TCG_COND_GE] =  { OPC_BLE,  true  },
706    [TCG_COND_LE] =  { OPC_BLE,  false },
707    [TCG_COND_GT] =  { OPC_BGT,  false },
708    [TCG_COND_LTU] = { OPC_BGTU, true  },
709    [TCG_COND_GEU] = { OPC_BLEU, true  },
710    [TCG_COND_LEU] = { OPC_BLEU, false },
711    [TCG_COND_GTU] = { OPC_BGTU, false }
712};
713
714static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1,
715                           TCGReg arg2, TCGLabel *l)
716{
717    LoongArchInsn op = tcg_brcond_to_loongarch[cond].op;
718
719    tcg_debug_assert(op != 0);
720
721    if (tcg_brcond_to_loongarch[cond].swap) {
722        TCGReg t = arg1;
723        arg1 = arg2;
724        arg2 = t;
725    }
726
727    /* all conditional branch insns belong to DJSk16-format */
728    tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0);
729    tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0));
730}
731
732static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail)
733{
734    TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA;
735    ptrdiff_t offset = tcg_pcrel_diff(s, arg);
736
737    tcg_debug_assert((offset & 3) == 0);
738    if (offset == sextreg(offset, 0, 28)) {
739        /* short jump: +/- 256MiB */
740        if (tail) {
741            tcg_out_opc_b(s, offset >> 2);
742        } else {
743            tcg_out_opc_bl(s, offset >> 2);
744        }
745    } else if (offset == sextreg(offset, 0, 38)) {
746        /* long jump: +/- 256GiB */
747        tcg_target_long lo = sextreg(offset, 0, 18);
748        tcg_target_long hi = offset - lo;
749        tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18);
750        tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2);
751    } else {
752        /* far jump: 64-bit */
753        tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18);
754        tcg_target_long hi = (tcg_target_long)arg - lo;
755        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi);
756        tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2);
757    }
758}
759
760static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg,
761                         const TCGHelperInfo *info)
762{
763    tcg_out_call_int(s, arg, false);
764}
765
766/*
767 * Load/store helpers
768 */
769
770static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data,
771                         TCGReg addr, intptr_t offset)
772{
773    intptr_t imm12 = sextreg(offset, 0, 12);
774
775    if (offset != imm12) {
776        intptr_t diff = tcg_pcrel_diff(s, (void *)offset);
777
778        if (addr == TCG_REG_ZERO && diff == (int32_t)diff) {
779            imm12 = sextreg(diff, 0, 12);
780            tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12);
781        } else {
782            tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12);
783            if (addr != TCG_REG_ZERO) {
784                tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr);
785            }
786        }
787        addr = TCG_REG_TMP2;
788    }
789
790    switch (opc) {
791    case OPC_LD_B:
792    case OPC_LD_BU:
793    case OPC_LD_H:
794    case OPC_LD_HU:
795    case OPC_LD_W:
796    case OPC_LD_WU:
797    case OPC_LD_D:
798    case OPC_ST_B:
799    case OPC_ST_H:
800    case OPC_ST_W:
801    case OPC_ST_D:
802        tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12));
803        break;
804    default:
805        g_assert_not_reached();
806    }
807}
808
809static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
810                       TCGReg arg1, intptr_t arg2)
811{
812    bool is_32bit = type == TCG_TYPE_I32;
813    tcg_out_ldst(s, is_32bit ? OPC_LD_W : OPC_LD_D, arg, arg1, arg2);
814}
815
816static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
817                       TCGReg arg1, intptr_t arg2)
818{
819    bool is_32bit = type == TCG_TYPE_I32;
820    tcg_out_ldst(s, is_32bit ? OPC_ST_W : OPC_ST_D, arg, arg1, arg2);
821}
822
823static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val,
824                        TCGReg base, intptr_t ofs)
825{
826    if (val == 0) {
827        tcg_out_st(s, type, TCG_REG_ZERO, base, ofs);
828        return true;
829    }
830    return false;
831}
832
833/*
834 * Load/store helpers for SoftMMU, and qemu_ld/st implementations
835 */
836
837static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target)
838{
839    tcg_out_opc_b(s, 0);
840    return reloc_br_sd10k16(s->code_ptr - 1, target);
841}
842
843static const TCGLdstHelperParam ldst_helper_param = {
844    .ntmp = 1, .tmp = { TCG_REG_TMP0 }
845};
846
847static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
848{
849    MemOp opc = get_memop(l->oi);
850
851    /* resolve label address */
852    if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
853        return false;
854    }
855
856    tcg_out_ld_helper_args(s, l, &ldst_helper_param);
857    tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false);
858    tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param);
859    return tcg_out_goto(s, l->raddr);
860}
861
862static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l)
863{
864    MemOp opc = get_memop(l->oi);
865
866    /* resolve label address */
867    if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) {
868        return false;
869    }
870
871    tcg_out_st_helper_args(s, l, &ldst_helper_param);
872    tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false);
873    return tcg_out_goto(s, l->raddr);
874}
875
876typedef struct {
877    TCGReg base;
878    TCGReg index;
879    TCGAtomAlign aa;
880} HostAddress;
881
882bool tcg_target_has_memory_bswap(MemOp memop)
883{
884    return false;
885}
886
887/* We expect to use a 12-bit negative offset from ENV.  */
888#define MIN_TLB_MASK_TABLE_OFS  -(1 << 11)
889
890/*
891 * For system-mode, perform the TLB load and compare.
892 * For user-mode, perform any required alignment tests.
893 * In both cases, return a TCGLabelQemuLdst structure if the slow path
894 * is required and fill in @h with the host address for the fast path.
895 */
896static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h,
897                                           TCGReg addr_reg, MemOpIdx oi,
898                                           bool is_ld)
899{
900    TCGType addr_type = s->addr_type;
901    TCGLabelQemuLdst *ldst = NULL;
902    MemOp opc = get_memop(oi);
903    MemOp a_bits;
904
905    h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false);
906    a_bits = h->aa.align;
907
908    if (tcg_use_softmmu) {
909        unsigned s_bits = opc & MO_SIZE;
910        int mem_index = get_mmuidx(oi);
911        int fast_ofs = tlb_mask_table_ofs(s, mem_index);
912        int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask);
913        int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table);
914
915        ldst = new_ldst_label(s);
916        ldst->is_ld = is_ld;
917        ldst->oi = oi;
918        ldst->addrlo_reg = addr_reg;
919
920        tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs);
921        tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs);
922
923        tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg,
924                           s->page_bits - CPU_TLB_ENTRY_BITS);
925        tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0);
926        tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1);
927
928        /* Load the tlb comparator and the addend.  */
929        QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN);
930        tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2,
931                   is_ld ? offsetof(CPUTLBEntry, addr_read)
932                         : offsetof(CPUTLBEntry, addr_write));
933        tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2,
934                   offsetof(CPUTLBEntry, addend));
935
936        /*
937         * For aligned accesses, we check the first byte and include the
938         * alignment bits within the address.  For unaligned access, we
939         * check that we don't cross pages using the address of the last
940         * byte of the access.
941         */
942        if (a_bits < s_bits) {
943            unsigned a_mask = (1u << a_bits) - 1;
944            unsigned s_mask = (1u << s_bits) - 1;
945            tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask);
946        } else {
947            tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg);
948        }
949        tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO,
950                              a_bits, s->page_bits - 1);
951
952        /* Compare masked address with the TLB entry.  */
953        ldst->label_ptr[0] = s->code_ptr;
954        tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0);
955
956        h->index = TCG_REG_TMP2;
957    } else {
958        if (a_bits) {
959            ldst = new_ldst_label(s);
960
961            ldst->is_ld = is_ld;
962            ldst->oi = oi;
963            ldst->addrlo_reg = addr_reg;
964
965            /*
966             * Without micro-architecture details, we don't know which of
967             * bstrpick or andi is faster, so use bstrpick as it's not
968             * constrained by imm field width. Not to say alignments >= 2^12
969             * are going to happen any time soon.
970             */
971            tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
972
973            ldst->label_ptr[0] = s->code_ptr;
974            tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0);
975        }
976
977        h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
978    }
979
980    if (addr_type == TCG_TYPE_I32) {
981        h->base = TCG_REG_TMP0;
982        tcg_out_ext32u(s, h->base, addr_reg);
983    } else {
984        h->base = addr_reg;
985    }
986
987    return ldst;
988}
989
990static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type,
991                                    TCGReg rd, HostAddress h)
992{
993    /* Byte swapping is left to middle-end expansion.  */
994    tcg_debug_assert((opc & MO_BSWAP) == 0);
995
996    switch (opc & MO_SSIZE) {
997    case MO_UB:
998        tcg_out_opc_ldx_bu(s, rd, h.base, h.index);
999        break;
1000    case MO_SB:
1001        tcg_out_opc_ldx_b(s, rd, h.base, h.index);
1002        break;
1003    case MO_UW:
1004        tcg_out_opc_ldx_hu(s, rd, h.base, h.index);
1005        break;
1006    case MO_SW:
1007        tcg_out_opc_ldx_h(s, rd, h.base, h.index);
1008        break;
1009    case MO_UL:
1010        if (type == TCG_TYPE_I64) {
1011            tcg_out_opc_ldx_wu(s, rd, h.base, h.index);
1012            break;
1013        }
1014        /* fallthrough */
1015    case MO_SL:
1016        tcg_out_opc_ldx_w(s, rd, h.base, h.index);
1017        break;
1018    case MO_UQ:
1019        tcg_out_opc_ldx_d(s, rd, h.base, h.index);
1020        break;
1021    default:
1022        g_assert_not_reached();
1023    }
1024}
1025
1026static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1027                            MemOpIdx oi, TCGType data_type)
1028{
1029    TCGLabelQemuLdst *ldst;
1030    HostAddress h;
1031
1032    ldst = prepare_host_addr(s, &h, addr_reg, oi, true);
1033    tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h);
1034
1035    if (ldst) {
1036        ldst->type = data_type;
1037        ldst->datalo_reg = data_reg;
1038        ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1039    }
1040}
1041
1042static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc,
1043                                    TCGReg rd, HostAddress h)
1044{
1045    /* Byte swapping is left to middle-end expansion.  */
1046    tcg_debug_assert((opc & MO_BSWAP) == 0);
1047
1048    switch (opc & MO_SIZE) {
1049    case MO_8:
1050        tcg_out_opc_stx_b(s, rd, h.base, h.index);
1051        break;
1052    case MO_16:
1053        tcg_out_opc_stx_h(s, rd, h.base, h.index);
1054        break;
1055    case MO_32:
1056        tcg_out_opc_stx_w(s, rd, h.base, h.index);
1057        break;
1058    case MO_64:
1059        tcg_out_opc_stx_d(s, rd, h.base, h.index);
1060        break;
1061    default:
1062        g_assert_not_reached();
1063    }
1064}
1065
1066static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1067                            MemOpIdx oi, TCGType data_type)
1068{
1069    TCGLabelQemuLdst *ldst;
1070    HostAddress h;
1071
1072    ldst = prepare_host_addr(s, &h, addr_reg, oi, false);
1073    tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h);
1074
1075    if (ldst) {
1076        ldst->type = data_type;
1077        ldst->datalo_reg = data_reg;
1078        ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1079    }
1080}
1081
1082static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi,
1083                                   TCGReg addr_reg, MemOpIdx oi, bool is_ld)
1084{
1085    TCGLabelQemuLdst *ldst;
1086    HostAddress h;
1087
1088    ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld);
1089
1090    if (h.aa.atom == MO_128) {
1091        /*
1092         * Use VLDX/VSTX when 128-bit atomicity is required.
1093         * If address is aligned to 16-bytes, the 128-bit load/store is atomic.
1094         */
1095        if (is_ld) {
1096            tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index);
1097            tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0);
1098            tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1);
1099        } else {
1100            tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0);
1101            tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1);
1102            tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index);
1103        }
1104    } else {
1105        /* Otherwise use a pair of LD/ST. */
1106        tcg_out_opc_add_d(s, TCG_REG_TMP0, h.base, h.index);
1107        if (is_ld) {
1108            tcg_out_opc_ld_d(s, data_lo, TCG_REG_TMP0, 0);
1109            tcg_out_opc_ld_d(s, data_hi, TCG_REG_TMP0, 8);
1110        } else {
1111            tcg_out_opc_st_d(s, data_lo, TCG_REG_TMP0, 0);
1112            tcg_out_opc_st_d(s, data_hi, TCG_REG_TMP0, 8);
1113        }
1114    }
1115
1116    if (ldst) {
1117        ldst->type = TCG_TYPE_I128;
1118        ldst->datalo_reg = data_lo;
1119        ldst->datahi_reg = data_hi;
1120        ldst->raddr = tcg_splitwx_to_rx(s->code_ptr);
1121    }
1122}
1123
1124/*
1125 * Entry-points
1126 */
1127
1128static const tcg_insn_unit *tb_ret_addr;
1129
1130static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0)
1131{
1132    /* Reuse the zeroing that exists for goto_ptr.  */
1133    if (a0 == 0) {
1134        tcg_out_call_int(s, tcg_code_gen_epilogue, true);
1135    } else {
1136        tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0);
1137        tcg_out_call_int(s, tb_ret_addr, true);
1138    }
1139}
1140
1141static void tcg_out_goto_tb(TCGContext *s, int which)
1142{
1143    /*
1144     * Direct branch, or load indirect address, to be patched
1145     * by tb_target_set_jmp_target.  Check indirect load offset
1146     * in range early, regardless of direct branch distance,
1147     * via assert within tcg_out_opc_pcaddu2i.
1148     */
1149    uintptr_t i_addr = get_jmp_target_addr(s, which);
1150    intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr);
1151
1152    set_jmp_insn_offset(s, which);
1153    tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2);
1154
1155    /* Finish the load and indirect branch. */
1156    tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0);
1157    tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0);
1158    set_jmp_reset_offset(s, which);
1159}
1160
1161void tb_target_set_jmp_target(const TranslationBlock *tb, int n,
1162                              uintptr_t jmp_rx, uintptr_t jmp_rw)
1163{
1164    uintptr_t d_addr = tb->jmp_target_addr[n];
1165    ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2;
1166    tcg_insn_unit insn;
1167
1168    /* Either directly branch, or load slot address for indirect branch. */
1169    if (d_disp == sextreg(d_disp, 0, 26)) {
1170        insn = encode_sd10k16_insn(OPC_B, d_disp);
1171    } else {
1172        uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n];
1173        intptr_t i_disp = i_addr - jmp_rx;
1174        insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2);
1175    }
1176
1177    qatomic_set((tcg_insn_unit *)jmp_rw, insn);
1178    flush_idcache_range(jmp_rx, jmp_rw, 4);
1179}
1180
1181static void tcg_out_op(TCGContext *s, TCGOpcode opc,
1182                       const TCGArg args[TCG_MAX_OP_ARGS],
1183                       const int const_args[TCG_MAX_OP_ARGS])
1184{
1185    TCGArg a0 = args[0];
1186    TCGArg a1 = args[1];
1187    TCGArg a2 = args[2];
1188    TCGArg a3 = args[3];
1189    int c2 = const_args[2];
1190
1191    switch (opc) {
1192    case INDEX_op_mb:
1193        tcg_out_mb(s, a0);
1194        break;
1195
1196    case INDEX_op_goto_ptr:
1197        tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0);
1198        break;
1199
1200    case INDEX_op_br:
1201        tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, arg_label(a0),
1202                      0);
1203        tcg_out_opc_b(s, 0);
1204        break;
1205
1206    case INDEX_op_brcond_i32:
1207    case INDEX_op_brcond_i64:
1208        tcg_out_brcond(s, a2, a0, a1, arg_label(args[3]));
1209        break;
1210
1211    case INDEX_op_extrh_i64_i32:
1212        tcg_out_opc_srai_d(s, a0, a1, 32);
1213        break;
1214
1215    case INDEX_op_not_i32:
1216    case INDEX_op_not_i64:
1217        tcg_out_opc_nor(s, a0, a1, TCG_REG_ZERO);
1218        break;
1219
1220    case INDEX_op_nor_i32:
1221    case INDEX_op_nor_i64:
1222        if (c2) {
1223            tcg_out_opc_ori(s, a0, a1, a2);
1224            tcg_out_opc_nor(s, a0, a0, TCG_REG_ZERO);
1225        } else {
1226            tcg_out_opc_nor(s, a0, a1, a2);
1227        }
1228        break;
1229
1230    case INDEX_op_andc_i32:
1231    case INDEX_op_andc_i64:
1232        if (c2) {
1233            /* guaranteed to fit due to constraint */
1234            tcg_out_opc_andi(s, a0, a1, ~a2);
1235        } else {
1236            tcg_out_opc_andn(s, a0, a1, a2);
1237        }
1238        break;
1239
1240    case INDEX_op_orc_i32:
1241    case INDEX_op_orc_i64:
1242        if (c2) {
1243            /* guaranteed to fit due to constraint */
1244            tcg_out_opc_ori(s, a0, a1, ~a2);
1245        } else {
1246            tcg_out_opc_orn(s, a0, a1, a2);
1247        }
1248        break;
1249
1250    case INDEX_op_and_i32:
1251    case INDEX_op_and_i64:
1252        if (c2) {
1253            tcg_out_opc_andi(s, a0, a1, a2);
1254        } else {
1255            tcg_out_opc_and(s, a0, a1, a2);
1256        }
1257        break;
1258
1259    case INDEX_op_or_i32:
1260    case INDEX_op_or_i64:
1261        if (c2) {
1262            tcg_out_opc_ori(s, a0, a1, a2);
1263        } else {
1264            tcg_out_opc_or(s, a0, a1, a2);
1265        }
1266        break;
1267
1268    case INDEX_op_xor_i32:
1269    case INDEX_op_xor_i64:
1270        if (c2) {
1271            tcg_out_opc_xori(s, a0, a1, a2);
1272        } else {
1273            tcg_out_opc_xor(s, a0, a1, a2);
1274        }
1275        break;
1276
1277    case INDEX_op_extract_i32:
1278        tcg_out_opc_bstrpick_w(s, a0, a1, a2, a2 + args[3] - 1);
1279        break;
1280    case INDEX_op_extract_i64:
1281        tcg_out_opc_bstrpick_d(s, a0, a1, a2, a2 + args[3] - 1);
1282        break;
1283
1284    case INDEX_op_deposit_i32:
1285        tcg_out_opc_bstrins_w(s, a0, a2, args[3], args[3] + args[4] - 1);
1286        break;
1287    case INDEX_op_deposit_i64:
1288        tcg_out_opc_bstrins_d(s, a0, a2, args[3], args[3] + args[4] - 1);
1289        break;
1290
1291    case INDEX_op_bswap16_i32:
1292    case INDEX_op_bswap16_i64:
1293        tcg_out_opc_revb_2h(s, a0, a1);
1294        if (a2 & TCG_BSWAP_OS) {
1295            tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0);
1296        } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1297            tcg_out_ext16u(s, a0, a0);
1298        }
1299        break;
1300
1301    case INDEX_op_bswap32_i32:
1302        /* All 32-bit values are computed sign-extended in the register.  */
1303        a2 = TCG_BSWAP_OS;
1304        /* fallthrough */
1305    case INDEX_op_bswap32_i64:
1306        tcg_out_opc_revb_2w(s, a0, a1);
1307        if (a2 & TCG_BSWAP_OS) {
1308            tcg_out_ext32s(s, a0, a0);
1309        } else if ((a2 & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) {
1310            tcg_out_ext32u(s, a0, a0);
1311        }
1312        break;
1313
1314    case INDEX_op_bswap64_i64:
1315        tcg_out_opc_revb_d(s, a0, a1);
1316        break;
1317
1318    case INDEX_op_clz_i32:
1319        tcg_out_clzctz(s, OPC_CLZ_W, a0, a1, a2, c2, true);
1320        break;
1321    case INDEX_op_clz_i64:
1322        tcg_out_clzctz(s, OPC_CLZ_D, a0, a1, a2, c2, false);
1323        break;
1324
1325    case INDEX_op_ctz_i32:
1326        tcg_out_clzctz(s, OPC_CTZ_W, a0, a1, a2, c2, true);
1327        break;
1328    case INDEX_op_ctz_i64:
1329        tcg_out_clzctz(s, OPC_CTZ_D, a0, a1, a2, c2, false);
1330        break;
1331
1332    case INDEX_op_shl_i32:
1333        if (c2) {
1334            tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f);
1335        } else {
1336            tcg_out_opc_sll_w(s, a0, a1, a2);
1337        }
1338        break;
1339    case INDEX_op_shl_i64:
1340        if (c2) {
1341            tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f);
1342        } else {
1343            tcg_out_opc_sll_d(s, a0, a1, a2);
1344        }
1345        break;
1346
1347    case INDEX_op_shr_i32:
1348        if (c2) {
1349            tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f);
1350        } else {
1351            tcg_out_opc_srl_w(s, a0, a1, a2);
1352        }
1353        break;
1354    case INDEX_op_shr_i64:
1355        if (c2) {
1356            tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f);
1357        } else {
1358            tcg_out_opc_srl_d(s, a0, a1, a2);
1359        }
1360        break;
1361
1362    case INDEX_op_sar_i32:
1363        if (c2) {
1364            tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f);
1365        } else {
1366            tcg_out_opc_sra_w(s, a0, a1, a2);
1367        }
1368        break;
1369    case INDEX_op_sar_i64:
1370        if (c2) {
1371            tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f);
1372        } else {
1373            tcg_out_opc_sra_d(s, a0, a1, a2);
1374        }
1375        break;
1376
1377    case INDEX_op_rotl_i32:
1378        /* transform into equivalent rotr/rotri */
1379        if (c2) {
1380            tcg_out_opc_rotri_w(s, a0, a1, (32 - a2) & 0x1f);
1381        } else {
1382            tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
1383            tcg_out_opc_rotr_w(s, a0, a1, TCG_REG_TMP0);
1384        }
1385        break;
1386    case INDEX_op_rotl_i64:
1387        /* transform into equivalent rotr/rotri */
1388        if (c2) {
1389            tcg_out_opc_rotri_d(s, a0, a1, (64 - a2) & 0x3f);
1390        } else {
1391            tcg_out_opc_sub_w(s, TCG_REG_TMP0, TCG_REG_ZERO, a2);
1392            tcg_out_opc_rotr_d(s, a0, a1, TCG_REG_TMP0);
1393        }
1394        break;
1395
1396    case INDEX_op_rotr_i32:
1397        if (c2) {
1398            tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f);
1399        } else {
1400            tcg_out_opc_rotr_w(s, a0, a1, a2);
1401        }
1402        break;
1403    case INDEX_op_rotr_i64:
1404        if (c2) {
1405            tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f);
1406        } else {
1407            tcg_out_opc_rotr_d(s, a0, a1, a2);
1408        }
1409        break;
1410
1411    case INDEX_op_add_i32:
1412        if (c2) {
1413            tcg_out_addi(s, TCG_TYPE_I32, a0, a1, a2);
1414        } else {
1415            tcg_out_opc_add_w(s, a0, a1, a2);
1416        }
1417        break;
1418    case INDEX_op_add_i64:
1419        if (c2) {
1420            tcg_out_addi(s, TCG_TYPE_I64, a0, a1, a2);
1421        } else {
1422            tcg_out_opc_add_d(s, a0, a1, a2);
1423        }
1424        break;
1425
1426    case INDEX_op_sub_i32:
1427        if (c2) {
1428            tcg_out_addi(s, TCG_TYPE_I32, a0, a1, -a2);
1429        } else {
1430            tcg_out_opc_sub_w(s, a0, a1, a2);
1431        }
1432        break;
1433    case INDEX_op_sub_i64:
1434        if (c2) {
1435            tcg_out_addi(s, TCG_TYPE_I64, a0, a1, -a2);
1436        } else {
1437            tcg_out_opc_sub_d(s, a0, a1, a2);
1438        }
1439        break;
1440
1441    case INDEX_op_mul_i32:
1442        tcg_out_opc_mul_w(s, a0, a1, a2);
1443        break;
1444    case INDEX_op_mul_i64:
1445        tcg_out_opc_mul_d(s, a0, a1, a2);
1446        break;
1447
1448    case INDEX_op_mulsh_i32:
1449        tcg_out_opc_mulh_w(s, a0, a1, a2);
1450        break;
1451    case INDEX_op_mulsh_i64:
1452        tcg_out_opc_mulh_d(s, a0, a1, a2);
1453        break;
1454
1455    case INDEX_op_muluh_i32:
1456        tcg_out_opc_mulh_wu(s, a0, a1, a2);
1457        break;
1458    case INDEX_op_muluh_i64:
1459        tcg_out_opc_mulh_du(s, a0, a1, a2);
1460        break;
1461
1462    case INDEX_op_div_i32:
1463        tcg_out_opc_div_w(s, a0, a1, a2);
1464        break;
1465    case INDEX_op_div_i64:
1466        tcg_out_opc_div_d(s, a0, a1, a2);
1467        break;
1468
1469    case INDEX_op_divu_i32:
1470        tcg_out_opc_div_wu(s, a0, a1, a2);
1471        break;
1472    case INDEX_op_divu_i64:
1473        tcg_out_opc_div_du(s, a0, a1, a2);
1474        break;
1475
1476    case INDEX_op_rem_i32:
1477        tcg_out_opc_mod_w(s, a0, a1, a2);
1478        break;
1479    case INDEX_op_rem_i64:
1480        tcg_out_opc_mod_d(s, a0, a1, a2);
1481        break;
1482
1483    case INDEX_op_remu_i32:
1484        tcg_out_opc_mod_wu(s, a0, a1, a2);
1485        break;
1486    case INDEX_op_remu_i64:
1487        tcg_out_opc_mod_du(s, a0, a1, a2);
1488        break;
1489
1490    case INDEX_op_setcond_i32:
1491    case INDEX_op_setcond_i64:
1492        tcg_out_setcond(s, args[3], a0, a1, a2, c2);
1493        break;
1494
1495    case INDEX_op_movcond_i32:
1496    case INDEX_op_movcond_i64:
1497        tcg_out_movcond(s, args[5], a0, a1, a2, c2, args[3], args[4]);
1498        break;
1499
1500    case INDEX_op_ld8s_i32:
1501    case INDEX_op_ld8s_i64:
1502        tcg_out_ldst(s, OPC_LD_B, a0, a1, a2);
1503        break;
1504    case INDEX_op_ld8u_i32:
1505    case INDEX_op_ld8u_i64:
1506        tcg_out_ldst(s, OPC_LD_BU, a0, a1, a2);
1507        break;
1508    case INDEX_op_ld16s_i32:
1509    case INDEX_op_ld16s_i64:
1510        tcg_out_ldst(s, OPC_LD_H, a0, a1, a2);
1511        break;
1512    case INDEX_op_ld16u_i32:
1513    case INDEX_op_ld16u_i64:
1514        tcg_out_ldst(s, OPC_LD_HU, a0, a1, a2);
1515        break;
1516    case INDEX_op_ld_i32:
1517    case INDEX_op_ld32s_i64:
1518        tcg_out_ldst(s, OPC_LD_W, a0, a1, a2);
1519        break;
1520    case INDEX_op_ld32u_i64:
1521        tcg_out_ldst(s, OPC_LD_WU, a0, a1, a2);
1522        break;
1523    case INDEX_op_ld_i64:
1524        tcg_out_ldst(s, OPC_LD_D, a0, a1, a2);
1525        break;
1526
1527    case INDEX_op_st8_i32:
1528    case INDEX_op_st8_i64:
1529        tcg_out_ldst(s, OPC_ST_B, a0, a1, a2);
1530        break;
1531    case INDEX_op_st16_i32:
1532    case INDEX_op_st16_i64:
1533        tcg_out_ldst(s, OPC_ST_H, a0, a1, a2);
1534        break;
1535    case INDEX_op_st_i32:
1536    case INDEX_op_st32_i64:
1537        tcg_out_ldst(s, OPC_ST_W, a0, a1, a2);
1538        break;
1539    case INDEX_op_st_i64:
1540        tcg_out_ldst(s, OPC_ST_D, a0, a1, a2);
1541        break;
1542
1543    case INDEX_op_qemu_ld_a32_i32:
1544    case INDEX_op_qemu_ld_a64_i32:
1545        tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
1546        break;
1547    case INDEX_op_qemu_ld_a32_i64:
1548    case INDEX_op_qemu_ld_a64_i64:
1549        tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
1550        break;
1551    case INDEX_op_qemu_ld_a32_i128:
1552    case INDEX_op_qemu_ld_a64_i128:
1553        tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true);
1554        break;
1555    case INDEX_op_qemu_st_a32_i32:
1556    case INDEX_op_qemu_st_a64_i32:
1557        tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
1558        break;
1559    case INDEX_op_qemu_st_a32_i64:
1560    case INDEX_op_qemu_st_a64_i64:
1561        tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
1562        break;
1563    case INDEX_op_qemu_st_a32_i128:
1564    case INDEX_op_qemu_st_a64_i128:
1565        tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false);
1566        break;
1567
1568    case INDEX_op_mov_i32:  /* Always emitted via tcg_out_mov.  */
1569    case INDEX_op_mov_i64:
1570    case INDEX_op_call:     /* Always emitted via tcg_out_call.  */
1571    case INDEX_op_exit_tb:  /* Always emitted via tcg_out_exit_tb.  */
1572    case INDEX_op_goto_tb:  /* Always emitted via tcg_out_goto_tb.  */
1573    case INDEX_op_ext8s_i32:  /* Always emitted via tcg_reg_alloc_op.  */
1574    case INDEX_op_ext8s_i64:
1575    case INDEX_op_ext8u_i32:
1576    case INDEX_op_ext8u_i64:
1577    case INDEX_op_ext16s_i32:
1578    case INDEX_op_ext16s_i64:
1579    case INDEX_op_ext16u_i32:
1580    case INDEX_op_ext16u_i64:
1581    case INDEX_op_ext32s_i64:
1582    case INDEX_op_ext32u_i64:
1583    case INDEX_op_ext_i32_i64:
1584    case INDEX_op_extu_i32_i64:
1585    case INDEX_op_extrl_i64_i32:
1586    default:
1587        g_assert_not_reached();
1588    }
1589}
1590
1591static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece,
1592                            TCGReg rd, TCGReg rs)
1593{
1594    switch (vece) {
1595    case MO_8:
1596        tcg_out_opc_vreplgr2vr_b(s, rd, rs);
1597        break;
1598    case MO_16:
1599        tcg_out_opc_vreplgr2vr_h(s, rd, rs);
1600        break;
1601    case MO_32:
1602        tcg_out_opc_vreplgr2vr_w(s, rd, rs);
1603        break;
1604    case MO_64:
1605        tcg_out_opc_vreplgr2vr_d(s, rd, rs);
1606        break;
1607    default:
1608        g_assert_not_reached();
1609    }
1610    return true;
1611}
1612
1613static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece,
1614                             TCGReg r, TCGReg base, intptr_t offset)
1615{
1616    /* Handle imm overflow and division (vldrepl.d imm is divided by 8) */
1617    if (offset < -0x800 || offset > 0x7ff || \
1618        (offset & ((1 << vece) - 1)) != 0) {
1619        tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset);
1620        base = TCG_REG_TMP0;
1621        offset = 0;
1622    }
1623    offset >>= vece;
1624
1625    switch (vece) {
1626    case MO_8:
1627        tcg_out_opc_vldrepl_b(s, r, base, offset);
1628        break;
1629    case MO_16:
1630        tcg_out_opc_vldrepl_h(s, r, base, offset);
1631        break;
1632    case MO_32:
1633        tcg_out_opc_vldrepl_w(s, r, base, offset);
1634        break;
1635    case MO_64:
1636        tcg_out_opc_vldrepl_d(s, r, base, offset);
1637        break;
1638    default:
1639        g_assert_not_reached();
1640    }
1641    return true;
1642}
1643
1644static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece,
1645                             TCGReg rd, int64_t v64)
1646{
1647    /* Try vldi if imm can fit */
1648    int64_t value = sextract64(v64, 0, 8 << vece);
1649    if (-0x200 <= value && value <= 0x1FF) {
1650        uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF);
1651        tcg_out_opc_vldi(s, rd, imm);
1652        return;
1653    }
1654
1655    /* TODO: vldi patterns when imm 12 is set */
1656
1657    /* Fallback to vreplgr2vr */
1658    tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value);
1659    switch (vece) {
1660    case MO_8:
1661        tcg_out_opc_vreplgr2vr_b(s, rd, TCG_REG_TMP0);
1662        break;
1663    case MO_16:
1664        tcg_out_opc_vreplgr2vr_h(s, rd, TCG_REG_TMP0);
1665        break;
1666    case MO_32:
1667        tcg_out_opc_vreplgr2vr_w(s, rd, TCG_REG_TMP0);
1668        break;
1669    case MO_64:
1670        tcg_out_opc_vreplgr2vr_d(s, rd, TCG_REG_TMP0);
1671        break;
1672    default:
1673        g_assert_not_reached();
1674    }
1675}
1676
1677static void tcg_out_addsub_vec(TCGContext *s, unsigned vece, const TCGArg a0,
1678                               const TCGArg a1, const TCGArg a2,
1679                               bool a2_is_const, bool is_add)
1680{
1681    static const LoongArchInsn add_vec_insn[4] = {
1682        OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D
1683    };
1684    static const LoongArchInsn add_vec_imm_insn[4] = {
1685        OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU
1686    };
1687    static const LoongArchInsn sub_vec_insn[4] = {
1688        OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D
1689    };
1690    static const LoongArchInsn sub_vec_imm_insn[4] = {
1691        OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU
1692    };
1693
1694    if (a2_is_const) {
1695        int64_t value = sextract64(a2, 0, 8 << vece);
1696        if (!is_add) {
1697            value = -value;
1698        }
1699
1700        /* Try vaddi/vsubi */
1701        if (0 <= value && value <= 0x1f) {
1702            tcg_out32(s, encode_vdvjuk5_insn(add_vec_imm_insn[vece], a0, \
1703                                             a1, value));
1704            return;
1705        } else if (-0x1f <= value && value < 0) {
1706            tcg_out32(s, encode_vdvjuk5_insn(sub_vec_imm_insn[vece], a0, \
1707                                             a1, -value));
1708            return;
1709        }
1710
1711        /* constraint TCG_CT_CONST_VADD ensures unreachable */
1712        g_assert_not_reached();
1713    }
1714
1715    if (is_add) {
1716        tcg_out32(s, encode_vdvjvk_insn(add_vec_insn[vece], a0, a1, a2));
1717    } else {
1718        tcg_out32(s, encode_vdvjvk_insn(sub_vec_insn[vece], a0, a1, a2));
1719    }
1720}
1721
1722static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
1723                           unsigned vecl, unsigned vece,
1724                           const TCGArg args[TCG_MAX_OP_ARGS],
1725                           const int const_args[TCG_MAX_OP_ARGS])
1726{
1727    TCGType type = vecl + TCG_TYPE_V64;
1728    TCGArg a0, a1, a2, a3;
1729    TCGReg temp = TCG_REG_TMP0;
1730    TCGReg temp_vec = TCG_VEC_TMP0;
1731
1732    static const LoongArchInsn cmp_vec_insn[16][4] = {
1733        [TCG_COND_EQ] = {OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D},
1734        [TCG_COND_LE] = {OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D},
1735        [TCG_COND_LEU] = {OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU},
1736        [TCG_COND_LT] = {OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D},
1737        [TCG_COND_LTU] = {OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU},
1738    };
1739    static const LoongArchInsn cmp_vec_imm_insn[16][4] = {
1740        [TCG_COND_EQ] = {OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D},
1741        [TCG_COND_LE] = {OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D},
1742        [TCG_COND_LEU] = {OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU},
1743        [TCG_COND_LT] = {OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D},
1744        [TCG_COND_LTU] = {OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU},
1745    };
1746    LoongArchInsn insn;
1747    static const LoongArchInsn neg_vec_insn[4] = {
1748        OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D
1749    };
1750    static const LoongArchInsn mul_vec_insn[4] = {
1751        OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D
1752    };
1753    static const LoongArchInsn smin_vec_insn[4] = {
1754        OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D
1755    };
1756    static const LoongArchInsn umin_vec_insn[4] = {
1757        OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU
1758    };
1759    static const LoongArchInsn smax_vec_insn[4] = {
1760        OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D
1761    };
1762    static const LoongArchInsn umax_vec_insn[4] = {
1763        OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU
1764    };
1765    static const LoongArchInsn ssadd_vec_insn[4] = {
1766        OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D
1767    };
1768    static const LoongArchInsn usadd_vec_insn[4] = {
1769        OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU
1770    };
1771    static const LoongArchInsn sssub_vec_insn[4] = {
1772        OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D
1773    };
1774    static const LoongArchInsn ussub_vec_insn[4] = {
1775        OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU
1776    };
1777    static const LoongArchInsn shlv_vec_insn[4] = {
1778        OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D
1779    };
1780    static const LoongArchInsn shrv_vec_insn[4] = {
1781        OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D
1782    };
1783    static const LoongArchInsn sarv_vec_insn[4] = {
1784        OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D
1785    };
1786    static const LoongArchInsn shli_vec_insn[4] = {
1787        OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D
1788    };
1789    static const LoongArchInsn shri_vec_insn[4] = {
1790        OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D
1791    };
1792    static const LoongArchInsn sari_vec_insn[4] = {
1793        OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D
1794    };
1795    static const LoongArchInsn rotrv_vec_insn[4] = {
1796        OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D
1797    };
1798
1799    a0 = args[0];
1800    a1 = args[1];
1801    a2 = args[2];
1802    a3 = args[3];
1803
1804    /* Currently only supports V128 */
1805    tcg_debug_assert(type == TCG_TYPE_V128);
1806
1807    switch (opc) {
1808    case INDEX_op_st_vec:
1809        /* Try to fit vst imm */
1810        if (-0x800 <= a2 && a2 <= 0x7ff) {
1811            tcg_out_opc_vst(s, a0, a1, a2);
1812        } else {
1813            tcg_out_movi(s, TCG_TYPE_I64, temp, a2);
1814            tcg_out_opc_vstx(s, a0, a1, temp);
1815        }
1816        break;
1817    case INDEX_op_ld_vec:
1818        /* Try to fit vld imm */
1819        if (-0x800 <= a2 && a2 <= 0x7ff) {
1820            tcg_out_opc_vld(s, a0, a1, a2);
1821        } else {
1822            tcg_out_movi(s, TCG_TYPE_I64, temp, a2);
1823            tcg_out_opc_vldx(s, a0, a1, temp);
1824        }
1825        break;
1826    case INDEX_op_and_vec:
1827        tcg_out_opc_vand_v(s, a0, a1, a2);
1828        break;
1829    case INDEX_op_andc_vec:
1830        /*
1831         * vandn vd, vj, vk: vd = vk & ~vj
1832         * andc_vec vd, vj, vk: vd = vj & ~vk
1833         * vk and vk are swapped
1834         */
1835        tcg_out_opc_vandn_v(s, a0, a2, a1);
1836        break;
1837    case INDEX_op_or_vec:
1838        tcg_out_opc_vor_v(s, a0, a1, a2);
1839        break;
1840    case INDEX_op_orc_vec:
1841        tcg_out_opc_vorn_v(s, a0, a1, a2);
1842        break;
1843    case INDEX_op_xor_vec:
1844        tcg_out_opc_vxor_v(s, a0, a1, a2);
1845        break;
1846    case INDEX_op_nor_vec:
1847        tcg_out_opc_vnor_v(s, a0, a1, a2);
1848        break;
1849    case INDEX_op_not_vec:
1850        tcg_out_opc_vnor_v(s, a0, a1, a1);
1851        break;
1852    case INDEX_op_cmp_vec:
1853        {
1854            TCGCond cond = args[3];
1855            if (const_args[2]) {
1856                /*
1857                 * cmp_vec dest, src, value
1858                 * Try vseqi/vslei/vslti
1859                 */
1860                int64_t value = sextract64(a2, 0, 8 << vece);
1861                if ((cond == TCG_COND_EQ || cond == TCG_COND_LE || \
1862                     cond == TCG_COND_LT) && (-0x10 <= value && value <= 0x0f)) {
1863                    tcg_out32(s, encode_vdvjsk5_insn(cmp_vec_imm_insn[cond][vece], \
1864                                                     a0, a1, value));
1865                    break;
1866                } else if ((cond == TCG_COND_LEU || cond == TCG_COND_LTU) &&
1867                    (0x00 <= value && value <= 0x1f)) {
1868                    tcg_out32(s, encode_vdvjuk5_insn(cmp_vec_imm_insn[cond][vece], \
1869                                                     a0, a1, value));
1870                    break;
1871                }
1872
1873                /*
1874                 * Fallback to:
1875                 * dupi_vec temp, a2
1876                 * cmp_vec a0, a1, temp, cond
1877                 */
1878                tcg_out_dupi_vec(s, type, vece, temp_vec, a2);
1879                a2 = temp_vec;
1880            }
1881
1882            insn = cmp_vec_insn[cond][vece];
1883            if (insn == 0) {
1884                TCGArg t;
1885                t = a1, a1 = a2, a2 = t;
1886                cond = tcg_swap_cond(cond);
1887                insn = cmp_vec_insn[cond][vece];
1888                tcg_debug_assert(insn != 0);
1889            }
1890            tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2));
1891        }
1892        break;
1893    case INDEX_op_add_vec:
1894        tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], true);
1895        break;
1896    case INDEX_op_sub_vec:
1897        tcg_out_addsub_vec(s, vece, a0, a1, a2, const_args[2], false);
1898        break;
1899    case INDEX_op_neg_vec:
1900        tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], a0, a1));
1901        break;
1902    case INDEX_op_mul_vec:
1903        tcg_out32(s, encode_vdvjvk_insn(mul_vec_insn[vece], a0, a1, a2));
1904        break;
1905    case INDEX_op_smin_vec:
1906        tcg_out32(s, encode_vdvjvk_insn(smin_vec_insn[vece], a0, a1, a2));
1907        break;
1908    case INDEX_op_smax_vec:
1909        tcg_out32(s, encode_vdvjvk_insn(smax_vec_insn[vece], a0, a1, a2));
1910        break;
1911    case INDEX_op_umin_vec:
1912        tcg_out32(s, encode_vdvjvk_insn(umin_vec_insn[vece], a0, a1, a2));
1913        break;
1914    case INDEX_op_umax_vec:
1915        tcg_out32(s, encode_vdvjvk_insn(umax_vec_insn[vece], a0, a1, a2));
1916        break;
1917    case INDEX_op_ssadd_vec:
1918        tcg_out32(s, encode_vdvjvk_insn(ssadd_vec_insn[vece], a0, a1, a2));
1919        break;
1920    case INDEX_op_usadd_vec:
1921        tcg_out32(s, encode_vdvjvk_insn(usadd_vec_insn[vece], a0, a1, a2));
1922        break;
1923    case INDEX_op_sssub_vec:
1924        tcg_out32(s, encode_vdvjvk_insn(sssub_vec_insn[vece], a0, a1, a2));
1925        break;
1926    case INDEX_op_ussub_vec:
1927        tcg_out32(s, encode_vdvjvk_insn(ussub_vec_insn[vece], a0, a1, a2));
1928        break;
1929    case INDEX_op_shlv_vec:
1930        tcg_out32(s, encode_vdvjvk_insn(shlv_vec_insn[vece], a0, a1, a2));
1931        break;
1932    case INDEX_op_shrv_vec:
1933        tcg_out32(s, encode_vdvjvk_insn(shrv_vec_insn[vece], a0, a1, a2));
1934        break;
1935    case INDEX_op_sarv_vec:
1936        tcg_out32(s, encode_vdvjvk_insn(sarv_vec_insn[vece], a0, a1, a2));
1937        break;
1938    case INDEX_op_shli_vec:
1939        tcg_out32(s, encode_vdvjuk3_insn(shli_vec_insn[vece], a0, a1, a2));
1940        break;
1941    case INDEX_op_shri_vec:
1942        tcg_out32(s, encode_vdvjuk3_insn(shri_vec_insn[vece], a0, a1, a2));
1943        break;
1944    case INDEX_op_sari_vec:
1945        tcg_out32(s, encode_vdvjuk3_insn(sari_vec_insn[vece], a0, a1, a2));
1946        break;
1947    case INDEX_op_rotrv_vec:
1948        tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1, a2));
1949        break;
1950    case INDEX_op_rotlv_vec:
1951        /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */
1952        tcg_out32(s, encode_vdvj_insn(neg_vec_insn[vece], temp_vec, a2));
1953        tcg_out32(s, encode_vdvjvk_insn(rotrv_vec_insn[vece], a0, a1,
1954                                        temp_vec));
1955        break;
1956    case INDEX_op_rotli_vec:
1957        /* rotli_vec a1, a2 = rotri_vec a1, -a2 */
1958        a2 = extract32(-a2, 0, 3 + vece);
1959        switch (vece) {
1960        case MO_8:
1961            tcg_out_opc_vrotri_b(s, a0, a1, a2);
1962            break;
1963        case MO_16:
1964            tcg_out_opc_vrotri_h(s, a0, a1, a2);
1965            break;
1966        case MO_32:
1967            tcg_out_opc_vrotri_w(s, a0, a1, a2);
1968            break;
1969        case MO_64:
1970            tcg_out_opc_vrotri_d(s, a0, a1, a2);
1971            break;
1972        default:
1973            g_assert_not_reached();
1974        }
1975        break;
1976    case INDEX_op_bitsel_vec:
1977        /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */
1978        tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1);
1979        break;
1980    case INDEX_op_dupm_vec:
1981        tcg_out_dupm_vec(s, type, vece, a0, a1, a2);
1982        break;
1983    default:
1984        g_assert_not_reached();
1985    }
1986}
1987
1988int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
1989{
1990    switch (opc) {
1991    case INDEX_op_ld_vec:
1992    case INDEX_op_st_vec:
1993    case INDEX_op_dup_vec:
1994    case INDEX_op_dupm_vec:
1995    case INDEX_op_cmp_vec:
1996    case INDEX_op_add_vec:
1997    case INDEX_op_sub_vec:
1998    case INDEX_op_and_vec:
1999    case INDEX_op_andc_vec:
2000    case INDEX_op_or_vec:
2001    case INDEX_op_orc_vec:
2002    case INDEX_op_xor_vec:
2003    case INDEX_op_nor_vec:
2004    case INDEX_op_not_vec:
2005    case INDEX_op_neg_vec:
2006    case INDEX_op_mul_vec:
2007    case INDEX_op_smin_vec:
2008    case INDEX_op_smax_vec:
2009    case INDEX_op_umin_vec:
2010    case INDEX_op_umax_vec:
2011    case INDEX_op_ssadd_vec:
2012    case INDEX_op_usadd_vec:
2013    case INDEX_op_sssub_vec:
2014    case INDEX_op_ussub_vec:
2015    case INDEX_op_shlv_vec:
2016    case INDEX_op_shrv_vec:
2017    case INDEX_op_sarv_vec:
2018    case INDEX_op_bitsel_vec:
2019        return 1;
2020    default:
2021        return 0;
2022    }
2023}
2024
2025void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece,
2026                       TCGArg a0, ...)
2027{
2028    g_assert_not_reached();
2029}
2030
2031static TCGConstraintSetIndex tcg_target_op_def(TCGOpcode op)
2032{
2033    switch (op) {
2034    case INDEX_op_goto_ptr:
2035        return C_O0_I1(r);
2036
2037    case INDEX_op_st8_i32:
2038    case INDEX_op_st8_i64:
2039    case INDEX_op_st16_i32:
2040    case INDEX_op_st16_i64:
2041    case INDEX_op_st32_i64:
2042    case INDEX_op_st_i32:
2043    case INDEX_op_st_i64:
2044    case INDEX_op_qemu_st_a32_i32:
2045    case INDEX_op_qemu_st_a64_i32:
2046    case INDEX_op_qemu_st_a32_i64:
2047    case INDEX_op_qemu_st_a64_i64:
2048        return C_O0_I2(rZ, r);
2049
2050    case INDEX_op_qemu_ld_a32_i128:
2051    case INDEX_op_qemu_ld_a64_i128:
2052        return C_O2_I1(r, r, r);
2053
2054    case INDEX_op_qemu_st_a32_i128:
2055    case INDEX_op_qemu_st_a64_i128:
2056        return C_O0_I3(r, r, r);
2057
2058    case INDEX_op_brcond_i32:
2059    case INDEX_op_brcond_i64:
2060        return C_O0_I2(rZ, rZ);
2061
2062    case INDEX_op_ext8s_i32:
2063    case INDEX_op_ext8s_i64:
2064    case INDEX_op_ext8u_i32:
2065    case INDEX_op_ext8u_i64:
2066    case INDEX_op_ext16s_i32:
2067    case INDEX_op_ext16s_i64:
2068    case INDEX_op_ext16u_i32:
2069    case INDEX_op_ext16u_i64:
2070    case INDEX_op_ext32s_i64:
2071    case INDEX_op_ext32u_i64:
2072    case INDEX_op_extu_i32_i64:
2073    case INDEX_op_extrl_i64_i32:
2074    case INDEX_op_extrh_i64_i32:
2075    case INDEX_op_ext_i32_i64:
2076    case INDEX_op_not_i32:
2077    case INDEX_op_not_i64:
2078    case INDEX_op_extract_i32:
2079    case INDEX_op_extract_i64:
2080    case INDEX_op_bswap16_i32:
2081    case INDEX_op_bswap16_i64:
2082    case INDEX_op_bswap32_i32:
2083    case INDEX_op_bswap32_i64:
2084    case INDEX_op_bswap64_i64:
2085    case INDEX_op_ld8s_i32:
2086    case INDEX_op_ld8s_i64:
2087    case INDEX_op_ld8u_i32:
2088    case INDEX_op_ld8u_i64:
2089    case INDEX_op_ld16s_i32:
2090    case INDEX_op_ld16s_i64:
2091    case INDEX_op_ld16u_i32:
2092    case INDEX_op_ld16u_i64:
2093    case INDEX_op_ld32s_i64:
2094    case INDEX_op_ld32u_i64:
2095    case INDEX_op_ld_i32:
2096    case INDEX_op_ld_i64:
2097    case INDEX_op_qemu_ld_a32_i32:
2098    case INDEX_op_qemu_ld_a64_i32:
2099    case INDEX_op_qemu_ld_a32_i64:
2100    case INDEX_op_qemu_ld_a64_i64:
2101        return C_O1_I1(r, r);
2102
2103    case INDEX_op_andc_i32:
2104    case INDEX_op_andc_i64:
2105    case INDEX_op_orc_i32:
2106    case INDEX_op_orc_i64:
2107        /*
2108         * LoongArch insns for these ops don't have reg-imm forms, but we
2109         * can express using andi/ori if ~constant satisfies
2110         * TCG_CT_CONST_U12.
2111         */
2112        return C_O1_I2(r, r, rC);
2113
2114    case INDEX_op_shl_i32:
2115    case INDEX_op_shl_i64:
2116    case INDEX_op_shr_i32:
2117    case INDEX_op_shr_i64:
2118    case INDEX_op_sar_i32:
2119    case INDEX_op_sar_i64:
2120    case INDEX_op_rotl_i32:
2121    case INDEX_op_rotl_i64:
2122    case INDEX_op_rotr_i32:
2123    case INDEX_op_rotr_i64:
2124        return C_O1_I2(r, r, ri);
2125
2126    case INDEX_op_add_i32:
2127        return C_O1_I2(r, r, ri);
2128    case INDEX_op_add_i64:
2129        return C_O1_I2(r, r, rJ);
2130
2131    case INDEX_op_and_i32:
2132    case INDEX_op_and_i64:
2133    case INDEX_op_nor_i32:
2134    case INDEX_op_nor_i64:
2135    case INDEX_op_or_i32:
2136    case INDEX_op_or_i64:
2137    case INDEX_op_xor_i32:
2138    case INDEX_op_xor_i64:
2139        /* LoongArch reg-imm bitops have their imms ZERO-extended */
2140        return C_O1_I2(r, r, rU);
2141
2142    case INDEX_op_clz_i32:
2143    case INDEX_op_clz_i64:
2144    case INDEX_op_ctz_i32:
2145    case INDEX_op_ctz_i64:
2146        return C_O1_I2(r, r, rW);
2147
2148    case INDEX_op_deposit_i32:
2149    case INDEX_op_deposit_i64:
2150        /* Must deposit into the same register as input */
2151        return C_O1_I2(r, 0, rZ);
2152
2153    case INDEX_op_sub_i32:
2154    case INDEX_op_setcond_i32:
2155        return C_O1_I2(r, rZ, ri);
2156    case INDEX_op_sub_i64:
2157    case INDEX_op_setcond_i64:
2158        return C_O1_I2(r, rZ, rJ);
2159
2160    case INDEX_op_mul_i32:
2161    case INDEX_op_mul_i64:
2162    case INDEX_op_mulsh_i32:
2163    case INDEX_op_mulsh_i64:
2164    case INDEX_op_muluh_i32:
2165    case INDEX_op_muluh_i64:
2166    case INDEX_op_div_i32:
2167    case INDEX_op_div_i64:
2168    case INDEX_op_divu_i32:
2169    case INDEX_op_divu_i64:
2170    case INDEX_op_rem_i32:
2171    case INDEX_op_rem_i64:
2172    case INDEX_op_remu_i32:
2173    case INDEX_op_remu_i64:
2174        return C_O1_I2(r, rZ, rZ);
2175
2176    case INDEX_op_movcond_i32:
2177    case INDEX_op_movcond_i64:
2178        return C_O1_I4(r, rZ, rJ, rZ, rZ);
2179
2180    case INDEX_op_ld_vec:
2181    case INDEX_op_dupm_vec:
2182    case INDEX_op_dup_vec:
2183        return C_O1_I1(w, r);
2184
2185    case INDEX_op_st_vec:
2186        return C_O0_I2(w, r);
2187
2188    case INDEX_op_cmp_vec:
2189        return C_O1_I2(w, w, wM);
2190
2191    case INDEX_op_add_vec:
2192    case INDEX_op_sub_vec:
2193        return C_O1_I2(w, w, wA);
2194
2195    case INDEX_op_and_vec:
2196    case INDEX_op_andc_vec:
2197    case INDEX_op_or_vec:
2198    case INDEX_op_orc_vec:
2199    case INDEX_op_xor_vec:
2200    case INDEX_op_nor_vec:
2201    case INDEX_op_mul_vec:
2202    case INDEX_op_smin_vec:
2203    case INDEX_op_smax_vec:
2204    case INDEX_op_umin_vec:
2205    case INDEX_op_umax_vec:
2206    case INDEX_op_ssadd_vec:
2207    case INDEX_op_usadd_vec:
2208    case INDEX_op_sssub_vec:
2209    case INDEX_op_ussub_vec:
2210    case INDEX_op_shlv_vec:
2211    case INDEX_op_shrv_vec:
2212    case INDEX_op_sarv_vec:
2213    case INDEX_op_rotrv_vec:
2214    case INDEX_op_rotlv_vec:
2215        return C_O1_I2(w, w, w);
2216
2217    case INDEX_op_not_vec:
2218    case INDEX_op_neg_vec:
2219    case INDEX_op_shli_vec:
2220    case INDEX_op_shri_vec:
2221    case INDEX_op_sari_vec:
2222    case INDEX_op_rotli_vec:
2223        return C_O1_I1(w, w);
2224
2225    case INDEX_op_bitsel_vec:
2226        return C_O1_I3(w, w, w, w);
2227
2228    default:
2229        g_assert_not_reached();
2230    }
2231}
2232
2233static const int tcg_target_callee_save_regs[] = {
2234    TCG_REG_S0,     /* used for the global env (TCG_AREG0) */
2235    TCG_REG_S1,
2236    TCG_REG_S2,
2237    TCG_REG_S3,
2238    TCG_REG_S4,
2239    TCG_REG_S5,
2240    TCG_REG_S6,
2241    TCG_REG_S7,
2242    TCG_REG_S8,
2243    TCG_REG_S9,
2244    TCG_REG_RA,     /* should be last for ABI compliance */
2245};
2246
2247/* Stack frame parameters.  */
2248#define REG_SIZE   (TCG_TARGET_REG_BITS / 8)
2249#define SAVE_SIZE  ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE)
2250#define TEMP_SIZE  (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
2251#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \
2252                     + TCG_TARGET_STACK_ALIGN - 1) \
2253                    & -TCG_TARGET_STACK_ALIGN)
2254#define SAVE_OFS   (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE)
2255
2256/* We're expecting to be able to use an immediate for frame allocation.  */
2257QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff);
2258
2259/* Generate global QEMU prologue and epilogue code */
2260static void tcg_target_qemu_prologue(TCGContext *s)
2261{
2262    int i;
2263
2264    tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE);
2265
2266    /* TB prologue */
2267    tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE);
2268    for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2269        tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2270                   TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2271    }
2272
2273    if (!tcg_use_softmmu && guest_base) {
2274        tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base);
2275        tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
2276    }
2277
2278    /* Call generated code */
2279    tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
2280    tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0);
2281
2282    /* Return path for goto_ptr. Set return value to 0 */
2283    tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr);
2284    tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO);
2285
2286    /* TB epilogue */
2287    tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr);
2288    for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) {
2289        tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
2290                   TCG_REG_SP, SAVE_OFS + i * REG_SIZE);
2291    }
2292
2293    tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE);
2294    tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0);
2295}
2296
2297static void tcg_out_tb_start(TCGContext *s)
2298{
2299    /* nothing to do */
2300}
2301
2302static void tcg_target_init(TCGContext *s)
2303{
2304    unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2305
2306    /* Server and desktop class cpus have UAL; embedded cpus do not. */
2307    if (!(hwcap & HWCAP_LOONGARCH_UAL)) {
2308        error_report("TCG: unaligned access support required; exiting");
2309        exit(EXIT_FAILURE);
2310    }
2311
2312    if (hwcap & HWCAP_LOONGARCH_LSX) {
2313        use_lsx_instructions = 1;
2314    }
2315
2316    tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;
2317    tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS;
2318
2319    tcg_target_call_clobber_regs = ALL_GENERAL_REGS;
2320    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0);
2321    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1);
2322    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2);
2323    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3);
2324    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4);
2325    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5);
2326    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6);
2327    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7);
2328    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8);
2329    tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9);
2330
2331    if (use_lsx_instructions) {
2332        tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS;
2333        tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24);
2334        tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25);
2335        tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26);
2336        tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27);
2337        tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28);
2338        tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29);
2339        tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30);
2340        tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31);
2341    }
2342
2343    s->reserved_regs = 0;
2344    tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO);
2345    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0);
2346    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1);
2347    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2);
2348    tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP);
2349    tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP);
2350    tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED);
2351    tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0);
2352}
2353
2354typedef struct {
2355    DebugFrameHeader h;
2356    uint8_t fde_def_cfa[4];
2357    uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2];
2358} DebugFrame;
2359
2360#define ELF_HOST_MACHINE EM_LOONGARCH
2361
2362static const DebugFrame debug_frame = {
2363    .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */
2364    .h.cie.id = -1,
2365    .h.cie.version = 1,
2366    .h.cie.code_align = 1,
2367    .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */
2368    .h.cie.return_column = TCG_REG_RA,
2369
2370    /* Total FDE size does not include the "len" member.  */
2371    .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset),
2372
2373    .fde_def_cfa = {
2374        12, TCG_REG_SP,                 /* DW_CFA_def_cfa sp, ...  */
2375        (FRAME_SIZE & 0x7f) | 0x80,     /* ... uleb128 FRAME_SIZE */
2376        (FRAME_SIZE >> 7)
2377    },
2378    .fde_reg_ofs = {
2379        0x80 + 23, 11,                  /* DW_CFA_offset, s0, -88 */
2380        0x80 + 24, 10,                  /* DW_CFA_offset, s1, -80 */
2381        0x80 + 25, 9,                   /* DW_CFA_offset, s2, -72 */
2382        0x80 + 26, 8,                   /* DW_CFA_offset, s3, -64 */
2383        0x80 + 27, 7,                   /* DW_CFA_offset, s4, -56 */
2384        0x80 + 28, 6,                   /* DW_CFA_offset, s5, -48 */
2385        0x80 + 29, 5,                   /* DW_CFA_offset, s6, -40 */
2386        0x80 + 30, 4,                   /* DW_CFA_offset, s7, -32 */
2387        0x80 + 31, 3,                   /* DW_CFA_offset, s8, -24 */
2388        0x80 + 22, 2,                   /* DW_CFA_offset, s9, -16 */
2389        0x80 + 1 , 1,                   /* DW_CFA_offset, ra, -8 */
2390    }
2391};
2392
2393void tcg_register_jit(const void *buf, size_t buf_size)
2394{
2395    tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2396}
2397