1/* 2 * Tiny Code Generator for QEMU 3 * 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 * 6 * Based on tcg/riscv/tcg-target.c.inc 7 * 8 * Copyright (c) 2018 SiFive, Inc 9 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> 10 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> 11 * Copyright (c) 2008 Fabrice Bellard 12 * 13 * Permission is hereby granted, free of charge, to any person obtaining a copy 14 * of this software and associated documentation files (the "Software"), to deal 15 * in the Software without restriction, including without limitation the rights 16 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 17 * copies of the Software, and to permit persons to whom the Software is 18 * furnished to do so, subject to the following conditions: 19 * 20 * The above copyright notice and this permission notice shall be included in 21 * all copies or substantial portions of the Software. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 24 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 25 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 26 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 27 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 28 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 29 * THE SOFTWARE. 30 */ 31 32#include <asm/hwcap.h> 33 34/* used for function call generation */ 35#define TCG_REG_CALL_STACK TCG_REG_SP 36#define TCG_TARGET_STACK_ALIGN 16 37#define TCG_TARGET_CALL_STACK_OFFSET 0 38#define TCG_TARGET_CALL_ARG_I32 TCG_CALL_ARG_NORMAL 39#define TCG_TARGET_CALL_ARG_I64 TCG_CALL_ARG_NORMAL 40#define TCG_TARGET_CALL_ARG_I128 TCG_CALL_ARG_NORMAL 41#define TCG_TARGET_CALL_RET_I128 TCG_CALL_RET_NORMAL 42 43#ifdef CONFIG_DEBUG_TCG 44static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { 45 "zero", 46 "ra", 47 "tp", 48 "sp", 49 "a0", 50 "a1", 51 "a2", 52 "a3", 53 "a4", 54 "a5", 55 "a6", 56 "a7", 57 "t0", 58 "t1", 59 "t2", 60 "t3", 61 "t4", 62 "t5", 63 "t6", 64 "t7", 65 "t8", 66 "r21", /* reserved in the LP64* ABI, hence no ABI name */ 67 "s9", 68 "s0", 69 "s1", 70 "s2", 71 "s3", 72 "s4", 73 "s5", 74 "s6", 75 "s7", 76 "s8", 77 "vr0", 78 "vr1", 79 "vr2", 80 "vr3", 81 "vr4", 82 "vr5", 83 "vr6", 84 "vr7", 85 "vr8", 86 "vr9", 87 "vr10", 88 "vr11", 89 "vr12", 90 "vr13", 91 "vr14", 92 "vr15", 93 "vr16", 94 "vr17", 95 "vr18", 96 "vr19", 97 "vr20", 98 "vr21", 99 "vr22", 100 "vr23", 101 "vr24", 102 "vr25", 103 "vr26", 104 "vr27", 105 "vr28", 106 "vr29", 107 "vr30", 108 "vr31", 109}; 110#endif 111 112static const int tcg_target_reg_alloc_order[] = { 113 /* Registers preserved across calls */ 114 /* TCG_REG_S0 reserved for TCG_AREG0 */ 115 TCG_REG_S1, 116 TCG_REG_S2, 117 TCG_REG_S3, 118 TCG_REG_S4, 119 TCG_REG_S5, 120 TCG_REG_S6, 121 TCG_REG_S7, 122 TCG_REG_S8, 123 TCG_REG_S9, 124 125 /* Registers (potentially) clobbered across calls */ 126 TCG_REG_T0, 127 TCG_REG_T1, 128 TCG_REG_T2, 129 TCG_REG_T3, 130 TCG_REG_T4, 131 TCG_REG_T5, 132 TCG_REG_T6, 133 TCG_REG_T7, 134 TCG_REG_T8, 135 136 /* Argument registers, opposite order of allocation. */ 137 TCG_REG_A7, 138 TCG_REG_A6, 139 TCG_REG_A5, 140 TCG_REG_A4, 141 TCG_REG_A3, 142 TCG_REG_A2, 143 TCG_REG_A1, 144 TCG_REG_A0, 145 146 /* Vector registers */ 147 TCG_REG_V0, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3, 148 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7, 149 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11, 150 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15, 151 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19, 152 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23, 153 /* V24 - V31 are caller-saved, and skipped. */ 154}; 155 156static const int tcg_target_call_iarg_regs[] = { 157 TCG_REG_A0, 158 TCG_REG_A1, 159 TCG_REG_A2, 160 TCG_REG_A3, 161 TCG_REG_A4, 162 TCG_REG_A5, 163 TCG_REG_A6, 164 TCG_REG_A7, 165}; 166 167static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot) 168{ 169 tcg_debug_assert(kind == TCG_CALL_RET_NORMAL); 170 tcg_debug_assert(slot >= 0 && slot <= 1); 171 return TCG_REG_A0 + slot; 172} 173 174#define TCG_GUEST_BASE_REG TCG_REG_S1 175 176#define TCG_CT_CONST_S12 0x100 177#define TCG_CT_CONST_S32 0x200 178#define TCG_CT_CONST_U12 0x400 179#define TCG_CT_CONST_WSZ 0x800 180#define TCG_CT_CONST_VCMP 0x1000 181#define TCG_CT_CONST_VADD 0x2000 182 183#define ALL_GENERAL_REGS MAKE_64BIT_MASK(0, 32) 184#define ALL_VECTOR_REGS MAKE_64BIT_MASK(32, 32) 185 186static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) 187{ 188 return sextract64(val, pos, len); 189} 190 191/* test if a constant matches the constraint */ 192static bool tcg_target_const_match(int64_t val, int ct, 193 TCGType type, TCGCond cond, int vece) 194{ 195 if (ct & TCG_CT_CONST) { 196 return true; 197 } 198 if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { 199 return true; 200 } 201 if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) { 202 return true; 203 } 204 if ((ct & TCG_CT_CONST_U12) && val >= 0 && val <= 0xfff) { 205 return true; 206 } 207 if ((ct & TCG_CT_CONST_WSZ) && val == (type == TCG_TYPE_I32 ? 32 : 64)) { 208 return true; 209 } 210 if (ct & (TCG_CT_CONST_VCMP | TCG_CT_CONST_VADD)) { 211 int64_t vec_val = sextract64(val, 0, 8 << vece); 212 if (ct & TCG_CT_CONST_VCMP) { 213 switch (cond) { 214 case TCG_COND_EQ: 215 case TCG_COND_LE: 216 case TCG_COND_LT: 217 return -0x10 <= vec_val && vec_val <= 0x0f; 218 case TCG_COND_LEU: 219 case TCG_COND_LTU: 220 return 0x00 <= vec_val && vec_val <= 0x1f; 221 default: 222 return false; 223 } 224 } 225 if ((ct & TCG_CT_CONST_VADD) && -0x1f <= vec_val && vec_val <= 0x1f) { 226 return true; 227 } 228 } 229 return false; 230} 231 232/* 233 * Relocations 234 */ 235 236/* 237 * Relocation records defined in LoongArch ELF psABI v1.00 is way too 238 * complicated; a whopping stack machine is needed to stuff the fields, at 239 * the very least one SOP_PUSH and one SOP_POP (of the correct format) are 240 * needed. 241 * 242 * Hence, define our own simpler relocation types. Numbers are chosen as to 243 * not collide with potential future additions to the true ELF relocation 244 * type enum. 245 */ 246 247/* Field Sk16, shifted right by 2; suitable for conditional jumps */ 248#define R_LOONGARCH_BR_SK16 256 249/* Field Sd10k16, shifted right by 2; suitable for B and BL */ 250#define R_LOONGARCH_BR_SD10K16 257 251 252static bool reloc_br_sk16(tcg_insn_unit *src_rw, const tcg_insn_unit *target) 253{ 254 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 255 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 256 257 tcg_debug_assert((offset & 3) == 0); 258 offset >>= 2; 259 if (offset == sextreg(offset, 0, 16)) { 260 *src_rw = deposit64(*src_rw, 10, 16, offset); 261 return true; 262 } 263 264 return false; 265} 266 267static bool reloc_br_sd10k16(tcg_insn_unit *src_rw, 268 const tcg_insn_unit *target) 269{ 270 const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); 271 intptr_t offset = (intptr_t)target - (intptr_t)src_rx; 272 273 tcg_debug_assert((offset & 3) == 0); 274 offset >>= 2; 275 if (offset == sextreg(offset, 0, 26)) { 276 *src_rw = deposit64(*src_rw, 0, 10, offset >> 16); /* slot d10 */ 277 *src_rw = deposit64(*src_rw, 10, 16, offset); /* slot k16 */ 278 return true; 279 } 280 281 return false; 282} 283 284static bool patch_reloc(tcg_insn_unit *code_ptr, int type, 285 intptr_t value, intptr_t addend) 286{ 287 tcg_debug_assert(addend == 0); 288 switch (type) { 289 case R_LOONGARCH_BR_SK16: 290 return reloc_br_sk16(code_ptr, (tcg_insn_unit *)value); 291 case R_LOONGARCH_BR_SD10K16: 292 return reloc_br_sd10k16(code_ptr, (tcg_insn_unit *)value); 293 default: 294 g_assert_not_reached(); 295 } 296} 297 298#include "tcg-insn-defs.c.inc" 299 300/* 301 * TCG intrinsics 302 */ 303 304static void tcg_out_mb(TCGContext *s, unsigned a0) 305{ 306 /* Baseline LoongArch only has the full barrier, unfortunately. */ 307 tcg_out_opc_dbar(s, 0); 308} 309 310static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 311{ 312 if (ret == arg) { 313 return true; 314 } 315 switch (type) { 316 case TCG_TYPE_I32: 317 case TCG_TYPE_I64: 318 if (ret < TCG_REG_V0) { 319 if (arg < TCG_REG_V0) { 320 /* 321 * Conventional register-register move used in LoongArch is 322 * `or dst, src, zero`. 323 */ 324 tcg_out_opc_or(s, ret, arg, TCG_REG_ZERO); 325 } else { 326 tcg_out_opc_movfr2gr_d(s, ret, arg); 327 } 328 } else { 329 if (arg < TCG_REG_V0) { 330 tcg_out_opc_movgr2fr_d(s, ret, arg); 331 } else { 332 tcg_out_opc_fmov_d(s, ret, arg); 333 } 334 } 335 break; 336 case TCG_TYPE_V64: 337 case TCG_TYPE_V128: 338 tcg_out_opc_vori_b(s, ret, arg, 0); 339 break; 340 case TCG_TYPE_V256: 341 tcg_out_opc_xvori_b(s, ret, arg, 0); 342 break; 343 default: 344 g_assert_not_reached(); 345 } 346 return true; 347} 348 349/* Loads a 32-bit immediate into rd, sign-extended. */ 350static void tcg_out_movi_i32(TCGContext *s, TCGReg rd, int32_t val) 351{ 352 tcg_target_long lo = sextreg(val, 0, 12); 353 tcg_target_long hi12 = sextreg(val, 12, 20); 354 355 /* Single-instruction cases. */ 356 if (hi12 == 0) { 357 /* val fits in uimm12: ori rd, zero, val */ 358 tcg_out_opc_ori(s, rd, TCG_REG_ZERO, val); 359 return; 360 } 361 if (hi12 == sextreg(lo, 12, 20)) { 362 /* val fits in simm12: addi.w rd, zero, val */ 363 tcg_out_opc_addi_w(s, rd, TCG_REG_ZERO, val); 364 return; 365 } 366 367 /* High bits must be set; load with lu12i.w + optional ori. */ 368 tcg_out_opc_lu12i_w(s, rd, hi12); 369 if (lo != 0) { 370 tcg_out_opc_ori(s, rd, rd, lo & 0xfff); 371 } 372} 373 374static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, 375 tcg_target_long val) 376{ 377 /* 378 * LoongArch conventionally loads 64-bit immediates in at most 4 steps, 379 * with dedicated instructions for filling the respective bitfields 380 * below: 381 * 382 * 6 5 4 3 383 * 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 384 * +-----------------------+---------------------------------------+... 385 * | hi52 | hi32 | 386 * +-----------------------+---------------------------------------+... 387 * 3 2 1 388 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 389 * ...+-------------------------------------+-------------------------+ 390 * | hi12 | lo | 391 * ...+-------------------------------------+-------------------------+ 392 * 393 * Check if val belong to one of the several fast cases, before falling 394 * back to the slow path. 395 */ 396 397 intptr_t src_rx, pc_offset; 398 tcg_target_long hi12, hi32, hi52; 399 400 /* Value fits in signed i32. */ 401 if (type == TCG_TYPE_I32 || val == (int32_t)val) { 402 tcg_out_movi_i32(s, rd, val); 403 return; 404 } 405 406 /* PC-relative cases. */ 407 src_rx = (intptr_t)tcg_splitwx_to_rx(s->code_ptr); 408 if ((val & 3) == 0) { 409 pc_offset = val - src_rx; 410 if (pc_offset == sextreg(pc_offset, 0, 22)) { 411 /* Single pcaddu2i. */ 412 tcg_out_opc_pcaddu2i(s, rd, pc_offset >> 2); 413 return; 414 } 415 } 416 417 pc_offset = (val >> 12) - (src_rx >> 12); 418 if (pc_offset == sextreg(pc_offset, 0, 20)) { 419 /* Load with pcalau12i + ori. */ 420 tcg_target_long val_lo = val & 0xfff; 421 tcg_out_opc_pcalau12i(s, rd, pc_offset); 422 if (val_lo != 0) { 423 tcg_out_opc_ori(s, rd, rd, val_lo); 424 } 425 return; 426 } 427 428 hi12 = sextreg(val, 12, 20); 429 hi32 = sextreg(val, 32, 20); 430 hi52 = sextreg(val, 52, 12); 431 432 /* Single cu52i.d case. */ 433 if ((hi52 != 0) && (ctz64(val) >= 52)) { 434 tcg_out_opc_cu52i_d(s, rd, TCG_REG_ZERO, hi52); 435 return; 436 } 437 438 /* Slow path. Initialize the low 32 bits, then concat high bits. */ 439 tcg_out_movi_i32(s, rd, val); 440 441 /* Load hi32 and hi52 explicitly when they are unexpected values. */ 442 if (hi32 != sextreg(hi12, 20, 20)) { 443 tcg_out_opc_cu32i_d(s, rd, hi32); 444 } 445 446 if (hi52 != sextreg(hi32, 20, 12)) { 447 tcg_out_opc_cu52i_d(s, rd, rd, hi52); 448 } 449} 450 451static void tcg_out_addi(TCGContext *s, TCGType type, TCGReg rd, 452 TCGReg rs, tcg_target_long imm) 453{ 454 tcg_target_long lo12 = sextreg(imm, 0, 12); 455 tcg_target_long hi16 = sextreg(imm - lo12, 16, 16); 456 457 /* 458 * Note that there's a hole in between hi16 and lo12: 459 * 460 * 3 2 1 0 461 * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 462 * ...+-------------------------------+-------+-----------------------+ 463 * | hi16 | | lo12 | 464 * ...+-------------------------------+-------+-----------------------+ 465 * 466 * For bits within that hole, it's more efficient to use LU12I and ADD. 467 */ 468 if (imm == (hi16 << 16) + lo12) { 469 if (hi16) { 470 tcg_out_opc_addu16i_d(s, rd, rs, hi16); 471 rs = rd; 472 } 473 if (type == TCG_TYPE_I32) { 474 tcg_out_opc_addi_w(s, rd, rs, lo12); 475 } else if (lo12) { 476 tcg_out_opc_addi_d(s, rd, rs, lo12); 477 } else { 478 tcg_out_mov(s, type, rd, rs); 479 } 480 } else { 481 tcg_out_movi(s, type, TCG_REG_TMP0, imm); 482 if (type == TCG_TYPE_I32) { 483 tcg_out_opc_add_w(s, rd, rs, TCG_REG_TMP0); 484 } else { 485 tcg_out_opc_add_d(s, rd, rs, TCG_REG_TMP0); 486 } 487 } 488} 489 490static bool tcg_out_xchg(TCGContext *s, TCGType type, TCGReg r1, TCGReg r2) 491{ 492 return false; 493} 494 495static void tcg_out_addi_ptr(TCGContext *s, TCGReg rd, TCGReg rs, 496 tcg_target_long imm) 497{ 498 /* This function is only used for passing structs by reference. */ 499 g_assert_not_reached(); 500} 501 502static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) 503{ 504 tcg_out_opc_andi(s, ret, arg, 0xff); 505} 506 507static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) 508{ 509 tcg_out_opc_bstrpick_w(s, ret, arg, 0, 15); 510} 511 512static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) 513{ 514 tcg_out_opc_bstrpick_d(s, ret, arg, 0, 31); 515} 516 517static void tcg_out_ext8s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 518{ 519 tcg_out_opc_sext_b(s, ret, arg); 520} 521 522static void tcg_out_ext16s(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) 523{ 524 tcg_out_opc_sext_h(s, ret, arg); 525} 526 527static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) 528{ 529 tcg_out_opc_addi_w(s, ret, arg, 0); 530} 531 532static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 533{ 534 if (ret != arg) { 535 tcg_out_ext32s(s, ret, arg); 536 } 537} 538 539static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) 540{ 541 tcg_out_ext32u(s, ret, arg); 542} 543 544static void tcg_out_extrl_i64_i32(TCGContext *s, TCGReg ret, TCGReg arg) 545{ 546 tcg_out_ext32s(s, ret, arg); 547} 548 549#define SETCOND_INV TCG_TARGET_NB_REGS 550#define SETCOND_NEZ (SETCOND_INV << 1) 551#define SETCOND_FLAGS (SETCOND_INV | SETCOND_NEZ) 552 553static int tcg_out_setcond_int(TCGContext *s, TCGCond cond, TCGReg ret, 554 TCGReg arg1, tcg_target_long arg2, bool c2) 555{ 556 int flags = 0; 557 558 switch (cond) { 559 case TCG_COND_EQ: /* -> NE */ 560 case TCG_COND_GE: /* -> LT */ 561 case TCG_COND_GEU: /* -> LTU */ 562 case TCG_COND_GT: /* -> LE */ 563 case TCG_COND_GTU: /* -> LEU */ 564 cond = tcg_invert_cond(cond); 565 flags ^= SETCOND_INV; 566 break; 567 default: 568 break; 569 } 570 571 switch (cond) { 572 case TCG_COND_LE: 573 case TCG_COND_LEU: 574 /* 575 * If we have a constant input, the most efficient way to implement 576 * LE is by adding 1 and using LT. Watch out for wrap around for LEU. 577 * We don't need to care for this for LE because the constant input 578 * is still constrained to int32_t, and INT32_MAX+1 is representable 579 * in the 64-bit temporary register. 580 */ 581 if (c2) { 582 if (cond == TCG_COND_LEU) { 583 /* unsigned <= -1 is true */ 584 if (arg2 == -1) { 585 tcg_out_movi(s, TCG_TYPE_REG, ret, !(flags & SETCOND_INV)); 586 return ret; 587 } 588 cond = TCG_COND_LTU; 589 } else { 590 cond = TCG_COND_LT; 591 } 592 arg2 += 1; 593 } else { 594 TCGReg tmp = arg2; 595 arg2 = arg1; 596 arg1 = tmp; 597 cond = tcg_swap_cond(cond); /* LE -> GE */ 598 cond = tcg_invert_cond(cond); /* GE -> LT */ 599 flags ^= SETCOND_INV; 600 } 601 break; 602 default: 603 break; 604 } 605 606 switch (cond) { 607 case TCG_COND_NE: 608 flags |= SETCOND_NEZ; 609 if (!c2) { 610 tcg_out_opc_xor(s, ret, arg1, arg2); 611 } else if (arg2 == 0) { 612 ret = arg1; 613 } else if (arg2 >= 0 && arg2 <= 0xfff) { 614 tcg_out_opc_xori(s, ret, arg1, arg2); 615 } else { 616 tcg_out_addi(s, TCG_TYPE_REG, ret, arg1, -arg2); 617 } 618 break; 619 620 case TCG_COND_LT: 621 case TCG_COND_LTU: 622 if (c2) { 623 if (arg2 >= -0x800 && arg2 <= 0x7ff) { 624 if (cond == TCG_COND_LT) { 625 tcg_out_opc_slti(s, ret, arg1, arg2); 626 } else { 627 tcg_out_opc_sltui(s, ret, arg1, arg2); 628 } 629 break; 630 } 631 tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP0, arg2); 632 arg2 = TCG_REG_TMP0; 633 } 634 if (cond == TCG_COND_LT) { 635 tcg_out_opc_slt(s, ret, arg1, arg2); 636 } else { 637 tcg_out_opc_sltu(s, ret, arg1, arg2); 638 } 639 break; 640 641 default: 642 g_assert_not_reached(); 643 } 644 645 return ret | flags; 646} 647 648static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, 649 TCGReg arg1, tcg_target_long arg2, 650 bool c2, bool neg) 651{ 652 int tmpflags = tcg_out_setcond_int(s, cond, ret, arg1, arg2, c2); 653 TCGReg tmp = tmpflags & ~SETCOND_FLAGS; 654 655 if (neg) { 656 /* If intermediate result is zero/non-zero: test != 0. */ 657 if (tmpflags & SETCOND_NEZ) { 658 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 659 tmp = ret; 660 } 661 /* Produce the 0/-1 result. */ 662 if (tmpflags & SETCOND_INV) { 663 tcg_out_opc_addi_d(s, ret, tmp, -1); 664 } else { 665 tcg_out_opc_sub_d(s, ret, TCG_REG_ZERO, tmp); 666 } 667 } else { 668 switch (tmpflags & SETCOND_FLAGS) { 669 case 0: 670 tcg_debug_assert(tmp == ret); 671 break; 672 case SETCOND_INV: 673 /* Intermediate result is boolean: simply invert. */ 674 tcg_out_opc_xori(s, ret, tmp, 1); 675 break; 676 case SETCOND_NEZ: 677 /* Intermediate result is zero/non-zero: test != 0. */ 678 tcg_out_opc_sltu(s, ret, TCG_REG_ZERO, tmp); 679 break; 680 case SETCOND_NEZ | SETCOND_INV: 681 /* Intermediate result is zero/non-zero: test == 0. */ 682 tcg_out_opc_sltui(s, ret, tmp, 1); 683 break; 684 default: 685 g_assert_not_reached(); 686 } 687 } 688} 689 690static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond, 691 TCGReg dest, TCGReg arg1, TCGReg arg2) 692{ 693 tcg_out_setcond(s, cond, dest, arg1, arg2, false, false); 694} 695 696static void tgen_setcondi(TCGContext *s, TCGType type, TCGCond cond, 697 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 698{ 699 tcg_out_setcond(s, cond, dest, arg1, arg2, true, false); 700} 701 702static const TCGOutOpSetcond outop_setcond = { 703 .base.static_constraint = C_O1_I2(r, r, rJ), 704 .out_rrr = tgen_setcond, 705 .out_rri = tgen_setcondi, 706}; 707 708static void tgen_negsetcond(TCGContext *s, TCGType type, TCGCond cond, 709 TCGReg dest, TCGReg arg1, TCGReg arg2) 710{ 711 tcg_out_setcond(s, cond, dest, arg1, arg2, false, true); 712} 713 714static void tgen_negsetcondi(TCGContext *s, TCGType type, TCGCond cond, 715 TCGReg dest, TCGReg arg1, tcg_target_long arg2) 716{ 717 tcg_out_setcond(s, cond, dest, arg1, arg2, true, true); 718} 719 720static const TCGOutOpSetcond outop_negsetcond = { 721 .base.static_constraint = C_O1_I2(r, r, rJ), 722 .out_rrr = tgen_negsetcond, 723 .out_rri = tgen_negsetcondi, 724}; 725 726static void tgen_movcond(TCGContext *s, TCGType type, TCGCond cond, 727 TCGReg ret, TCGReg c1, TCGArg c2, bool const_c2, 728 TCGArg v1, bool const_v1, TCGArg v2, bool const_v2) 729{ 730 int tmpflags = tcg_out_setcond_int(s, cond, TCG_REG_TMP0, c1, c2, const_c2); 731 TCGReg t; 732 733 /* Standardize the test below to t != 0. */ 734 if (tmpflags & SETCOND_INV) { 735 t = v1, v1 = v2, v2 = t; 736 } 737 738 t = tmpflags & ~SETCOND_FLAGS; 739 if (v1 == TCG_REG_ZERO) { 740 tcg_out_opc_masknez(s, ret, v2, t); 741 } else if (v2 == TCG_REG_ZERO) { 742 tcg_out_opc_maskeqz(s, ret, v1, t); 743 } else { 744 tcg_out_opc_masknez(s, TCG_REG_TMP2, v2, t); /* t ? 0 : v2 */ 745 tcg_out_opc_maskeqz(s, TCG_REG_TMP1, v1, t); /* t ? v1 : 0 */ 746 tcg_out_opc_or(s, ret, TCG_REG_TMP1, TCG_REG_TMP2); 747 } 748} 749 750static const TCGOutOpMovcond outop_movcond = { 751 .base.static_constraint = C_O1_I4(r, r, rJ, rz, rz), 752 .out = tgen_movcond, 753}; 754 755/* 756 * Branch helpers 757 */ 758 759static void tcg_out_br(TCGContext *s, TCGLabel *l) 760{ 761 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SD10K16, l, 0); 762 tcg_out_opc_b(s, 0); 763} 764 765static const struct { 766 LoongArchInsn op; 767 bool swap; 768} tcg_brcond_to_loongarch[] = { 769 [TCG_COND_EQ] = { OPC_BEQ, false }, 770 [TCG_COND_NE] = { OPC_BNE, false }, 771 [TCG_COND_LT] = { OPC_BGT, true }, 772 [TCG_COND_GE] = { OPC_BLE, true }, 773 [TCG_COND_LE] = { OPC_BLE, false }, 774 [TCG_COND_GT] = { OPC_BGT, false }, 775 [TCG_COND_LTU] = { OPC_BGTU, true }, 776 [TCG_COND_GEU] = { OPC_BLEU, true }, 777 [TCG_COND_LEU] = { OPC_BLEU, false }, 778 [TCG_COND_GTU] = { OPC_BGTU, false } 779}; 780 781static void tgen_brcond(TCGContext *s, TCGType type, TCGCond cond, 782 TCGReg arg1, TCGReg arg2, TCGLabel *l) 783{ 784 LoongArchInsn op = tcg_brcond_to_loongarch[cond].op; 785 786 tcg_debug_assert(op != 0); 787 788 if (tcg_brcond_to_loongarch[cond].swap) { 789 TCGReg t = arg1; 790 arg1 = arg2; 791 arg2 = t; 792 } 793 794 /* all conditional branch insns belong to DJSk16-format */ 795 tcg_out_reloc(s, s->code_ptr, R_LOONGARCH_BR_SK16, l, 0); 796 tcg_out32(s, encode_djsk16_insn(op, arg1, arg2, 0)); 797} 798 799static const TCGOutOpBrcond outop_brcond = { 800 .base.static_constraint = C_O0_I2(r, rz), 801 .out_rr = tgen_brcond, 802}; 803 804static void tcg_out_call_int(TCGContext *s, const tcg_insn_unit *arg, bool tail) 805{ 806 TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; 807 ptrdiff_t offset = tcg_pcrel_diff(s, arg); 808 809 tcg_debug_assert((offset & 3) == 0); 810 if (offset == sextreg(offset, 0, 28)) { 811 /* short jump: +/- 256MiB */ 812 if (tail) { 813 tcg_out_opc_b(s, offset >> 2); 814 } else { 815 tcg_out_opc_bl(s, offset >> 2); 816 } 817 } else if (offset == sextreg(offset, 0, 38)) { 818 /* long jump: +/- 256GiB */ 819 tcg_target_long lo = sextreg(offset, 0, 18); 820 tcg_target_long hi = offset - lo; 821 tcg_out_opc_pcaddu18i(s, TCG_REG_TMP0, hi >> 18); 822 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 823 } else { 824 /* far jump: 64-bit */ 825 tcg_target_long lo = sextreg((tcg_target_long)arg, 0, 18); 826 tcg_target_long hi = (tcg_target_long)arg - lo; 827 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, hi); 828 tcg_out_opc_jirl(s, link, TCG_REG_TMP0, lo >> 2); 829 } 830} 831 832static void tcg_out_call(TCGContext *s, const tcg_insn_unit *arg, 833 const TCGHelperInfo *info) 834{ 835 tcg_out_call_int(s, arg, false); 836} 837 838/* 839 * Load/store helpers 840 */ 841 842static void tcg_out_ldst(TCGContext *s, LoongArchInsn opc, TCGReg data, 843 TCGReg addr, intptr_t offset) 844{ 845 intptr_t imm12 = sextreg(offset, 0, 12); 846 847 if (offset != imm12) { 848 intptr_t diff = tcg_pcrel_diff(s, (void *)offset); 849 850 if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { 851 imm12 = sextreg(diff, 0, 12); 852 tcg_out_opc_pcaddu12i(s, TCG_REG_TMP2, (diff - imm12) >> 12); 853 } else { 854 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); 855 if (addr != TCG_REG_ZERO) { 856 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, addr); 857 } 858 } 859 addr = TCG_REG_TMP2; 860 } 861 862 switch (opc) { 863 case OPC_LD_B: 864 case OPC_LD_BU: 865 case OPC_LD_H: 866 case OPC_LD_HU: 867 case OPC_LD_W: 868 case OPC_LD_WU: 869 case OPC_LD_D: 870 case OPC_ST_B: 871 case OPC_ST_H: 872 case OPC_ST_W: 873 case OPC_ST_D: 874 tcg_out32(s, encode_djsk12_insn(opc, data, addr, imm12)); 875 break; 876 case OPC_FLD_S: 877 case OPC_FLD_D: 878 case OPC_FST_S: 879 case OPC_FST_D: 880 tcg_out32(s, encode_fdjsk12_insn(opc, data, addr, imm12)); 881 break; 882 default: 883 g_assert_not_reached(); 884 } 885} 886 887static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg dest, 888 TCGReg base, intptr_t offset) 889{ 890 switch (type) { 891 case TCG_TYPE_I32: 892 if (dest < TCG_REG_V0) { 893 tcg_out_ldst(s, OPC_LD_W, dest, base, offset); 894 } else { 895 tcg_out_ldst(s, OPC_FLD_S, dest, base, offset); 896 } 897 break; 898 case TCG_TYPE_I64: 899 case TCG_TYPE_V64: 900 if (dest < TCG_REG_V0) { 901 tcg_out_ldst(s, OPC_LD_D, dest, base, offset); 902 } else { 903 tcg_out_ldst(s, OPC_FLD_D, dest, base, offset); 904 } 905 break; 906 case TCG_TYPE_V128: 907 if (-0x800 <= offset && offset <= 0x7ff) { 908 tcg_out_opc_vld(s, dest, base, offset); 909 } else { 910 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 911 tcg_out_opc_vldx(s, dest, base, TCG_REG_TMP0); 912 } 913 break; 914 case TCG_TYPE_V256: 915 if (-0x800 <= offset && offset <= 0x7ff) { 916 tcg_out_opc_xvld(s, dest, base, offset); 917 } else { 918 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 919 tcg_out_opc_xvldx(s, dest, base, TCG_REG_TMP0); 920 } 921 break; 922 default: 923 g_assert_not_reached(); 924 } 925} 926 927static void tcg_out_st(TCGContext *s, TCGType type, TCGReg src, 928 TCGReg base, intptr_t offset) 929{ 930 switch (type) { 931 case TCG_TYPE_I32: 932 if (src < TCG_REG_V0) { 933 tcg_out_ldst(s, OPC_ST_W, src, base, offset); 934 } else { 935 tcg_out_ldst(s, OPC_FST_S, src, base, offset); 936 } 937 break; 938 case TCG_TYPE_I64: 939 case TCG_TYPE_V64: 940 if (src < TCG_REG_V0) { 941 tcg_out_ldst(s, OPC_ST_D, src, base, offset); 942 } else { 943 tcg_out_ldst(s, OPC_FST_D, src, base, offset); 944 } 945 break; 946 case TCG_TYPE_V128: 947 if (-0x800 <= offset && offset <= 0x7ff) { 948 tcg_out_opc_vst(s, src, base, offset); 949 } else { 950 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 951 tcg_out_opc_vstx(s, src, base, TCG_REG_TMP0); 952 } 953 break; 954 case TCG_TYPE_V256: 955 if (-0x800 <= offset && offset <= 0x7ff) { 956 tcg_out_opc_xvst(s, src, base, offset); 957 } else { 958 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, offset); 959 tcg_out_opc_xvstx(s, src, base, TCG_REG_TMP0); 960 } 961 break; 962 default: 963 g_assert_not_reached(); 964 } 965} 966 967static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, 968 TCGReg base, intptr_t ofs) 969{ 970 if (val == 0) { 971 tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); 972 return true; 973 } 974 return false; 975} 976 977/* 978 * Load/store helpers for SoftMMU, and qemu_ld/st implementations 979 */ 980 981static bool tcg_out_goto(TCGContext *s, const tcg_insn_unit *target) 982{ 983 tcg_out_opc_b(s, 0); 984 return reloc_br_sd10k16(s->code_ptr - 1, target); 985} 986 987static const TCGLdstHelperParam ldst_helper_param = { 988 .ntmp = 1, .tmp = { TCG_REG_TMP0 } 989}; 990 991static bool tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 992{ 993 MemOp opc = get_memop(l->oi); 994 995 /* resolve label address */ 996 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 997 return false; 998 } 999 1000 tcg_out_ld_helper_args(s, l, &ldst_helper_param); 1001 tcg_out_call_int(s, qemu_ld_helpers[opc & MO_SIZE], false); 1002 tcg_out_ld_helper_ret(s, l, false, &ldst_helper_param); 1003 return tcg_out_goto(s, l->raddr); 1004} 1005 1006static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) 1007{ 1008 MemOp opc = get_memop(l->oi); 1009 1010 /* resolve label address */ 1011 if (!reloc_br_sk16(l->label_ptr[0], tcg_splitwx_to_rx(s->code_ptr))) { 1012 return false; 1013 } 1014 1015 tcg_out_st_helper_args(s, l, &ldst_helper_param); 1016 tcg_out_call_int(s, qemu_st_helpers[opc & MO_SIZE], false); 1017 return tcg_out_goto(s, l->raddr); 1018} 1019 1020typedef struct { 1021 TCGReg base; 1022 TCGReg index; 1023 TCGAtomAlign aa; 1024} HostAddress; 1025 1026bool tcg_target_has_memory_bswap(MemOp memop) 1027{ 1028 return false; 1029} 1030 1031/* We expect to use a 12-bit negative offset from ENV. */ 1032#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) 1033 1034/* 1035 * For system-mode, perform the TLB load and compare. 1036 * For user-mode, perform any required alignment tests. 1037 * In both cases, return a TCGLabelQemuLdst structure if the slow path 1038 * is required and fill in @h with the host address for the fast path. 1039 */ 1040static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, 1041 TCGReg addr_reg, MemOpIdx oi, 1042 bool is_ld) 1043{ 1044 TCGType addr_type = s->addr_type; 1045 TCGLabelQemuLdst *ldst = NULL; 1046 MemOp opc = get_memop(oi); 1047 MemOp a_bits; 1048 1049 h->aa = atom_and_align_for_opc(s, opc, MO_ATOM_IFALIGN, false); 1050 a_bits = h->aa.align; 1051 1052 if (tcg_use_softmmu) { 1053 unsigned s_bits = opc & MO_SIZE; 1054 int mem_index = get_mmuidx(oi); 1055 int fast_ofs = tlb_mask_table_ofs(s, mem_index); 1056 int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); 1057 int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); 1058 1059 ldst = new_ldst_label(s); 1060 ldst->is_ld = is_ld; 1061 ldst->oi = oi; 1062 ldst->addr_reg = addr_reg; 1063 1064 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); 1065 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); 1066 1067 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg, 1068 s->page_bits - CPU_TLB_ENTRY_BITS); 1069 tcg_out_opc_and(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP0); 1070 tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); 1071 1072 /* Load the tlb comparator and the addend. */ 1073 QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); 1074 tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, 1075 is_ld ? offsetof(CPUTLBEntry, addr_read) 1076 : offsetof(CPUTLBEntry, addr_write)); 1077 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, 1078 offsetof(CPUTLBEntry, addend)); 1079 1080 /* 1081 * For aligned accesses, we check the first byte and include the 1082 * alignment bits within the address. For unaligned access, we 1083 * check that we don't cross pages using the address of the last 1084 * byte of the access. 1085 */ 1086 if (a_bits < s_bits) { 1087 unsigned a_mask = (1u << a_bits) - 1; 1088 unsigned s_mask = (1u << s_bits) - 1; 1089 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask); 1090 } else { 1091 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg); 1092 } 1093 tcg_out_opc_bstrins_d(s, TCG_REG_TMP1, TCG_REG_ZERO, 1094 a_bits, s->page_bits - 1); 1095 1096 /* Compare masked address with the TLB entry. */ 1097 ldst->label_ptr[0] = s->code_ptr; 1098 tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); 1099 1100 h->index = TCG_REG_TMP2; 1101 } else { 1102 if (a_bits) { 1103 ldst = new_ldst_label(s); 1104 1105 ldst->is_ld = is_ld; 1106 ldst->oi = oi; 1107 ldst->addr_reg = addr_reg; 1108 1109 /* 1110 * Without micro-architecture details, we don't know which of 1111 * bstrpick or andi is faster, so use bstrpick as it's not 1112 * constrained by imm field width. Not to say alignments >= 2^12 1113 * are going to happen any time soon. 1114 */ 1115 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1); 1116 1117 ldst->label_ptr[0] = s->code_ptr; 1118 tcg_out_opc_bne(s, TCG_REG_TMP1, TCG_REG_ZERO, 0); 1119 } 1120 1121 h->index = guest_base ? TCG_GUEST_BASE_REG : TCG_REG_ZERO; 1122 } 1123 1124 if (addr_type == TCG_TYPE_I32) { 1125 h->base = TCG_REG_TMP0; 1126 tcg_out_ext32u(s, h->base, addr_reg); 1127 } else { 1128 h->base = addr_reg; 1129 } 1130 1131 return ldst; 1132} 1133 1134static void tcg_out_qemu_ld_indexed(TCGContext *s, MemOp opc, TCGType type, 1135 TCGReg rd, HostAddress h) 1136{ 1137 /* Byte swapping is left to middle-end expansion. */ 1138 tcg_debug_assert((opc & MO_BSWAP) == 0); 1139 1140 switch (opc & MO_SSIZE) { 1141 case MO_UB: 1142 tcg_out_opc_ldx_bu(s, rd, h.base, h.index); 1143 break; 1144 case MO_SB: 1145 tcg_out_opc_ldx_b(s, rd, h.base, h.index); 1146 break; 1147 case MO_UW: 1148 tcg_out_opc_ldx_hu(s, rd, h.base, h.index); 1149 break; 1150 case MO_SW: 1151 tcg_out_opc_ldx_h(s, rd, h.base, h.index); 1152 break; 1153 case MO_UL: 1154 if (type == TCG_TYPE_I64) { 1155 tcg_out_opc_ldx_wu(s, rd, h.base, h.index); 1156 break; 1157 } 1158 /* fallthrough */ 1159 case MO_SL: 1160 tcg_out_opc_ldx_w(s, rd, h.base, h.index); 1161 break; 1162 case MO_UQ: 1163 tcg_out_opc_ldx_d(s, rd, h.base, h.index); 1164 break; 1165 default: 1166 g_assert_not_reached(); 1167 } 1168} 1169 1170static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1171 MemOpIdx oi, TCGType data_type) 1172{ 1173 TCGLabelQemuLdst *ldst; 1174 HostAddress h; 1175 1176 ldst = prepare_host_addr(s, &h, addr_reg, oi, true); 1177 tcg_out_qemu_ld_indexed(s, get_memop(oi), data_type, data_reg, h); 1178 1179 if (ldst) { 1180 ldst->type = data_type; 1181 ldst->datalo_reg = data_reg; 1182 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1183 } 1184} 1185 1186static void tcg_out_qemu_st_indexed(TCGContext *s, MemOp opc, 1187 TCGReg rd, HostAddress h) 1188{ 1189 /* Byte swapping is left to middle-end expansion. */ 1190 tcg_debug_assert((opc & MO_BSWAP) == 0); 1191 1192 switch (opc & MO_SIZE) { 1193 case MO_8: 1194 tcg_out_opc_stx_b(s, rd, h.base, h.index); 1195 break; 1196 case MO_16: 1197 tcg_out_opc_stx_h(s, rd, h.base, h.index); 1198 break; 1199 case MO_32: 1200 tcg_out_opc_stx_w(s, rd, h.base, h.index); 1201 break; 1202 case MO_64: 1203 tcg_out_opc_stx_d(s, rd, h.base, h.index); 1204 break; 1205 default: 1206 g_assert_not_reached(); 1207 } 1208} 1209 1210static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg, 1211 MemOpIdx oi, TCGType data_type) 1212{ 1213 TCGLabelQemuLdst *ldst; 1214 HostAddress h; 1215 1216 ldst = prepare_host_addr(s, &h, addr_reg, oi, false); 1217 tcg_out_qemu_st_indexed(s, get_memop(oi), data_reg, h); 1218 1219 if (ldst) { 1220 ldst->type = data_type; 1221 ldst->datalo_reg = data_reg; 1222 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1223 } 1224} 1225 1226static void tcg_out_qemu_ldst_i128(TCGContext *s, TCGReg data_lo, TCGReg data_hi, 1227 TCGReg addr_reg, MemOpIdx oi, bool is_ld) 1228{ 1229 TCGLabelQemuLdst *ldst; 1230 HostAddress h; 1231 1232 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld); 1233 1234 if (h.aa.atom == MO_128) { 1235 /* 1236 * Use VLDX/VSTX when 128-bit atomicity is required. 1237 * If address is aligned to 16-bytes, the 128-bit load/store is atomic. 1238 */ 1239 if (is_ld) { 1240 tcg_out_opc_vldx(s, TCG_VEC_TMP0, h.base, h.index); 1241 tcg_out_opc_vpickve2gr_d(s, data_lo, TCG_VEC_TMP0, 0); 1242 tcg_out_opc_vpickve2gr_d(s, data_hi, TCG_VEC_TMP0, 1); 1243 } else { 1244 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_lo, 0); 1245 tcg_out_opc_vinsgr2vr_d(s, TCG_VEC_TMP0, data_hi, 1); 1246 tcg_out_opc_vstx(s, TCG_VEC_TMP0, h.base, h.index); 1247 } 1248 } else { 1249 /* Otherwise use a pair of LD/ST. */ 1250 TCGReg base = h.base; 1251 if (h.index != TCG_REG_ZERO) { 1252 base = TCG_REG_TMP0; 1253 tcg_out_opc_add_d(s, base, h.base, h.index); 1254 } 1255 if (is_ld) { 1256 tcg_debug_assert(base != data_lo); 1257 tcg_out_opc_ld_d(s, data_lo, base, 0); 1258 tcg_out_opc_ld_d(s, data_hi, base, 8); 1259 } else { 1260 tcg_out_opc_st_d(s, data_lo, base, 0); 1261 tcg_out_opc_st_d(s, data_hi, base, 8); 1262 } 1263 } 1264 1265 if (ldst) { 1266 ldst->type = TCG_TYPE_I128; 1267 ldst->datalo_reg = data_lo; 1268 ldst->datahi_reg = data_hi; 1269 ldst->raddr = tcg_splitwx_to_rx(s->code_ptr); 1270 } 1271} 1272 1273/* 1274 * Entry-points 1275 */ 1276 1277static const tcg_insn_unit *tb_ret_addr; 1278 1279static void tcg_out_exit_tb(TCGContext *s, uintptr_t a0) 1280{ 1281 /* Reuse the zeroing that exists for goto_ptr. */ 1282 if (a0 == 0) { 1283 tcg_out_call_int(s, tcg_code_gen_epilogue, true); 1284 } else { 1285 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); 1286 tcg_out_call_int(s, tb_ret_addr, true); 1287 } 1288} 1289 1290static void tcg_out_goto_tb(TCGContext *s, int which) 1291{ 1292 /* 1293 * Direct branch, or load indirect address, to be patched 1294 * by tb_target_set_jmp_target. Check indirect load offset 1295 * in range early, regardless of direct branch distance, 1296 * via assert within tcg_out_opc_pcaddu2i. 1297 */ 1298 uintptr_t i_addr = get_jmp_target_addr(s, which); 1299 intptr_t i_disp = tcg_pcrel_diff(s, (void *)i_addr); 1300 1301 set_jmp_insn_offset(s, which); 1302 tcg_out_opc_pcaddu2i(s, TCG_REG_TMP0, i_disp >> 2); 1303 1304 /* Finish the load and indirect branch. */ 1305 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_TMP0, 0); 1306 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_TMP0, 0); 1307 set_jmp_reset_offset(s, which); 1308} 1309 1310static void tcg_out_goto_ptr(TCGContext *s, TCGReg a0) 1311{ 1312 tcg_out_opc_jirl(s, TCG_REG_ZERO, a0, 0); 1313} 1314 1315void tb_target_set_jmp_target(const TranslationBlock *tb, int n, 1316 uintptr_t jmp_rx, uintptr_t jmp_rw) 1317{ 1318 uintptr_t d_addr = tb->jmp_target_addr[n]; 1319 ptrdiff_t d_disp = (ptrdiff_t)(d_addr - jmp_rx) >> 2; 1320 tcg_insn_unit insn; 1321 1322 /* Either directly branch, or load slot address for indirect branch. */ 1323 if (d_disp == sextreg(d_disp, 0, 26)) { 1324 insn = encode_sd10k16_insn(OPC_B, d_disp); 1325 } else { 1326 uintptr_t i_addr = (uintptr_t)&tb->jmp_target_addr[n]; 1327 intptr_t i_disp = i_addr - jmp_rx; 1328 insn = encode_dsj20_insn(OPC_PCADDU2I, TCG_REG_TMP0, i_disp >> 2); 1329 } 1330 1331 qatomic_set((tcg_insn_unit *)jmp_rw, insn); 1332 flush_idcache_range(jmp_rx, jmp_rw, 4); 1333} 1334 1335 1336static void tgen_add(TCGContext *s, TCGType type, 1337 TCGReg a0, TCGReg a1, TCGReg a2) 1338{ 1339 if (type == TCG_TYPE_I32) { 1340 tcg_out_opc_add_w(s, a0, a1, a2); 1341 } else { 1342 tcg_out_opc_add_d(s, a0, a1, a2); 1343 } 1344} 1345 1346static const TCGOutOpBinary outop_add = { 1347 .base.static_constraint = C_O1_I2(r, r, rJ), 1348 .out_rrr = tgen_add, 1349 .out_rri = tcg_out_addi, 1350}; 1351 1352static const TCGOutOpBinary outop_addco = { 1353 .base.static_constraint = C_NotImplemented, 1354}; 1355 1356static const TCGOutOpAddSubCarry outop_addci = { 1357 .base.static_constraint = C_NotImplemented, 1358}; 1359 1360static const TCGOutOpBinary outop_addcio = { 1361 .base.static_constraint = C_NotImplemented, 1362}; 1363 1364static void tcg_out_set_carry(TCGContext *s) 1365{ 1366 g_assert_not_reached(); 1367} 1368 1369static void tgen_and(TCGContext *s, TCGType type, 1370 TCGReg a0, TCGReg a1, TCGReg a2) 1371{ 1372 tcg_out_opc_and(s, a0, a1, a2); 1373} 1374 1375static void tgen_andi(TCGContext *s, TCGType type, 1376 TCGReg a0, TCGReg a1, tcg_target_long a2) 1377{ 1378 tcg_out_opc_andi(s, a0, a1, a2); 1379} 1380 1381static const TCGOutOpBinary outop_and = { 1382 .base.static_constraint = C_O1_I2(r, r, rU), 1383 .out_rrr = tgen_and, 1384 .out_rri = tgen_andi, 1385}; 1386 1387static void tgen_andc(TCGContext *s, TCGType type, 1388 TCGReg a0, TCGReg a1, TCGReg a2) 1389{ 1390 tcg_out_opc_andn(s, a0, a1, a2); 1391} 1392 1393static const TCGOutOpBinary outop_andc = { 1394 .base.static_constraint = C_O1_I2(r, r, r), 1395 .out_rrr = tgen_andc, 1396}; 1397 1398static void tgen_clzi(TCGContext *s, TCGType type, 1399 TCGReg a0, TCGReg a1, tcg_target_long a2) 1400{ 1401 /* a2 is constrained to exactly the type width. */ 1402 if (type == TCG_TYPE_I32) { 1403 tcg_out_opc_clz_w(s, a0, a1); 1404 } else { 1405 tcg_out_opc_clz_d(s, a0, a1); 1406 } 1407} 1408 1409static void tgen_clz(TCGContext *s, TCGType type, 1410 TCGReg a0, TCGReg a1, TCGReg a2) 1411{ 1412 tgen_clzi(s, type, TCG_REG_TMP0, a1, /* ignored */ 0); 1413 /* a0 = a1 ? REG_TMP0 : a2 */ 1414 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 1415 tcg_out_opc_masknez(s, a0, a2, a1); 1416 tcg_out_opc_or(s, a0, a0, TCG_REG_TMP0); 1417} 1418 1419static const TCGOutOpBinary outop_clz = { 1420 .base.static_constraint = C_O1_I2(r, r, rW), 1421 .out_rrr = tgen_clz, 1422 .out_rri = tgen_clzi, 1423}; 1424 1425static const TCGOutOpUnary outop_ctpop = { 1426 .base.static_constraint = C_NotImplemented, 1427}; 1428 1429static void tgen_ctzi(TCGContext *s, TCGType type, 1430 TCGReg a0, TCGReg a1, tcg_target_long a2) 1431{ 1432 /* a2 is constrained to exactly the type width. */ 1433 if (type == TCG_TYPE_I32) { 1434 tcg_out_opc_ctz_w(s, a0, a1); 1435 } else { 1436 tcg_out_opc_ctz_d(s, a0, a1); 1437 } 1438} 1439 1440static void tgen_ctz(TCGContext *s, TCGType type, 1441 TCGReg a0, TCGReg a1, TCGReg a2) 1442{ 1443 tgen_ctzi(s, type, TCG_REG_TMP0, a1, /* ignored */ 0); 1444 /* a0 = a1 ? REG_TMP0 : a2 */ 1445 tcg_out_opc_maskeqz(s, TCG_REG_TMP0, TCG_REG_TMP0, a1); 1446 tcg_out_opc_masknez(s, a0, a2, a1); 1447 tcg_out_opc_or(s, a0, a0, TCG_REG_TMP0); 1448} 1449 1450static const TCGOutOpBinary outop_ctz = { 1451 .base.static_constraint = C_O1_I2(r, r, rW), 1452 .out_rrr = tgen_ctz, 1453 .out_rri = tgen_ctzi, 1454}; 1455 1456static void tgen_divs(TCGContext *s, TCGType type, 1457 TCGReg a0, TCGReg a1, TCGReg a2) 1458{ 1459 if (type == TCG_TYPE_I32) { 1460 tcg_out_opc_div_w(s, a0, a1, a2); 1461 } else { 1462 tcg_out_opc_div_d(s, a0, a1, a2); 1463 } 1464} 1465 1466static const TCGOutOpBinary outop_divs = { 1467 .base.static_constraint = C_O1_I2(r, r, r), 1468 .out_rrr = tgen_divs, 1469}; 1470 1471static const TCGOutOpDivRem outop_divs2 = { 1472 .base.static_constraint = C_NotImplemented, 1473}; 1474 1475static void tgen_divu(TCGContext *s, TCGType type, 1476 TCGReg a0, TCGReg a1, TCGReg a2) 1477{ 1478 if (type == TCG_TYPE_I32) { 1479 tcg_out_opc_div_wu(s, a0, a1, a2); 1480 } else { 1481 tcg_out_opc_div_du(s, a0, a1, a2); 1482 } 1483} 1484 1485static const TCGOutOpBinary outop_divu = { 1486 .base.static_constraint = C_O1_I2(r, r, r), 1487 .out_rrr = tgen_divu, 1488}; 1489 1490static const TCGOutOpDivRem outop_divu2 = { 1491 .base.static_constraint = C_NotImplemented, 1492}; 1493 1494static const TCGOutOpBinary outop_eqv = { 1495 .base.static_constraint = C_NotImplemented, 1496}; 1497 1498static void tgen_extrh_i64_i32(TCGContext *s, TCGType t, TCGReg a0, TCGReg a1) 1499{ 1500 tcg_out_opc_srai_d(s, a0, a1, 32); 1501} 1502 1503static const TCGOutOpUnary outop_extrh_i64_i32 = { 1504 .base.static_constraint = C_O1_I1(r, r), 1505 .out_rr = tgen_extrh_i64_i32, 1506}; 1507 1508static void tgen_mul(TCGContext *s, TCGType type, 1509 TCGReg a0, TCGReg a1, TCGReg a2) 1510{ 1511 if (type == TCG_TYPE_I32) { 1512 tcg_out_opc_mul_w(s, a0, a1, a2); 1513 } else { 1514 tcg_out_opc_mul_d(s, a0, a1, a2); 1515 } 1516} 1517 1518static const TCGOutOpBinary outop_mul = { 1519 .base.static_constraint = C_O1_I2(r, r, r), 1520 .out_rrr = tgen_mul, 1521}; 1522 1523static const TCGOutOpMul2 outop_muls2 = { 1524 .base.static_constraint = C_NotImplemented, 1525}; 1526 1527static void tgen_mulsh(TCGContext *s, TCGType type, 1528 TCGReg a0, TCGReg a1, TCGReg a2) 1529{ 1530 if (type == TCG_TYPE_I32) { 1531 tcg_out_opc_mulh_w(s, a0, a1, a2); 1532 } else { 1533 tcg_out_opc_mulh_d(s, a0, a1, a2); 1534 } 1535} 1536 1537static const TCGOutOpBinary outop_mulsh = { 1538 .base.static_constraint = C_O1_I2(r, r, r), 1539 .out_rrr = tgen_mulsh, 1540}; 1541 1542static const TCGOutOpMul2 outop_mulu2 = { 1543 .base.static_constraint = C_NotImplemented, 1544}; 1545 1546static void tgen_muluh(TCGContext *s, TCGType type, 1547 TCGReg a0, TCGReg a1, TCGReg a2) 1548{ 1549 if (type == TCG_TYPE_I32) { 1550 tcg_out_opc_mulh_wu(s, a0, a1, a2); 1551 } else { 1552 tcg_out_opc_mulh_du(s, a0, a1, a2); 1553 } 1554} 1555 1556static const TCGOutOpBinary outop_muluh = { 1557 .base.static_constraint = C_O1_I2(r, r, r), 1558 .out_rrr = tgen_muluh, 1559}; 1560 1561static const TCGOutOpBinary outop_nand = { 1562 .base.static_constraint = C_NotImplemented, 1563}; 1564 1565static void tgen_nor(TCGContext *s, TCGType type, 1566 TCGReg a0, TCGReg a1, TCGReg a2) 1567{ 1568 tcg_out_opc_nor(s, a0, a1, a2); 1569} 1570 1571static const TCGOutOpBinary outop_nor = { 1572 .base.static_constraint = C_O1_I2(r, r, r), 1573 .out_rrr = tgen_nor, 1574}; 1575 1576static void tgen_or(TCGContext *s, TCGType type, 1577 TCGReg a0, TCGReg a1, TCGReg a2) 1578{ 1579 tcg_out_opc_or(s, a0, a1, a2); 1580} 1581 1582static void tgen_ori(TCGContext *s, TCGType type, 1583 TCGReg a0, TCGReg a1, tcg_target_long a2) 1584{ 1585 tcg_out_opc_ori(s, a0, a1, a2); 1586} 1587 1588static const TCGOutOpBinary outop_or = { 1589 .base.static_constraint = C_O1_I2(r, r, rU), 1590 .out_rrr = tgen_or, 1591 .out_rri = tgen_ori, 1592}; 1593 1594static void tgen_orc(TCGContext *s, TCGType type, 1595 TCGReg a0, TCGReg a1, TCGReg a2) 1596{ 1597 tcg_out_opc_orn(s, a0, a1, a2); 1598} 1599 1600static const TCGOutOpBinary outop_orc = { 1601 .base.static_constraint = C_O1_I2(r, r, r), 1602 .out_rrr = tgen_orc, 1603}; 1604 1605static void tgen_rems(TCGContext *s, TCGType type, 1606 TCGReg a0, TCGReg a1, TCGReg a2) 1607{ 1608 if (type == TCG_TYPE_I32) { 1609 tcg_out_opc_mod_w(s, a0, a1, a2); 1610 } else { 1611 tcg_out_opc_mod_d(s, a0, a1, a2); 1612 } 1613} 1614 1615static const TCGOutOpBinary outop_rems = { 1616 .base.static_constraint = C_O1_I2(r, r, r), 1617 .out_rrr = tgen_rems, 1618}; 1619 1620static void tgen_remu(TCGContext *s, TCGType type, 1621 TCGReg a0, TCGReg a1, TCGReg a2) 1622{ 1623 if (type == TCG_TYPE_I32) { 1624 tcg_out_opc_mod_wu(s, a0, a1, a2); 1625 } else { 1626 tcg_out_opc_mod_du(s, a0, a1, a2); 1627 } 1628} 1629 1630static const TCGOutOpBinary outop_remu = { 1631 .base.static_constraint = C_O1_I2(r, r, r), 1632 .out_rrr = tgen_remu, 1633}; 1634 1635static const TCGOutOpBinary outop_rotl = { 1636 .base.static_constraint = C_NotImplemented, 1637}; 1638 1639static void tgen_rotr(TCGContext *s, TCGType type, 1640 TCGReg a0, TCGReg a1, TCGReg a2) 1641{ 1642 if (type == TCG_TYPE_I32) { 1643 tcg_out_opc_rotr_w(s, a0, a1, a2); 1644 } else { 1645 tcg_out_opc_rotr_d(s, a0, a1, a2); 1646 } 1647} 1648 1649static void tgen_rotri(TCGContext *s, TCGType type, 1650 TCGReg a0, TCGReg a1, tcg_target_long a2) 1651{ 1652 if (type == TCG_TYPE_I32) { 1653 tcg_out_opc_rotri_w(s, a0, a1, a2 & 0x1f); 1654 } else { 1655 tcg_out_opc_rotri_d(s, a0, a1, a2 & 0x3f); 1656 } 1657} 1658 1659static const TCGOutOpBinary outop_rotr = { 1660 .base.static_constraint = C_O1_I2(r, r, ri), 1661 .out_rrr = tgen_rotr, 1662 .out_rri = tgen_rotri, 1663}; 1664 1665static void tgen_sar(TCGContext *s, TCGType type, 1666 TCGReg a0, TCGReg a1, TCGReg a2) 1667{ 1668 if (type == TCG_TYPE_I32) { 1669 tcg_out_opc_sra_w(s, a0, a1, a2); 1670 } else { 1671 tcg_out_opc_sra_d(s, a0, a1, a2); 1672 } 1673} 1674 1675static void tgen_sari(TCGContext *s, TCGType type, 1676 TCGReg a0, TCGReg a1, tcg_target_long a2) 1677{ 1678 if (type == TCG_TYPE_I32) { 1679 tcg_out_opc_srai_w(s, a0, a1, a2 & 0x1f); 1680 } else { 1681 tcg_out_opc_srai_d(s, a0, a1, a2 & 0x3f); 1682 } 1683} 1684 1685static const TCGOutOpBinary outop_sar = { 1686 .base.static_constraint = C_O1_I2(r, r, ri), 1687 .out_rrr = tgen_sar, 1688 .out_rri = tgen_sari, 1689}; 1690 1691static void tgen_shl(TCGContext *s, TCGType type, 1692 TCGReg a0, TCGReg a1, TCGReg a2) 1693{ 1694 if (type == TCG_TYPE_I32) { 1695 tcg_out_opc_sll_w(s, a0, a1, a2); 1696 } else { 1697 tcg_out_opc_sll_d(s, a0, a1, a2); 1698 } 1699} 1700 1701static void tgen_shli(TCGContext *s, TCGType type, 1702 TCGReg a0, TCGReg a1, tcg_target_long a2) 1703{ 1704 if (type == TCG_TYPE_I32) { 1705 tcg_out_opc_slli_w(s, a0, a1, a2 & 0x1f); 1706 } else { 1707 tcg_out_opc_slli_d(s, a0, a1, a2 & 0x3f); 1708 } 1709} 1710 1711static const TCGOutOpBinary outop_shl = { 1712 .base.static_constraint = C_O1_I2(r, r, ri), 1713 .out_rrr = tgen_shl, 1714 .out_rri = tgen_shli, 1715}; 1716 1717static void tgen_shr(TCGContext *s, TCGType type, 1718 TCGReg a0, TCGReg a1, TCGReg a2) 1719{ 1720 if (type == TCG_TYPE_I32) { 1721 tcg_out_opc_srl_w(s, a0, a1, a2); 1722 } else { 1723 tcg_out_opc_srl_d(s, a0, a1, a2); 1724 } 1725} 1726 1727static void tgen_shri(TCGContext *s, TCGType type, 1728 TCGReg a0, TCGReg a1, tcg_target_long a2) 1729{ 1730 if (type == TCG_TYPE_I32) { 1731 tcg_out_opc_srli_w(s, a0, a1, a2 & 0x1f); 1732 } else { 1733 tcg_out_opc_srli_d(s, a0, a1, a2 & 0x3f); 1734 } 1735} 1736 1737static const TCGOutOpBinary outop_shr = { 1738 .base.static_constraint = C_O1_I2(r, r, ri), 1739 .out_rrr = tgen_shr, 1740 .out_rri = tgen_shri, 1741}; 1742 1743static void tgen_sub(TCGContext *s, TCGType type, 1744 TCGReg a0, TCGReg a1, TCGReg a2) 1745{ 1746 if (type == TCG_TYPE_I32) { 1747 tcg_out_opc_sub_w(s, a0, a1, a2); 1748 } else { 1749 tcg_out_opc_sub_d(s, a0, a1, a2); 1750 } 1751} 1752 1753static const TCGOutOpSubtract outop_sub = { 1754 .base.static_constraint = C_O1_I2(r, r, r), 1755 .out_rrr = tgen_sub, 1756}; 1757 1758static const TCGOutOpAddSubCarry outop_subbo = { 1759 .base.static_constraint = C_NotImplemented, 1760}; 1761 1762static const TCGOutOpAddSubCarry outop_subbi = { 1763 .base.static_constraint = C_NotImplemented, 1764}; 1765 1766static const TCGOutOpAddSubCarry outop_subbio = { 1767 .base.static_constraint = C_NotImplemented, 1768}; 1769 1770static void tcg_out_set_borrow(TCGContext *s) 1771{ 1772 g_assert_not_reached(); 1773} 1774 1775static void tgen_xor(TCGContext *s, TCGType type, 1776 TCGReg a0, TCGReg a1, TCGReg a2) 1777{ 1778 tcg_out_opc_xor(s, a0, a1, a2); 1779} 1780 1781static void tgen_xori(TCGContext *s, TCGType type, 1782 TCGReg a0, TCGReg a1, tcg_target_long a2) 1783{ 1784 tcg_out_opc_xori(s, a0, a1, a2); 1785} 1786 1787static const TCGOutOpBinary outop_xor = { 1788 .base.static_constraint = C_O1_I2(r, r, rU), 1789 .out_rrr = tgen_xor, 1790 .out_rri = tgen_xori, 1791}; 1792 1793static void tgen_bswap16(TCGContext *s, TCGType type, 1794 TCGReg a0, TCGReg a1, unsigned flags) 1795{ 1796 tcg_out_opc_revb_2h(s, a0, a1); 1797 if (flags & TCG_BSWAP_OS) { 1798 tcg_out_ext16s(s, TCG_TYPE_REG, a0, a0); 1799 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1800 tcg_out_ext16u(s, a0, a0); 1801 } 1802} 1803 1804static const TCGOutOpBswap outop_bswap16 = { 1805 .base.static_constraint = C_O1_I1(r, r), 1806 .out_rr = tgen_bswap16, 1807}; 1808 1809static void tgen_bswap32(TCGContext *s, TCGType type, 1810 TCGReg a0, TCGReg a1, unsigned flags) 1811{ 1812 tcg_out_opc_revb_2w(s, a0, a1); 1813 1814 /* All 32-bit values are computed sign-extended in the register. */ 1815 if (type == TCG_TYPE_I32 || (flags & TCG_BSWAP_OS)) { 1816 tcg_out_ext32s(s, a0, a0); 1817 } else if ((flags & (TCG_BSWAP_IZ | TCG_BSWAP_OZ)) == TCG_BSWAP_OZ) { 1818 tcg_out_ext32u(s, a0, a0); 1819 } 1820} 1821 1822static const TCGOutOpBswap outop_bswap32 = { 1823 .base.static_constraint = C_O1_I1(r, r), 1824 .out_rr = tgen_bswap32, 1825}; 1826 1827static void tgen_bswap64(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1828{ 1829 tcg_out_opc_revb_d(s, a0, a1); 1830} 1831 1832static const TCGOutOpUnary outop_bswap64 = { 1833 .base.static_constraint = C_O1_I1(r, r), 1834 .out_rr = tgen_bswap64, 1835}; 1836 1837static void tgen_neg(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1838{ 1839 tgen_sub(s, type, a0, TCG_REG_ZERO, a1); 1840} 1841 1842static const TCGOutOpUnary outop_neg = { 1843 .base.static_constraint = C_O1_I1(r, r), 1844 .out_rr = tgen_neg, 1845}; 1846 1847static void tgen_not(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1) 1848{ 1849 tgen_nor(s, type, a0, a1, TCG_REG_ZERO); 1850} 1851 1852static const TCGOutOpUnary outop_not = { 1853 .base.static_constraint = C_O1_I1(r, r), 1854 .out_rr = tgen_not, 1855}; 1856 1857static void tgen_deposit(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1858 TCGReg a2, unsigned ofs, unsigned len) 1859{ 1860 if (type == TCG_TYPE_I32) { 1861 tcg_out_opc_bstrins_w(s, a0, a2, ofs, ofs + len - 1); 1862 } else { 1863 tcg_out_opc_bstrins_d(s, a0, a2, ofs, ofs + len - 1); 1864 } 1865} 1866 1867static const TCGOutOpDeposit outop_deposit = { 1868 .base.static_constraint = C_O1_I2(r, 0, rz), 1869 .out_rrr = tgen_deposit, 1870}; 1871 1872static void tgen_extract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1873 unsigned ofs, unsigned len) 1874{ 1875 if (ofs == 0 && len <= 12) { 1876 tcg_out_opc_andi(s, a0, a1, (1 << len) - 1); 1877 } else if (type == TCG_TYPE_I32) { 1878 tcg_out_opc_bstrpick_w(s, a0, a1, ofs, ofs + len - 1); 1879 } else { 1880 tcg_out_opc_bstrpick_d(s, a0, a1, ofs, ofs + len - 1); 1881 } 1882} 1883 1884static const TCGOutOpExtract outop_extract = { 1885 .base.static_constraint = C_O1_I1(r, r), 1886 .out_rr = tgen_extract, 1887}; 1888 1889static void tgen_sextract(TCGContext *s, TCGType type, TCGReg a0, TCGReg a1, 1890 unsigned ofs, unsigned len) 1891{ 1892 if (ofs == 0) { 1893 switch (len) { 1894 case 8: 1895 tcg_out_ext8s(s, type, a0, a1); 1896 return; 1897 case 16: 1898 tcg_out_ext16s(s, type, a0, a1); 1899 return; 1900 case 32: 1901 tcg_out_ext32s(s, a0, a1); 1902 return; 1903 } 1904 } else if (ofs + len == 32) { 1905 tcg_out_opc_srai_w(s, a0, a1, ofs); 1906 return; 1907 } 1908 g_assert_not_reached(); 1909} 1910 1911static const TCGOutOpExtract outop_sextract = { 1912 .base.static_constraint = C_O1_I1(r, r), 1913 .out_rr = tgen_sextract, 1914}; 1915 1916static const TCGOutOpExtract2 outop_extract2 = { 1917 .base.static_constraint = C_NotImplemented, 1918}; 1919 1920static void tgen_ld8u(TCGContext *s, TCGType type, TCGReg dest, 1921 TCGReg base, ptrdiff_t offset) 1922{ 1923 tcg_out_ldst(s, OPC_LD_BU, dest, base, offset); 1924} 1925 1926static const TCGOutOpLoad outop_ld8u = { 1927 .base.static_constraint = C_O1_I1(r, r), 1928 .out = tgen_ld8u, 1929}; 1930 1931static void tgen_ld8s(TCGContext *s, TCGType type, TCGReg dest, 1932 TCGReg base, ptrdiff_t offset) 1933{ 1934 tcg_out_ldst(s, OPC_LD_B, dest, base, offset); 1935} 1936 1937static const TCGOutOpLoad outop_ld8s = { 1938 .base.static_constraint = C_O1_I1(r, r), 1939 .out = tgen_ld8s, 1940}; 1941 1942static void tgen_ld16u(TCGContext *s, TCGType type, TCGReg dest, 1943 TCGReg base, ptrdiff_t offset) 1944{ 1945 tcg_out_ldst(s, OPC_LD_HU, dest, base, offset); 1946} 1947 1948static const TCGOutOpLoad outop_ld16u = { 1949 .base.static_constraint = C_O1_I1(r, r), 1950 .out = tgen_ld16u, 1951}; 1952 1953static void tgen_ld16s(TCGContext *s, TCGType type, TCGReg dest, 1954 TCGReg base, ptrdiff_t offset) 1955{ 1956 tcg_out_ldst(s, OPC_LD_H, dest, base, offset); 1957} 1958 1959static const TCGOutOpLoad outop_ld16s = { 1960 .base.static_constraint = C_O1_I1(r, r), 1961 .out = tgen_ld16s, 1962}; 1963 1964static void tgen_ld32u(TCGContext *s, TCGType type, TCGReg dest, 1965 TCGReg base, ptrdiff_t offset) 1966{ 1967 tcg_out_ldst(s, OPC_LD_WU, dest, base, offset); 1968} 1969 1970static const TCGOutOpLoad outop_ld32u = { 1971 .base.static_constraint = C_O1_I1(r, r), 1972 .out = tgen_ld32u, 1973}; 1974 1975static void tgen_ld32s(TCGContext *s, TCGType type, TCGReg dest, 1976 TCGReg base, ptrdiff_t offset) 1977{ 1978 tcg_out_ldst(s, OPC_LD_W, dest, base, offset); 1979} 1980 1981static const TCGOutOpLoad outop_ld32s = { 1982 .base.static_constraint = C_O1_I1(r, r), 1983 .out = tgen_ld32s, 1984}; 1985 1986static void tgen_st8_r(TCGContext *s, TCGType type, TCGReg data, 1987 TCGReg base, ptrdiff_t offset) 1988{ 1989 tcg_out_ldst(s, OPC_ST_B, data, base, offset); 1990} 1991 1992static const TCGOutOpStore outop_st8 = { 1993 .base.static_constraint = C_O0_I2(rz, r), 1994 .out_r = tgen_st8_r, 1995}; 1996 1997static void tgen_st16_r(TCGContext *s, TCGType type, TCGReg data, 1998 TCGReg base, ptrdiff_t offset) 1999{ 2000 tcg_out_ldst(s, OPC_ST_H, data, base, offset); 2001} 2002 2003static const TCGOutOpStore outop_st16 = { 2004 .base.static_constraint = C_O0_I2(rz, r), 2005 .out_r = tgen_st16_r, 2006}; 2007 2008static const TCGOutOpStore outop_st = { 2009 .base.static_constraint = C_O0_I2(rz, r), 2010 .out_r = tcg_out_st, 2011}; 2012 2013static void tcg_out_op(TCGContext *s, TCGOpcode opc, TCGType type, 2014 const TCGArg args[TCG_MAX_OP_ARGS], 2015 const int const_args[TCG_MAX_OP_ARGS]) 2016{ 2017 TCGArg a0 = args[0]; 2018 TCGArg a1 = args[1]; 2019 TCGArg a2 = args[2]; 2020 TCGArg a3 = args[3]; 2021 2022 switch (opc) { 2023 case INDEX_op_qemu_ld_i32: 2024 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32); 2025 break; 2026 case INDEX_op_qemu_ld_i64: 2027 tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64); 2028 break; 2029 case INDEX_op_qemu_ld_i128: 2030 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, true); 2031 break; 2032 case INDEX_op_qemu_st_i32: 2033 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32); 2034 break; 2035 case INDEX_op_qemu_st_i64: 2036 tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64); 2037 break; 2038 case INDEX_op_qemu_st_i128: 2039 tcg_out_qemu_ldst_i128(s, a0, a1, a2, a3, false); 2040 break; 2041 2042 case INDEX_op_call: /* Always emitted via tcg_out_call. */ 2043 case INDEX_op_exit_tb: /* Always emitted via tcg_out_exit_tb. */ 2044 case INDEX_op_goto_tb: /* Always emitted via tcg_out_goto_tb. */ 2045 default: 2046 g_assert_not_reached(); 2047 } 2048} 2049 2050static bool tcg_out_dup_vec(TCGContext *s, TCGType type, unsigned vece, 2051 TCGReg rd, TCGReg rs) 2052{ 2053 static const LoongArchInsn repl_insn[2][4] = { 2054 { OPC_VREPLGR2VR_B, OPC_VREPLGR2VR_H, 2055 OPC_VREPLGR2VR_W, OPC_VREPLGR2VR_D }, 2056 { OPC_XVREPLGR2VR_B, OPC_XVREPLGR2VR_H, 2057 OPC_XVREPLGR2VR_W, OPC_XVREPLGR2VR_D }, 2058 }; 2059 bool lasx = type == TCG_TYPE_V256; 2060 2061 tcg_debug_assert(vece <= MO_64); 2062 tcg_out32(s, encode_vdj_insn(repl_insn[lasx][vece], rd, rs)); 2063 return true; 2064} 2065 2066static bool tcg_out_dupm_vec(TCGContext *s, TCGType type, unsigned vece, 2067 TCGReg r, TCGReg base, intptr_t offset) 2068{ 2069 bool lasx = type == TCG_TYPE_V256; 2070 2071 /* Handle imm overflow and division (vldrepl.d imm is divided by 8). */ 2072 if (offset < -0x800 || offset > 0x7ff || 2073 (offset & ((1 << vece) - 1)) != 0) { 2074 tcg_out_addi(s, TCG_TYPE_I64, TCG_REG_TMP0, base, offset); 2075 base = TCG_REG_TMP0; 2076 offset = 0; 2077 } 2078 offset >>= vece; 2079 2080 switch (vece) { 2081 case MO_8: 2082 if (lasx) { 2083 tcg_out_opc_xvldrepl_b(s, r, base, offset); 2084 } else { 2085 tcg_out_opc_vldrepl_b(s, r, base, offset); 2086 } 2087 break; 2088 case MO_16: 2089 if (lasx) { 2090 tcg_out_opc_xvldrepl_h(s, r, base, offset); 2091 } else { 2092 tcg_out_opc_vldrepl_h(s, r, base, offset); 2093 } 2094 break; 2095 case MO_32: 2096 if (lasx) { 2097 tcg_out_opc_xvldrepl_w(s, r, base, offset); 2098 } else { 2099 tcg_out_opc_vldrepl_w(s, r, base, offset); 2100 } 2101 break; 2102 case MO_64: 2103 if (lasx) { 2104 tcg_out_opc_xvldrepl_d(s, r, base, offset); 2105 } else { 2106 tcg_out_opc_vldrepl_d(s, r, base, offset); 2107 } 2108 break; 2109 default: 2110 g_assert_not_reached(); 2111 } 2112 return true; 2113} 2114 2115static void tcg_out_dupi_vec(TCGContext *s, TCGType type, unsigned vece, 2116 TCGReg rd, int64_t v64) 2117{ 2118 /* Try vldi if imm can fit */ 2119 int64_t value = sextract64(v64, 0, 8 << vece); 2120 if (-0x200 <= value && value <= 0x1FF) { 2121 uint32_t imm = (vece << 10) | ((uint32_t)v64 & 0x3FF); 2122 2123 if (type == TCG_TYPE_V256) { 2124 tcg_out_opc_xvldi(s, rd, imm); 2125 } else { 2126 tcg_out_opc_vldi(s, rd, imm); 2127 } 2128 return; 2129 } 2130 2131 /* TODO: vldi patterns when imm 12 is set */ 2132 2133 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP0, value); 2134 tcg_out_dup_vec(s, type, vece, rd, TCG_REG_TMP0); 2135} 2136 2137static void tcg_out_addsub_vec(TCGContext *s, bool lasx, unsigned vece, 2138 TCGArg a0, TCGArg a1, TCGArg a2, 2139 bool a2_is_const, bool is_add) 2140{ 2141 static const LoongArchInsn add_vec_insn[2][4] = { 2142 { OPC_VADD_B, OPC_VADD_H, OPC_VADD_W, OPC_VADD_D }, 2143 { OPC_XVADD_B, OPC_XVADD_H, OPC_XVADD_W, OPC_XVADD_D }, 2144 }; 2145 static const LoongArchInsn add_vec_imm_insn[2][4] = { 2146 { OPC_VADDI_BU, OPC_VADDI_HU, OPC_VADDI_WU, OPC_VADDI_DU }, 2147 { OPC_XVADDI_BU, OPC_XVADDI_HU, OPC_XVADDI_WU, OPC_XVADDI_DU }, 2148 }; 2149 static const LoongArchInsn sub_vec_insn[2][4] = { 2150 { OPC_VSUB_B, OPC_VSUB_H, OPC_VSUB_W, OPC_VSUB_D }, 2151 { OPC_XVSUB_B, OPC_XVSUB_H, OPC_XVSUB_W, OPC_XVSUB_D }, 2152 }; 2153 static const LoongArchInsn sub_vec_imm_insn[2][4] = { 2154 { OPC_VSUBI_BU, OPC_VSUBI_HU, OPC_VSUBI_WU, OPC_VSUBI_DU }, 2155 { OPC_XVSUBI_BU, OPC_XVSUBI_HU, OPC_XVSUBI_WU, OPC_XVSUBI_DU }, 2156 }; 2157 LoongArchInsn insn; 2158 2159 if (a2_is_const) { 2160 int64_t value = sextract64(a2, 0, 8 << vece); 2161 2162 if (!is_add) { 2163 value = -value; 2164 } 2165 if (value < 0) { 2166 insn = sub_vec_imm_insn[lasx][vece]; 2167 value = -value; 2168 } else { 2169 insn = add_vec_imm_insn[lasx][vece]; 2170 } 2171 2172 /* Constraint TCG_CT_CONST_VADD ensures validity. */ 2173 tcg_debug_assert(0 <= value && value <= 0x1f); 2174 2175 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, value)); 2176 return; 2177 } 2178 2179 if (is_add) { 2180 insn = add_vec_insn[lasx][vece]; 2181 } else { 2182 insn = sub_vec_insn[lasx][vece]; 2183 } 2184 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 2185} 2186 2187static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc, 2188 unsigned vecl, unsigned vece, 2189 const TCGArg args[TCG_MAX_OP_ARGS], 2190 const int const_args[TCG_MAX_OP_ARGS]) 2191{ 2192 TCGType type = vecl + TCG_TYPE_V64; 2193 bool lasx = type == TCG_TYPE_V256; 2194 TCGArg a0, a1, a2, a3; 2195 LoongArchInsn insn; 2196 2197 static const LoongArchInsn cmp_vec_insn[16][2][4] = { 2198 [TCG_COND_EQ] = { 2199 { OPC_VSEQ_B, OPC_VSEQ_H, OPC_VSEQ_W, OPC_VSEQ_D }, 2200 { OPC_XVSEQ_B, OPC_XVSEQ_H, OPC_XVSEQ_W, OPC_XVSEQ_D }, 2201 }, 2202 [TCG_COND_LE] = { 2203 { OPC_VSLE_B, OPC_VSLE_H, OPC_VSLE_W, OPC_VSLE_D }, 2204 { OPC_XVSLE_B, OPC_XVSLE_H, OPC_XVSLE_W, OPC_XVSLE_D }, 2205 }, 2206 [TCG_COND_LEU] = { 2207 { OPC_VSLE_BU, OPC_VSLE_HU, OPC_VSLE_WU, OPC_VSLE_DU }, 2208 { OPC_XVSLE_BU, OPC_XVSLE_HU, OPC_XVSLE_WU, OPC_XVSLE_DU }, 2209 }, 2210 [TCG_COND_LT] = { 2211 { OPC_VSLT_B, OPC_VSLT_H, OPC_VSLT_W, OPC_VSLT_D }, 2212 { OPC_XVSLT_B, OPC_XVSLT_H, OPC_XVSLT_W, OPC_XVSLT_D }, 2213 }, 2214 [TCG_COND_LTU] = { 2215 { OPC_VSLT_BU, OPC_VSLT_HU, OPC_VSLT_WU, OPC_VSLT_DU }, 2216 { OPC_XVSLT_BU, OPC_XVSLT_HU, OPC_XVSLT_WU, OPC_XVSLT_DU }, 2217 } 2218 }; 2219 static const LoongArchInsn cmp_vec_imm_insn[16][2][4] = { 2220 [TCG_COND_EQ] = { 2221 { OPC_VSEQI_B, OPC_VSEQI_H, OPC_VSEQI_W, OPC_VSEQI_D }, 2222 { OPC_XVSEQI_B, OPC_XVSEQI_H, OPC_XVSEQI_W, OPC_XVSEQI_D }, 2223 }, 2224 [TCG_COND_LE] = { 2225 { OPC_VSLEI_B, OPC_VSLEI_H, OPC_VSLEI_W, OPC_VSLEI_D }, 2226 { OPC_XVSLEI_B, OPC_XVSLEI_H, OPC_XVSLEI_W, OPC_XVSLEI_D }, 2227 }, 2228 [TCG_COND_LEU] = { 2229 { OPC_VSLEI_BU, OPC_VSLEI_HU, OPC_VSLEI_WU, OPC_VSLEI_DU }, 2230 { OPC_XVSLEI_BU, OPC_XVSLEI_HU, OPC_XVSLEI_WU, OPC_XVSLEI_DU }, 2231 }, 2232 [TCG_COND_LT] = { 2233 { OPC_VSLTI_B, OPC_VSLTI_H, OPC_VSLTI_W, OPC_VSLTI_D }, 2234 { OPC_XVSLTI_B, OPC_XVSLTI_H, OPC_XVSLTI_W, OPC_XVSLTI_D }, 2235 }, 2236 [TCG_COND_LTU] = { 2237 { OPC_VSLTI_BU, OPC_VSLTI_HU, OPC_VSLTI_WU, OPC_VSLTI_DU }, 2238 { OPC_XVSLTI_BU, OPC_XVSLTI_HU, OPC_XVSLTI_WU, OPC_XVSLTI_DU }, 2239 } 2240 }; 2241 static const LoongArchInsn neg_vec_insn[2][4] = { 2242 { OPC_VNEG_B, OPC_VNEG_H, OPC_VNEG_W, OPC_VNEG_D }, 2243 { OPC_XVNEG_B, OPC_XVNEG_H, OPC_XVNEG_W, OPC_XVNEG_D }, 2244 }; 2245 static const LoongArchInsn mul_vec_insn[2][4] = { 2246 { OPC_VMUL_B, OPC_VMUL_H, OPC_VMUL_W, OPC_VMUL_D }, 2247 { OPC_XVMUL_B, OPC_XVMUL_H, OPC_XVMUL_W, OPC_XVMUL_D }, 2248 }; 2249 static const LoongArchInsn smin_vec_insn[2][4] = { 2250 { OPC_VMIN_B, OPC_VMIN_H, OPC_VMIN_W, OPC_VMIN_D }, 2251 { OPC_XVMIN_B, OPC_XVMIN_H, OPC_XVMIN_W, OPC_XVMIN_D }, 2252 }; 2253 static const LoongArchInsn umin_vec_insn[2][4] = { 2254 { OPC_VMIN_BU, OPC_VMIN_HU, OPC_VMIN_WU, OPC_VMIN_DU }, 2255 { OPC_XVMIN_BU, OPC_XVMIN_HU, OPC_XVMIN_WU, OPC_XVMIN_DU }, 2256 }; 2257 static const LoongArchInsn smax_vec_insn[2][4] = { 2258 { OPC_VMAX_B, OPC_VMAX_H, OPC_VMAX_W, OPC_VMAX_D }, 2259 { OPC_XVMAX_B, OPC_XVMAX_H, OPC_XVMAX_W, OPC_XVMAX_D }, 2260 }; 2261 static const LoongArchInsn umax_vec_insn[2][4] = { 2262 { OPC_VMAX_BU, OPC_VMAX_HU, OPC_VMAX_WU, OPC_VMAX_DU }, 2263 { OPC_XVMAX_BU, OPC_XVMAX_HU, OPC_XVMAX_WU, OPC_XVMAX_DU }, 2264 }; 2265 static const LoongArchInsn ssadd_vec_insn[2][4] = { 2266 { OPC_VSADD_B, OPC_VSADD_H, OPC_VSADD_W, OPC_VSADD_D }, 2267 { OPC_XVSADD_B, OPC_XVSADD_H, OPC_XVSADD_W, OPC_XVSADD_D }, 2268 }; 2269 static const LoongArchInsn usadd_vec_insn[2][4] = { 2270 { OPC_VSADD_BU, OPC_VSADD_HU, OPC_VSADD_WU, OPC_VSADD_DU }, 2271 { OPC_XVSADD_BU, OPC_XVSADD_HU, OPC_XVSADD_WU, OPC_XVSADD_DU }, 2272 }; 2273 static const LoongArchInsn sssub_vec_insn[2][4] = { 2274 { OPC_VSSUB_B, OPC_VSSUB_H, OPC_VSSUB_W, OPC_VSSUB_D }, 2275 { OPC_XVSSUB_B, OPC_XVSSUB_H, OPC_XVSSUB_W, OPC_XVSSUB_D }, 2276 }; 2277 static const LoongArchInsn ussub_vec_insn[2][4] = { 2278 { OPC_VSSUB_BU, OPC_VSSUB_HU, OPC_VSSUB_WU, OPC_VSSUB_DU }, 2279 { OPC_XVSSUB_BU, OPC_XVSSUB_HU, OPC_XVSSUB_WU, OPC_XVSSUB_DU }, 2280 }; 2281 static const LoongArchInsn shlv_vec_insn[2][4] = { 2282 { OPC_VSLL_B, OPC_VSLL_H, OPC_VSLL_W, OPC_VSLL_D }, 2283 { OPC_XVSLL_B, OPC_XVSLL_H, OPC_XVSLL_W, OPC_XVSLL_D }, 2284 }; 2285 static const LoongArchInsn shrv_vec_insn[2][4] = { 2286 { OPC_VSRL_B, OPC_VSRL_H, OPC_VSRL_W, OPC_VSRL_D }, 2287 { OPC_XVSRL_B, OPC_XVSRL_H, OPC_XVSRL_W, OPC_XVSRL_D }, 2288 }; 2289 static const LoongArchInsn sarv_vec_insn[2][4] = { 2290 { OPC_VSRA_B, OPC_VSRA_H, OPC_VSRA_W, OPC_VSRA_D }, 2291 { OPC_XVSRA_B, OPC_XVSRA_H, OPC_XVSRA_W, OPC_XVSRA_D }, 2292 }; 2293 static const LoongArchInsn shli_vec_insn[2][4] = { 2294 { OPC_VSLLI_B, OPC_VSLLI_H, OPC_VSLLI_W, OPC_VSLLI_D }, 2295 { OPC_XVSLLI_B, OPC_XVSLLI_H, OPC_XVSLLI_W, OPC_XVSLLI_D }, 2296 }; 2297 static const LoongArchInsn shri_vec_insn[2][4] = { 2298 { OPC_VSRLI_B, OPC_VSRLI_H, OPC_VSRLI_W, OPC_VSRLI_D }, 2299 { OPC_XVSRLI_B, OPC_XVSRLI_H, OPC_XVSRLI_W, OPC_XVSRLI_D }, 2300 }; 2301 static const LoongArchInsn sari_vec_insn[2][4] = { 2302 { OPC_VSRAI_B, OPC_VSRAI_H, OPC_VSRAI_W, OPC_VSRAI_D }, 2303 { OPC_XVSRAI_B, OPC_XVSRAI_H, OPC_XVSRAI_W, OPC_XVSRAI_D }, 2304 }; 2305 static const LoongArchInsn rotrv_vec_insn[2][4] = { 2306 { OPC_VROTR_B, OPC_VROTR_H, OPC_VROTR_W, OPC_VROTR_D }, 2307 { OPC_XVROTR_B, OPC_XVROTR_H, OPC_XVROTR_W, OPC_XVROTR_D }, 2308 }; 2309 static const LoongArchInsn rotri_vec_insn[2][4] = { 2310 { OPC_VROTRI_B, OPC_VROTRI_H, OPC_VROTRI_W, OPC_VROTRI_D }, 2311 { OPC_XVROTRI_B, OPC_XVROTRI_H, OPC_XVROTRI_W, OPC_XVROTRI_D }, 2312 }; 2313 2314 a0 = args[0]; 2315 a1 = args[1]; 2316 a2 = args[2]; 2317 a3 = args[3]; 2318 2319 switch (opc) { 2320 case INDEX_op_st_vec: 2321 tcg_out_st(s, type, a0, a1, a2); 2322 break; 2323 case INDEX_op_ld_vec: 2324 tcg_out_ld(s, type, a0, a1, a2); 2325 break; 2326 case INDEX_op_and_vec: 2327 insn = lasx ? OPC_XVAND_V : OPC_VAND_V; 2328 goto vdvjvk; 2329 case INDEX_op_andc_vec: 2330 /* 2331 * vandn vd, vj, vk: vd = vk & ~vj 2332 * andc_vec vd, vj, vk: vd = vj & ~vk 2333 * vj and vk are swapped 2334 */ 2335 a1 = a2; 2336 a2 = args[1]; 2337 insn = lasx ? OPC_XVANDN_V : OPC_VANDN_V; 2338 goto vdvjvk; 2339 case INDEX_op_or_vec: 2340 insn = lasx ? OPC_XVOR_V : OPC_VOR_V; 2341 goto vdvjvk; 2342 case INDEX_op_orc_vec: 2343 insn = lasx ? OPC_XVORN_V : OPC_VORN_V; 2344 goto vdvjvk; 2345 case INDEX_op_xor_vec: 2346 insn = lasx ? OPC_XVXOR_V : OPC_VXOR_V; 2347 goto vdvjvk; 2348 case INDEX_op_not_vec: 2349 a2 = a1; 2350 /* fall through */ 2351 case INDEX_op_nor_vec: 2352 insn = lasx ? OPC_XVNOR_V : OPC_VNOR_V; 2353 goto vdvjvk; 2354 case INDEX_op_cmp_vec: 2355 { 2356 TCGCond cond = args[3]; 2357 2358 if (const_args[2]) { 2359 /* 2360 * cmp_vec dest, src, value 2361 * Try vseqi/vslei/vslti 2362 */ 2363 int64_t value = sextract64(a2, 0, 8 << vece); 2364 switch (cond) { 2365 case TCG_COND_EQ: 2366 case TCG_COND_LE: 2367 case TCG_COND_LT: 2368 insn = cmp_vec_imm_insn[cond][lasx][vece]; 2369 tcg_out32(s, encode_vdvjsk5_insn(insn, a0, a1, value)); 2370 break; 2371 case TCG_COND_LEU: 2372 case TCG_COND_LTU: 2373 insn = cmp_vec_imm_insn[cond][lasx][vece]; 2374 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, value)); 2375 break; 2376 default: 2377 g_assert_not_reached(); 2378 } 2379 break; 2380 } 2381 2382 insn = cmp_vec_insn[cond][lasx][vece]; 2383 if (insn == 0) { 2384 TCGArg t; 2385 t = a1, a1 = a2, a2 = t; 2386 cond = tcg_swap_cond(cond); 2387 insn = cmp_vec_insn[cond][lasx][vece]; 2388 tcg_debug_assert(insn != 0); 2389 } 2390 } 2391 goto vdvjvk; 2392 case INDEX_op_add_vec: 2393 tcg_out_addsub_vec(s, lasx, vece, a0, a1, a2, const_args[2], true); 2394 break; 2395 case INDEX_op_sub_vec: 2396 tcg_out_addsub_vec(s, lasx, vece, a0, a1, a2, const_args[2], false); 2397 break; 2398 case INDEX_op_neg_vec: 2399 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[lasx][vece], a0, a1)); 2400 break; 2401 case INDEX_op_mul_vec: 2402 insn = mul_vec_insn[lasx][vece]; 2403 goto vdvjvk; 2404 case INDEX_op_smin_vec: 2405 insn = smin_vec_insn[lasx][vece]; 2406 goto vdvjvk; 2407 case INDEX_op_smax_vec: 2408 insn = smax_vec_insn[lasx][vece]; 2409 goto vdvjvk; 2410 case INDEX_op_umin_vec: 2411 insn = umin_vec_insn[lasx][vece]; 2412 goto vdvjvk; 2413 case INDEX_op_umax_vec: 2414 insn = umax_vec_insn[lasx][vece]; 2415 goto vdvjvk; 2416 case INDEX_op_ssadd_vec: 2417 insn = ssadd_vec_insn[lasx][vece]; 2418 goto vdvjvk; 2419 case INDEX_op_usadd_vec: 2420 insn = usadd_vec_insn[lasx][vece]; 2421 goto vdvjvk; 2422 case INDEX_op_sssub_vec: 2423 insn = sssub_vec_insn[lasx][vece]; 2424 goto vdvjvk; 2425 case INDEX_op_ussub_vec: 2426 insn = ussub_vec_insn[lasx][vece]; 2427 goto vdvjvk; 2428 case INDEX_op_shlv_vec: 2429 insn = shlv_vec_insn[lasx][vece]; 2430 goto vdvjvk; 2431 case INDEX_op_shrv_vec: 2432 insn = shrv_vec_insn[lasx][vece]; 2433 goto vdvjvk; 2434 case INDEX_op_sarv_vec: 2435 insn = sarv_vec_insn[lasx][vece]; 2436 goto vdvjvk; 2437 case INDEX_op_rotlv_vec: 2438 /* rotlv_vec a1, a2 = rotrv_vec a1, -a2 */ 2439 tcg_out32(s, encode_vdvj_insn(neg_vec_insn[lasx][vece], 2440 TCG_VEC_TMP0, a2)); 2441 a2 = TCG_VEC_TMP0; 2442 /* fall through */ 2443 case INDEX_op_rotrv_vec: 2444 insn = rotrv_vec_insn[lasx][vece]; 2445 goto vdvjvk; 2446 case INDEX_op_shli_vec: 2447 insn = shli_vec_insn[lasx][vece]; 2448 goto vdvjukN; 2449 case INDEX_op_shri_vec: 2450 insn = shri_vec_insn[lasx][vece]; 2451 goto vdvjukN; 2452 case INDEX_op_sari_vec: 2453 insn = sari_vec_insn[lasx][vece]; 2454 goto vdvjukN; 2455 case INDEX_op_rotli_vec: 2456 /* rotli_vec a1, a2 = rotri_vec a1, -a2 */ 2457 a2 = extract32(-a2, 0, 3 + vece); 2458 insn = rotri_vec_insn[lasx][vece]; 2459 goto vdvjukN; 2460 case INDEX_op_bitsel_vec: 2461 /* vbitsel vd, vj, vk, va = bitsel_vec vd, va, vk, vj */ 2462 if (lasx) { 2463 tcg_out_opc_xvbitsel_v(s, a0, a3, a2, a1); 2464 } else { 2465 tcg_out_opc_vbitsel_v(s, a0, a3, a2, a1); 2466 } 2467 break; 2468 case INDEX_op_dupm_vec: 2469 tcg_out_dupm_vec(s, type, vece, a0, a1, a2); 2470 break; 2471 default: 2472 g_assert_not_reached(); 2473 vdvjvk: 2474 tcg_out32(s, encode_vdvjvk_insn(insn, a0, a1, a2)); 2475 break; 2476 vdvjukN: 2477 switch (vece) { 2478 case MO_8: 2479 tcg_out32(s, encode_vdvjuk3_insn(insn, a0, a1, a2)); 2480 break; 2481 case MO_16: 2482 tcg_out32(s, encode_vdvjuk4_insn(insn, a0, a1, a2)); 2483 break; 2484 case MO_32: 2485 tcg_out32(s, encode_vdvjuk5_insn(insn, a0, a1, a2)); 2486 break; 2487 case MO_64: 2488 tcg_out32(s, encode_vdvjuk6_insn(insn, a0, a1, a2)); 2489 break; 2490 default: 2491 g_assert_not_reached(); 2492 } 2493 break; 2494 } 2495} 2496 2497int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece) 2498{ 2499 switch (opc) { 2500 case INDEX_op_ld_vec: 2501 case INDEX_op_st_vec: 2502 case INDEX_op_dup_vec: 2503 case INDEX_op_dupm_vec: 2504 case INDEX_op_cmp_vec: 2505 case INDEX_op_add_vec: 2506 case INDEX_op_sub_vec: 2507 case INDEX_op_and_vec: 2508 case INDEX_op_andc_vec: 2509 case INDEX_op_or_vec: 2510 case INDEX_op_orc_vec: 2511 case INDEX_op_xor_vec: 2512 case INDEX_op_nor_vec: 2513 case INDEX_op_not_vec: 2514 case INDEX_op_neg_vec: 2515 case INDEX_op_mul_vec: 2516 case INDEX_op_smin_vec: 2517 case INDEX_op_smax_vec: 2518 case INDEX_op_umin_vec: 2519 case INDEX_op_umax_vec: 2520 case INDEX_op_ssadd_vec: 2521 case INDEX_op_usadd_vec: 2522 case INDEX_op_sssub_vec: 2523 case INDEX_op_ussub_vec: 2524 case INDEX_op_shlv_vec: 2525 case INDEX_op_shrv_vec: 2526 case INDEX_op_sarv_vec: 2527 case INDEX_op_bitsel_vec: 2528 return 1; 2529 default: 2530 return 0; 2531 } 2532} 2533 2534void tcg_expand_vec_op(TCGOpcode opc, TCGType type, unsigned vece, 2535 TCGArg a0, ...) 2536{ 2537 g_assert_not_reached(); 2538} 2539 2540static TCGConstraintSetIndex 2541tcg_target_op_def(TCGOpcode op, TCGType type, unsigned flags) 2542{ 2543 switch (op) { 2544 case INDEX_op_qemu_st_i32: 2545 case INDEX_op_qemu_st_i64: 2546 return C_O0_I2(rz, r); 2547 2548 case INDEX_op_qemu_ld_i128: 2549 return C_N2_I1(r, r, r); 2550 2551 case INDEX_op_qemu_st_i128: 2552 return C_O0_I3(r, r, r); 2553 2554 case INDEX_op_qemu_ld_i32: 2555 case INDEX_op_qemu_ld_i64: 2556 return C_O1_I1(r, r); 2557 2558 case INDEX_op_ld_vec: 2559 case INDEX_op_dupm_vec: 2560 case INDEX_op_dup_vec: 2561 return C_O1_I1(w, r); 2562 2563 case INDEX_op_st_vec: 2564 return C_O0_I2(w, r); 2565 2566 case INDEX_op_cmp_vec: 2567 return C_O1_I2(w, w, wM); 2568 2569 case INDEX_op_add_vec: 2570 case INDEX_op_sub_vec: 2571 return C_O1_I2(w, w, wA); 2572 2573 case INDEX_op_and_vec: 2574 case INDEX_op_andc_vec: 2575 case INDEX_op_or_vec: 2576 case INDEX_op_orc_vec: 2577 case INDEX_op_xor_vec: 2578 case INDEX_op_nor_vec: 2579 case INDEX_op_mul_vec: 2580 case INDEX_op_smin_vec: 2581 case INDEX_op_smax_vec: 2582 case INDEX_op_umin_vec: 2583 case INDEX_op_umax_vec: 2584 case INDEX_op_ssadd_vec: 2585 case INDEX_op_usadd_vec: 2586 case INDEX_op_sssub_vec: 2587 case INDEX_op_ussub_vec: 2588 case INDEX_op_shlv_vec: 2589 case INDEX_op_shrv_vec: 2590 case INDEX_op_sarv_vec: 2591 case INDEX_op_rotrv_vec: 2592 case INDEX_op_rotlv_vec: 2593 return C_O1_I2(w, w, w); 2594 2595 case INDEX_op_not_vec: 2596 case INDEX_op_neg_vec: 2597 case INDEX_op_shli_vec: 2598 case INDEX_op_shri_vec: 2599 case INDEX_op_sari_vec: 2600 case INDEX_op_rotli_vec: 2601 return C_O1_I1(w, w); 2602 2603 case INDEX_op_bitsel_vec: 2604 return C_O1_I3(w, w, w, w); 2605 2606 default: 2607 return C_NotImplemented; 2608 } 2609} 2610 2611static const int tcg_target_callee_save_regs[] = { 2612 TCG_REG_S0, /* used for the global env (TCG_AREG0) */ 2613 TCG_REG_S1, 2614 TCG_REG_S2, 2615 TCG_REG_S3, 2616 TCG_REG_S4, 2617 TCG_REG_S5, 2618 TCG_REG_S6, 2619 TCG_REG_S7, 2620 TCG_REG_S8, 2621 TCG_REG_S9, 2622 TCG_REG_RA, /* should be last for ABI compliance */ 2623}; 2624 2625/* Stack frame parameters. */ 2626#define REG_SIZE (TCG_TARGET_REG_BITS / 8) 2627#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) 2628#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) 2629#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ 2630 + TCG_TARGET_STACK_ALIGN - 1) \ 2631 & -TCG_TARGET_STACK_ALIGN) 2632#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) 2633 2634/* We're expecting to be able to use an immediate for frame allocation. */ 2635QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); 2636 2637/* Generate global QEMU prologue and epilogue code */ 2638static void tcg_target_qemu_prologue(TCGContext *s) 2639{ 2640 int i; 2641 2642 tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); 2643 2644 /* TB prologue */ 2645 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); 2646 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2647 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2648 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2649 } 2650 2651 if (!tcg_use_softmmu && guest_base) { 2652 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); 2653 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); 2654 } 2655 2656 /* Call generated code */ 2657 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); 2658 tcg_out_opc_jirl(s, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); 2659 2660 /* Return path for goto_ptr. Set return value to 0 */ 2661 tcg_code_gen_epilogue = tcg_splitwx_to_rx(s->code_ptr); 2662 tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); 2663 2664 /* TB epilogue */ 2665 tb_ret_addr = tcg_splitwx_to_rx(s->code_ptr); 2666 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { 2667 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], 2668 TCG_REG_SP, SAVE_OFS + i * REG_SIZE); 2669 } 2670 2671 tcg_out_opc_addi_d(s, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); 2672 tcg_out_opc_jirl(s, TCG_REG_ZERO, TCG_REG_RA, 0); 2673} 2674 2675static void tcg_out_tb_start(TCGContext *s) 2676{ 2677 /* nothing to do */ 2678} 2679 2680static void tcg_out_nop_fill(tcg_insn_unit *p, int count) 2681{ 2682 for (int i = 0; i < count; ++i) { 2683 /* Canonical nop is andi r0,r0,0 */ 2684 p[i] = OPC_ANDI; 2685 } 2686} 2687 2688static void tcg_target_init(TCGContext *s) 2689{ 2690 unsigned long hwcap = qemu_getauxval(AT_HWCAP); 2691 2692 /* Server and desktop class cpus have UAL; embedded cpus do not. */ 2693 if (!(hwcap & HWCAP_LOONGARCH_UAL)) { 2694 error_report("TCG: unaligned access support required; exiting"); 2695 exit(EXIT_FAILURE); 2696 } 2697 2698 tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS; 2699 tcg_target_available_regs[TCG_TYPE_I64] = ALL_GENERAL_REGS; 2700 2701 tcg_target_call_clobber_regs = ALL_GENERAL_REGS | ALL_VECTOR_REGS; 2702 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); 2703 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); 2704 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); 2705 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); 2706 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); 2707 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); 2708 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); 2709 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); 2710 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); 2711 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); 2712 2713 if (cpuinfo & CPUINFO_LSX) { 2714 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS; 2715 tcg_target_available_regs[TCG_TYPE_V128] = ALL_VECTOR_REGS; 2716 if (cpuinfo & CPUINFO_LASX) { 2717 tcg_target_available_regs[TCG_TYPE_V256] = ALL_VECTOR_REGS; 2718 } 2719 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V24); 2720 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V25); 2721 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V26); 2722 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V27); 2723 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V28); 2724 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V29); 2725 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V30); 2726 tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_V31); 2727 } 2728 2729 s->reserved_regs = 0; 2730 tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); 2731 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); 2732 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); 2733 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); 2734 tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); 2735 tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); 2736 tcg_regset_set_reg(s->reserved_regs, TCG_REG_RESERVED); 2737 tcg_regset_set_reg(s->reserved_regs, TCG_VEC_TMP0); 2738} 2739 2740typedef struct { 2741 DebugFrameHeader h; 2742 uint8_t fde_def_cfa[4]; 2743 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; 2744} DebugFrame; 2745 2746#define ELF_HOST_MACHINE EM_LOONGARCH 2747 2748static const DebugFrame debug_frame = { 2749 .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ 2750 .h.cie.id = -1, 2751 .h.cie.version = 1, 2752 .h.cie.code_align = 1, 2753 .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ 2754 .h.cie.return_column = TCG_REG_RA, 2755 2756 /* Total FDE size does not include the "len" member. */ 2757 .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), 2758 2759 .fde_def_cfa = { 2760 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ 2761 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ 2762 (FRAME_SIZE >> 7) 2763 }, 2764 .fde_reg_ofs = { 2765 0x80 + 23, 11, /* DW_CFA_offset, s0, -88 */ 2766 0x80 + 24, 10, /* DW_CFA_offset, s1, -80 */ 2767 0x80 + 25, 9, /* DW_CFA_offset, s2, -72 */ 2768 0x80 + 26, 8, /* DW_CFA_offset, s3, -64 */ 2769 0x80 + 27, 7, /* DW_CFA_offset, s4, -56 */ 2770 0x80 + 28, 6, /* DW_CFA_offset, s5, -48 */ 2771 0x80 + 29, 5, /* DW_CFA_offset, s6, -40 */ 2772 0x80 + 30, 4, /* DW_CFA_offset, s7, -32 */ 2773 0x80 + 31, 3, /* DW_CFA_offset, s8, -24 */ 2774 0x80 + 22, 2, /* DW_CFA_offset, s9, -16 */ 2775 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ 2776 } 2777}; 2778 2779void tcg_register_jit(const void *buf, size_t buf_size) 2780{ 2781 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); 2782} 2783