1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Define target-specific opcode support 4 * Copyright (c) 2021 WANG Xuerui <git@xen0n.name> 5 */ 6 7 #ifndef TCG_TARGET_HAS_H 8 #define TCG_TARGET_HAS_H 9 10 #include "host/cpuinfo.h" 11 12 /* optional instructions */ 13 #define TCG_TARGET_HAS_add2_i32 0 14 #define TCG_TARGET_HAS_sub2_i32 0 15 #define TCG_TARGET_HAS_qemu_st8_i32 0 16 17 /* 64-bit operations */ 18 #define TCG_TARGET_HAS_extr_i64_i32 1 19 #define TCG_TARGET_HAS_add2_i64 0 20 #define TCG_TARGET_HAS_sub2_i64 0 21 22 #define TCG_TARGET_HAS_qemu_ldst_i128 (cpuinfo & CPUINFO_LSX) 23 24 #define TCG_TARGET_HAS_tst 0 25 26 #define TCG_TARGET_HAS_v64 (cpuinfo & CPUINFO_LSX) 27 #define TCG_TARGET_HAS_v128 (cpuinfo & CPUINFO_LSX) 28 #define TCG_TARGET_HAS_v256 (cpuinfo & CPUINFO_LASX) 29 30 #define TCG_TARGET_HAS_not_vec 1 31 #define TCG_TARGET_HAS_neg_vec 1 32 #define TCG_TARGET_HAS_abs_vec 0 33 #define TCG_TARGET_HAS_andc_vec 1 34 #define TCG_TARGET_HAS_orc_vec 1 35 #define TCG_TARGET_HAS_nand_vec 0 36 #define TCG_TARGET_HAS_nor_vec 1 37 #define TCG_TARGET_HAS_eqv_vec 0 38 #define TCG_TARGET_HAS_mul_vec 1 39 #define TCG_TARGET_HAS_shi_vec 1 40 #define TCG_TARGET_HAS_shs_vec 0 41 #define TCG_TARGET_HAS_shv_vec 1 42 #define TCG_TARGET_HAS_roti_vec 1 43 #define TCG_TARGET_HAS_rots_vec 0 44 #define TCG_TARGET_HAS_rotv_vec 1 45 #define TCG_TARGET_HAS_sat_vec 1 46 #define TCG_TARGET_HAS_minmax_vec 1 47 #define TCG_TARGET_HAS_bitsel_vec 1 48 #define TCG_TARGET_HAS_cmpsel_vec 0 49 #define TCG_TARGET_HAS_tst_vec 0 50 51 #define TCG_TARGET_extract_valid(type, ofs, len) 1 52 #define TCG_TARGET_deposit_valid(type, ofs, len) 1 53 54 static inline bool 55 tcg_target_sextract_valid(TCGType type, unsigned ofs, unsigned len) 56 { 57 if (type == TCG_TYPE_I64 && ofs + len == 32) { 58 return true; 59 } 60 return ofs == 0 && (len == 8 || len == 16); 61 } 62 #define TCG_TARGET_sextract_valid tcg_target_sextract_valid 63 64 #endif 65